Texas Instruments | SN74LVC10A (Rev. O) | Datasheet | Texas Instruments SN74LVC10A (Rev. O) Datasheet

Texas Instruments SN74LVC10A (Rev. O) Datasheet
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
www.ti.com
SCAS284O – JANUARY 1993 – REVISED JULY 2005
FEATURES
•
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
1C
1Y
3C
3B
3A
3Y
RGY PACKAGE
(TOP VIEW)
1B
2A
2B
2C
2Y
VCC
•
1
1
14
13 1C
12 1Y
2
3
4
11 3C
5
6
10 3B
9 3A
7
8
3Y
•
1A
1B
2A
2B
2C
2Y
GND
1A
•
•
•
D, DB, NS, OR PW PACKAGE
(TOP VIEW)
Operates From 1.65 V to 3.6 V
Specified From –40°C to 85°C and
– 40°C to 125°C
Inputs Accept Voltages to 5.5 V
Max tpd of 4.9 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
GND
•
•
DESCRIPTION/ORDERING INFORMATION
This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC10A performs the Boolean function Y = A • B • C or Y = A + B + C in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
QFN – RGY
Tube of 50
SN74LVC10AD
Reel of 2500
SN74LVC10ADR
Reel of 250
SN74LVC10ADT
SOP – NS
Reel of 2000
SN74LVC10ANSR
LVC10A
SSOP – DB
Reel of 2000
SN74LVC10ADBR
LC10A
Tube of 90
SN74LVC10APW
Reel of 2000
SN74LVC10APWR
Reel of 250
SN74LVC10APWT
TSSOP – PW
(1)
TOP-SIDE MARKING
SN74LVC10ARGYR
SOIC – D
–40°C to 125°C
ORDERABLE PART NUMBER
Reel of 1000
LC10A
LVC10A
LC10A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
www.ti.com
SCAS284O – JANUARY 1993 – REVISED JULY 2005
FUNCTION TABLE
(EACH GATE)
INPUTS
A
B
C
OUTPUT
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
X
L
H
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A
Y
B
C
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
VO
Output voltage range (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
D package
θJA
Package thermal impedance
(4)
86
DB package (4)
96
NS package (4)
76
package (4)
113
PW
RGY package (5)
Tstg
Ptot
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2
Storage temperature range
Power dissipation
47
–65
TA = –40°C to
125°C (6) (7)
°C/W
150
°C
500
mW
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
www.ti.com
SCAS284O – JANUARY 1993 – REVISED JULY 2005
Recommended Operating Conditions
(1)
TA = 25°C
VCC
Supply voltage
VIH
High-level input
voltage
Low-level input
voltage
VIL
VI
Input voltage
VO
Output voltage
High-level
output current
IOH
Operating
Data retention only
MAX
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.65
3.6
1.5
1.5
1.5
0.65 × VCC
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
2
VCC = 1.65 V to 1.95 V
UNIT
V
V
0.35 × VCC
0.35 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
0.8
VCC = 1.65 V to 1.95 V
V
0
5.5
0
5.5
0
5.5
V
0
VCC
0
VCC
0
VCC
V
VCC = 1.65 V
–4
–4
–4
VCC = 2.3 V
–8
–8
–8
VCC = 2.7 V
–12
–12
–12
VCC = 3 V
–24
–24
–24
4
4
4
Low-level output VCC = 2.3 V
current
VCC = 2.7 V
VCC = 3 V
(1)
–40 TO 125°C
MIN
VCC = 1.65 V
IOL
–40 TO 85°C
8
8
8
12
12
12
24
24
24
mA
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 3.6 V
MIN
–40 TO 125°C
MAX
MIN
MAX
VCC – 0.2
VCC – 0.2
VCC – 0.3
1.29
1.2
1.05
IOH = –8 mA
2.3 V
1.9
1.7
1.55
2.7 V
2.2
2.2
2.05
3V
2.4
2.4
2.25
IOH = –24 mA
3V
2.3
IOL = 100 µA
1.65 V to 3.6 V
0.1
0.2
0.3
IOL = 4 mA
1.65 V
0.24
0.45
0.6
IOL = 8 mA
2.3 V
0.3
0.7
0.75
IOL = 12 mA
2.7 V
0.4
0.4
0.6
3V
IOL = 24 mA
VI = 5.5 V or GND
ICC
VI = VCC or GND,
Ci
–40 TO 85°C
TYP MAX
1.65 V
II
∆ICC
TA = 25°C
MIN
IOH = –4 mA
IOH = –12 mA
VOL
VCC
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or
GND
VI = VCC or GND
2.2
UNIT
V
2
V
0.55
0.55
0.8
3.6 V
±1
±5
±20
µA
3.6 V
1
10
40
µA
500
500
5000
µA
2.7 V to 3.6 V
3.3 V
5
pF
3
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
www.ti.com
SCAS284O – JANUARY 1993 – REVISED JULY 2005
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
VCC
TA = 25°C
–40 TO 85°C
TYP
MAX
MIN
MAX
MIN
MAX
1.8 V ± 0.15 V
1
4.2
10.1
1
10.6
1
12.1
2.5 V ± 0.2 V
1
2.9
7.3
1
7.8
1
9.9
2.7 V
1
3.1
5.6
1
5.8
1
7.4
3.3 V ± 0.3 V
1
2.7
4.7
1
4.9
1
6
3.3 V ± 0.3 V
tsk(o)
–40 TO 125°C
MIN
1
1.5
UNIT
ns
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance per gate
TEST
CONDITIONS
f = 10 MHz
VCC
TYP
1.8 V
9
2.5 V
10
3.3 V
11
UNIT
pF
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
www.ti.com
SCAS284O – JANUARY 1993 – REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC10AD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC10A
SN74LVC10ADBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC10A
SN74LVC10ADBRE4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC10A
SN74LVC10ADG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC10A
SN74LVC10ADR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC10A
SN74LVC10ADT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC10A
SN74LVC10ANSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC10A
SN74LVC10APW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC10A
SN74LVC10APWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC10A
SN74LVC10APWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC10A
SN74LVC10APWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC10A
SN74LVC10ARGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC10A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74LVC10ADR
SOIC
D
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
6.5
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.0
2.1
8.0
16.0
Q1
SN74LVC10ADT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC10ANSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LVC10APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC10APWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC10ARGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC10ADR
SOIC
D
14
2500
367.0
367.0
38.0
SN74LVC10ADT
SOIC
D
14
250
210.0
185.0
35.0
SN74LVC10ANSR
SO
NS
14
2000
367.0
367.0
38.0
SN74LVC10APWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LVC10APWT
TSSOP
PW
14
250
367.0
367.0
35.0
SN74LVC10ARGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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