Texas Instruments | SN54LV20A, SN74LV20A (Rev. E) | Datasheet | Texas Instruments SN54LV20A, SN74LV20A (Rev. E) Datasheet

Texas Instruments SN54LV20A, SN74LV20A (Rev. E) Datasheet
 SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005
D 2-V to 5.5-V VCC Operation
D Max tpd of 6 ns at 5 V
D Typical VOLP (Output Ground Bounce)
D
D
D
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
1A
1B
NC
1C
1D
1Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2D
2C
NC
2B
2A
2Y
SN54LV20A . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
VCC
2D
D
SN54LV20A . . . J OR W PACKAGE
SN74LV20A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
NC
NC
1C
NC
1D
These dual 4-input positive-NAND gates are
designed for 2-V to 5.5-V VCC operation.
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2C
NC
NC
NC
2B
1Y
GND
NC
2Y
2A
The ’LV20A devices perform the Boolean function
Y = A • B • C • D or Y = A + B + C + D in positive
logic.
4
These devices are fully specified for
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing
damaging current backflow through the devices
when they are powered down.
NC − No internal connection
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube of 50
SN74LV20AD
Reel of 2500
SN74LV20ADR
SOP − NS
Reel of 2000
SN74LV20ANSR
74LV20A
SSOP − DB
Reel of 2000
SN74LV20ADBR
LV20A
Tube of 90
SN74LV20APW
Reel of 2000
SN74LV20APWR
Reel of 250
SN74LV20APWT
TVSOP − DGV
Reel of 2000
SN74LV20ADGVR
LV20A
CDIP − J
Tube of 25
SNJ54LV20AJ
SNJ54LV20AJ
CFP − W
Tube of 150
SNJ54LV20AW
SNJ54LV20AW
LCCC − FK
Tube of 55
SNJ54LV20AFK
SOIC − D
−40°C to 85°C
TSSOP − PW
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV20A
LV20A
SNJ54LV20AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2005, Texas Instruments Incorporated
!"# #$# %
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'# ('"#/ " # #""$'*. #*" "#/ & $**
($'$!""'+
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1
SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005
FUNCTION TABLE
(each gate)
INPUTS
A
B
C
D
OUTPUT
Y
H
H
H
H
L
L
X
X
X
H
X
L
X
X
H
X
X
L
X
H
X
X
X
L
H
logic diagram (positive logic)
1A
1B
1C
1D
1
2
4
5
6
2A
2B
2C
2D
1Y
9
10
12
13
8
2Y
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range applied in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005
recommended operating conditions (see Note 4)
SN54LV20A
VCC
VIH
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
IOH
IOL
∆t/∆v
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
2
5.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
Output voltage
0
0.5
0
VCC
−50
VCC × 0.3
5.5
0
VCC
−50
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
V
V
µA
−2
−6
−6
−12
−12
VCC = 2 V
VCC = 2.3 V to 2.7 V
50
50
2
2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
6
6
12
12
200
200
100
100
20
20
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
VCC = 2 V
VCC = 2.3 V to 2.7 V
UNIT
V
0.5
VCC × 0.3
VCC × 0.3
0
Input transition rise or fall rate
MAX
1.5
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level output current
MIN
1.5
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level output current
SN74LV20A
mA
µA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV20A
PARAMETER
VOH
VOL
TEST CONDITIONS
IOH = −50 µA
IOH = −2 mA
2 V to 5.5 V
IOL = 50 µA
IOL = 2 mA
IOL = 6 mA
IOL = 12 mA
VI = 5.5 V or GND
VI = VCC or GND,
Ioff
Ci
VI or VO = 0 to 5.5 V
VI = VCC or GND
IO = 0
MIN
TYP
SN74LV20A
MAX
MIN
VCC−0.1
2
VCC−0.1
2
3V
2.48
2.48
4.5 V
3.8
2.3 V
IOH = −6 mA
IOH = −12 mA
II
ICC
VCC
TYP
MAX
UNIT
V
3.8
2 V to 5.5 V
0.1
0.1
2.3 V
0.4
0.4
3V
0.44
0.44
4.5 V
V
0.55
0.55
0 to 5.5 V
±1
±1
µA
5.5 V
20
20
µA
0
5
5
µA
3.3 V
1.9
1.9
pF
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switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tpd
A, B, C, or D
Y
CL = 15 pF
6.8*
tpd
A, B, C, or D
Y
CL = 50 pF
9.2
MIN
SN54LV20A
SN74LV20A
UNIT
MIN
MAX
MIN
MAX
11.6*
1*
13.5*
1
13.5
ns
15.3
1
18.5
1
18.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TA = 25°C
MIN
TYP
MAX
tpd
A, B, C, or D
Y
CL = 15 pF
4.9*
tpd
A, B, C, or D
Y
CL = 50 pF
6.5
SN54LV20A
SN74LV20A
UNIT
MIN
MAX
MIN
MAX
6.6*
1*
8*
1
8
ns
10.1
1
11.5
1
11.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tpd
A, B, C, or D
Y
CL = 15 pF
3.7*
tpd
A, B, C, or D
Y
CL = 50 pF
4.8
MIN
SN54LV20A
SN74LV20A
UNIT
MIN
MAX
MIN
MAX
5*
1*
6*
1
6
ns
7
1
8
1
8
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
SN74LV20A
PARAMETER
MIN
MAX
0.2
0.8
V
−0.8
V
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
0
VOH(V)
VIH(D)
Quiet output, minimum dynamic VOH
3.2
High-level dynamic input voltage
UNIT
TYP
V
2.31
V
VIL(D)
Low-level dynamic input voltage
NOTE 5: Characteristics are for surface-mount packages only.
0.99
V
VCC
3.3 V
TYP
UNIT
5V
23.9
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
% #&'!$# #"'# (' # " &'!$0" '
"/# ($" & "0"*(!"#+ %$'$"' $$ $# "'
("&$# $'" "/# /$*+ ",$ #'!"# '""'0" " '/ $#/" ' ##" "" (' - #"+
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f = 10 MHz
20.5
pF
SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
50% VCC
tPZL
tPHL
tPHL
Out-of-Phase
Output
0V
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
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24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV20AD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV20A
SN74LV20ADBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV20A
SN74LV20ADG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV20A
SN74LV20ADGVR
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV20A
SN74LV20ADR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV20A
SN74LV20ANSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV20A
SN74LV20APW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV20A
SN74LV20APWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV20A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74LV20ADGVR
TVSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DGV
14
2000
330.0
12.4
6.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
4.0
1.6
8.0
12.0
Q1
SN74LV20ADR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LV20ANSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LV20APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV20ADGVR
TVSOP
DGV
14
2000
367.0
367.0
35.0
SN74LV20ADR
SOIC
D
14
2500
367.0
367.0
38.0
SN74LV20ANSR
SO
NS
14
2000
367.0
367.0
38.0
SN74LV20APWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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