Texas Instruments | SN74LV4320A (Rev. A) | Datasheet | Texas Instruments SN74LV4320A (Rev. A) Datasheet

Texas Instruments SN74LV4320A (Rev. A) Datasheet
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D Member of the Texas Instruments
D
D
D
D
D Ioff Supports Partial-Power-Down Mode
Widebus+ Family
Designed to Optimize Power Savings in
Portable Applications
1.65-V to 5.5-V Level Translation Using Dual
Supplies
Matched Pinout With CompactFlash (CF)
Connector Pin Configurations to Optimize
PCB Layout
Input-Disable Feature Allows Floating Input
Conditions
D
D
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD
− 15-kV Human-Body Model
− +4-kV IEC61000-4-2, Contact Discharge
(Latch-Up Immune)
description/ordering information
This CompactFlash (CF) interface chip is designed to provide a single-chip solution for CF card interfaces.
Separate VCC rails for the system bus side and the CF connector bus side allow voltage-level shifting. This is
helpful for interfacing between a core chipset, which may operate from 3.3 V down to 1.65 V, and CF cards, which
operate from 3.3-V or 5-V supply voltages. All the input buffers feature the input-disable function, which allows
conditional floating input signals. The input, output, and I/O buffers on the CF connector side have been defined
to comply with CF+ and CompactFlash specification revisions 1.4 and 2.0.
This device has 16-bit data lines and 24-bit address/command lines. CD1 and CD2 have internal pullup resistors
to pull them to a high logic state if there is no card in the CF slot. The presence of a CF card in the CF card slot
generates a low logic signal at SCD. A separate power-supply pin, VCC_SD, controls the SCD output buffer. The
SCD signal can be used to control a voltage regulator, which may power the CF slot and the CF side of this
device. VCC_SD is particularly helpful when the core processor operates at a low VCC, but the regulator needs
a higher control signal voltage.
The MASTER_EN signal controls all the buffers and transceivers except CD1 and CD2. If MASTER_EN is high,
the SN74LV4320A is in a power-down mode. The BUF_EN signal, in conjunction with MASTER_EN, controls
the 11-bit address lines and 13-bit control/command lines.
The 16-bit data lines use two separate enable signals. ENL, in conjunction with MASTER_EN, controls the lower
8-bit data lines (D07−D00). ENH, in conjunction with MASTER_EN, controls the upper 8-bit data lines
(D15−D08). A DIR(S/CF) input controls the data direction between the system bus and the CF card. An
additional DIR_OUT pin generates the DIR(S/CF) signal using the SOE and SIORD signals. With either SOE
or SIORD being low, the data direction is from the CF card side to the system side (DIR_OUT = L). DIR(S/CF)
and DIR_OUT are placed adjacent to each other, which is convenient for connecting DIR(S/CF) and DIR_OUT,
if DIR_OUT is used. This saves an additional signal from the system controller to control the data direction.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
LFBGA − GKF
Tape and reel
SN74LV4320AGKFR
LM320A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
CompactFlash is a trademark of Sandisk Corporation.
Copyright  2005, Texas Instruments Incorporated
()*+() (" ,++-) " * ,.!(() /-0
+/," )*+ "-(*(()" -+ #- -+" * -1" )"+,-)"
")/+/ 2++)30 +/,() +-""()4 /-" ) )--""+(!3 ()!,/-"()4 * !! +--+"0
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description/ordering information (continued)
BVD1, BVD2, INPACK, READY, WAIT, and WP have 100-kΩ internal pullup resistors, eliminating the need for
external pullups. The resistors are within the tolerance of CF+ and CompactFlash specification revisions 1.4
and 2.0.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
board-optimized pin configuration
GKF PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
A
D12
D04
D03
SD14
SD12
SD11
B
D13
D05
D11
SD13
SD10
SD09
C
D14
D06
SD15
SINPACK
SD08
SD07
D
D15
D07
SD05
CE2
CE1
VCC_S
GND
SD06
E
VCC_CF
GND
SD04
SD03
VCC_CF
GND
VCC_S
GND
SD02
SD01
SD00
SCE1
A
B
C
D
E
F
6
F
OE
A10
G
G
A09
IORD
H
H
A08
IOWR
A07
WE
VCC_S
GND
EN_H
J
VCC_CF
GND
EN_L
J
MASTER_EN
BUF_EN
K
K
A06
READY
A05
SCE2
SOE
SIORD
L
L
A04
RESET
GND
GND
SWE
SIOWR
M
M
A03
WAIT
SRESET
N
A02
INPACK
VCC_S
GND
SREADY
N
VCC_CF
GND
SWAIT
SREG
P
R
T
U
V
W
2
P
A01
REG
R
A00
BVD2
VCC_CF
VCC_CF
GND
SBVD2
SBVD1
VCC_S
DIR(S/CF)
SA10
SWP
SA08
SA09
DIR_OUT
SA06
SA07
T
D00
BVD1
U
D01
D08
VCC_SD
CD1
V
D02
D09
CD2
SA00
SA04
SA05
W
WP
D10
SCD
SA01
SA02
SA03
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FUNCTION TABLES
Lower 8-Bit Data Bus Transceivers (D07–D00, SD07–SD00)
INPUTS
OPERATION
MASTER_EN
ENL
DIR (S/CF)
L
L
H
SD data to D bus
L
L
L
D data to SD bus
L
H
X
Isolation. D07–D00 and SD07–SD00 inputs can float.
H
X
X
Isolation, low power mode
X = H or L
Upper 8-Bit Data Bus Transceivers (D15–D08, SD15–SD08)
INPUTS
MASTER_EN
ENH
DIR (S/CF)
L
L
H
OPERATION
SD data to D bus
L
L
L
D data to SD bus
L
H
X
Isolation. D15–D08 and SD15–SD08 inputs can float.
H
X
X
Isolation, low power mode
X = H or L
Address Bus Buffers
INPUTS
MASTER_EN
BUF_EN
SA
OUTPUT
A
L
L
H
H
L
L
L
L
L
H
X
Z. SA inputs can float.
H
X
X
Z, low power mode
X = H or L
Command Line Buffers
(BVD1, BVD2, INPACK, OE, IORD, IOWR,
READY, REG, CE1, CE2, WAIT, WE, WP, )
INPUTS
MASTER_EN
BUF_EN
INPUT
L
L
H
OUTPUT
H
L
L
L
L
L
H
X
Z. Command line buffer inputs can float.
H
X
X
Z, low power mode
X = H or L
Reset
INPUTS
MASTER_EN
SRESET
OUTPUT
RESET
L
H
H
L
L
L
H
X
Z, low power mode
X = H or L
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FUNCTION TABLES (Continued)
DIR_OUT
INPUTS
BUF_EN
MASTER_EN
L
L
L
L
L
L
SIORD
OUTPUT
DIR_OUT
L
L
L
L
H
L
H
L
L
SOE
L
L
H
H
H
H
L
X
X
L
X
H
X
X
Z, low power mode
X = H or L
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logic diagram
VCC_SD
R INT
VCC_SD
CD1
VCC_SD
R INT
SCD
CD2
VCC_CF
VCC_S
SIORD−INT
SOE−INT
DIR_OUT
DIR(S/CF)
VCC_S
R INT
ENL
MASTER_EN
D07−D00
8
8
To 7 Other Channels
VCC_S
R INT
O
N
To 7 Other Channels
SD07−SD00
A
T
I
ENH
8
L
8
SD15−SD08
To 7 Other Channels
A
To 7 Other Channels
N
S
D15−D08
R
RESET
SRESET
T
VCC_S
R INT
BUF_EN
A10−A00
11
11
SIORD−INT
SOE−INT
CE1, CE2, IORD,
IOWR, OE, REG, WE
BVD1, BVD2, INPACK,
READY, WAIT, WP
SA10−SA00
2
7
7
VCC_CF
R INT
6
6
SCE1, SCE2, SIORD,
SIOWR, SOE, SREG,
SWE
SBVD1, SBVD2, SINPACK,
SREADY, SWAIT, SWP
NOTE: R INT ≥ 100 kΩ
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC_S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
VCC_CF, VCC_SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI: I/O ports (SD, SA) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I/O ports (D, A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input ports (SCE1, SCE2, SIORD, SIOWR, SOE, SREG, SWE) . . . −0.5 V to 4.6 V
Input ports (BVD1, BVD2, READY, INPACK, WAIT, WP) . . . . . . . . . −0.5 V to 6.5 V
Control ports (DIR(S/CF), MASTER_EN, ENL, ENH) . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): System port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CF port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2): System port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC_S + 0.5 V
CF port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC_CF + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC_S, VCC_CF, VCC_SD, or GND . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output-current ratings are observed.
2. This value is limited to 6.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
6
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recommended operating conditions (see Notes 4 through 6)
VCCI
VCCO
MIN
MAX
UNIT
VCC_SD
VCC_S
Card-detect supply voltage
1.65
5.5
V
System-side supply voltage
1.65
V
VCC_CF
CF-side supply voltage
VCC_CF
5.5
VIH
High-level
input
voltage
Card-detect inputs
(CD1, CD2,)
1.65 V to 5.5 V
VIL
Low-level
input
voltage
Card-detect inputs
(CD1, CD2,)
1.65 V to 5.5 V
VIH
High-level
input
voltage
System port
(SD, SA, SRESET)
Low-level
input
voltage
System port
(SD, SA, SRESET)
High-level
input
voltage
Control inputs
(DIR, MASTER_EN, ENL,
ENH, BUF_EN)
1.65 V to 1.95 V
Low-level
input
voltage
Control inputs
(DIR, MASTER_EN, ENL,
ENH, BUF_EN)
1.65 V to 1.95 V
VIL
VIH
High-level
input
voltage
VIL
Low-level
input
voltage
VIL
VIH
VO
Output
voltage
3
VCC_SD × 0.65
1.95 V to 2.7 V
VCC_S × 0.65
1.7
2.7 V to 3.6 V
2
VCC_S × 0.35
0.7
2.7 V to 3.6 V
0.8
1.95 V to 2.7 V
VCC_S × 0.65
1.7
2.7 V to 3.6 V
2
2.7 V to 3.6 V
IOL
High-level
output
current
2
CF port (D, A)
Low-level
output
current
V
VCC_CF × 0.7
4.5 V to 5.5 V
3 V to 3.6 V
0.8
VCC_CF × 0.3
4.5 V to 5.5 V
Card-detect output voltage
0
VCC_SD
System-side output
voltage
0
VCC_S
0
1.65 V to 1.95 V
VCC_CF
−2
1.95 V to 2.7 V
−4
2.7 V to 3.6 V
−8
4.5 V to 5.5 V
−12
Card detect
Card detect
V
0.8
3 V to 3.6 V
CF-side output voltage
IOH
V
V
VCC_S × 0.35
0.7
1.95 V to 2.7 V
V
V
1.95 V to 2.7 V
1.65 V to 1.95 V
CF port (D, A)
V
VCC_SD × 0.35
1.65 V to 1.95 V
V
1.65 V to 1.95 V
2
1.95 V to 2.7 V
4
2.7 V to 3.6 V
8
4.5 V to 5.5 V
12
V
V
mA
mA
NOTES: 4. VCCI is the VCC associated with the data input port.
5. VCCO is the VCC associated with the output port.
6. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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recommended operating conditions (see Notes 4 through 6) (continued)
VCCI
IOH
IOL
Low-level output current
System port
System port
IOH
High-level output current
CF port
IOL
Low-level output current
CF port
∆t/∆v
t/ v
TA
NOTES: 4.
5.
6.
8
High-level output current
Input transition rise or fall rate
VCCO
1.65 V to 1.95 V
MIN
MAX
2
1.95 V to 2.7 V
6
2.7 V to 3.6 V
12
1.65 V to 1.95 V
2
1.95 V to 2.7 V
6
2.7 V to 3.6 V
12
3 V to 3.6 V
12
4.5 V to 5.5 V
16
3 V to 3.6 V
12
4.5 V to 5.5 V
16
1.65 V to 2.7 V
>20
2.7 V to 3.6 V
>20
4.5 V to 5.5 V
>20
Operating free-air temperature
UNIT
−40
85
mA
mA
mA
mA
ns/V
°C
VCCI is the VCC associated with the data input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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electrical characteristics over recommended operating free-air temperature range (CF card-detect
logic) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100 µA
IOH = −2 mA
IOH = −4 mA
VOH
IOH = −6 mA
IOH = −8 mA
1.65 V to 5.5 V
1.65 V
VI = VIH
IOH = −12 mA
IOL = 100 µA
IOL = 2 mA
IOL = 4 mA
VOL
IOL = 6 mA
IOL = 8 mA
VI = VIL
IOL = 12 mA
VI = VCC_SD
II
Ioff
VI = 0 V
VI or VO = 0 to 5.5 V
RINT
CD1 = GND, CD2 = GND
VCC_SD
TA = 25°C
MIN TYP
CD1 or CD2 = GND,
CD2 or CD1 = VCC_SD
VCC_SD−0.2
1.2
1.2
2.3 V
2
2
2.7 V
2.3
2.3
3V
2.4
2.4
4.5 V
3.8
Ci
VI = VCC_SD or GND
CD1 or CD2
MAX
3.8
0.1
0.2
1.65 V
0.2
0.2
2.3 V
0.2
0.2
2.7 V
0.3
0.3
3V
0.4
0.4
1.65 V to 5.5 V
0V
1.65 V to 5.5 V
150
5.5 V
5.5 V
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UNIT
V
1.65 V to 5.5 V
4.5 V
IO_SD = 0
MIN
VCC_SD−0.1
CD1 and CD2 = VCC_SD
ICC_SD
−40°C to 85°C
MAX
9
V
0.5
0.5
±0.5
±1
−55
−60
55
60
µA
300
kΩ
300
100
0.5
1
10
10
µA
µA
pF
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC_S
TA = 25°C
TYP
MAX
VCC_CF
MIN
1.65 V
VT+
VT−
SOE, SCE1, SCE2,
SIORD, SIOWR,
SWE, SREG
2.3 V
3 V to 5.5 V
2.7 V
SOE, SCE1, SCE2,
SIORD, SIOWR,
SWE, SREG
0.8
0.98
0.49
1.32
3 V to 5.5 V
3V
1.08
0.59
1.5
1.65 V
0.31
0.1
0.7
2.3 V
0.46
0.25
0.7
0.52
0.3
0.9
1.65 V to
3.6 V
∆VT
BVD1, BVD2,
READY, INPACT,
WAIT
1.65 V to
3.6 V
3 V to 5.5 V
0.61
0.4
0.9
3V
1.67
1.3
2.2
4.5 V
2.44
1.9
3.1
3V
1.11
0.6
1.5
4.5 V
1.43
1
2
3V
0.58
0.35
1
4.5 V
1.02
0.6
1.5
1.65 V
1
0.6
1.4
2.3 V
1.37
1.1
1.8
1.54
1.1
2
2.2
3V
1.72
1.3
0.34
0.15
1
2.3 V
0.63
0.15
1.2
0.75
0.2
1.32
3 V to 5.5 V
3V
0.88
0.4
1.5
1.65 V
0.67
0.08
1.1
2.3 V
0.76
0.2
1.2
0.8
0.26
1.3
0.3
1.4
3 V to 5.5 V
2.7 V
VCC_S
−0.1 V
VCC_S
−0.2 V
1.2
1.2
2
2
1.65 V
3 V to 5.5 V
IOH = −6 mA
IOH = −12 mA
2.7 V
2.3
2.3
3V
2.4
2.4
IOL = 100 µA
1.65 V to
3.6 V
IOL = 2 mA
IOL = 4 mA
IOL = 6 mA
IOL = 12 mA
10
0.86
1.65 V to
3.6 V
2.3 V
0.2
0.2
0.2
0.2
0.2
2.7 V
0.3
0.3
3V
0.5
0.5
2.3 V
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V
V
V
V
0.1
1.65 V
VI = VIL
V
V
1.65 V
2.7 V
V
V
3 V to 5.5 V
2.7 V
UNIT
V
3V
VOL_S
2.2
1.15
BVD1, BVD2,
READY, INPACK,
WAIT, WP
VI = VIH
2
0.39
VT−
IOH = −2 mA
IOH = −4 mA
1.8
1
0.87
1.65 V to
3.6 V
VOH_S
0.9
1.49
2.3 V
VT+
IOH = −100 µA
1.32
1.2
2.7 V
BUF_EN, ENH,
ENL, MASTER_EN
1.4
0.19
3V
∆VT
0.6
0.66
BVD1, BVD2,
READY, INPACT,
WAIT
VT−
0.95
1.67
∆VT
BUF_EN, ENH,
ENL, MASTER_EN
MAX
3V
2.7 V
BUF_EN, ENH,
ENL, MASTER_EN
MIN
1.65 V
SOE, SCE1, SCE2,
SIORD, SIOWR,
SWE, SREG
VT+
−40°C to 85°C
V
!"# $ %& ' %% ' % ' SCES628A − APRIL 2005 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)(see Notes 4 and 5) (continued)
PARAMETER
TEST CONDITIONS
IOH = −100 µA
VOH_CF
IOH = 12 mA
IOH = 16 mA
VI = VIH
IOL = 100 µA
VOL_CF
II
IOL = 12 mA
IOL = 16 mA
VI = VIL
Inputs without
pullup resistor
VI = GND to VCCI (see Note 7)
Inputs with pullup
resistor
VI = VCCI (see Note 7)
VI = 0 V
S port
Ioff
VI or VO = 0 to 5.5 V
CF port
IOZ†
S or CF output
ports
CF outputs
Inputs
SD15-SD00,
SA10-SA00,
SCE1, SCE2,
SIORD, SIOWR,
SOE, SREG,
SWE)
ICC_S
Control inputs
(ENL, ENH,
BUF_EN)
VO = VCCO
or GND,
VI = VCCI
or GND
VI = VCC_S
or GND
ENL = ENH =
BUF_EN =
VCC_S
One of ENL,
ENH,
BUF_EN =
GND, Others
= VCC_S
MASTER_EN =
VIH
MASTER_EN =
don’t care
VCC_S
1.65 V
to 3.6 V
1.65 V
to 3.6 V
VCC_CF
TA = 25°C
TYP
MAX
−40°C to 85°C
MIN
MIN
VCC_CF
−0.1 V
VCC_CF
−0.2 V
3V
2.4
2.4
5.5 V
3.8
3.8
3 V to
5.5 V
MAX
V
3 V to
5.5 V
0.1
0.2
3V
0.5
0.5
5.5 V
0.5
0.5
3.6 V to
5.5 V
±0.5
±1
3 V to
5.5 V
±0.5
±1
55
60
0V
0 to
5.5 V
±0.5
±1
0 to
3.6 V
0V
±0.5
±1
5.5 V
±0.5
±1
0V
±0.5
±1
1.5
3
1.5
3
36
36
1.65 V
to 3.6 V
V
A
µA
A
µA
A
µA
3.6 V
IO = 0,
ENL = VCC_S,
ENH = VCC_S,
BUF_EN =
VCC_S,
DIR(S/CF) =
VCC_S
1.65 V
to 3.6 V
UNIT
3.6 V to
5.5 V
IO = 0, DIR(S/CF)
= VCC_S,
All other inputs =
VCC_S or GND
µA
† For I/O ports, the parameter IOZ includes the input leakage current.
NOTES: 4. VCCI is the VCC associated with the data input port.
5. VCCO is the VCC associated with the output port.
7. VCCI = VCC_S for DIR(S/CF), ENL, ENH, SD15–SD00, SA10–SA00, MASTER_EN, SRESET, SCE1, SCE2, SIORD, SIOWR, SOE,
SREG, SWE, BUF_EN
VCCI = VCC_CF for D15–D00, BVD1, BVD2, INPACK, READY, WAIT, WP
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
!"# $ %& ' %% ' % ' SCES628A − APRIL 2005 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
VCC_S
MIN
ICC_CF
Input
(D15–D00)
VI = VCC_CF
or GND
Inputs
(BVD1, BVD2,
INPACK,
READY, WAIT,
WP)
BVD1 = BVD2 =
INPACK =
READY WAIT =
WP = VCC_CF
One of BVD1,
DVD2, INPACK,
READY, WAIT,
WP = GND. All
others= VCC_CF
IO = 0,
DIR(S/CF) =
GND, BVD1,
BVD2, INPACK,
READY, WAIT,
WP = VCC_CF
IO = 0,
DIR(S/CF) =
GND,
D15–D00 =
VCC_CF or GND
IO = 0,
DIR(S/CF) =
GND,
D15–D00 =
VCC_CF or GND
RINT
Ci
UNIT
MAX
1.5
3
1.65 V
to 3.6 V
3 V to
5.5 V
1.5
3
1.65 V
to 3.6 V
3 V to
5.5 V
60
60
1.65 V
to 3.6 V
3 V to
5.5 V
300
300
150
3
3
3.3 V
3.3 V
µA
kΩ
pF
9
S I/O ports
12
MIN
3 V to
5.5 V
SAxx, SOE,
SCE1, SCE2,
SIORD, SIOWR,
SREG, SWE
CF I/O ports
MAX
1.65 V
to 3.6 V
Axx, BVD1,
BVD2, READY,
INPACK, WAIT,
WP
Cio
TYP
Control inputs
VI = 3.3 V or GND
−40°C to
85°C
TA = 25°C
VCC_CF
7
VO = 3.3 V or GND
POST OFFICE BOX 655303
3.3 V
3.3 V
• DALLAS, TEXAS 75265
12
pF
!"# $ %& ' %% ' % ' SCES628A − APRIL 2005 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range (CD1, CD2)
(see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
CD1 or CD2
TO
(OUTPUT)
TEST
CONDITIONS
−40°C to
85°C
TA = 25°C
VCC_SD
UNIT
MIN
TYP
MAX
MIN
MAX
1.8 V ± 0.15 V
3.1
7.1
13.5
1.8
15.5
2.5 V ± 0.2 V
2.7
4.6
7.1
1.6
9.1
2.4
4
5.7
1.6
9.1
2
3.4
5.1
1.2
6.8
1.7
2.6
3.6
1
5.5
SCD
2.7 V
3.3 V ± 0.3 V
5 V ± 0.5 V
ns
switching characteristics over recommended operating free-air temperature range
(BVD1, BVD2, INPACK, READY, WAIT, WP) (see Figure 1)
PARAMETER
tpd
ten
tdis
ten
tdis
FROM
(INPUT)
CF input
MASTER_EN
MASTER_EN
BUF_EN
BUF_EN
TO
(OUTPUT)
S output
S output
S output
S output
S output
TEST
CONDITIONS
MASTER_EN
= BUF_EN =
VIL
BUF_EN = VIL
BUF_EN = VIL
MASTER_EN
= VIL
MASTER_EN
= VIL
VCC_S
VCC_CF
−40°C to
85°C
TA = 25°C
MIN
UNIT
TYP
MAX
MIN
MAX
1.8 V ± 0.15 V
3.3 V ± 0.3 V
3.1
6
10.2
2.4
12.9
1.8 V ± 0.15 V
5 V ± 0.5 V
2.9
5.6
9.6
2.2
13.9
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.7
4.6
6.5
1.9
10
2.5 V ± 0.2 V
5 V ± 0.5 V
2.5
4.2
5.8
1.7
8.6
3.3 V ± 0.3 V
3.3 V ± 0.3 V
2.5
4
5.6
1.6
8.8
3.3 V ± 0.3 V
5 V ± 0.5 V
2.3
3.6
4.9
1.5
7
1.8 V ± 0.15 V
3.3 V ± 0.3 V
11.1
18.9
30.7
9.2
35.5
1.8 V ± 0.15 V
5 V ± 0.5 V
11.1
19.3
30.9
8
35.6
2.5 V ± 0.2 V
3.3 V ± 0.3 V
9.9
12.9
17.4
6.9
22.6
2.5 V ± 0.2 V
5 V ± 0.5 V
9.9
13.1
17.4
7
22.6
3.3 V ± 0.3 V
3.3 V ± 0.3 V
9.5
11.2
13.4
6.3
18.3
3.3 V ± 0.3 V
5 V ± 0.5 V
9.5
11.3
13.5
6.3
18.2
1.8 V ± 0.15 V
3.3 V ± 0.3 V
6.8
13.7
23.9
6
25.1
1.8 V ± 0.15 V
5 V ± 0.5 V
6.1
13.4
22
5.4
23.3
2.5 V ± 0.2 V
3.3 V ± 0.3 V
4.9
8.6
13.3
4
14.5
2.5 V ± 0.2 V
5 V ± 0.5 V
4.6
8.5
13.6
3.9
14.5
3.3 V ± 0.3 V
3.3 V ± 0.3 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1.8 V ± 0.15 V
1.8 V ± 0.15 V
5
8.1
12.2
4.2
13.2
4.5
8
12.2
3.6
18.2
3.3 V ± 0.3 V
8.7
17.7
33.2
7.6
35.5
5 V ± 0.5 V
10.7
18.3
29.3
8.7
35.6
2.5 V ± 0.2 V
3.3 V ± 0.3 V
9.6
12.4
16.6
6.6
22.6
2.5 V ± 0.2 V
5 V ± 0.5 V
9.6
12.6
16.7
6.6
22.6
3.3 V ± 0.3 V
3.3 V ± 0.3 V
9.2
10.9
13
6.1
18.3
3.3 V ± 0.3 V
5 V ± 0.5 V
9.2
10.9
13
6.1
18.2
1.8 V ± 0.15 V
3.3 V ± 0.3 V
6.9
12.9
22.3
5.9
24.2
1.8 V ± 0.15 V
5 V ± 0.5 V
5.4
12.4
20.5
4.8
22.8
2.5 V ± 0.2 V
3.3 V ± 0.3 V
4.4
8
12.7
3.6
14.5
2.5 V ± 0.2 V
5 V ± 0.5 V
4.2
7.9
12.8
3.6
14.2
3.3 V ± 0.3 V
3.3 V ± 0.3 V
4.6
7.7
11.7
3.8
12.3
3.3 V ± 0.3 V
5 V ± 0.5 V
4.1
7.6
11.7
3.3
12.4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
ns
ns
ns
ns
13
!"# $ %& ' %% ' % ' SCES628A − APRIL 2005 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range (data bus I/Os)
(see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCC_S
1.8 V ± 0.15 V
D
2.5 V ± 0.2 V
SD
MASTER_EN
= ENL = ENH
= VIL
tpd
SD
3.3 V ± 0.3 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
D
3.3 V ± 0.3 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
D
ten
ENL = ENH =
VIL
MASTER_EN
3.3 V ± 0.3 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
SD
3.3 V ± 0.3 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
D
tdis
ENL = ENH =
VIL
MASTER_EN
SD
3.3 V ± 0.3 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
14
POST OFFICE BOX 655303
VCC_CF
−40°C to
85°C
TA = 25°C
TYP
3.3 V ± 0.3 V
4.2
7.2
5 V ± 0.5 V
3.7
6.4
3.3 V ± 0.3 V
3.8
5.7
8
2.4
10
5 V ± 0.5 V
3.3
4.9
6.8
2.1
12.4
3.3 V ± 0.3 V
3.5
5.1
6.9
2.2
8.8
5 V ± 0.5 V
MAX
UNIT
MIN
MIN
MAX
11.8
3
13.7
10.7
2.7
13.9
3
4.3
5.7
1.8
7
3.3 V ± 0.3 V
3.4
5.7
9.8
2.6
11.1
5 V ± 0.5 V
3.1
5.4
9.6
2.4
9.6
3.3 V ± 0.3 V
2.8
4.3
6.2
1.9
8.2
5 V ± 0.5 V
2.6
3.8
5.4
1.7
7
3.3 V ± 0.3 V
2.5
3.7
5.2
1.5
7.2
5 V ± 0.5 V
2.2
3.3
4.5
1.4
6
3.3 V ± 0.3 V
13.7
18.2
24.4
9.4
27.9
5.5 V ± 0.5 V
13.7
17.9
29.9
8
31
3.3 V ± 0.3 V
12.3
15.1
18.8
7.9
23
5.5 V ± 0.5 V
12.3
14.8
17.6
8
21.8
3.3 V ± 0.3 V
11.6
14
17.1
7.3
21.4
5.5 V ± 0.5 V
11.6
13.7
15.9
7.4
20.3
3.3 V ± 0.3 V
11.6
19.6
31.8
9.4
36.3
5.5 V ± 0.5 V
11.7
20.1
32
9.5
36.2
3.3 V ± 0.3 V
10.3
13.4
18
7.2
22.6
5.5 V ± 0.5 V
10.3
13.6
18.1
7.1
22.6
3.3 V ± 0.3 V
9.8
11.6
14
6.4
18.3
5.5 V ± 0.5 V
9.8
11.7
14
6.4
18.2
3.3 V ± 0.3 V
8.6
12.8
18.1
7.3
20.2
5.5 V ± 0.5 V
7.6
11.5
16.4
6.3
17.8
3.3 V ± 0.3 V
7.8
10.8
14.7
6.4
16.4
5.5 V ± 0.5 V
6.7
9.4
12.6
5.4
13.8
3.3 V ± 0.3 V
7.2
9.9
13.4
5.9
15
5.5 V ± 0.5 V
6.1
8.6
11.4
4.8
12.5
3.3 V ± 0.3 V
6.9
12.9
21.7
6
24.2
5.5 V ± 0.5 V
6.1
12.6
20.8
5.3
22.8
3.3 V ± 0.3 V
4.9
7.9
11.8
4.1
14.5
5.5 V ± 0.5 V
4.7
7.8
11.7
3.9
14.2
3.3 V ± 0.3 V
5
7.1
9.8
4
12
5.5 V ± 0.5 V
4.7
7
9.8
3.8
18.2
• DALLAS, TEXAS 75265
ns
ns
ns
!"# $ %& ' %% ' % ' SCES628A − APRIL 2005 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range (data bus I/Os)
(see Figure 1) (continued)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCC_S
1.8 V ± 0.15 V
2.5 V ± 0.2 V
D
ten
MASTER_EN
= VIL
ENL or ENH
3.3 V ± 0.3 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
SD
3.3 V ± 0.3 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
D
tdis
MASTER_EN
= VIL
ENL or ENH
SD
3.3 V ± 0.3 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V± 0.3 V
POST OFFICE BOX 655303
VCC_CF
−40°C to
85°C
TA = 25°C
MIN
TYP
MAX
MIN
MAX
3.3 V ± 0.3 V
9.4
17.6
23.4
8.3
27.2
5.5 V ± 0.5 V
13.5
17.4
22.6
7.7
27.8
3.3 V ± 0.3 V
12.3
15
18.5
7.9
22.8
5.5 V ± 0.5 V
12.3
14.7
17.4
8
21.6
3.3 V ± 0.3 V
11.7
14.1
17
7.3
21.4
5.5 V ± 0.5 V
11.6
13.7
16
7.4
20.3
3.3 V ± 0.3 V
9.5
18.7
30.5
9.1
35.5
5.5 V ± 0.5 V
9.6
19.1
30.5
9.1
35.6
3.3 V ± 0.3 V
10
13
17.4
6.8
22.6
5.5 V ± 0.5 V
10
13.2
17.4
6.8
22.6
3.3 V ± 0.3 V
9.6
11.3
13.6
6.2
18.3
5.5 V ± 0.5 V
9.6
11.4
13.6
6.3
18.2
3.3 V ± 0.3 V
8.5
12.1
16.8
7.2
20.2
5.5 V ± 0.5 V
7.7
10.8
15
6.3
16.6
3.3 V ± 0.3 V
7.6
10.4
13.8
6.2
16.4
5.5 V ± 0.5 V
6.9
9.1
11.9
5.4
13.1
3.3 V ± 0.3 V
7.3
9.7
12.9
5.9
15
5.5 V ± 0.5 V
6.5
8.4
11
5.2
12
3.3 V ± 0.3 V
6.5
12
20
5.7
24.2
5.5 V ± 0.5 V
5.7
11.8
19
5
22.8
3.3 V ± 0.3 V
4.6
7.4
11.1
3.8
14.5
5.5 V ± 0.5 V
4.4
7.3
11.1
3.7
14.2
3.3 V ± 0.3 V
4.9
6.8
9.3
4
12
5.5 V ± 0.5 V
4.3
6.7
9.2
3.5
18.2
• DALLAS, TEXAS 75265
UNIT
ns
ns
15
!"# $ %& ' %% ' % ' SCES628A − APRIL 2005 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range
(SA10–SA00, SCE1, SCE2, SIORD, SIOWR, SOE, SREG, SWE) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CF output
(control)
tpd
tdis
ten
tdis
16
MASTER_EN
= BUF_EN =
VIL
S input
CF output
(A pins)
ten
TEST
CONDITIONS
MASTER_EN
MASTER_EN
BUF_EN
BUF_EN
CF output
(control)
CF output
(control)
CF output
(A pins)
CF output
(A pins)
MASTER_EN
= BUF_EN =
VIL
BUF_EN = VIL
BUF_EN = VIL
MASTER_EN
= VIL
MASTER_EN
= VIL
VCC_S
VCC_CF
−40°C to
85°C
TA = 25°C
UNIT
MIN
TYP
MAX
MIN
MAX
3.4
6.1
9.8
2.5
10.4
3
5.8
9.7
2.4
10.2
1.8 V ± 0.15 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
5 V ± 0.5 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.6
4.5
6.7
1.8
8.4
2.5 V ± 0.2 V
5 V ± 0.5 V
2.4
4.1
6
1.7
6.8
3.3 V ± 0.3 V
3.3 V ± 0.3 V
2.2
3.9
5.8
1.4
7
3.3 V ± 0.3 V
5 V ± 0.5 V
2
3.5
5
1.3
5.8
1.8 V ± 0.15 V
3.3 V ± 0.3 V
3.4
5.7
8.7
2.8
10.3
1.8 V ± 0.15 V
5 V ± 0.5 V
3.3
5.4
8.2
2.8
9.7
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.9
4.3
6.2
1.9
8.4
2.5 V ± 0.2 V
5 V ± 0.5 V
2.7
3.9
5.4
1.9
6.8
3.3 V ± 0.3 V
3.3 V ± 0.3 V
2.6
3.7
5.2
1.7
7
3.3 V ± 0.3 V
5 V ± 0.5 V
2.3
3.3
4.4
1.5
5.8
1.8 V ± 0.15 V
3.3 V ± 0.3 V
10.8
17.9
24.8
7.9
29.7
1.8 V ± 0.15 V
5 V ± 0.5 V
10.8
17.5
26.2
8.1
30.2
2.5 V ± 0.2 V
3.3 V ± 0.3 V
9.4
14.2
19.4
6.4
23.3
2.5 V ± 0.2 V
5 V ± 0.5 V
9.4
14.1
19.3
6.6
23.1
3.3 V ± 0.3 V
3.3 V ± 0.3 V
8.7
13.1
17.8
5.8
21.4
3.3 V ± 0.3 V
5 V ± 0.5 V
8.7
13
17.5
6
21.2
1.8 V ± 0.15 V
3.3 V ± 0.3 V
7.3
13.8
22.5
6.2
25.8
1.8 V ± 0.15 V
5 V ± 0.5 V
6.8
12.1
19.7
5.9
26.3
2.5 V ± 0.2 V
3.3 V ± 0.3 V
6.1
11.8
19.2
4.9
20.2
2.5 V ± 0.2 V
5 V ± 0.5 V
5.9
10
16.3
4.6
19.8
3.3 V ± 0.3 V
3.3 V ± 0.3 V
5.6
11
18.3
4.6
19.1
3.3 V ± 0.3 V
5 V ± 0.5 V
5.4
9.2
15.5
3.9
18
1.8 V ± 0.15 V
3.3 V ± 0.3 V
12.9
17.5
23.7
7.7
29.7
1.8 V ± 0.15 V
5 V ± 0.5 V
13.3
17.8
24.4
9.4
30.2
2.5 V ± 0.2 V
3.3 V ± 0.3 V
11.7
14.4
17.9
7.5
23.3
2.5 V ± 0.2 V
5 V ± 0.5 V
11.8
14.3
17.1
7.7
23.1
3.3 V ± 0.3 V
3.3 V ± 0.3 V
11
13.3
16.2
6.9
21.4
3.3 V ± 0.3 V
5 V ± 0.5 V
11.1
13.2
15.3
6.5
21.2
1.8 V ± 0.15 V
3.3 V ± 0.3 V
8.9
13.6
19.7
7.5
25.8
1.8 V ± 0.15 V
5 V ± 0.5 V
7.6
11.8
17.1
6.6
26.3
2.5 V ± 0.2 V
3.3 V ± 0.3 V
8
11.6
16
6.6
20.1
2.5 V ± 0.2 V
5 V ± 0.5 V
6.7
9.7
13.2
5
19.8
3.3 V ± 0.3 V
3.3 V ± 0.3 V
7.7
10.6
14.7
6
18.2
3.3 V ± 0.3 V
5 V ± 0.5 V
6.1
8.9
11.9
4.9
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
ns
ns
ns
ns
!"# $ %& ' %% ' % ' SCES628A − APRIL 2005 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range
(SA10–SA00, SCE1, SCE2, SIORD, SIOWR, SOE, SREG, SWE) (see Figure 1) (continued)
PARAMETER
ten
tdis
ten
tdis
FROM
(INPUT)
BUF_EN
BUF_EN
BUF_EN
BUF_EN
TO
(OUTPUT)
CF output
(A pins)
CF output
(A pins)
CF output
CF output
TEST
CONDITIONS
MASTER_EN
= VIL
MASTER_EN
= VIL
MASTER_EN
= VIL
MASTER_EN
= VIL
VCC_S
MASTER_EN
DIR_OUT
BUF_EN = VIL
DIR_OUT
BUF_EN = VIL
DIR_OUT
BUF_EN = VIL
MAX
12.3
16.4
21.9
7.7
27.2
12.6
16.7
22.6
8.6
29.1
2.5 V ± 0.2 V
3.3 V ± 0.3 V
11.2
13.8
17
7.1
21.7
2.5 V ± 0.2 V
5 V ± 0.5 V
11.4
13.7
16.3
7.3
21.5
3.3 V ± 0.3 V
3.3 V ± 0.3 V
10.7
12.9
15.6
6.7
19.5
3.3 V ± 0.3 V
5 V ± 0.5 V
10.8
12.8
14.8
6.5
19.6
1.8 V ± 0.15 V
3.3 V ± 0.3 V
8.4
13.9
21.2
7.2
23.2
1.8 V ± 0.15 V
5 V ± 0.5 V
7.6
12.3
18.5
6.6
23.7
2.5 V ± 0.2 V
3.3 V ± 0.3 V
7.7
12.3
18.2
6.4
19.8
2.5 V ± 0.2 V
5 V ± 0.5 V
6.7
10.6
15.3
5
18.4
3.3 V ± 0.3 V
3.3 V ± 0.3 V
7.2
11.5
16.4
5.9
18
3.3 V ± 0.3 V
5 V ± 0.5 V
6.4
10
14.3
4.9
17
1.8 V ± 0.15 V
3.3 V ± 0.3 V
12.5
16.6
22.3
8.7
27.2
1.8 V ± 0.15 V
5 V ± 0.5 V
12.8
17
23.1
8.8
29.1
2.5 V ± 0.2 V
3.3 V ± 0.3 V
11.4
14.1
17.5
7.3
21.7
2.5 V ± 0.2 V
5 V ± 0.5 V
11.6
14
16.9
7.4
21.5
3.3 V ± 0.3 V
3.3 V ± 0.3 V
10.9
13.2
16
6.8
20
3.3 V ± 0.3 V
5 V ± 0.5 V
11
13.1
15.3
6.5
19.6
1.8 V ± 0.15 V
3.3 V ± 0.3 V
8.6
13.9
21.5
7.4
23.2
1.8 V ± 0.15 V
5 V ± 0.5 V
7.7
12.1
19.8
6.6
23.7
2.5 V ± 0.2 V
3.3 V ± 0.3 V
7.9
12.3
18.5
6.5
19.8
2.5 V ± 0.2 V
5 V ± 0.5 V
6.6
10.4
17.1
5
18.4
3.3 V ± 0.3 V
3.3 V ± 0.3 V
7.4
11.7
17.5
6.1
18.9
3.3 V ± 0.3 V
5 V ± 0.5 V
6.1
9.7
16.2
4.9
17
3.3 V ± 0.3 V
6.1
14.2
29.6
4.9
32.8
2.5 V ± 0.2 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
SIORD or
SOE
MIN
5 V ± 0.5 V
3.3 V ± 0.3 V
tpd
MAX
3.3 V ± 0.3 V
1.8 V ± 0.15 V
MASTER_EN
TYP
1.8 V ± 0.15 V
3.3 V ± 0.3 V
tdis
MIN
1.8 V ± 0.15 V
1.8 V ± 0.15 V
ten
VCC_CF
−40°C to
85°C
TA = 25°C
2.5 V ± 0.2 V
3.3 V ± 0.3 V
POST OFFICE BOX 655303
5 V ± 0.5 V
6
14.2
30
4.9
33.2
3.3 V ± 0.3 V
4.8
8.8
15.4
3.4
19.3
5 V ± 0.5 V
4.8
8.8
15.5
3.4
19.3
3.3 V ± 0.3 V
4.2
6.9
11.1
2.7
14.4
5 V ± 0.5 V
4.2
6.9
11.1
2.6
14.4
3.3 V ± 0.3 V
5.4
10
16.6
4.2
32.6
5 V ± 0.5 V
5.4
9.9
16.1
4.8
32.6
3.3 V ± 0.3 V
3.9
6.5
10.5
1.5
19.3
5 V ± 0.5 V
3.9
6.6
10.4
1.7
19.3
3.3 V ± 0.3 V
4.4
6.7
10.3
1.4
14.4
5 V ± 0.5 V
4.3
6.7
10.1
1.5
14.4
3.3 V ± 0.3 V
5
9.3
15.7
4
17.9
5 V ± 0.5 V
5
9.3
15.7
4
17.9
3.3 V ± 0.3 V
3.9
6
8.5
2.8
11
5 V ± 0.5 V
3.9
6
8.5
2.8
11
3.3 V ± 0.3 V
3.3
4.7
6.2
2.2
8.2
5 V ± 0.5 V
3.3
4.7
6.2
2.2
8.2
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
ns
17
!"# $ %& ' %% ' % ' SCES628A − APRIL 2005 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range
(SA10–SA00, SCE1, SCE2, SIORD, SIOWR, SOE, SREG, SWE) (see Figure 1) (continued)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCC_S
1.8 V ± 0.15 V
tpd
BUF_EN
DIR_OUT
BUF_EN = VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
VCC_CF
−40°C to
85°C
TA = 25°C
MIN
TYP
MAX
MIN
MAX
3.3 V ± 0.3 V
8.9
19.5
35.9
7.1
39.2
5 V ± 0.5 V
8.9
19.5
35.8
7
39.3
3.3 V ± 0.3 V
6.8
11.9
19.1
5
22.8
5 V ± 0.5 V
6.8
11.9
19.2
4.9
22.8
3.3 V ± 0.3 V
5.8
9
13.3
4
15.8
5 V ± 0.5 V
5.8
9
13.3
3.9
15.9
UNIT
ns
operating characteristics, VCCS and VCC_CF = 3.3 V, TA = 25°C
PARAMETER
Power dissipation capacitance per transceiver,
system-port input, CF-port output
CpdS
CpdCF
18
TEST CONDITIONS
Outputs enabled
TYP
1.93
Outputs disabled
0.04
CL = 0,
f = 10 MHz
Power dissipation capacitance per transceiver,
CF-port input, system-port output
Outputs enabled
Outputs disabled
0.04
Power dissipation capacitance per transceiver,
system-port input, CF-port output
Outputs enabled
22.85
Power dissipation capacitance per transceiver,
CF-port input, system-port output
Outputs enabled
POST OFFICE BOX 655303
Outputs disabled
Outputs disabled
• DALLAS, TEXAS 75265
UNIT
14.35
pF
0.04
CL = 0,
f = 10 MHz
4.66
3.65
pF
!"# $ %& ' %% ' % ' SCES628A − APRIL 2005 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
VLOAD
Open
S1
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 ± 0.2 V
2.7 V
3.3 V ± 0.3 V
5.5 V ± 0.5 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
6V
15 pF
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
0.3 V
0.5 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLZ
VLOAD/2
VM
tPZH
tPHL
VOH
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV4320AGKFR
NRND
BGA
MICROSTAR
GKF
114
1000
TBD
SNPB
Level-2-235C-1 YEAR
-40 to 85
LW320A
SN74LV4320AZKFR
NRND
LFBGA
ZKF
114
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
LW320A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV4320AGKFR
BGA MI
CROSTA
R
GKF
114
1000
330.0
24.4
5.8
16.3
1.8
8.0
24.0
Q1
SN74LV4320AZKFR
LFBGA
ZKF
114
1000
330.0
24.4
5.8
16.3
1.8
8.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV4320AGKFR
BGA MICROSTAR
GKF
114
1000
336.6
336.6
41.3
SN74LV4320AZKFR
LFBGA
ZKF
114
1000
336.6
336.6
41.3
Pack Materials-Page 2
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