Texas Instruments | SN74AUC74 (Rev. A) | Datasheet | Texas Instruments SN74AUC74 (Rev. A) Datasheet

Texas Instruments SN74AUC74 (Rev. A) Datasheet
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES483A – AUGUST 2003 – REVISED MARCH 2005
FEATURES
•
VCC
1
14
2
13 2CLR
3
4
12 2D
5
10 2PRE
9 2Q
11 2CLK
6
7
8
2Q
•
•
•
•
•
1D
1CLK
1PRE
1Q
1Q
1CLR
•
RGY PACKAGE
(TOP VIEW)
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.8 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
GND
•
DESCRIPTION/ORDERING INFORMATION
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically
for 1.65-V to 1.95-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
QFN – RGY
ORDERABLE PART NUMBER
Tape and reel
SN74AUC74RGYR
TOP-SIDE MARKING
MS74
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
X
L
X
X
L
H
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES483A – AUGUST 2003 – REVISED MARCH 2005
LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC)
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
3.6
V
VI
Input voltage range (2)
–0.5
3.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
3.6
V
VO
Output voltage range (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
±100
Continuous current through VCC or GND
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
2
–65
mA
47
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-5.
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES483A – AUGUST 2003 – REVISED MARCH 2005
Recommended Operating Conditions
VCC
(1)
MIN
MAX
0.8
2.7
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
UNIT
V
VCC
VCC = 1.1 V to 1.95 V
0.65 × VCC
VCC = 2.3 V to 2.7 V
V
1.7
VCC = 0.8 V
0
0.35 × VCC
VIL
Low-level input voltage
VCC = 1.1 V to 1.95 V
VI
Input voltage
0
3.6
V
VO
Output voltage
0
VCC
V
VCC = 2.3 V to 2.7 V
IOH
High-level output current
IOL
Low-level output current
0.7
VCC = 0.8 V
–0.7
VCC = 1.1 V
–3
VCC = 1.4 V
–5
VCC = 1.65 V
–8
VCC = 2.3 V
–9
VCC = 0.8 V
0.7
VCC = 1.1 V
3
VCC = 1.4 V
5
VCC = 1.65 V
8
VCC = 2.3 V
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
mA
mA
9
–40
20
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VCC
MIN
TYP (1) MAX
IOH = –100 µA
0.8 V to 2.7 V
IOH = –0.7 mA
0.8 V
IOH = –3 mA
1.1 V
0.8
IOH = –5 mA
1.4 V
1
IOH = –8 mA
1.65 V
1.2
IOH = –9 mA
2.3 V
1.8
IOL = 100 µA
0.8 V to 2.7 V
IOL = 0.7 mA
0.8 V
IOL = 3 mA
1.1 V
0.3
IOL = 5 mA
1.4 V
0.4
IOL = 8 mA
1.65 V
0.45
2.3 V
0.6
IOL = 9 mA
UNIT
VCC – 0.1
0.55
V
0.2
0.25
V
II
VI = VCC or GND
0 to 2.7 V
±5
µA
Ioff
VI or VO = 2.7 V
0
±10
µA
10
µA
ICC
Ci
(1)
VI = VCC or GND,
IO = 0
0.8 V to 2.7 V
D inputs
VI = VCC or GND
2.5 V
2
Control inputs
VI = VCC or GND
2.5 V
2.5
pF
All typical values are at TA = 25°C.
3
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES483A – AUGUST 2003 – REVISED MARCH 2005
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
TYP
fclock
tw
tsu
th
Clock frequency
Pulse duration
VCC = 1.5 V
± 0.1 V
MIN MAX
100
VCC = 1.8 V
± 0.15 V
MIN MAX
225
MIN
VCC = 2.5 V
± 0.2 V
MAX
250
300
350
CLK high or low
4.6
1.3
0.6
0.5
0.5
CLR low
6.6
2
1.5
1.5
1.5
PRE low
4.8
1.8
1.5
1.5
1.5
Data
2.3
1
0.6
0.6
0.7
0
0
0
0
0.3
0
0
0
0.2
0.3
0.3
0.3
0.3
0.3
Setup time before
CLR inactive
CLK↑
PRE inactive
Hold time, data after CLK↑
2.1
UNIT
MIN MAX
MHz
ns
ns
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
fmax
CLK
tpd
CLR
Q or Q
PRE
VCC = 1.2 V
± 0.1 V
MAX
VCC = 1.5 V
± 0.1 V
TYP
MIN
MIN
MAX
100
225
9.5
1.3
4
0.7
2.5
10.5
1.5
4.1
1.1
12
1.6
4.7
1.1
VCC = 1.8 V
± 0.15 V
TYP
MAX
0.5
1.2
2.1
0.5
1.4
2.9
0.9
1.4
2.4
0.7
1.6
2.8
0.9
1.4
2.4
0.7
1.6
250
MIN
VCC = 2.5 V
± 0.2 V
300
MIN
UNIT
MAX
350
MHz
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
MIN
fmax
TYP MAX
300
CLK
tpd
VCC = 2.5 V
± 0.2 V
CLR
Q or Q
PRE
UNIT
MIN MAX
350
MHz
1.2
1.9
2.8
1
2.2
1.3
2.1
3
1.1
2.4
1.3
2.1
3.1
1.1
2.5
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
4
Power dissipation
capacitance
TEST
CONDITIONS
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
f = 10 MHz
36
36
36
37
41
UNIT
pF
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCES483A – AUGUST 2003 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
LOAD CIRCUIT
VCC
CL
RL
V∆
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
th
VCC
VCC/2
Input
VCC/2
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74AUC74RGYR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGY
14
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
MS74
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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