Texas Instruments | CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 (Rev. I) | Datasheet | Texas Instruments CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 (Rev. I) Datasheet

Texas Instruments CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 (Rev. I) Datasheet
[ /Title
(CD74H
C4049,
CD74H
C4050)
/Subject
(High
Speed
CMOS
Logic
Hex
CD54HC4049, CD74HC4049,
CD54HC4050, CD74HC4050
Data sheet acquired from Harris Semiconductor
SCHS205I
High-Speed CMOS Logic
Hex Buffers, Inverting and Non-Inverting
February 1998 - Revised February 2005
Features
Description
• Typical Propagation Delay: 6ns at VCC = 5V,
CL = 15pF, TA = 25oC
The ’HC4049 and ’HC4050 are fabricated with high-speed
silicon gate technology. They have a modified input
protection structure that enables these parts to be usedas
logic level translators which convert high-level logic to a lowlevel logic while operating off the low-level logic supply. For
example, 15-V input pulse levels can be down-converted to
0-V to 5-V logic levels. The modified input protection
structure protects the input from negative electrostatic
discharge. These parts also can be used as simple buffers
or inverters without level translation. The ’HC4049 and
’HC4050 are enhanced versions of equivalent CMOS types.
• High-to-Low Voltage Level Converter for up to Vl = 16V
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . .–55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
PART NUMBER
Pinout
CD54HC4049, CD54HC4050
(CERDIP)
CD74HC4049, CD74HC4050
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
4050
4049
TEMP. RANGE
(oC)
PACKAGE
CD54HC4049F3A
–55 to 125
16 Ld CERDIP
CD54HC4050F3A
–55 to 125
16 Ld CERDIP
CD74HC4049E
–55 to 125
16 Ld PDIP
CD74HC4049M
–55 to 125
16 Ld SOIC
CD74HCT4050MT
–55 to 125
16 Ld SOIC
CD74HC4049M96
–55 to 125
16 Ld SOIC
CD74HC4049NSR
–55 to 125
16 Ld SOP
CD74HC4049PW
–55 to 125
16 Ld TSSOP
4049
4050
VCC
VCC 1
16 NC
NC
1Y
1Y 2
15 6Y
6Y
1A
1A 3
14 6A
6A
CD74HC4049PWR
–55 to 125
16 Ld TSSOP
CD74HC4049PWT
–55 to 125
16 Ld TSSOP
CD74HC4050E
–55 to 125
16 Ld PDIP
CD74HC4050M
–55 to 125
16 Ld SOIC
CD74HC4050MT
–55 to 125
16 Ld SOIC
CD74HC4050M96
–55 to 125
16 Ld SOIC
CD74HC4050NSR
–55 to 125
16 Ld SOP
CD74HC4050PW
–55 to 125
16 Ld TSSOP
CD74HC4050PWR
–55 to 125
16 Ld TSSOP
CD74HC4050PWT
–55 to 125
16 Ld TSSOP
2Y
2Y 4
13 NC
NC
2A
2A 5
12 5Y
5Y
3Y
3Y 6
11 5A
5A
3A
3A 7
10 4Y
4Y
GND
GND 8
9 4A
4A
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2005,Texas Instruments Incorporated
1
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050
Functional Diagram
4050
4049
16
1
VCC
2
15
6Y
3
6A
4
13
2Y
NC
5
NC
12
2A
5Y
6
3Y
6Y
14
1A
2Y
4050
NC
1Y
1Y
4049
11
3Y
5A
7
5Y
10
3A
4Y
8
9
4A
GND
Logic Diagrams
HC4049
A
HC4050
A
Y
2
Y
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 16V
DC Input Diode Current, IIK
For VI < –0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20mA
DC Output Diode Current, IOK
For VO < –0.5V or VO > VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > –0.5V or VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Package Thermal Impedance, θJA (see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . –65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
VCC
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .–55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 15V
DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
VOLTAGE
RELATIONSHIPS
MAXIMUM LIMITS
Vl
+7V
+16V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
25oC
–40oC TO 85oC
–55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
High Level Input
Voltage
VIH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
PARAMETER
HC TYPES
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
-
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
–0.02
2
1.9
-
-
1.9
-
1.9
-
V
–0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
–0.02
6
5.9
-
-
5.9
-
5.9
-
V
–4
4.5
3.98
-
-
3.84
-
3.7
-
V
–5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
15
-
6
-
-
±0.5
-
±5
-
±5
3
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Quiescent Device
Current
25oC
–40oC TO 85oC
–55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
ICC
VCC or
GND
0
6
-
-
2
-
20
-
40
µA
Switching Specifications Input tr, tf = 6ns
PARAMETER
HC TYPES
Propagation Delay,
nA to nY HC4049
nA to nY HC4050
Transition Times (Figure 1)
Input Capacitance
Power Dissipation Capacitance
(Notes 2, 3)
–40oC TO
85oC
25oC
–55oC TO
125oC
SYMBOL
TEST
CONDITIONS
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tPLH, tPHL
CL = 50pF
2
-
-
85
-
105
-
130
ns
tTLH, tTHL
4.5
-
-
17
-
21
-
26
ns
6
-
-
14
-
18
-
22
ns
CL = 15pF
5
-
6
-
-
-
-
-
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
35
-
-
-
-
-
pF
NOTES:
2. CPD is used to determine the dynamic power consumption, per gate.
3. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuit and Waveform
tr = 6ns
tf = 6ns
VCC
90%
50%
10%
INPUT
GND
tTHL
tTLH
90%
50%
10%
INVERTING
OUTPUT
tPLH
tPHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
4
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-8681901EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8681901EA
CD54HC4049F3A
5962-8682001EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8682001EA
CD54HC4050F3A
CD54HC4049F3A
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8681901EA
CD54HC4049F3A
CD54HC4050F3A
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8682001EA
CD54HC4050F3A
CD74HC4049E
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4049E
CD74HC4049EE4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4049E
CD74HC4049M
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4049M
CD74HC4049M96
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4049M
CD74HC4049M96E4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4049M
CD74HC4049M96G4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4049M
CD74HC4049MT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4049M
CD74HC4049NS
ACTIVE
SO
NS
16
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4049M
CD74HC4049NSRE4
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4049M
CD74HC4049PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4049
CD74HC4049PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4049
CD74HC4050E
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4050E
Addendum-Page 1
HC4049M
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
26-Sep-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD74HC4050EE4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4050E
CD74HC4050M
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4050M
CD74HC4050M96
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4050M
CD74HC4050ME4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4050M
CD74HC4050MT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4050M
CD74HC4050NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4050M
CD74HC4050PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4050
CD74HC4050PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4050
CD74HC4050PWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4050
CD74HC4050PWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4050
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
26-Sep-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4049, CD54HC4050, CD74HC4049, CD74HC4050 :
• Catalog: CD74HC4049, CD74HC4050
• Military: CD54HC4049, CD54HC4050
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CD74HC4049M96
Package Package Pins
Type Drawing
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD74HC4049NSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
CD74HC4049PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD74HC4050M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD74HC4050NSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
CD74HC4050PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD74HC4050PWT
TSSOP
PW
16
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC4049M96
SOIC
D
16
2500
333.2
345.9
28.6
CD74HC4049NSR
SO
NS
16
2000
367.0
367.0
38.0
CD74HC4049PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
CD74HC4050M96
SOIC
D
16
2500
333.2
345.9
28.6
CD74HC4050NSR
SO
NS
16
2000
367.0
367.0
38.0
CD74HC4050PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
CD74HC4050PWT
TSSOP
PW
16
250
367.0
367.0
35.0
Pack Materials-Page 2
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