Texas Instruments | CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54 (Rev. E) | Datasheet | Texas Instruments CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54 (Rev. E) Datasheet

Texas Instruments CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54 (Rev. E) Datasheet
[ /Title
(CD74
HC240
,
CD74
HCT24
0,
CD74
HC241
,
CD74
HCT24
1,
CD74
HC244
,
CD74
Data sheet acquired from Harris Semiconductor
SCHS167E
CD54/74HC240, CD54/74HCT240,
CD74HC241, CD54/74HCT241,
CD54/74HC244, CD54/74HCT244
High-Speed CMOS Logic
Octal Buffer/Line Drivers, Three-State
November 1997 - Revised October 2004
Features
Ordering Information
• HC/HCT240 Inverting
PART NUMBER
• HC/HCT241 Non-Inverting
TEMP. RANGE
(oC)
PACKAGE
• HC/HCT244 Non-Inverting
CD54HC240F3A
-55 to 125
20 Ld CERDIP
• Typical Propagation Delay = 8ns at VCC = 5V,
CL = 15pF, TA = 25oC for HC240
CD54HC244F3A
-55 to 125
20 Ld CERDIP
• Three-State Outputs
CD54HCT240F3A
-55 to 125
20 Ld CERDIP
• Buffered Inputs
CD54HCT241F3A
-55 to 125
20 Ld CERDIP
• High-Current Bus Driver Outputs
CD54HCT244F3A
-55 to 125
20 Ld CERDIP
CD74HC240E
-55 to 125
20 Ld PDIP
CD74HC240M
-55 to 125
20 Ld SOIC
• Wide Operating Temperature Range . . . -55oC to 125oC
CD74HC240M96
-55 to 125
20 Ld SOIC
• Balanced Propagation Delay and Transition Times
CD74HC241E
-55 to 125
20 Ld PDIP
• Significant Power Reduction Compared to LSTTL
Logic ICs
CD74HC241M
-55 to 125
20 Ld SOIC
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
CD74HC241M96
-55 to 125
20 Ld SOIC
CD74HC244E
-55 to 125
20 Ld PDIP
CD74HC244M
-55 to 125
20 Ld SOIC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HC244M96
-55 to 125
20 Ld SOIC
CD74HCT240E
-55 to 125
20 Ld PDIP
CD74HCT240M
-55 to 125
20 Ld SOIC
CD74HCT240M96
-55 to 125
20 Ld SOIC
Description
CD74HCT240PW
-55 to 125
20 Ld TSSOP
The ’HC240 and ’HCT240 are inverting three-state buffers
having two active-low output enables. The CD74HC241,
’HCT241, ’HC244 and ’HCT244 are non-inverting threestate buffers that differ only in that the 241 has one activehigh and one active-low output enable, and the 244 has two
active-low output enables. All three types have identical
pinouts.
CD74HCT240PWR
-55 to 125
20 Ld TSSOP
CD74HCT240PWT
-55 to 125
20 Ld TSSOP
CD74HCT241E
-55 to 125
20 Ld PDIP
CD74HCT241M
-55 to 125
20 Ld SOIC
CD74HCT241M96
-55 to 125
20 Ld SOIC
CD74HCT244E
-55 to 125
20 Ld PDIP
CD74HCT244M
-55 to 125
20 Ld SOIC
CD74HCT244M96
-55 to 125
20 Ld SOIC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
1
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
Pinout
CD54HC240, CD54HCT240, CD54HCT241,
CD54HC244, CD54HCT244
(CERDIP)
CD74HC240, CD74HC241, CD74HCT241,
CD74HC244, CD74HCT244
(PDIP, SOIC)
CD74HCT240,
(PDIP, SOIC, TSSOP)
TOP VIEW
240
241
244
1OE
1OE
1
1A0
1A0
2
19 2OE (241) 2OE (240, 244)
2Y3
2Y3
3
18 1Y0
1Y0
1A1
1A1
4
17 2A3
2A3
2Y2
2Y2
5
16 1Y1
1Y1
1A2
1A2
6
15 2A2
2A2
2Y1
2Y1
7
14 1Y2
1Y2
1A3
1A3
8
13 2A1
2A1
2Y0
2Y0
9
12 1Y3
1Y3
GND 10
11 2A0
2A0
GND
241
244
20 VCC
240
VCC
Functional Diagram
241
AND
244 240
2
18
4
16
6
14
8
12
11
9
13
7
15
5
240
17
AND 2A3
244 241
3
1A0
1A1
1A2
1A3
2A0
2A1
2A2
1
1OE 1OE
2OE 2OE
19
2
1Y0
1Y0
1Y1
1Y1
1Y2
1Y2
1Y3
1Y3
2Y0
2Y0
2Y1
2Y1
2Y2
2Y2
2Y3
2Y3
VCC = 20
GND = 10
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA
Thermal Resistance (Typical, Note 1)
θJA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . .
69oC/W
M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . .
58oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . .
83oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance wIth JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
3
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
25oC
-55oC TO 125oC
SYMBOL
VI (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
IOZ
VIL or
VIH
-
6
-
-
±0.5
-
±0.5
-
±10
µA
High Level Input
Voltage
VIH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
VOH
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
PARAMETER
Three-State Leakage
Current
IO (mA) VCC (V)
-40oC TO 85oC
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
II
VCC to
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 2)
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Three-State Leakage
Current
IOZ
VIL or
VIH
-
5.5
-
-
±0.5
-
±5
-
±10
µA
Input Leakage
Current
Quiescent Device
Current
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
nA0-A3
1.5
1OE
0.7
2OE
0.7
nA0-A3
0.7
1OE
0.7
2OE
1.5
nA0-A3
0.7
1OE
0.7
2OE
0.7
HCT240
HCT241
HCT244
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.
4
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
Switching Specifications
PARAMETER
CL = 50pF, Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC
-55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
2
-
-
100
-
-
125
-
-
150
ns
4.5
-
-
20
-
-
25
-
-
30
ns
CL = 15pF
5
-
8
-
-
-
-
-
-
-
ns
CL = 50pF
6
-
-
17
-
-
21
-
-
26
ns
CL = 50pF
2
-
-
110
-
-
140
-
-
165
ns
4.5
-
-
22
-
-
28
-
-
33
ns
CL = 15pF
5
-
9
-
-
-
-
-
-
-
ns
CL = 50pF
6
-
-
19
-
-
24
-
-
28
ns
CL = 50pF
2
-
-
110
-
-
140
-
-
165
ns
4.5
-
-
22
-
-
28
-
-
33
ns
CL = 15pF
5
-
9
-
-
-
-
-
-
-
ns
CL = 50pF
6
-
-
19
-
-
24
-
-
28
ns
CL = 50pF
2
-
-
150
-
-
190
-
-
225
ns
4.5
-
-
30
-
-
38
-
-
45
ns
5
-
12
-
-
-
-
-
-
-
ns
6
-
-
26
-
-
33
-
-
38
ns
2
-
-
60
-
-
75
-
-
90
ns
4.5
-
-
12
-
-
15
-
-
18
ns
6
-
-
10
-
-
13
-
-
15
ns
MAX UNITS
HC TYPES
Propagation Delay
Data to Outputs
HC240
Data to Outputs
HC241
Data to Outputs
HC244
Output Enable and Disable
Time
Output Transition Time
tPLH, tPHL
tPLH, tPHL
tTHL, tTLH
tTLH, tTHL
CL = 50pF
Input Capacitance
CI
CL = 50pF
-
10
-
10
-
-
10
-
-
10
pF
Three-State Output
Capacitance
CO
CL = 50pF
-
-
-
20
-
-
20
-
-
20
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
CL = 15pF
HC240
5
-
38
-
-
-
-
-
-
-
pF
HC241
5
-
34
-
-
-
-
-
-
-
pF
HC244
5
-
46
-
-
-
-
-
-
-
pF
CL = 50pF
4.5
-
-
22
-
-
28
-
-
33
ns
CL = 15pF
5
-
9
-
-
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
25
-
-
31
-
-
38
ns
CL = 15pF
5
-
10
-
-
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
25
-
-
31
-
-
38
ns
CL = 15pF
5
-
10
-
-
-
-
-
-
-
ns
HCT TYPES
Propagation Delay
Data to Outputs
HCT240
tPHL, tPLH
Data to Outputs
HCT241
tPHL, tPLH
Data to Outputs
HCT244
tPHL, tPLH
5
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
Switching Specifications
CL = 50pF, Input tr, tf = 6ns (Continued)
25oC
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
Output Enable and Disable
Times
tTLH, tTHL
CL = 50pF
4.5
-
-
30
-
-
38
-
-
45
ns
Output Transition Time
tTHL, tTLH
CL = 50pF
4.5
-
-
12
-
-
15
-
-
18
ns
CI
CL = 50pF
-
10
-
10
-
-
10
-
-
10
pF
HCT240
-
5
-
40
-
-
-
-
-
-
-
pF
HCT241
-
5
-
38
-
-
-
-
-
-
-
pF
HCT244
-
5
-
40
-
-
-
-
-
-
-
pF
PARAMETER
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
MAX UNITS
CPD
NOTES:
3. CPD is used to determine the dynamic power consumption, per channel.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
VCC
90%
50%
10%
INPUT
GND
tTLH
90%
INVERTING
OUTPUT
tPHL
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
tr
VCC
10%
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
0.3
GND
1.3V
10%
OUTPUT HIGH
TO OFF
50%
3V
tPZL
tPHZ
tPZH
90%
6ns
2.7
1.3
tPLZ
10%
tPHZ
tf
GND
50%
OUTPUT HIGH
TO OFF
6ns
OUTPUT
DISABLE
tPZL
tPLZ
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
90%
50%
tTLH
1.3V
10%
tPLH
tPHL
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
OUTPUT
DISABLE
tf = 6ns
tr = 6ns
90%
tPZH
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
6
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
Test Circuits and Waveforms
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
(Continued)
IC WITH
THREESTATE
OUTPUT
OUTPUT
RL = 1kΩ
CL
50pF
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
7
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD54HC240F3A
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8407401RA
CD54HC240F3A
CD54HC244F
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD54HC244F
CD54HC244F3A
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409601RA
CD54HC244F3A
CD54HCT240F3A
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8550501RA
CD54HCT240F3A
CD54HCT241F3A
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD54HCT241F3A
CD54HCT244F
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD54HCT244F
CD54HCT244F3A
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8513001RA
CD54HCT244F3A
CD74HC240E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC240E
CD74HC240M
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC240M
CD74HC240M96
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC240M
CD74HC241E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC241E
CD74HC241M
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC241M
CD74HC241M96
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC241M
CD74HC241M96E4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC241M
CD74HC241MG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC241M
CD74HC244E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC244E
CD74HC244EE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC244E
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD74HC244M
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC244M
CD74HC244M96
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC244M
CD74HC244M96E4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC244M
CD74HC244M96G4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC244M
CD74HCT240E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT240E
CD74HCT240EE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT240E
CD74HCT240M
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT240M
CD74HCT240M96
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT240M
CD74HCT240MG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT240M
CD74HCT240PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HK240
CD74HCT240PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HK240
CD74HCT240PWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HK240
CD74HCT241E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT241E
CD74HCT241EE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT241E
CD74HCT241M
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT241M
CD74HCT241M96
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT241M
CD74HCT244E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT244E
CD74HCT244M
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT244M
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD74HCT244M96
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT244M
CD74HCT244ME4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT244M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC240, CD54HC244, CD54HCT240, CD54HCT241, CD54HCT244, CD74HC240, CD74HC244, CD74HCT240, CD74HCT241,
CD74HCT244 :
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
• Catalog: CD74HC240, CD74HC244, CD74HCT240, CD74HCT241, CD74HCT244
• Military: CD54HC240, CD54HC244, CD54HCT240, CD54HCT241, CD54HCT244
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC240M96
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
CD74HC241M96
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
CD74HC244M96
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
CD74HCT240M96
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
CD74HCT240PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
CD74HCT240PWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
CD74HCT241M96
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
CD74HCT244M96
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC240M96
SOIC
DW
20
2000
367.0
367.0
45.0
CD74HC241M96
SOIC
DW
20
2000
367.0
367.0
45.0
CD74HC244M96
SOIC
DW
20
2000
367.0
367.0
45.0
CD74HCT240M96
SOIC
DW
20
2000
367.0
367.0
45.0
CD74HCT240PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
CD74HCT240PWT
TSSOP
PW
20
250
367.0
367.0
38.0
CD74HCT241M96
SOIC
DW
20
2000
367.0
367.0
45.0
CD74HCT244M96
SOIC
DW
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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