Texas Instruments | SN74ALVC16834 (Rev. I) | Datasheet | Texas Instruments SN74ALVC16834 (Rev. I) Datasheet

Texas Instruments SN74ALVC16834 (Rev. I) Datasheet
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES140I – JULY 1998 – REVISED OCTOBER 2004
FEATURES
•
•
•
•
•
•
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Max tpd of 3.6 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
DESCRIPTION/ORDERING INFORMATION
This 18-bit universal bus driver is designed for 1.65-V
to 3.6-V VCC operation.
Data flow from A to Y is controlled by the
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
low. The A data is latched if the clock (CLK) input is
held at a high or low logic level. If LE is high, the A
data is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is high, the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
NC − No internal connection
ORDERING INFORMATION
PACKAGE (1)
TA
Tape and reel
SN74ALVC16834DLR
TSSOP - DGG
Tape and reel
SN74ALVC16834DGGR
ALVC16834
TVSOP - DGV
Tape and reel
SN74ALVC16834DGVR
VC834
VFBGA - GQL
VFBGA - ZQL (Pb-free)
(1)
TOP-SIDE MARKING
SN74ALVC16834DL
SSOP - DL
-40°C to 85°C
ORDERABLE PART NUMBER
Tube
Tape and reel
SN74ALVC16834GQLR
SN74ALVC16834ZQLR
ALVC16834
VC834
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2004, Texas Instruments Incorporated
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES140I – JULY 1998 – REVISED OCTOBER 2004
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
TERMINAL ASSIGNMENTS(1)
6
3
4
5
6
NC
NC
GND
NC
A1
Y2
GND
GND
A2
A3
Y5
Y4
VCC
VCC
A4
A5
D
Y7
Y6
GND
GND
A6
A7
E
Y9
Y8
A8
A9
F
F
Y10
Y11
A11
A10
G
G
Y12
Y13
GND
GND
A13
A12
H
H
Y14
Y15
VCC
VCC
A15
A14
J
J
Y16
Y17
GND
GND
A17
A16
K
Y18
OE
LE
GND
CLK
A18
A
1
2
A
Y1
B
Y3
C
B
C
D
E
K
(1) NC − No internal connection
FUNCTION TABLE
INPUTS
(1)
(2)
OE
LE
CLK
A
OUTPUT
Y
H
X
X
X
Z
L
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
L
H
H
X
Y0 (1)
L
H
L
X
Y0 (2)
Output level before the indicated steady-state input conditions were
established, provided that CLK is high before LE goes high
Output level before the indicated steady-state input conditions were
established
LOGIC DIAGRAM (POSITIVE LOGIC)
OE
CLK
LE
A1
27
30
28
54
1D
C1
CLK
To 17 Other Channels
Pin numbers shown are for the DGG, DGV, and DL packages.
2
3
Y1
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES140I – JULY 1998 – REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
-0.5
4.6
V
VI
Input voltage range (2)
-0.5
4.6
V
VO
Output voltage range (2) (3)
-0.5
VCC + 0.5
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
mA
-50
mA
±50
mA
±100
mA
DGG package
64
DGV package
48
DL package
56
GQL/ZQL package
V
-50
°C/W
42
-65
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
VI
Input voltage
0
3.6
V
VO
Output voltage
0
VCC
V
VCC = 2.7 V to 3.6 V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0.8
VCC = 1.65 V
-4
VCC = 2.3 V
-12
VCC = 2.7 V
-12
VCC = 3 V
-24
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
-40
mA
mA
10
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES140I – JULY 1998 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
1.65 V to 3.6 V
1.65 V
IOH = -6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = -24 mA
3V
2
IOL = 100 µA
IOH = -12 mA
0.2
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
II
VI = VCC or GND
IOZ
VO = VCC or GND
ICC
VI = VCC or GND,
∆ICC
One input at VCC - 0.6 V, Other inputs at VCC or GND
Control inputs
Data inputs
Co
(1)
Outputs
V
1.65 V to 3.6 V
IOL = 24 mA
UNIT
1.2
IOL = 4 mA
IOL = 12 mA
Ci
MAX
VCC - 0.2
IOH = -4 mA
VOH
VOL
MIN TYP (1)
VCC
2.7 V
0.4
3V
0.55
V
3.6 V
±5
µA
3.6 V
±10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
IO = 0
VI = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
4
pF
5.5
7
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
MIN
fclock
tw
tsu
th
(1)
4
Setup time
Hold time
MIN
(1)
Clock frequency
Pulse duration
MAX
VCC = 2.5 V
± 0.2 V
MAX
VCC = 2.7 V
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
150
LE low
(1)
3.3
3.3
3.3
CLK high or low
(1)
3.3
3.3
3.3
Data before CLK↑
(1)
2.1
2.1
1.7
CLK high
(1)
2.2
2.3
1.9
CLK low
(1)
1.5
1.9
1.5
(1)
0.6
0.6
0.7
(1)
0.8
0.8
0.9
Data before LE↑
Data after CLK↑
Data after LE↑
CLK high or low
This information was not available at the time of publication.
UNIT
MAX
MHz
ns
ns
ns
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES140I – JULY 1998 – REVISED OCTOBER 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
MIN
TYP
(1)
fmax
tpd
LE
tdis
OE
MIN
150
MAX
150
MIN
UNIT
MAX
150
MHz
4.4
4.2
1
3.6
(1)
1.3
6
5.9
1.5
4.9
(1)
1.2
6
5.3
1.5
4.6
Y
(1)
1.4
5.6
5.6
1.5
5
ns
Y
(1)
1
4
4.7
1.8
4.5
ns
Y
OE
MAX
VCC = 3.3 V
± 0.3 V
1
CLK
ten
MIN
VCC = 2.7 V
(1)
A
(1)
VCC = 2.5 V
± 0.2 V
VCC = 1.8 V
ns
This information was not available at the time of publication.
SWITCHING CHARACTERISTICS
from 0°C to 65°C, CL = 50 pF
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
CLK
Y
VCC = 3.3 V
± 0.15 V
MIN
MAX
1.7
4.3
UNIT
ns
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
(1)
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
f = 10 MHz
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP
TYP
TYP
(1)
38
41
(1)
13
15
UNIT
pF
This information was not available at the time of publication.
5
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES140I – JULY 1998 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74ALVC16834ZQLR
NRND
Package Type Package Pins Package
Drawing
Qty
BGA
MICROSTAR
JUNIOR
ZQL
56
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
VC834
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74ALVC16834ZQLR
Package Package Pins
Type Drawing
BGA MI
CROSTA
R JUNI
OR
ZQL
56
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
4.8
B0
(mm)
K0
(mm)
P1
(mm)
7.3
1.5
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ALVC16834ZQLR
BGA MICROSTAR
JUNIOR
ZQL
56
1000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
ZQL0056A
JRBGA - 1 mm max height
SCALE 2.100
PLASTIC BALL GRID ARRAY
4.6
4.4
B
A
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.35
TYP
0.15
BALL TYP
0.1 C
3.25 TYP
(0.625) TYP
SYMM
K
(0.575) TYP
J
H
G
5.85
TYP
SYMM
F
E
D
C
56X
NOTE 3
B
A
0.65 TYP
BALL A1 CORNER
1
2
3
4
5
0.45
0.35
0.15
0.08
C B A
C
6
0.65 TYP
4219711/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. No metal in this area, indicates orientation.
www.ti.com
EXAMPLE BOARD LAYOUT
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
56X ( 0.33)
2
1
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
( 0.33)
METAL
( 0.33)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219711/B 01/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
56X ( 0.33)
(0.65) TYP
1
2
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4219711/B 01/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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