Texas Instruments | SN74ALVCH32245 (Rev. D) | Datasheet | Texas Instruments SN74ALVCH32245 (Rev. D) Datasheet

Texas Instruments SN74ALVCH32245 (Rev. D) Datasheet
SN74ALVCH32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES282D – OCTOBER 1999 – REVISED SEPTEMBER 2004
•
FEATURES
•
•
•
•
•
Member of the Texas Instruments Widebus+™
Family
Operates From 1.65 V to 3.6 V
Max tpd of 3 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 32-bit noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH32245 is designed for asynchronous communication between data buses. The control-function
implementation minimizes external timing requirements.
This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows
data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses
effectively are isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
PACKAGE (1)
TA
-40°C to 85°C
(1)
LFBGA - GKE
LFBGA - ZKE (Pb-free)
ORDERABLE PART NUMBER
Tape and reel
SN74ALVCH32245KR
74ALVCH32245ZKER
TOP-SIDE MARKING
ACH245
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2004, Texas Instruments Incorporated
SN74ALVCH32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES282D – OCTOBER 1999 – REVISED SEPTEMBER 2004
TERMINAL ASSIGNMENTS
GKE OR ZKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
1
2
3
4
5
6
A
1B2
1B1
1DIR
1OE
1A1
1A2
B
1B4
1B3
GND
GND
1A3
1A4
C
1B6
1B5
VCC
VCC
1A5
1A6
B
D
1B8
1B7
GND
GND
1A7
1A8
C
E
2B2
2B1
GND
GND
2A1
2A2
D
F
2B4
2B3
VCC
VCC
2A3
2A4
E
G
2B6
2B5
GND
GND
2A5
2A6
F
H
2B7
2B8
2DIR
2OE
2A8
2A7
G
J
3B2
3B1
3DIR
3OE
3A1
3A2
K
3B4
3B3
GND
GND
3A3
3A4
L
3B6
3B5
VCC
VCC
3A5
3A6
M
3B8
3B7
GND
GND
3A7
3A8
N
4B2
4B1
GND
GND
4A1
4A2
P
4B4
4B3
VCC
VCC
4A3
4A4
R
4B6
4B5
GND
GND
4A5
4A6
T
4B7
4B8
4DIR
4OE
4A8
4A7
H
J
K
L
M
N
P
R
T
LOGIC DIAGRAM (POSITIVE LOGIC)
1DIR
A3
2DIR
A4
1A1
H4
1OE
A5
2A1
A2
H3
E5
E2
1B1
To Seven Other Channels
3DIR
J3
4DIR
2
T4
4A1
J2
T3
3OE
J5
To Seven Other Channels
2B1
To Seven Other Channels
J4
3A1
2OE
4OE
N5
N2
3B1
To Seven Other Channels
4B1
SN74ALVCH32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES282D – OCTOBER 1999 – REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
MIN
MAX
-0.5
4.6
Except I/O ports (2)
-0.5
4.6
I/O ports (2) (3)
-0.5
VCC + 0.5
-0.5
VCC + 0.5
UNIT
V
VI
Input voltage range
VO
Output voltage range
IIK
Input clamp current
VI < 0
-50
mA
IOK
Output clamp current
VO < 0
-50
mA
IO
Continuous output current
±50
mA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
V
±100
Continuous current through each VCC or GND
θJA
V
GKE/ZKE package
-65
mA
40
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Low-level input voltage
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
-4
VCC = 2.3 V
-8
VCC = 2.7 V
-12
VCC = 3 V
-24
VCC = 1.65 V
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
-40
mA
mA
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74ALVCH32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES282D – OCTOBER 1999 – REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
VOH
1.65 V to 3.6 V
1.65 V
1.2
IOH = -8 mA
2.3 V
1.7
2.7 V
2.2
II(hold)
V
3V
2.4
IOH = -24 mA
3V
2.2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
3V
0.55
IOL = 24 mA
II
±5
VI = VCC or GND
3.6 V
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
-25
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
VI = 0.8 V
3V
75
3V
-75
VI = 2 V
UNIT
VCC - 0.2
IOH = -4 mA
IOH = -12 mA
VOL
MIN TYP (1) MAX
VCC
V
µA
µA
VI = 0 to 3.6 V (2)
3.6 V
±500
IOZ (3)
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND,
IO = 0
3.6 V
80
µA
∆ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V
750
µA
Ci
Control inputs
VI = VCC or GND
3.3 V
4
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
8
pF
(1)
(2)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
(3)
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A or B
tpd
(1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
B or A
(1)
(1)
1
(1)
1
(1)
1
ten
OE
A or B
(1)
tdis
OE
A or B
(1)
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
3.7
3.6
1
3
ns
5.7
5.4
1
4.4
ns
5.2
4.6
1
4.1
ns
This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
(1)
4
Power dissipation
capacitance
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF,
This information was not available at the time of publication.
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
22
29
(1)
4
5
UNIT
pF
SN74ALVCH32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES282D – OCTOBER 1999 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74ALVCH32245ZKER
NRND
LFBGA
ZKE
96
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
ACH245
SN74ALVCH32245KR
NRND
LFBGA
GKE
96
1000
TBD
SNPB
Level-2-235C-1 YEAR
-40 to 85
ACH245
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
74ALVCH32245ZKER
LFBGA
ZKE
96
1000
330.0
24.4
5.7
13.7
2.0
8.0
24.0
Q1
SN74ALVCH32245KR
LFBGA
GKE
96
1000
330.0
24.4
5.7
13.7
2.0
8.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Nov-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74ALVCH32245ZKER
SN74ALVCH32245KR
LFBGA
ZKE
96
1000
336.6
336.6
41.3
LFBGA
GKE
96
1000
336.6
336.6
41.3
Pack Materials-Page 2
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