Texas Instruments | SN74ALVCF162835 (Rev. A) | Datasheet | Texas Instruments SN74ALVCF162835 (Rev. A) Datasheet

Texas Instruments SN74ALVCF162835 (Rev. A) Datasheet
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES397A – JULY 2002 – REVISED AUGUST 2004
FEATURES
•
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
Ideal for Use in PC133 Register DIMM
Typical Output Skew . . . <250 ps
VCC = 3.3 V ± 0.3 V . . . Normal Range
VCC = 2.7 V to 3.6 V . . . Extended Range
VCC = 2.5 V ± 0.2 V
Rail-to-Rail Output Swing for Increased Noise
Margin
Balanced Output Drivers . . . ±18 mA
Low Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
•
•
•
•
•
•
•
•
•
•
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
DESCRIPTION/ORDERING INFORMATION
This 18-bit universal bus driver is designed for 2.3-V
to 3.6-V VCC operation.
Data flow from A to Y is controlled by the
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
high. When LE is low, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is high,
the outputs are in the high-impedance state.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
NC − No internal connection
The SN74ALVCF162835 has series damping
resistors in the device output structure that reduce
switching noise in 128-MB and 256-MB SDRAM
modules. Designed with a drive capability of ±18 mA,
this device is a midway drive between the
SN74ALVC162835 (±12 mA) and SN74ALVC16835
(±24 mA).
ORDERING INFORMATION
PACKAGE (1)
TA
(1)
TOP-SIDE MARKING
Tube
SN74ALVCF162835DL
Tape and reel
SN74ALVCF162835DLR
TSSOP - DGG
Tape and reel
SN74ALVCF162835GR
ALVCF162835
TVSOP - DGV
Tape and reel
SN74ALVCF162835VR
VF2835
SSOP - DL
-40°C to 85°C
ORDERABLE PART NUMBER
ALVCF162835
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES397A – JULY 2002 – REVISED AUGUST 2004
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and,
particularly, SDRAM modules clocked at 133 MHz.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
(1)
OE
LE
CLK
A
OUTPUT
Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
L or H
X
Y0 (1)
Output level before the indicated steady-state input conditions were
established
LOGIC DIAGRAM (POSITIVE LOGIC)
OE
CLK
LE
A1
27
30
28
54
1D
C1
CLK
To 17 Other Channels
2
3
Y1
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES397A – JULY 2002 – REVISED AUGUST 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
-0.5
4.6
V
VI
Input voltage range (2)
-0.5
4.6
V
VO
Output voltage range (2) (3)
-0.5
VCC + 0.5
IIK
Input clamp current
VI < 0 or VI < VCC
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
(1)
(2)
(3)
(4)
mA
-50
mA
±50
mA
±100
mA
DGG package
64
DGV package
48
DL package
56
Storage temperature range
-65
V
-50
°C/W
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
MIN
MAX
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
UNIT
V
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
High-level output current
-8
-6
VCC = 2.7 V
-8
-18
6
VCC = 2.3 V
Low-level output current
8
6
VCC = 2.7 V
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
mA
12
8
VCC = 3 V
∆t/∆v
mA
-12
VCC = 3 V
IOL
V
-6
VCC = 2.3 V
IOH
V
18
-40
10
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES397A – JULY 2002 – REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -0.1 mA
2.3 V to 3.6 V
IOH = -6 mA
IOH = -6 mA
IOH = -8 mA
IOL = 0.1 mA
2.2
V
2
2.4
2
2.3 V to 3.6 V
IOL = 6 mA
0.2
0.4
2.3 V
IOL = 8 mA
VOL
1.7
3V
IOH = -18 mA
IOL = 6 mA
0.55
0.4
2.7 V
IOL = 12 mA
IOL = 8 mA
II = -18 mA
V
0.6
0.55
3V
IOL = 18 mA
UNIT
1.9
2.7 V
IOH = -12 mA
MAX
VCC - 0.2
2.3 V
IOH = -8 mA
VOH
MIN TYP (1)
VCC
0.8
VIK
VCC = 2.3 V,
Vhys
VCC = 3.6 V
3.6 V
3.6 V
II
VI = VCC or GND
3.6 V
IOZ
VO = VCC or GND
ICC
VI = VCC or GND,
IO = 0
∆ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
-1.2
100
3.6 V
3.6 V
0.1
3 V to 3.6 V
V
mV
±5
µA
±10
µA
40
µA
750
µA
Ci
Inputs
VI = 0 V
3.3 V
3.5
pF
Co
Outputs
VO = 0 V
3.3 V
4.5
pF
(1)
All typical values are at VCC = 3.3 V, TA = 25°C.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Figure 2)
VCC = 2.5 V
± 0.2 V
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
th
4
Setup time
Hold time
MAX
VCC = 2.7 V
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
150
LE high
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
Data before CLK↑
1.8
1.5
1
CLK high
1.9
1.6
1.5
CLK low
1.3
1.1
1
0.6
0.6
0.6
1.4
1.7
1.4
Data before LE↓
Data after CLK↑
Data after LE↓
CLK high or low
UNIT
MAX
MHz
ns
ns
ns
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES397A – JULY 2002 – REVISED AUGUST 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Figure 2)
FROM
(INPUT)
PARAMETER
VCC = 2.5 V
± 0.2 V
TO
(OUTPUT)
MIN
fmax
MAX
MIN
150
A
tpd
LE
Y
CLK
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
150
MIN
UNIT
MAX
150
MHz
1
4
4.6
1
3.5
1.3
5.5
5.4
1.3
4.6
1.4
5.9
5.6
1.4
3.5
5
ns
4.2
ns
500
ps
ten
OE
Y
1.4
5.9
6
1.1
tdis
OE
Y
1
4.7
4.6
1.3
tsk(o)
ns
SWITCHING CHARACTERISTICS
from 0°C to 65°C, CL = 50 pF
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
CLK
Y
VCC = 3.3 V
± 0.15 V
MIN
MAX
1.8
3.5
UNIT
ns
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0 pF,
f = 10 MHz
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
27
33
16
21
UNIT
pF
5
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES397A – JULY 2002 – REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
500 Ω
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES397A – JULY 2002 – REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
Input
1.5 V
1.5 V
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
Output
Control
(low-level
enabling)
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
1.5 V
VOH − 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74ALVCF162835GR
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCF162835
SN74ALVCF162835VR
ACTIVE
TVSOP
DGV
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VF2835
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74ALVCF162835GR
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
SN74ALVCF162835VR
TVSOP
DGV
56
2000
330.0
24.4
6.8
11.7
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ALVCF162835GR
TSSOP
DGG
56
2000
367.0
367.0
45.0
SN74ALVCF162835VR
TVSOP
DGV
56
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
SCALE 1.200
SMALL OUTLINE PACKAGE
C
8.3
TYP
7.9
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
6.2
6.0
29
56X
0.27
0.17
0.08
1.2 MAX
C A
B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
29
28
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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