Texas Instruments | CD54HC04, CD74HC04, CD54HCT04, CD74HCT04 (Rev. E) | Datasheet | Texas Instruments CD54HC04, CD74HC04, CD54HCT04, CD74HCT04 (Rev. E) Datasheet

Texas Instruments CD54HC04, CD74HC04, CD54HCT04, CD74HCT04 (Rev. E) Datasheet
[ /Title
(CD54H
C04,
CD54H
CT04,
CD74H
C04,
CD74H
CT04)
/Subject
(High
Speed
CD54HC04, CD74HC04,
CD54HCT04, CD74HCT04
Data sheet acquired from Harris Semiconductor
SCHS117E
High-Speed CMOS Logic Hex Inverter
August 1997 - Revised June 2004
Features
Description
• Buffered Inputs
The
CD54HC04,
CD54HCT04,
CD74HC04
and
CD74HCT04 logic gates utilize silicon-gate CMOS
technology to achieve operating speeds similar to LSTTL
gates, with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family functionally is pin
compatible with the standard 74LS logic family.
• Typical Propagation Delay: 6ns at VCC = 5V,
CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
Ordering Information
• Balanced Propagation Delay and Transition Times
PART NUMBER
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2-V to 6-V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
TEMP. RANGE
(oC)
PACKAGE
CD54HC04F3A
-55 to 125
14 Ld CERDIP
CD54HCT04F3A
-55 to 125
14 Ld CERDIP
CD74HC04E
-55 to 125
14 Ld PDIP
CD74HC04M
-55 to 125
14 Ld SOIC
CD74HC04MT
-55 to 125
14 Ld SOIC
CD74HC04M96
-55 to 125
14 Ld SOIC
CD74HCT04E
-55 to 125
14 Ld PDIP
CD74HCT04M
-55 to 125
14 Ld SOIC
CD74HCT04MT
-55 to 125
14 Ld SOIC
CD74HCT04M96
-55 to 125
14 Ld SOIC
CD74HCT04PWR
-55 to 125
14 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel. The suffix T denotes a
small-quantity reel of 250.
Pinout
CD54HC04, CD54HCT04 (CERDIP)
CD74HC04 (PDIP, SOIC)
CD74HCT04 (PDIP, SOIC, TSSOP)
TOP VIEW
1A 1
14 VCC
1Y 2
13 6A
2A 3
12 6Y
2Y 4
11 5A
3A 5
10 5Y
3Y 6
9 4A
GND 7
8 4Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
1
CD54HC04, CD74HC04, CD54HCT04, CD74HCT04
Functional Diagram
1
14
2
13
1A
6A
1Y
2A
2Y
3A
3Y
GND
VCC
3
12
4
11
5
10
6
9
7
8
6Y
5A
5Y
4A
4Y
TRUTH TABLE
INPUTS
nA
nY
L
H
H
L
H = High Voltage Level, L = Low Voltage Level
Logic Symbol
nA
nY
2
CD54HC04, CD74HC04, CD54HCT04, CD74HCT04
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
25oC
IO (mA) VCC (V)
-40oC TO +85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
HC TYPES
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
-
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
3
CD54HC04, CD74HC04, CD54HCT04, CD74HCT04
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
ICC
VCC or
GND
0
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
PARAMETER
Quiescent Device
Current
25oC
IO (mA) VCC (V)
-40oC TO +85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
-
2
-
20
-
40
µA
-
4.5 to
5.5
2
-
-
2
-
2
-
V
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC
and
GND
0
5.5
-
ICC
VCC or
GND
0
5.5
-
-
2
-
20
-
40
µA
∆ICC
(Note 2)
VCC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE:
2. For dual-supply systems, theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
nB
1.2
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
85
-
105
-
130
ns
4.5
-
-
17
-
21
-
26
ns
6
-
-
14
-
18
-
22
ns
5
-
6
-
-
-
-
-
ns
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
4
CD54HC04, CD74HC04, CD54HTC04, CD74HCT04
Switching Specifications Input tr, tf = 6ns
PARAMETER
Transition Times (Figure 1)
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
(Continued)
SYMBOL
TEST
CONDITIONS
tTLH, tTHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
75
-
95
18
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
21
-
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
tPLH, tPHL
CL = 50pF
4.5
-
-
19
-
24
-
29
ns
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
5
-
7
-
-
-
-
-
ns
Transition Times (Figure 2)
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
24
-
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
tPHL
tf = 6ns
tr = 6ns
VCC
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD54HC04F
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD54HC04F
CD54HC04F3A
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409801CA
CD54HC04F3A
CD54HCT04F
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD54HCT04F
CD54HCT04F3A
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8974701CA
CD54HCT04F3A
CD74HC04E
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC04E
CD74HC04M
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC04M
CD74HC04M96
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC04M
CD74HC04M96E4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC04M
CD74HC04MT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC04M
CD74HCT04E
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT04E
CD74HCT04EE4
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT04E
CD74HCT04M
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT04M
CD74HCT04M96
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT04M
CD74HCT04M96G4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT04M
CD74HCT04MT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT04M
CD74HCT04PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HK04
CD74HCT04PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HK04
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC04, CD54HCT04, CD74HC04, CD74HCT04 :
• Catalog: CD74HC04, CD74HCT04
• Military: CD54HC04, CD54HCT04
NOTE: Qualified Version Definitions:
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC04M96
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HC04M96
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HC04MT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HCT04M96
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HCT04M96
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HCT04MT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HCT04PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC04M96
SOIC
D
14
2500
333.2
345.9
28.6
CD74HC04M96
SOIC
D
14
2500
367.0
367.0
38.0
CD74HC04MT
SOIC
D
14
250
210.0
185.0
35.0
CD74HCT04M96
SOIC
D
14
2500
367.0
367.0
38.0
CD74HCT04M96
SOIC
D
14
2500
333.2
345.9
28.6
CD74HCT04MT
SOIC
D
14
250
210.0
185.0
35.0
CD74HCT04PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
SCALE 0.900
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID
(OPTIONAL)
A
4X .005 MIN
[0.13]
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
C
.13 MIN TYP
[3.3]
SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL A
SEE DETAIL B
1
14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
( .063)
[1.6]
SOLDER MASK
OPENING
METAL
(R.002 ) TYP
[0.05]
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
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