Texas Instruments | SN54ABT646A, SN74ABT646A (Rev. H) | Datasheet | Texas Instruments SN54ABT646A, SN74ABT646A (Rev. H) Datasheet

Texas Instruments SN54ABT646A, SN74ABT646A (Rev. H) Datasheet
 SCBS069H − JULY 1991 − REVISED MAY 2004
D Typical VOLP (Output Ground Bounce)
D
D
D Latch-Up Performance Exceeds 500 mA Per
<1 V at VCC = 5 V, TA = 25°C
High-Drive Outputs (−32-mA IOH, 64-mA IOL)
Ioff Supports Partial-Power-Down Mode
Operation
D
JEDEC Standard JESD-17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54ABT646A . . . JT OR W PACKAGE
SN74ABT646A . . . DB, DGV, DW, NS, NT, OR PW PACKAGE
(TOP VIEW)
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
DIR
SAB
CLKAB
NC
VCC
CLKBA
SBA
1
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
NC
A4
A5
A6
5
4
3
2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
1112 13 14 15 16 17 1819
OE
B1
B2
NC
B3
B4
B5
A7
A8
GND
NC
B8
B7
B6
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN54ABT646A . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
description/ordering information
These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ’ABT646A devices.
ORDERING INFORMATION
PDIP − NT
SN74ABT646ANT
Tube
SN74ABT646ADW
Tape and reel
SN74ABT646ADWR
SOP − NS
Tape and reel
SN74ABT646ANSR
ABT646A
SSOP − DB
Tape and reel
SN74ABT646ADBR
AB646A
Tube
SN74ABT646APW
Tape and reel
SN74ABT646APWR
TVSOP − DGV
Tape and reel
SN74ABT646ADGVR
AB646A
CDIP − JT
Tube
SNJ54ABT646AJT
SNJ54ABT646AJT
CFP − W
Tube
SNJ54ABT646AW
SNJ54ABT646AW
LCCC − FK
Tube
SNJ54ABT646AFK
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Tube
SOIC − DW
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SN74ABT646ANT
ABT646A
AB646A
SNJ54ABT646AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
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POST OFFICE BOX 655303
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1
SCBS069H − JULY 1991 − REVISED MAY 2004
description/ordering information(continued)
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port can be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),
A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
2
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21
OE
L
3
DIR
L
1
23
CLKAB CLKBA
X
X
2
SAB
X
BUS B
BUS A
BUS A
BUS B
SCBS069H − JULY 1991 − REVISED MAY 2004
22
SBA
L
21
OE
L
3
DIR
H
3
DIR
X
X
X
1
23
CLKAB CLKBA
X
↑
X
↑
↑
↑
2
SAB
X
X
X
2
SAB
L
22
SBA
X
BUS B
BUS A
BUS A
21
OE
X
X
H
23
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
1
CLKAB
X
22
SBA
X
X
X
21
OE
L
L
STORAGE FROM
A, B, OR A AND B
3
DIR
L
H
1
CLKAB
X
H or L
23
CLKBA
H or L
X
2
SAB
X
H
22
SBA
H
X
TRANSFER STORED DATA
TO A AND/OR B
Pin numbers shown are for the DB, DGV, DW, JT, NS, NT, PW, and W packages.
Figure 1. Bus-Management Functions
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3
SCBS069H − JULY 1991 − REVISED MAY 2004
FUNCTION TABLE
INPUTS
DATA I/Os
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1−A8
B1−B8
X
X
↑
X
X
X
Input
Unspecified†
X
X
X
↑
X
X
Unspecified†
Input
Store A, B unspecified†
Store B, A unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
† The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled, i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
logic diagram (positive logic)
21
OE
3
DIR
CLKBA
SBA
23
22
1
CLKAB
2
SAB
One of Eight
Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, JT, NS, NT, PW, and W packages.
4
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SCBS069H − JULY 1991 − REVISED MAY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT646A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT646A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C/W
(see Note 3): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-3.
recommended operating conditions (see Note 4)
SN54ABT646A
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
−24
Low-level output current
∆t/∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT646A
MIN
2
2
0.8
Input voltage
0
V
V
0.8
0
UNIT
V
VCC
−32
mA
V
48
64
mA
5
5
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SCBS069H − JULY 1991 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = −18 mA
IOH = −3 mA
VCC = 5 V,
VCC = 4.5 V
VOL
VCC = 4.5 V
MIN
TA = 25°C
TYP†
MAX
MIN
−1.2
SN74ABT646A
MAX
MIN
MAX
−1.2
2.5
2.5
IOH = −3 mA
IOH = −24 mA
3
3
3
2
2
IOH = −32 mA
IOL = 48 mA
2*
2
0.55
IOL = 64 mA
0.55
0.55*
Control inputs
VCC = 5.5 V, VI = VCC or GND
±1
±1
±1
±100
10§
±100
10§
±100
10§
−10§
−10§
µA
±100
µA
50
µA
−180
mA
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
−10§
Ioff
VCC = 0,
VCC = 5.5 V,
VO = 5.5 V
VI or VO ≤ 4.5 V
±100
VCC = 5.5 V,
VO = 2.5 V
Outputs high
IO¶
Outputs high
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
∆ICC#
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Ci
Control inputs
Cio
A or B ports
50
−50
−100
Outputs low
Outputs disabled
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
V
0.55
mV
IOZH‡
IOZL‡
ICEX
V
V
100
A or B ports
UNIT
−1.2
2.5
Vhys
II
SN54ABT646A
−180
50
−50
−180
−50
µA
A
µA
250
250
250
µA
30
30
30
mA
250
250
250
µA
1.5
1.5
1.5
mA
7
pF
12
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ This data-sheet limit may vary among suppliers.
¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
# This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT646A
VCC = 5 V,
TA = 25°C
MIN
6
fclock
tw
Clock frequency
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
MIN
Hold time, A or B after CLKAB↑ or CLKBA↑
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
125
Pulse duration, CLK high or low
MAX
125
MHz
4
4
ns
3
3.5
ns
1.5
1.5
ns
SCBS069H − JULY 1991 − REVISED MAY 2004
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT646A
VCC = 5 V,
TA = 25°C
MIN
MIN
MAX
UNIT
MAX
fclock
tw
Clock frequency
Pulse duration, CLK high or low
4
125
4
125
MHz
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
3
3
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
0
0
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
SN54ABT646A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
TYP
MIN
A or B
A or B
B or A
SAB or SBA†
B or A
OE
A or B
OE
A or B
DIR
A or B
125
• DALLAS, TEXAS 75265
MHz
2.2
4
5.1
2.2
6.7
1.7
4
5.1
1.2
6.7
1.5
3
4.3
1.5
5
1.5
3.3
4.6
1.5
5.6
1.5
4
5.7
1.5
7.8
1.5
3.6
4.9
1.5
6.2
1.5
4.3
5.3
1.5
7
3
5.8
8
3
10.5
1.5
3.5
5.8
1
7.3
1.5
3
4
1.5
5.7
1.5
4.5
5.7
1.5
7.3
2.5
6.5
9
2.5
11
1.5
3.8
6.5
DIR
A or B
tPLZ
1.5
3.8
4.7
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
POST OFFICE BOX 655303
UNIT
MAX
125
CLKBA or CLKAB
MAX
1
9
1.2
6.7
ns
ns
ns
ns
ns
ns
ns
7
SCBS069H − JULY 1991 − REVISED MAY 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
SN74ABT646A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
MIN
TYP
MAX
2.2
4
5.1
2.2
5.6
1.7
4
5.1
1.7
5.6
1.5
3
4.3
1.5
4.8
1.5
3.3
4.6
1.5
5.4
1.5
4
5.1
1.5
6.5
1.5
3.6
4.9
1.5
5.9
1.5
4.3
5.3
1.5
6.3
3
5.8
7.4
3
8.8
1.5
3.5
4.5
1.5
5
1.5
3
4
1.5
4.5
1.5
4.5
5.7
1.5
6.7
2.5
6.5
9
2.5
9.5
1.5
3.8
5
1.5
5.7
1.5
6
125
CLKBA or CLKAB
A or B
A or B
B or A
SAB or SBA†
B or A
OE
A or B
OE
A or B
DIR
A or B
DIR
A or B
125
tPLZ
1.5
3.8
4.7
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
SCBS069H − JULY 1991 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
Input
1.5 V
1.5 V
Data Input
0V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
1.5 V
Input
Output
Control
1.5 V
0V
1.5 V
1.5 V
VOL
VOH
Output
1.5 V
tPLZ
3.5 V
1.5 V
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
1.5 V
0V
Output
Waveform 1
S1 at 7 V
(see Note B)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
1.5 V
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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9
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9457702Q3A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629457702Q3A
SNJ54ABT
646AFK
5962-9457702QLA
ACTIVE
CDIP
JT
24
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9457702QL
A
SNJ54ABT646AJT
SN74ABT646ADBR
ACTIVE
SSOP
DB
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AB646A
SN74ABT646ADW
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT646A
SN74ABT646ADWG4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT646A
SN74ABT646ADWR
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT646A
SN74ABT646ANSR
ACTIVE
SO
NS
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT646A
SN74ABT646APW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AB646A
SNJ54ABT646AFK
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629457702Q3A
SNJ54ABT
646AFK
SNJ54ABT646AJT
ACTIVE
CDIP
JT
24
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9457702QL
A
SNJ54ABT646AJT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ABT646A, SN74ABT646A :
• Catalog: SN74ABT646A
• Military: SN54ABT646A
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74ABT646ADBR
SSOP
DB
24
2000
330.0
16.4
8.2
8.8
2.5
12.0
16.0
Q1
SN74ABT646ADWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
SN74ABT646ANSR
SO
NS
24
2000
330.0
24.4
8.3
15.4
2.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ABT646ADBR
SSOP
DB
24
2000
367.0
367.0
38.0
SN74ABT646ADWR
SOIC
DW
24
2000
350.0
350.0
43.0
SN74ABT646ANSR
SO
NS
24
2000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
13
24
B
1
24
28
A MAX
1.280
(32,51)
1.460
(37,08)
A MIN
1.240
(31,50)
1.440
(36,58)
B MAX
0.300
(7,62)
0.291
(7,39)
B MIN
0.245
(6,22)
0.285
(7,24)
DIM
12
0.070 (1,78)
0.030 (0,76)
0.100 (2,54) MAX
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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