Texas Instruments | SN54ABT8646, SN74ABT8646 (Rev. F) | Datasheet | Texas Instruments SN54ABT8646, SN74ABT8646 (Rev. F) Datasheet

Texas Instruments SN54ABT8646, SN74ABT8646 (Rev. F) Datasheet
 SCBS123F − AUGUST 1992 − REVISED APRIL 2004
D Members of the Texas Instruments
SCOPE  Family of Testability Products
D Compatible With the IEEE Standard
SN54ABT8646 . . . JT PACKAGE
SN74ABT8646 . . . DL OR DW PACKAGE
(TOP VIEW)
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
CLKAB
SAB
DIR
A1
A2
A3
GND
A4
A5
A6
A7
A8
TDO
TMS
D Functionally Equivalent to ’F646 and
’ABT646 in the Normal-Function Mode
D SCOPE  Instruction Set
− IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
− Parallel-Signature Analysis at Inputs
With Masking Option
− Pseudorandom Pattern Generation From
Outputs
− Sample Inputs/Toggle Outputs
− Binary Count From Outputs
− Even-Parity Opcodes
D Two Boundary-Scan Cells Per I/O for
Significantly Reduces Power Dissipation
D Package Options Include Plastic
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
CLKBA
SBA
OE
B1
B2
B3
B4
VCC
B5
B6
B7
B8
TDI
TCK
OE
SBA
CLKBA
CLKAB
SAB
DIR
A1
4
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
B7
B8
TDI
TCK
TMS
TDO
A8
A2
A3
GND
A4
A5
A6
A7
The ’ABT8646 and scan-test devices with octal
bus transceivers and registers are members of the
Texas
Instruments
SCOPE
testability
integrated-circuit family. This family of devices
supports IEEE Standard 1149.1-1990 boundary
scan to facilitate testing of complex circuit-board
assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port
(TAP) interface.
2
B1
B2
B3
B4
V CC
B5
B6
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
description
28
SN54ABT8646 . . . FK PACKAGE
(TOP VIEW)
Greater Flexibility
Small-Outline (DW) and Shrink
Small-Outline (DL) Packages, Ceramic Chip
Carriers (FK), and Standard Ceramic DIPs
(JT)
1
In the normal mode, these devices are functionally equivalent to the ’F646 and ’ABT646 octal bus transceivers
and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing
at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does
not affect the functional operation of the SCOPE octal bus transceivers and registers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments.
Copyright  2004, Texas Instruments Incorporated
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
description (continued)
Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the
transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR
is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both
buses.
Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is
clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data
is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for
presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB
and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that can be performed
with the ’ABT8646.
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO),
test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions
such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from
data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT8646 is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74ABT8646 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/O
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1−A8
B1−B8
X
X
↑
X
X
X
Input
Unspecified†
OPERATION OR FUNCTION
X
X
X
↑
X
X
Unspecified†
Input
Store A, B unspecified†
Store B, A unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input disabled
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input disabled
Output
Stored A data to B bus
† The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at
the bus pins is stored on every low-to-high transition of the clock inputs.
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26
OE
L
3
DIR
L
27
SBA
L
2
SAB
X
28
1
CLKAB CLKBA
X
X
BUS B
BUS A
BUS A
BUS B
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
26
OE
L
3
DIR
H
1
28
CLKAB CLKBA
X
↑
X
↑
↑
↑
2
SAB
L
2
SAB
X
X
X
27
SBA
X
BUS B
BUS A
BUS B
BUS A
3
DIR
X
X
X
28
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
26
OE
X
X
H
1
CLKAB
X
27
SBA
X
X
X
STORAGE FROM
A, B, OR A AND B
26
OE
L
L
3
DIR
L
H
1
CLKAB
X
H or L
28
CLKBA
H or L
X
2
SAB
X
H
27
SBA
H
X
TRANSFER STORED DATA
TO A AND/OR B
Pin numbers shown are for the DL, DW, and JT packages.
Figure 1. Bus-Management Functions
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
functional block diagram
Boundary-Scan Register
OE
DIR
CLKBA
SBA
CLKAB
SAB
26
3
28
27
1
2
C1
1D
A1
4
25
C1
1D
One of Eight Channels
Bypass Register
Boundary-Control
Register
VCC
TDI
13
16
Instruction Register
VCC
TMS
TCK
14
15
TAP
Controller
Pin numbers shown for the DL, DW, and JT packages.
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TDO
B1
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
Terminal Functions
TERMINAL
NAME
DESCRIPTION
A1−A8
Normal-function A-bus I/O ports. See function table for normal-mode logic.
B1−B8
Normal-function B-bus I/O ports. See function table for normal-mode logic.
CLKAB, CLKBA
Normal-function clock inputs. See function table for normal-mode logic.
DIR
Normal-function direction-control input. See function table for normal-mode logic.
GND
Ground
OE
SAB, SBA
Normal-function output-enable input. See function table for normal-mode logic.
Normal-function select inputs. See function table for normal-mode logic.
TCK
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous
to TCK. Data is captured on the rising edge of TCK, and outputs change on the falling edge of TCK.
TDI
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data
through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
TDO
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.
TMS
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS input directs the device through
its TAP controller states. An internal pullup forces TMS to a high level if left unconnected.
VCC
Supply voltage
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 2 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test-data registers: a 40-bit boundary-scan register, an
11-bit boundary-control register, and a 1-bit bypass register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
TMS = L
TMS = L
TMS = L
TMS = H
TMS = H
Capture-DR
Capture-IR
TMS = L
TMS = L
Shift-DR
Shift-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
TMS = H
Exit1-DR
Exit1-IR
TMS = L
TMS = L
Pause-DR
Pause-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = L
Exit2-DR
TMS = L
Exit2-IR
TMS = H
Update-DR
TMS = H
TMS = L
Figure 2. TAP-Controller State Diagram
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TMS = H
Update-IR
TMS = H
TMS = L
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
state diagram description
The TAP controller is a synchronous finite-state machine that provides test control signals throughout the
device. The state diagram shown in Figure 2 is in accordance with IEEE Standard 1149.1-1990. The TAP
controller proceeds through its states, based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’ABT8646, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. Each bit in the boundary-scan register is reset to logic 0. The boundary-control register is reset to
the binary value 00000000010, which selects the PSA test operation, with no input masking.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic actively can be running a test or can be idle.
The test operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.
On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the
high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, then such update
occurs on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK upon, which the TAP controller exits the Capture-IR state.
For the ’ABT8646, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.
On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the
high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
register overview
With the exception of the bypass register, any test register can be thought of as a serial-shift register with a
shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the
appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register
can be parallel loaded from a source specified by the current instruction. During the appropriate shift state
(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted
in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from
the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the three data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 3 lists the instructions supported by the ’ABT8646. The even-parity feature specified for SCOPE devices
is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for
SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated,
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 3.
TDI
Bit 7
Parity
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
TDO
Figure 3. Instruction Register Order of Scan
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
data register description
boundary-scan register
The boundary-scan register (BSR) is 40 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin, two BSCs for each normal-function I/O pin (one for input data and one for output data),
and one BSC for each of the internally decoded output-enable signals (OEA and OEB). The BSR is used 1) to
store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the
device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic
and/or externally at the device input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in Test-Logic-Reset, the value of each BSC is reset to logic 0.
When external data is to be captured, the BSCs for signals OEA and OEB capture logic values determined by
the following positive-logic equations: OEA + OE • DIR, and OEB + OE • DIR. When data is to be applied
externally, these BSCs control the drive state (active or high-impedance) of their respective outputs.
The BSR order of scan is from TDI through bits 39−0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
39
OEB
31
A8-I
23
A8-O
15
B8-I
7
B8-O
38
OEA
30
A7-I
22
A7-O
14
B7-I
6
B7-O
37
DIR
29
A6-I
21
A6-O
13
B6-I
5
B6-O
36
OE
28
A5-I
20
A5-O
12
B5-I
4
B5-O
35
CLKAB
27
A4-I
19
A4-O
11
B4-I
3
B4-O
34
CLKBA
26
A3-I
18
A3-O
10
B3-I
2
B3-O
33
SAB
25
A2-I
17
A2-O
9
B2-I
1
B2-O
32
SBA
24
A1-I
16
A1-O
8
B1-I
0
B1-O
10
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boundary-control register
The boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction to
implement additional test operations not included in the basic SCOPE instruction set. Such operations include
PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations that are
decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 00000000010, which selects the PSA test operation with no input masking.
The BCR order of scan is from TDI through bits 10−0 to TDO. Table 2 shows the BCR bits and their associated
test control signals.
Table 2. Boundary-Control Register Configuration
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
10
MASK8
6
MASK4
2
OPCODE2
9
MASK7
5
MASK3
1
OPCODE1
8
MASK6
4
MASK2
0
OPCODE0
7
MASK5
3
MASK1
−−
−−
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
thereby reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.
TDI
Bit 0
TDO
Figure 4. Bypass Register Order of Scan
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instruction-register opcode description
The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of
each instruction.
Table 3. Instruction-Register Opcodes
BINARY CODE†
BIT 7 → BIT 0
MSB → LSB
SCOPE OPCODE
DESCRIPTION
SELECTED DATA
REGISTER
EXTEST/INTEST
BYPASS‡
Boundary scan
Boundary scan
Test
10000001
Bypass scan
Bypass
Normal
10000010
SAMPLE/PRELOAD
Sample boundary
Boundary scan
Normal
00000011
Boundary scan
Boundary scan
Test
10000100
INTEST/EXTEST
BYPASS‡
Bypass scan
Bypass
Normal
00000101
BYPASS‡
Bypass scan
Bypass
Normal
00000110
HIGHZ
Control boundary to high impedance
Bypass
Modified test
10000111
CLAMP
BYPASS‡
Control boundary to 1/0
Bypass
Test
Bypass scan
Bypass
Normal
00001001
RUNT
Boundary run test
Bypass
Test
00001010
READBN
Boundary read
Boundary scan
Normal
10001011
READBT
Boundary read
Boundary scan
Test
00001100
CELLTST
Boundary self test
Boundary scan
Normal
10001101
TOPHIP
Boundary toggle outputs
Bypass
Test
10001110
SCANCN
Boundary-control register scan
Boundary control
Normal
00001111
SCANCT
Boundary-control register scan
Boundary control
Test
All others
BYPASS
Bypass scan
Bypass
Normal
00000000
10001000
MODE
† Bit 7 is used to maintain even parity in the 8-bit instruction.
‡ The BYPASS instruction is executed in lieu of a SCOPE  instruction that is not supported in the ’ABT8646.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned
into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into
the output BSCs is applied to the device output pins. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.
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control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device
input pins remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device
output pins. The device operates in the test mode.
boundary run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device output pins on each
falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the
inputs of the normal on-chip logic. Data appearing at the device input pins is not captured in the input BSCs.
The device operates in the test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to
be executed.
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13
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2−0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2 → BIT 0
MSB → LSB
DESCRIPTION
X00
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudorandom pattern generation/16-bit mode (PRPG)
X10
Parallel-signature analysis/16-bit mode (PSA)
011
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/8-bit mode (PSA/COUNT)
In general, while the control input BSCs (bits 39−32) are not included in the sample, toggle, PSA, PRPG, or
COUNT algorithms, the output-enable BSCs (bits 39−38 of the BSR) do control the drive state (active or high
impedance) of the selected device output pins. These BCR instructions are valid only when the device is
operating in one direction of data flow (that is, OEA ≠ OEB). Otherwise, the bypass instruction is operated.
PSA input masking
Bits 10−3 of the BCR specify device input pins to be masked from PSA operations. Bit 10 selects masking for
device input pin A8 during A-to-B data flow or for device input pin B8 during B-to-A data flow. Bit 3 selects
masking for device input pins A1 or B1 during A-to-B or B-to-A data flow, respectively. Bits intermediate to 10
and 3 mask corresponding device input pins, in order, from most significant to least significant, as indicated in
Table 3. When the mask bit that corresponds to a particular device input has a logic 1 value, the device input
pin is masked from any PSA operation, i.e., the state of the device input pin is ignored and has no effect on the
generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding device input is not
masked from the PSA operation.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input pins is captured in the shift-register elements of the selected BSCs
on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied
to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs is
toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output
pins on each falling edge of TCK.
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pseudorandom pattern generation (PRPG)
A pseudorandom pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs
of the normal on-chip logic. Figures 5 and 6 show the 16-bit linear-feedback shift-register algorithms through
which the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
=
Figure 5. 16-Bit PRPG Configuration (OEA = 0, OEB = 1)
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
=
Figure 6. 16-Bit PRPG Configuration (OEA=1, OEB= 0)
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
parallel-signature analysis (PSA)
MASKX
Data appearing at the selected device input pins is compressed into a 16-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow
latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow
latches of the selected output BSCs remains constant and is applied to the device outputs. Figures 7 and 8 show
the 16-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed
value should be scanned into the BSR before performing this operation.
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
=
=
MASKX
Figure 7. 16-Bit PSA Configuration (OEA = 0, OEB = 1)
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
=
=
Figure 8. 16-Bit PSA Configuration (OEA = 1, OEB = 0)
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simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 8-bit pseudorandom pattern is generated in the shift-register elements of the selected output BSCs on
each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on
each falling edge of TCK. Figures 9 and 10 show the 8-bit linear-feedback shift-register algorithms through
which the signature and patterns are generated. An initial seed value should be scanned into the BSR before
performing this operation. A seed value of all zeroes does not produce additional patterns.
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
MASKX
A8-I
=
=
Figure 9. 8-Bit PSA/PRPG Configuration (OEA = 0, OEB = 1)
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
MASKX
B8-I
=
=
Figure 10. 8-Bit PSA/PRPG Configuration (OEA = 1, OEB = 0)
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 8-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. In addition, the shift-register elements of the opposite output BSCs count carries
out of the selected output BSCs, extending the count to 16 bits. Figures 11 and 12 show the 8-bit linear-feedback
shift-register algorithms through which the signature is generated. An initial seed value should be scanned into
the BSR before performing this operation.
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
MASKX
A8-I
MSB
=
LSB
=
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
B2-I
B1-I
Figure 11. 8-Bit PSA/COUNT Configuration (OEA = 0, OEB = 1)
B7-I
B6-I
B5-I
B4-I
B3-I
MASKX
B8-I
=
MSB
LSB
=
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
Figure 12. 8-Bit PSA/COUNT Configuration (OEA = 1, OEB = 0)
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A2-O
A1-O
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
timing description
All test operations of the ’ABT8646 are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs
is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling
edge of TCK. The TAP controller is advanced through its states (as shown in Figure 2) by changing the value
of TMS on the falling edge of TCK and then applying a rising edge to TCK.
A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan
and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO
is used to output serial data. The TAP controller then is returned to the Test-Logic-Reset state. Table 5 details
the operation of the test circuitry during each TCK cycle.
Table 5. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
1
Test-Logic-Reset
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
2
Run-Test/Idle
3
Select-DR-Scan
4
Select-IR-Scan
5
Capture-IR
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
6
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
7−13
Shift-IR
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next
TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
14
Exit1-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
15
Update-IR
16
Select-DR-Scan
17
Capture-DR
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
18
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
19−20
Shift-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
21
Exit1-DR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
22
Update-DR
23
Select-DR-Scan
24
Select-IR-Scan
25
Test-Logic-Reset
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
In general, the selected data register is updated with the new data on the falling edge of TCK.
Test operation completed
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Test-Logic-Reset
Select-IR-Scan
Update-DR
Exit1-DR
Capture-DR
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Select-DR-Scan
ÎÎ
ÎÎ
Select-DR-Scan
Shift-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
TAP
Controller
State
Test-Logic-Reset
TDO
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Update-IR
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TDI
Exit1-IR
TMS
Shift-DR
TCK
3-State (TDO) or Don’t Care (TDI)
Figure 13. Timing Example
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . . −0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT8646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT8646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 0.7 W
DW package . . . . . . . . . . . . . . . . . . 1.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
recommended operating conditions (see Note 3)
SN54ABT8646
SN74ABT8646
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
−24
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
85
°C
High-level input voltage
2
2
0.8
Input voltage
0
TA
Operating free-air temperature
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
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−55
125
V
0.8
0
−40
V
VCC
−32
V
V
mA
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = −18 mA
IOH = −3 mA
VCC = 5 V,
VCC = 4.5 V
VOL
II
VCC = 4.5 V
CLK, DIR,
OE, S, TCK
MIN
TA = 25°C
TYP†
MAX
−1.2
3
2
2
IOH = −32 mA
IOL = 48 mA
2*
IOL = 64 mA
±1
±100
±100
±100
VI or VO ≤ 4.5 V
VO = 0.5 V or 2.7 V
±100
±50
IOZPD
ICEX
IO§
VCC = 2 V to 0,
VCC = 5.5 V,
VO = 0.5 V or 2.7 V
VO = 5.5 V
±50
50
VCC = 5.5 V,
VO = 2.5 V
Outputs high
10
−40
−160
A or B ports
Co
TDO
10
−40
−160
50
50
−50
−50
10
µA
µA
50
µA
−50
µA
µA
±50
±50
µA
±50
±50
µA
50
50
µA
−180
mA
−180
2
2
2
Outputs low
30
38
38
38
Outputs disabled
0.9
2
2
2
1.5
1.5
1.5
POST OFFICE BOX 655303
µA
±100
−180
−50
mA
mA
3
pF
10
pF
VO = 2.5 V or 0.5 V
8
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
22
V
−160
0.9
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
−50
−40
−100
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Cio
0.55
±1
VCC = 0,
VCC = 0 to 2 V,
Control inputs
0.55
±1
Ioff
IOZPU
Ci
V
V
0.55*
VO = 2.7 V
VO = 0.5 V
∆ICC¶
UNIT
2
0.55
−50
MAX
−1.2
3
VCC = 5.5 V, VI = VCC or GND
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
−1.2
3
VCC = 5.5 V,
VCC = 5.5 V,
A or B ports
MIN
IOH = −3 mA
IOH = −24 mA
IOZH‡
IOZL‡
Outputs high
SN74ABT8646
2.5
VI = VCC
VI = GND
TDI, TMS
MAX
2.5
VCC = 5.5 V,
VCC = 5.5 V,
ICC
TDI, TMS
MIN
2.5
A or B ports
IIH
IIL
SN54ABT8646
• DALLAS, TEXAS 75265
pF
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
SN54ABT8646
SN74ABT8646
MIN
MAX
MIN
MAX
100
0
100
UNIT
fclock
tw
Clock frequency
CLKAB or CLKBA
0
Pulse duration
CLKAB or CLKBA high or low
3
3
MHz
ns
tsu
th
Setup time
A before CLKAB↑ or B before CLKBA↑
4.7
4.5
ns
Hold time
A after CLKAB↑ or B after CLKBA↑
0
0
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
SN54ABT8646
fclock
tw
tsu
th
td
tr
SN74ABT8646
MIN
MAX
MIN
MAX
50
0
50
Clock frequency
TCK
0
Pulse duration
TCK high or low
5
5
A, B, CLK, DIR, OE, or S before TCK↑
7
5
Setup time
Hold time
Delay time
UNIT
MHz
ns
TDI before TCK↑
6
6
TMS before TCK↑
6
6
A, B, CLK, DIR, OE, or S after TCK↑
0
0
TDI after TCK↑
0
0
TMS after TCK↑
0
0
50*
50
ns
1*
1
µs
Power up to TCK↑
Rise time
VCC power up
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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ns
ns
23
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
SN54ABT8646
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
CLKAB or CLKBA
A or B
B or A
CLKAB or CLKBA
B or A
SAB or SBA
B or A
DIR
B or A
OE
B or A
DIR
B or A
OE
B or A
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
100
130
2
3.7
4.5
2
5.5
2
3.5
4.6
2
5.8
UNIT
MAX
100
MHz
3
4.4
5.3
3
6.3
2.5
4.3
5.2
2.5
6.7
2
4.8
6
2
7.5
2
4.7
5.9
2
7.8
2.5
4.4
5.4
2.5
6.6
3
4.8
6.2
3
8.1
2.5
4.4
5.4
2.5
6.7
3
5.2
6.2
3
7.6
3
6
7.9
3
8.9
3
5.2
6.6
3
8.1
2
5.9
7.7
2.8
8.6
3
5.2
6.2
3
8.3
ns
ns
ns
ns
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
SN74ABT8646
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
24
FROM
(INPUT)
TO
(OUTPUT)
CLKAB or CLKBA
A or B
B or A
CLKAB or CLKBA
B or A
SAB or SBA
B or A
DIR
B or A
OE
B or A
DIR
B or A
OE
B or A
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• DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
100
130
2
3.7
4.5
2
5.2
2
3.5
4.4
2
5.5
3
4.4
5.3
3
6
2.5
4.3
5.2
2.5
6.2
2
4.8
6
2
7.3
2
4.7
5.9
2
7.4
2.5
4.4
5.3
2.5
6.5
3
4.8
6.2
3
7.1
2.5
4.4
5.4
2.5
6.5
3
5.2
6.2
3
7.5
3
6
7
3
8.6
3
5.2
6.2
3
7.9
3
5.9
6.9
3
7.9
3
5.2
6.2
3
7.4
UNIT
MAX
100
MHz
ns
ns
ns
ns
ns
ns
ns
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
SN54ABT8646
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
TCK
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
VCC = 5 V,
TA = 25°C
MIN
TYP
MIN
MAX
UNIT
MAX
50
90
3.5
8
9.5
3.5
50
13.4
MHz
3
7.7
10
3
12
2.5
4.3
5.5
2.5
7
2.5
4.2
5.5
2.5
7
4.5
8.2
9.7
4.5
12.5
4.5
9
11.2
4.5
13.5
2.5
4.3
5.5
2.5
7
2.5
4.9
6
2.5
7.5
3.5
8.4
13
3.5
14.5
3
8
10.5
3
13.5
3
5.9
7
3
9
3
5
6.5
3
8
ns
ns
ns
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
SN74ABT8646
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
TCK
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN
TYP
MIN
MAX
UNIT
MAX
50
90
3.5
8
9.5
3.5
50
12
MHz
3
7.7
9
3
11.5
2.5
4.3
5.5
2.5
6.5
2.5
4.2
5.5
2.5
6.5
4.5
8.2
9.5
4.5
12
4.5
9
10.5
4.5
13
2.5
4.3
5.5
2.5
6.5
2.5
4.9
6
2.5
7
3.5
8.4
10.5
3.5
13.5
3
8
10.5
3
13
3
5.9
7
3
8.5
3
5
6.5
3
7.5
ns
ns
ns
ns
ns
ns
25
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
1.5 V
tPLZ
3.5 V
1.5 V
tPZH
VOH
Output
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
90 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 14. Load Circuit and Voltage Waveforms
26
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• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9458601Q3A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629458601Q3A
SNJ54ABT
8646FK
5962-9458601QXA
ACTIVE
CDIP
JT
28
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9458601QX
A
SNJ54ABT8646JT
SN74ABT8646DL
ACTIVE
SSOP
DL
28
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT8646
SN74ABT8646DLR
ACTIVE
SSOP
DL
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT8646
SN74ABT8646DW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT8646
SNJ54ABT8646FK
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629458601Q3A
SNJ54ABT
8646FK
SNJ54ABT8646JT
ACTIVE
CDIP
JT
28
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9458601QX
A
SNJ54ABT8646JT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Aug-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ABT8646, SN74ABT8646 :
• Catalog: SN74ABT8646
• Military: SN54ABT8646
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
13
24
B
1
24
28
A MAX
1.280
(32,51)
1.460
(37,08)
A MIN
1.240
(31,50)
1.440
(36,58)
B MAX
0.300
(7,62)
0.291
(7,39)
B MIN
0.245
(6,22)
0.285
(7,24)
DIM
12
0.070 (1,78)
0.030 (0,76)
0.100 (2,54) MAX
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
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