Texas Instruments | LV1T Family of single supply translators (Rev. A) | Application notes | Texas Instruments LV1T Family of single supply translators (Rev. A) Application notes

Texas Instruments LV1T Family of single supply translators (Rev. A) Application notes
Application Report
SCEA047A – November 2013 – Revised December 2014
LV1T Family of Single Supply Translators
Chris Cockrill, Ryan Land ........................................................................................... Analog HVAL SLL
ABSTRACT
The LV1T family of devices is unique, combining a wide VIH range with a wide VCC range. The LV1T family
was created to allow up or down voltage translation with only one power rail. The family has overvoltagetolerant inputs that allow down translation from 5.5 V to VCC, which can be as low as 1.8 V. This family has
an optimized and balanced output drive of 7 mA at 3.3-V Vcc, which reduces line reflection, over/undershoot, and eliminates the need for a damping resistor.
Compared to other logic families, the LV1T family is the most well-rounded and universal in terms of
specifications. While there are other logic devices with wide-VIH TTL inputs, the LV1T family also has the
widest VCC range.
The family also has a lowered switching threshold that allows it to translate up to the Vcc level, as high as
5.5 V. See the following chart for the allowable translation levels.
AUP1G
9Best Power Consumption
X No Integrated Translation Function
AUP1T
9Integrated Translation Function
X No 1.8-V Support
AUC
9Best Signal Integrity / tpd
X No 3.3-V Support
LVC
9Wide VCC range
X No Integrated Translation Function
AHC
X
X
No 1.8-V Support
No Integrated Translation Function
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LV1T
Balanced performance
with the most flexible
operation
9Widest VCC Range (1.65 ± 5.5 V)
9Integrated Translation Function
9Drive Current Optimized for Signal
Integrity
LV1T Family of Single Supply Translators
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Vcc
UP
Down
1.8 V
Vcc
2.5 V
INPUT
1.2 V
1.8 V
2.5 V
3.3 V
5V
OUTPUT
INPUT
1.8 V
2.5 V
3.3 V
5V
OUTPUT
Vcc
1.8 V
3.3 V
Vcc
2.5 V
5V
INPUT
1.8 V
2.5 V
3.3 V
5V
OUTPUT
INPUT
2.5 V
3.3 V
5V
OUTPUT
3.3 V
5V
Advantages of Using the LV1T Gates and Buffers to Translate
1.
2.
3.
4.
5.
6.
Ease of use, with just a single power supply
Small packages (DCK package is 2 mm × 1.25 mm, 46% smaller than DBV)
No pullups or pull downs required
Optimized output driving capability
5-V tolerance for Industrial applications
Space and BOM savings (the gate can translate by itself, rather than using the gate plus translators)
Translating Down
Using these parts to translate down is very simple. Because the inputs are tolerant to 5.5 V at any valid
Vcc, they can be used to down translate. The input can be any level above Vcc and up to 5.5 V, and the
output equals the Vcc level, which can be as low as 1.8 V. One advantage to down translating using this
part is that the ICC current remains less than or equal to the specified value. The current draw when
translating can be seen in Figure 2.
Down translation possibilities with LV1T family:
With 1.8-V Vcc from 2.5 V, 3.3 V, or 5 V down to 1.8 V.
With 2.5-V Vcc from 3.3 V, to 5 V down to 2.5 V.
With 3.3-V Vcc from 5 V down to 3.3 V
Translating Up
Using the LV1T family to translate up is very simple. The input switching threshold is lowered, thus the
high level of the input voltage can be much lower than a typical CMOS VIH. For example, if the Vcc is 3.3V, the typical CMOS switching threshold would be VCC/2 or 1.65 V. Thus the input high level must be at
least Vcc × 0.7 or 2.31 V. On the LV1T devices, the input threshold for 3.3-V Vcc is approximately 1 V.
This allows a signal with a 1.8-V VIH to be translated up to the Vcc level of 3.3 V. See an example of this
in Figure 1.
With 2.5-V Vcc from 1.8 V to 2.5 V
With 3.3-V Vcc from 1.8 V or 2.5 V to 3.3 V
With 5-V Vcc from 2.5 V or 3.3 V to 5 V
2
LV1T Family of Single Supply Translators
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Figure 1. Switching Threshold with 3.3-V Vcc
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Because these parts are CMOS, there is more Icc current consumption only when the input is lower than
Vcc and signal translating. An example of this is shown in Figure 2.
Figure 2. Power Consumption when Translating
4
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Example Application 1: PWM with Filter
An application where the LV1T can be useful is in a PWM translation application. In this example, the
amplifier accepts a 5-V PWM into its input filter, but the MCU can only supply 3.3 V on its GPIOs. The
SN74LV1T34 is used in this example to translate the PWM signal to a 5-V level. It also serves to isolate
the MCU from excess line capacitance, making the signal cleaner at higher speeds.
3.3 V
1.8 V
1.8-V PWM
MCU
1
5
NC
VCC
2
4
SN74LV1T34
A
3.3-V PWM
Y
+
Filter
Output
GND
3
Figure 3. Example Schematic for LV1T PWM Circuit
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Example Application 2: PGOOD Circuit
In this example, the engineer wants to send a signal to the MCU when both power ICs have been ramped
to their appropriate output levels. Normally, this application would require an AND gate, combined with
appropriate translators for each level. The SN74LV1T08 positive AND gate can accept input voltages
different than VCC, even when the A and B inputs are at different levels. The LV1T device replace allows
the engineer to use a single device in the place of the AND gate and translators, which could have
previously required up to three devices.
LV1T functions as AND +
translator
3.3 V
Power IC
#1
PGOOD (1.8 V)
5
VCC
2
A
B
PGOOD (5 V)
PGOOD (3.3 V)
MCU
Y
1
Power IC
#2
4
SN74LV1T08
GND
3
Figure 4. PGOOD Circuit with LV1T Acting as Several Devices
Conclusion
The LV1T family of devices is a simple way to perform a function and translate to another voltage level,
whether translating up or down.
There will be a small amount of extra power consumption when translating up: consult the datasheet
specs if the power consumption is critical, as in a battery-powered device.
6
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Revision History
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Revision History
Changes from Original (November 2013) to A Revision ................................................................................................ Page
•
•
•
Modified Abstract. ......................................................................................................................... 1
Added Family Comparison graph. ...................................................................................................... 1
Updated Advantages section. ........................................................................................................... 2
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Revision History
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