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Texas Instruments Simultaneous-Switching Performance of TI Logic Devices (Rev. B) Application notes
Application Report
SZZA038B - February 2005
Simultaneous-Switching Performance of TI Logic Devices
Prasad Dhond and Chris Cockrill
Standard Linear & Logic
ABSTRACT
Simultaneous-switching noise can generate and propagate glitches in electronic systems.
Therefore, system designers are faced with challenges to minimize simultaneous-switching
noise, while increasing switching speed and improving signal quality. This report presents the
performance of different TI logic devices under various simultaneous-switching conditions.
Factors such as the number of bits switching, temperature, supply voltage, package type, and
output loads play a role in the amount of noise generated at the output of a device during
simultaneous switching. A discussion of the effects of these factors, along with concerns
regarding simultaneous-switching noise and suggestions for improvement of
simultaneous-switching performance, is provided. System designers concerned about
implications of simultaneous-switching noise can use this report to choose the right Texas
Instruments logic solution for their application.
Keywords: simultaneous switching, VOHV, VOHP, VOLV, VOLP, ground bounce, VCC bounce,
AUC
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Simultaneous-Switching Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Effect of the Number of Bits Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Effect of Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Effect of Power-Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Effect of Lumped and Distributed Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Effect of Package Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.1 Reducing Package Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.2 Multiple GND and VCC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Use of Series-Damping-Resistor Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Concerns Regarding Simultaneous-Switching Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Glitches or False Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Propagation-Delay Degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1 Causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2 Jitter in Clock-Distribution Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Increase in the Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks are the property of their respective owners.
1
SZZA038B
List of Figures
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Currents That Lead to Simultaneous-Switching Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Generation of Simultaneous-Switching Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ground Bounce vs Number of Bits Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ground Bounce vs Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ground Bounce vs Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Short and Long Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ground Bounce at the Driver Output and Receiver Input With a Distributed Capacitive Load . . 10
Effect of Output Capacitive Load on Ground Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ground Bounce Using SSOP 48-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ground Bounce Using TSSOP 48-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ground Bounce Using TVSOP 48-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ground Bounce on SN74LVC32244 Using LFBGA 96-Ball Package . . . . . . . . . . . . . . . . . . . . . . . 13
Damping Resistors Replace External Series Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Improvement in Simultaneous-Switching Performance
Using Device With Series-Damping-Resistor Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15. Change in Threshold Levels Caused by Ground Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16. Output Stage Modeled as RC Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
17. Propagation-Delay Degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
18. Eye Pattern for Signal 1 Switching at 100 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
19. Eye Pattern for Signal 1 Switching at 100 MHz, Using Multiple GND and VCC Pins . . . . . . . . . . 20
20. Increase in Supply Current With Number of Bits Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
A−1. Bounce on Quiet Output Held Low, While the Other Seven Outputs Are Switched
From H to L, SN74ALS244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
A−2. Bounce on Quiet Output Held Low, While the Other Seven Outputs Are Switched
From H to L, SN74ABT244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
A−3. Bounce on Quiet Output Held Low, While the Other Seven Outputs Are Switched
From H to L, SN74HC244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
A−4. Bounce on Quiet Output Held Low, While the Other Seven Outputs Are Switched
From H to L, SN74AHC244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
A−5. Bounce on Quiet Output Held Low, While the Other Seven Outputs Are Switched
From H to L, SN74LV244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
A−6. Bounce on Quiet Output Held Low, While the Other Seven Outputs Are Switched
From H to L, SN74AC244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
A−7. Bounce on Quiet Output Held Low, While the Other 15 Outputs Are Switched
From H to L, SN74LVC16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
A−8. Bounce on Quiet Output Held Low, While the Other Seven Outputs Are Switched
From H to L, SN74LVCH162244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
A−9. Bounce on Quiet Output Held Low, While the Other 15 Outputs Are Switched
From H to L, SN74ALVC16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
A−10.Bounce on Quiet Output Held Low, While the Other 15 Outputs Are Switched
From H to L, SN74AVC16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2
Simultaneous-Switching Performance of TI Logic Devices
SZZA038B
A−11. Bounce on Quiet Output Held Low, While the Other 15 Outputs Are Switched
From H to L, SN74AUC16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
List of Tables
1
2
Pin Inductance Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TI Logic Devices Available With Center GND and VCC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Simultaneous-Switching Performance of TI Logic Devices
3
SZZA038B
1
Introduction
Switching multiple output drivers simultaneously on the same device is called simultaneous
switching. The elements in the electrical path from the ground or power pads of the integrated
circuit (IC) to the ground or power planes on the printed circuit board (PCB) behave as
inductances with negligible resistive components.[1] In Figure 1, the inductive elements to the
power rail are shown collectively as Lpower, and the inductive elements to the ground rail are
shown collectively as LGND, while Linput and Loutput represent the inductive elements at the input
and output, respectively.
CMOS devices operate by charging and discharging a capacitive load (see Figure 1a). When
the output changes state from high to low or low to high, a current flows in the output loop. This
current determines the output edge rate (see Equation 1).
dV O
* i( t )
+
dt
CL
(1)
Figure 1b shows a CMOS inverter. When a high (H) signal is applied at the input, the upper
p-channel transistor is off and the lower n-channel transistor is on. The output is pulled to ground
(low) through the conducting n-channel. Similarly, when a low (L) signal is applied at the input,
the n-channel is off and the p-channel is on, pulling the output high through the conducting
p-channel. When changing states from high to low, the p-channel begins to turn off and the
n-channel begins to turn on. In the threshold region (VIL < Vinput < VIH), both these transistors
are partially ON, causing a through current, ICC, to flow from VCC to GND. A similar situation
exists when the output switches from L to H.
PCB Power
Lpower
PCB Power
Lpower
Vinput
Loutput
Linput
Output
ICC
Driver
i(t)
CL
LGND
a) Current due to charging and discharging of output load
LGND
b) Through current during switching of transistors
Figure 1. Currents That Lead to Simultaneous-Switching Noise
4
Simultaneous-Switching Performance of TI Logic Devices
SZZA038B
These currents interact with the inductances in their path to generate ground and VCC bounce
(see Figure 2). When the output changes from H to L, the output capacitor discharges to ground
through the n-channel pulldown, generating a current i(t) in the output loop. This current
interacts with the ground inductance (LGND) to generate ground bounce VGND (see Equation 2).
Similarly, when the output changes states from low to high, the current induces a voltage drop
on the power rail (see Equation 4).
V GND +
ǒ
L GND
N
Ǔǒ
di
dt
Ǔ
(2)
From Equations (1) and (2): V GND + –
V power +
ǒ
L power
N
Ǔǒ
di
dt
ǒ
L GND C L
N
Ǔǒ Ǔ
d 2V O
dt 2
(3)
Ǔ
(4)
From Equations (1) and (4): V power + –
ǒ
L power C L
N
Ǔǒ Ǔ
d 2V O
dt 2
(5)
VOHP
VOH
VOHV
Active
Outputs
VOLP
VOL
VOLV
VOHP
Quiet Outputs Under Test
VOH
VOHV
VOLP
VOL
VOLV
Figure 2. Generation of Simultaneous-Switching Noise
Simultaneous-Switching Performance of TI Logic Devices
5
SZZA038B
Whatever applies to ground bounce also applies to VCC bounce in a similar manner. Hence,
through the remainder of this application report, only the effects of ground bounce are
discussed.
For the simultaneous-switching measurement procedure, one input is connected to a fixed low
or high state while a specified number of other inputs are switched simultaneously. The outputs
of these drivers react to the changes in the corresponding inputs after a certain delay, while the
nonswitched output maintains a constant low (or high) state.
Figure 2 also sets out the parameters and definitions of significance for this measurement
procedure. Points on the curves are defined as:
•
VOHP (voltage output high peak): VCC bounce: peak output-voltage value during a static
high at the nonswitched output or during a low-to-high transition at a switching output.
•
VOHV (voltage output high valley): VCC bounce: minimum output-voltage value during a static
high at the nonswitched output or during a low-to-high transition at a switching output.
•
VOLP (voltage output low peak): Ground bounce: peak output-voltage value during a static
low at the nonswitched output or during a high-to-low transition at a switching output.
•
VOLV (voltage output low valley): Ground bounce: minimum output-voltage value during a
static low at the nonswitched output or during a high-to-low transition at a switching output.
VOLV and VOHP could cause damage if the voltage spike goes well beyond the rails and/or lasts
for a long period of time. VOLP and VOHV are critical because, in the worst case, they could
exceed the switching thresholds (VIH and VIL) of a subsequent receiver.[2]
6
Simultaneous-Switching Performance of TI Logic Devices
SZZA038B
2
Simultaneous-Switching Considerations
From Equations 3 and 5, output load, output edge rate, and package inductance affects ground
bounce. We have investigated how these and other factors affect ground bounce. In our
evaluation, the ’244 function (noninverting buffer/driver with 3-state outputs) is used as an
example.
2.1
Effect of the Number of Bits Switching
As more bits are switched simultaneously, more current flows in the output loop. From
Equations 2 and 4, ground bounce is expected to increase in proportion to the number of bits
switching. This relationship holds true until the device begins to limit the transient current flow.
Figure 3 shows the increase in ground bounce as the number of simultaneously switching bits
increases.
SN74AUC16244
VCC = 1.8 V, CL = 30 pF, RL = 1 kΩ, TSSOP Package
300
250
Ground Bounce − mV
200
150
100
VOLP
50
VOLV
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
−50
−100
−150
Number of Bits Switching
Figure 3. Ground Bounce vs Number of Bits Switching
2.2
Effect of Temperature
As CMOS devices operate at lower temperatures, they become intrinsically faster. This is
because electron and hole mobility increases with decreasing temperature. This results in faster
edges, causing simultaneous-switching noise to increase, with a decrease in temperature.[1]
Figure 4 shows the effect of temperature on the amount of ground bounce generated on a quiet
output held low when the other 15 outputs switch from H to L. Ground bounce increases as
temperature decreases.
Simultaneous-Switching Performance of TI Logic Devices
7
SZZA038B
SN74AUC16244
VCC = 1.8 V, CL = 30 pF, RL = 1 kΩ, TSSOP Package
Ground Bounce − mV
300
200
VOLP
100
VOLV
0
85°C
25°C
−40°C
−100
−200
TA − Temperature − °C
Figure 4. Ground Bounce vs Temperature
2.3
Effect of Power-Supply Voltage
Equations 3 and 5 show that the amount of noise generated is directly proportional to the output
voltage swing (dVO/dt). Hence, as the supply voltage increases, so do the output voltage swing
(dVO) and the ground bounce. The quiescent supply current also increases with a rise in the
supply voltage, contributing further to greater ground bounce. Figure 5 shows the effects of
supply voltage on ground bounce.
SN74AUC16244
CL = 30 pF, RL = 1 kΩ, TSSOP Package
500
Ground Bounce − mV
400
300
200
VOLP
100
VOLV
0
0.8 V
1.2 V
1.8 V
2.5 V
−100
−200
−300
−400
VCC − Supply Voltage − V
Figure 5. Ground Bounce vs Supply Voltage
CMOS outputs have a greater output voltage swing compared to TTL outputs. Because dVO/dt
is higher for CMOS devices than for TTL devices, CMOS devices generate more
simultaneous-switching noise compared to similar TTL devices.
8
Simultaneous-Switching Performance of TI Logic Devices
SZZA038B
2.4
Effect of Lumped and Distributed Loading
TI logic data sheets usually specify ac (switching) parameters using a lumped capacitive load at
the output. Typically, such lumped capacitances at the output in a system environment do not
occur. Instead, as shown in Figure 6, a driver output sees a short transmission line as a lumped
capacitance some distance away, whereas longer transmission lines appear as distributed
capacitive loads.[1] Equation 6 gives a rule of thumb for short and long transmission lines.
l short v
tr
t
, l long u r
2t pd
2t pd
(6)
Where:
tr = rise time of the output signal
tpd = flight time through the transmission line[3]
Short transmission line seen as a lumped capacitance by the output driver
Long transmission line seen as a distributed capacitive load by the output driver
Figure 6. Short and Long Transmission Lines
To simulate the system environment, ground bounce was measured by placing lumped and
distributed capacitances at a distance away from the output. The main effect of placement of
these capacitances at a distance away from the driving device is reduction of ground bounce at
the output of the driver. However, the magnitude of ground bounce at the input of the receiver is
not reduced (see Figure 7).
Simultaneous-Switching Performance of TI Logic Devices
9
SZZA038B
SN74AUC16244
VCC = 2.5 V, CL = 64 pF (Four 10-pF Capacitors 1 in. Apart),
RL = 500 Ω, TSSOP Package
1000
Ground Bounce − mV
800
600
Waveform at
Driver Output
400
200
0
−200
−400
Quiet Bit
Waveform at
Receiver Output
−600
−800
−30
−20
−10
0
10
20
30
Time − ns
Figure 7. Ground Bounce at the Driver Output and Receiver Input
With a Distributed Capacitive Load
Ground bounce would decrease if additional lumped capacitances were added at the device
output. This would seem to invalidate Equations 3 and 5, which indicate that ground bounce is
directly proportional to the output capacitive load. However, these equations also indicate that
ground bounce is proportional to the output edge rate (dVO/dt). The output edge rate is inversely
proportional to the capacitive load it is charging or discharging, which explains the reduction in
ground bounce with an increase in the lumped capacitance at the output.
10
Simultaneous-Switching Performance of TI Logic Devices
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SN74LVC16244
VCC = 3 V, TSSOP Package
1000
CL = 15 pF
800
Ground Bounce − mV
600
CL = 30 pF
400
CL = 100 pF
200
0
−200
−400
−600
−800
−40
−30
−20
−10
0
10
20
30
40
Time − ns
Figure 8. Effect of Output Capacitive Load on Ground Bounce
2.5
2.5.1
Effect of Package Options
Reducing Package Inductance
Ground bounce is directly proportional to the ground inductance LGND (see Equation 2). To
reduce simultaneous-switching noise, the value of the ground-lead inductances must be
reduced. However, all pins pose an inductance, so it is vital to use better packaging with
reduced lead inductance (see Table 1).
Table 1. Pin Inductance Values[4]
PACKAGE
MAXIMUM
DIE-TO-PIN INDUCTANCE
(nH)
48-pin SSOP
7.970
48-pin TSSOP
3.990
48-pin TVSOP
4.310
96-ball BGA
2.866
Lead inductance is proportional to lead length. Smaller packages with shorter leads reduce
simultaneous-switching noise. Figures 9−12 show ground bounce on the SN74LVCH16244
using different packages.[4] The maximum positive ground bounce is reduced from 1 V for the
SSOP package to about 300 mV for the LFBGA package – an improvement of 70%. TI also
offers devices in the quad flatpack no-lead (QFN) package, which has excellent thermal and
electrical characteristics. For more information on this package, please refer to TI application
report, Quad Flatpack No-Lead Logic Packages, literature number SCBA017. Using packages
such as TVSOP, QFN, and LFBGA, which demonstrate superior simultaneous-switching
performance, is recommended.
Simultaneous-Switching Performance of TI Logic Devices
11
SZZA038B
SN74LVCH16244 in SSOP 48-Pin Package
CL = 30 pF, RL = 500 Ω
1500
Ground Bounce − mV
1000
500
VOLP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VOLV
−500
−1000
−1500
Number of Bits Switching
Figure 9. Ground Bounce Using SSOP 48-Pin Package
SN74LVCH16244 in TSSOP 48-Pin Package
CL = 30 pF, RL = 500 Ω
1500
Ground Bounce − mV
1000
500
VOLP
VOLV
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
−500
−1000
−1500
Number of Bits Switching
Figure 10. Ground Bounce Using TSSOP 48-Pin Package
12
Simultaneous-Switching Performance of TI Logic Devices
SZZA038B
SN74LVCH16244 in TVSOP 48-Pin Package
CL = 30 pF, RL = 500 Ω
1000
800
Ground Bounce − mV
600
400
200
VOLP
0
1
2
3
4
5
6
7
8
9
11
10
12
13
VOLV
15
14
−200
−400
−600
−800
Number of Bits Switching
Figure 11. Ground Bounce Using TVSOP 48-Pin Package
SN74LVC32244 in LFBGA 96-Ball Package
CL = 30 pF, RL = 500 Ω
400
300
Ground Bounce − mV
200
100
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
−100
−200
VOLP
VOLV
−300
Number of Bits Switching
Figure 12. Ground Bounce on SN74LVC32244 Using LFBGA 96-Ball Package
Simultaneous-Switching Performance of TI Logic Devices
13
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2.5.2
Multiple GND and VCC Pins
Multiple ground pins reduce the total ground inductance because the total inductance is a
parallel combination of the ground-lead inductances. Hence, with n ground pins, the total ground
inductance is approximately 1/n times that of a similar chip with only one GND pin. TI Widebus
and 32-bit devices are available with multiple GND and VCC pins to improve
simultaneous-switching performance.
1 +
L total
1
L1
)
1
L2
1
) ... ) L1
(7)
N
Devices with center GND and VCC pins also show excellent simultaneous-switching
performance. The center pins are closest to the die, have the shortest leads, and have smaller
inductance values. Table 2 shows TI devices that are available with center pins for better
simultaneous-switching performance.
Table 2. TI Logic Devices Available With Center GND and VCC Pins
DEVICE
14
FUNCTION
DEVICE
FUNCTION
74AC1100
74ACT11000
Quad 2-Input Positive-NAND Gates
74AC11138
3-Line to 8-Line
Decoder/Demultiplexer
74AC11004
74ACT11004
Hex Inverter
74ACT11139
Dual 2-Line to 4-Line
Decoder/Demultiplexer
74AC11008
74ACT11008
Quad 2-Input Positive-AND Gates
74AC11175
Quad D-Type Flip-Flop with Clear
74ACT11030
8-Input Positive-NAND Gates
74AC11244
74ACT11244
Octal Buffer/Driver with 3-state
Outputs
74AC11032
74ACT11032
Quad 2-Input Positive-OR Gates
74AC11257
74AC11257
Quad 2-Line to 1-Line Data
Selector/Multiplexer with 3-state
Outputs
74AC11074
74AC11074
Dual Positive-Edge-Triggered D-type
Flip-Flop with Clear and Preset
74ACT11286
9-Bit Parity Generator/Checker with
Bus Driver Parity I/O ports
74AC11086
Quad 2-Input XOR Gate
74ACT11374
Octal Edge-Triggered D-Type
Flip-Flops with 3-state Outputs
Simultaneous-Switching Performance of TI Logic Devices
SZZA038B
Use of Series-Damping-Resistor Option
Several TI logic devices are offered with an output-damping-resistor option. This resistor
eliminates the need for an external damping resistor, provides current limiting, and offers better
signal integrity. Figure 13 shows a typical CMOS output with a series damping resistor. TI logic
devices with an extra ‘‘2’’ or ‘‘R’’ in the device name have the damping-resistor option, for
example, SN74LVC162244 or SN74LVCHR16245. Figure 14 shows the improvement in
simultaneous-switching performance by using the internal series damping resistor.
VCC
Output Pin
25 Ω
Figure 13. Damping Resistors Replace External Series Resistors
VCC = 3 V, CL = 50 pF, RL = 500 Ω, TSSOP Package
1000
500
Ground Bounce − mV
2.6
0
LVCH162244
−500
LVCH16244
−1000
−80
−40
0
40
80
Time − ns
Figure 14. Improvement in Simultaneous-Switching Performance
Using Device With Series-Damping-Resistor Option
Simultaneous-Switching Performance of TI Logic Devices
15
SZZA038B
3
Concerns Regarding Simultaneous-Switching Noise
3.1
Glitches or False Switching
The input threshold of CMOS devices depends on the voltage difference across the input
structure. Ground bounce causes a change in this voltage across the input structure, which
shifts the input threshold (see Figure 15).
For example, the input threshold for a 3.3-V LVTTL device is approximately 1.5 V. If a positive
ground bounce of 1 V is observed, the threshold shifts to 2.15 V [1 V of bounce + 50% of
(3.3 − 1)]. If there were a quiet input at 2 V, the input structure falsely detects a change of state.
Depending on the type of device and the input under question, this can alter the state of a
device, causing corruption of data.
3.3 V
3.3 V
3.3 V
Vt
Signals in these
regions might glitch
Vt = 1.5 V
Vt
GND
Normal
Condition
Shifted Voltages Due to
Positive Ground Bounce
Shifted Voltages Due to
Negative Ground Bounce
Figure 15. Change in Threshold Levels Caused by Ground Bounce
Ground bounce can cause failure in a system as well. If the ground bounce is very large and
crosses the input threshold of a subsequent device, the subsequent device might falsely switch.
If the subsequent device is an asynchronous device, such as an inverter, the device output
might falsely change states. Or, if the subsequent input is the clock input of a synchronous
device like a flip-flop, it may falsely trigger this input, latching in an incorrect value.
A slow-rising input edge, combined with ground-bounce effects, can cause the output to oscillate
because of a shift in the input threshold. For further information, please see TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
16
Simultaneous-Switching Performance of TI Logic Devices
SZZA038B
3.2
3.2.1
Propagation-Delay Degradation
Causes
As ground bounce increases, the propagation delay through the device is affected adversely. To
understand the cause of propagation-delay (tpd) degradation, consider Figure 16, which shows a
CMOS output stage modeled as an RC network. Ground bounce increases the voltage drop
across R2 (reduces the voltage across R1), reducing current in the output loop. The rate of
change of voltage across the capacitor (dVO/dt) is directly proportional to the current in the loop
(see Equation 1). As this current decreases, the output is slowed; hence, it takes more time to
transition from rail to rail.[1] This causes the tpd push-out shown in Figure 17.
PCB Power
Lpower
Loutput
Linput
Internal GND
i(t)
CL
R1
R2
CL
Internal GND
LGND
Figure 16. Output Stage Modeled as RC Network
Simultaneous-Switching Performance of TI Logic Devices
17
SZZA038B
SN74AUC16244
tpd vs Number of Outputs Switching
1 MHz, RL = 1 kΩ, CL = 30 pF, TSSOP Package
7.00
VCC = 0.8 V
6.00
t pd − ns
5.00
4.00
3.00
VCC = 1.2 V
2.00
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
1.00
0.00
1
3
5
7
9
11
13
Number of Outputs Switching
Figure 17. Propagation-Delay Degradation
18
Simultaneous-Switching Performance of TI Logic Devices
15
SZZA038B
3.2.2
Jitter in Clock-Distribution Applications
When clock signals with different frequencies are passed through a single logic device,
simultaneous switching can lead to output jitter because of propagation-delay degradation
(tpd pushout).
Because of the different clock frequencies, at any given time there might be a different number
of bits switching simultaneously. For example, at time t, there might be only one bit switching; at
time (t + x), there might be four bits switching simultaneously, whereas at time (t + y), there
might be three bits switching simultaneously. If the signals at time t, (t + x), (t + y), etc. are
overlaid, it produces an eye pattern that can be used to observe jitter.
Such an eye pattern for an SN74LVTH125DB is shown in Figure 18. Using HSPICE, four signals
were passed through the device model: signal 1 at 100 MHz, signal 2 at 50 MHz, signal 3 at
33 MHz, and signal 4 at 25 MHz. Figure 18 shows the jitter on signal 1 output to be 195 ps.
Figure 19 shows the same signal, but modeled using three GND and three VCC pins. The
observed jitter is reduced to 102 ps. Hence, devices with multiple GND and VCC pins can be
used to reduce the incidence of jitter in such clock-distribution applications.
SN74LVTH125
Bit 1 switching at 100 MHz, Bit 2 at 50 MHz, Bit 3 at 33 MHz, Bit 4 at 25 MHz
Jitter = 195 ps
Figure 18. Eye Pattern for Signal 1 Switching at 100 MHz
Simultaneous-Switching Performance of TI Logic Devices
19
SZZA038B
SN74LVTH125
Bit 1 switching at 100 MHz, Bit 2 at 50 MHz, Bit 3 at 33 MHz, Bit 4 at 25 MHz
Jitter = 102 ps
Figure 19. Eye Pattern for Signal 1 Switching at 100 MHz, Using Multiple GND and VCC Pins
3.3
Increase in the Supply Current
The length of the internal paths from different inputs to their corresponding outputs might be
different, even on the same device. Multiple-output drivers might not switch at exactly the same
time, causing paths from VCC to ground to exist during simultaneous switching. As the number
of simultaneously switching outputs increases, the paths from VCC to ground exist for a longer
time, leading to a greater supply current. This larger supply current interacts with the ground
inductance, leading to greater ground bounce (see Figure 20).
20
Simultaneous-Switching Performance of TI Logic Devices
SZZA038B
SN74AUC16244
RL = 0, CL= 0, ~15-pF Board Capacitance, TSSOP Package,
Outputs Switching at 100 MHz
1.6
2.5 V
1.4
Supply Current − mA
1.2
1.8 V
1
1.5 V
0.8
1.2 V
0.6
0.8 V
0.4
0.2
0
1
3
5
7
9
11
13
15
Number of Simultaneously Switching Outputs
Figure 20. Increase in Supply Current With Number of Bits Switching
Simultaneous-Switching Performance of TI Logic Devices
21
SZZA038B
4
Conclusion
Several factors affect the simultaneous-switching performance of a logic device. These include
temperature, supply voltage, number of bits switching, package options, and output loads.
Simultaneous-switching noise can lead to device and system-level issues. There are different
approaches to reducing this noise. One approach is to use devices with the damping resistor
option. Another approach is to use better package options that offer reduced lead inductances,
multiple GND and VCC pins, and/or center GND and VCC pins. TI AUC devices with advanced
package techniques demonstrate excellent ground-bounce performance. By knowing how
different factors affect ground bounce, systems can be optimized for better
simultaneous-switching performance.
5
Acknowledgments
The authors of this report thank Tomdio Nana and Ernest Cox for their contributions.
6
References
1. Scott Abramson, Charles Hefner, and Dan Powers, Simultaneous Switching Considerations,
1987.
2. Navid Madani, Simultaneous-Switching Noise Analysis for Texas Instruments FIFO Products,
Application Report, literature number SCAA008, 1996.
3. Mike Higgs, Advanced Schottky Load Management, Application Report, literature number
SDYA016, 1997.
4. Johannes Huchzermeier, Comparison of Electrical and Thermal Parameters of Widebus SMD,
and LFBGA Packages, Application Report, literature number SCYA007, 1999.
22
Simultaneous-Switching Performance of TI Logic Devices
SZZA038
Appendix A
Ground bounce of devices from different TI logic families is shown on the following pages. For
each device, the worst-case-condition bounce is shown (noise on one quiet output that is held
low, while all other outputs are switched from H to L).
SN74ALS244
VCC = 5 V, CL = 50 pF, RL = 500 Ω, SOIC Package
600
400
Ground Bounce − mV
200
0
−200
−400
−600
−800
−1000
−80
−60
−40
−20
0
20
40
60
80
Time − ns
Figure A−1. Bounce on Quiet Output Held Low, While
the Other Seven Outputs Are Switched From H to L, SN74ALS244
Simultaneous-Switching Performance of TI Logic Devices
23
SZZA038
SN74ABT244
VCC = 5 V, CL = 50 pF, RL = 500 Ω, SOIC Package
600
400
Ground Bounce − mV
200
0
−200
−400
−600
−800
−1000
−1200
−1400
−30
0
30
60
90
120
Time − ns
Figure A−2. Bounce on Quiet Output Held Low, While the
Other Seven Outputs Are Switched From H to L, SN74ABT244
SN74HC244
VCC = 5 V, CL = 50 pF, RL = 500 Ω, SOIC Package
800
600
Ground Bounce − mV
400
200
0
−200
−400
−600
−800
−30
0
30
60
90
120
Time − ns
Figure A−3. Bounce on Quiet Output Held Low, While
the Other Seven Outputs Are Switched From H to L, SN74HC244
24
Simultaneous-Switching Performance of TI Logic Devices
SZZA038
SN74AHC244
VCC = 5 V, CL = 50 pF, RL = 500 Ω, SOIC Package
800
600
200
0
−200
−400
−600
−60
−40
−20
20
0
40
60
80
100
Time − ns
Figure A−4. Bounce on Quiet Output Held Low, While the
Other Seven Outputs Are Switched From H to L, SN74AHC244
SN74LV244
VCC = 5 V, CL = 50 pF, RL = 500 Ω, SOIC Package
400
300
Ground Bounce − mV
Ground Bounce − mV
400
200
100
0
−100
−200
−300
−400
−500
−30
0
30
60
90
120
Time − ns
Figure A−5. Bounce on Quiet Output Held Low, While the
Other Seven Outputs Are Switched From H to L, SN74LV244
Simultaneous-Switching Performance of TI Logic Devices
25
SZZA038
SN74AC244
VCC = 5 V, CL = 50 pF, RL = 500 Ω, SOIC Package
2000
Ground Bounce − mV
1500
1000
500
0
−500
−1000
−1500
−2000
−30
0
30
Time − ns
60
90
120
Figure A−6. Bounce on Quiet Output Held Low, While the
Other Seven Outputs Are Switched From H to L, SN74AC244
SN74LVC16244
VCC = 3 V, CL = 50 pF, RL = 500 Ω, TSSOP Package
Ground Bounce − mV
1000
500
0
−500
−1000
−90
−60
−30
0
Time − ns
30
60
90
Figure A−7. Bounce on Quiet Output Held Low, While the
Other 15 Outputs Are Switched From H to L, SN74LVC16244
26
Simultaneous-Switching Performance of TI Logic Devices
SZZA038
SN74LVCH162244
VCC = 3 V, CL = 50 pF, RL = 500 Ω, TSSOP Package
600
Ground Bounce − mV
400
200
0
−200
−400
−80
−40
0
40
80
Time − ns
Figure A−8. Bounce on Quiet Output Held Low, While the
Other Seven Outputs Are Switched From H to L, SN74LVCH162244
SN74ALVC16244
VCC = 3 V, CL = 50 pF, RL = 500 Ω, TSSOP Package
1500
Ground Bounce − mV
1000
500
0
−500
−1000
−80
−40
0
40
80
Time − ns
Figure A−9. Bounce on Quiet Output Held Low, While the
Other 15 Outputs Are Switched From H to L, SN74ALVC16244
Simultaneous-Switching Performance of TI Logic Devices
27
SZZA038
SN74AVC16244
VCC = 3 V, CL = 50 pF, RL = 500 Ω, TSSOP Package
500
400
Ground Bounce − mV
300
200
100
0
−100
−200
−300
−400
−60
−40
−20
0
20
40
60
Time − ns
Figure A−10. Bounce on Quiet Output Held Low, While the
Other 15 Outputs Are Switched From H to L, SN74AVC16244
SN74AUC16244
VCC = 1.8 V, CL = 30 pF, RL = 1 kΩ, TSSOP Package
350
300
Ground Bounce − mV
250
200
150
100
50
0
−50
−100
−150
−200
Time − ns
Figure A−11. Bounce on Quiet Output Held Low, While the
Other 15 Outputs Are Switched From H to L, SN74AUC16244
28
Simultaneous-Switching Performance of TI Logic Devices
80
100
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