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Texas Instruments AUC Data Book, January 2003 (Rev. A) User guides
AUC
Advanced UltraĆLowĆVoltage CMOS
Data Book
January 2003
Logic Products
General Information
AUC Single Gates
AUC Widebus
AUC Widebus+
Application Reports
Mechanical Data
AUC
Advanced Ultra-Low-Voltage CMOS
Data Book
Printed on Recycled Paper
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2003, Texas Instruments Incorporated
INTRODUCTION
AUC (Advanced Ultra-Low-Voltage CMOS) is the industry’s first logic family optimized at 1.8 V
and operation from 0.8 V to 2.7 V, with an input tolerance of 3.6 V. This sub-1-V product family
meets a variety of demands that have been placed on logic designers by offering low-voltage
operation, faster speed, and lower power consumption while still maintaining overall signal
integrity. AUC was designed to meet advanced system performance requirements in
applications such as portable consumer electronics, telecommunications equipment, and
high-performance workstations. AUC features include bus hold and Ioff, which protect the
device by supporting partial power-down applications.
Little Logic is a product segment of single, dual, and triple gates (1G/2G/3G) available in
several standard logic functions. The principle driving Little Logic is derived from the standard
quad gate, which once was the smallest number of gate functions you could order on one
device. By providing only the needed number of gates at the desired location, designers can
reduce board space and unnecessary routing. In addition to providing a space savings, Little
Logic devices maximize ASIC design development by providing a quick-fix solution for signal
errors.
Texas Instruments offers Little Logic devices in 5-pin SOT-23 (DBV), 5-pin SC-70 (DCK), 6-pin
SOT-23 (DBV), 6-pin SC-70 (DCK), 8-pin SM-8 (DCT), 8-pin US-8 (DCU), and the smallest
logic packages available today NanoStar (YEA) and NanoFree (YZA) packages. NanoStar
and NanoFree devices are manufactured using a Wafer Chip Scale Package (WCSP)
process, also known as die-size ball grid array (DSBGA, JEDEC MO-211) and offer a 70%
reduction in area as compared to the 5-pin SC-70 package.
Along with Little Logic, various Widebus (16-bit) and Widebus+ (32-bit) products are
offered in this family. AUC offers a propagation delay of 2 ns at 1.8 V (SN74AUC16245) with
good signal integrity.
v
PRODUCT STAGE STATEMENTS
Product stage statements are used on Texas Instruments data sheets to indicate the
development stage(s) of the product(s) specified in the data sheets.
If all products specified in a data sheet are at the same development stage, the appropriate
statement from the following list is placed in the lower left corner of the first page of the
data sheet.
PRODUCTION DATA information is current as of publication date. Products conform
to specifications per the terms of Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction
phase of development. Characteristic data and other specifications are subject to
change without notice.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these products
without notice.
If not all products specified in a data sheet are at the PRODUCTION DATA stage, then the first
statement below is placed in the lower left corner of the first page of the data sheet.
Subsequent pages of the data sheet containing PRODUCT PREVIEW information or
ADVANCE INFORMATION are then marked in the lower left-hand corner with the appropriate
statement given below:
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA
information current as of publication date. Products conform to specifications per the
terms of Texas Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction
phase of development. Characteristic data and other specifications are subject to
change without notice.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these products
without notice.
vi
General Information
AUC Single Gates
AUC Widebus
AUC Widebus+
Application Reports
Mechanical Data
1–1
Contents
Page
General Information
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Explanation of Function Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-Type Flip-Flop and Latch Signal Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Names and Package Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
1–3
1–5
1–10
1–12
1–13
1–20
ALPHANUMERIC INDEX
DEVICE
PAGE
SN74AUC1G00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
SN74AUC1G02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
SN74AUC1G04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
SN74AUC1GU04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
SN74AUC1G06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
SN74AUC1G07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
SN74AUC1G08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
SN74AUC1G14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41
SN74AUC1G17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47
SN74AUC1G32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53
SN74AUC1G66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59
SN74AUC1G79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–69
SN74AUC1G80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–75
SN74AUC1G86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–81
SN74AUC1G125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–87
POST OFFICE BOX 655303
DEVICE
PAGE
SN74AUC1G126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–93
SN74AUC1G240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–99
SN74AUC16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
SN74AUC16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
SN74AUC16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31
SN74AUC16373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–43
SN74AUC16374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–55
SN74AUC32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
SN74AUCH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
SN74AUCH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
SN74AUCH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–37
SN74AUCH16373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49
SN74AUCH16374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–61
SN74AUCH32244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
• DALLAS, TEXAS 75265
1–3
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC Council
of the Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission
(IEC) for international use.
operating conditions and characteristics (in sequence by letter symbols)
Ci
Input capacitance
The capacitance of an input terminal of the device
Cio
Input/output capacitance
The capacitance of an input/output (I/O) terminal of the device with the input conditions applied that,
according to the product specification, establishes the high-impedance state at the output
Co
Output capacitance
The capacitance of an output terminal of the device with the input conditions applied that, according
to the product specification, establishes the high-impedance state at the output
Cpd
Power dissipation capacitance
Used to determine the no-load dynamic power dissipation per logic function (see individual circuit
pages): PD = Cpd VCC2 f + ICC VCC
fmax
Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required sequence
while maintaining stable transitions of logic level at the output with input conditions established that
should cause changes of output logic level in accordance with the specification
IBHH
Bus-hold high sustaining current
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should
be measured after raising VIN to VCC and then lowering it to VIH min.
IBHL
Bus-hold low sustaining current
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be
measured after lowering VIN to GND and then raising it to VIL max.
IBHHO
Bus-hold high overdrive current
An external driver must sink at least IBHHO to switch this node from high to low.
IBHLO
Bus-hold low overdrive current
An external driver must source at least IBHLO to switch this node from low to high.
ICC
Supply current
The current into* the VCC supply terminal of an integrated circuit
∆ICC
Supply current change
The increase in supply current for each input that is at one of the specified TTL voltage levels rather
than 0 V or VCC
ICEX
Output high leakage current
The maximum leakage current into* an output that is in a high state and VO = VCC
II(hold)
Input hold current
The input current that holds the input at the previous state when the driving device goes to the
high-impedance state
*Current out of a terminal is given as a negative value.
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1–5
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
IIH
High-level input current
The current into* an input when a high-level voltage is applied to that input
IIL
Low-level input current
The current into* an input when a low-level voltage is applied to that input
Ioff
Input/output power-off leakage current
The maximum leakage current into* an input or output terminal of the device with the specified voltage
applied to the terminal and VCC = 0 V
IOH
High-level output current
The current into* an output with input conditions applied that, according to the product specification,
establishes a high level at the output
IOHS
Static high-level output current
The static and testable current into* a DOC circuit output with input conditions applied that, according
to the product specifications, establishes a static high level at the output. The dynamic drive current is
not specified for devices with DOC circuit outputs because of its transient nature; however, it is similar
to the dynamic drive current that is available from a high-drive (nondamping resistor) standard-output
device.
IOL
Low-level output current
The current into* an output with input conditions applied that, according to the product specification,
establishes a low level at the output
IOLS
Static low-level output current
The static and testable current into* a DOC circuit output with input conditions applied that, according
to the product specifications, establishes a static low level at the output. The dynamic drive current is
not specified for devices with DOC circuit outputs because of its transient nature; however, it is similar
to the dynamic drive current that is available from a high-drive (nondamping resistor) standard-output
device.
IOZ
Off-state (high-impedance state) output current (of a 3-state output)
The current flowing into* an output with the input conditions applied that, according to the product
specification, establishes the high-impedance state at the output
IOZPD
Power-down off-state (high-impedance state) output current (of a 3-state output)
The current flowing into* an output that is switched to or held in the high-impedance state as the device
is being powered down to VCC = 0 V
IOZPU
Power-up off-state (high-impedance state) output current (of a 3-state output)
The current flowing into* an output that is switched to or held in the high-impedance state as the device
is being powered up from VCC = 0 V
jitter
Jitter
Dispersion of a time parameter of the pulse waveforms in a pulse train with respect to a reference time,
interval, or duration. Unless otherwise specified by a mathematical adjective, peak-to-peak jitter is
assumed.
jitter(RMS) RMS jitter
The root mean square jitter, one-sixth of the maximum peak-to-peak jitter
*Current out of a terminal is given as a negative value.
DOC is a trademark of Texas Instruments.
1–6
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GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
SR
Slew rate
The average rate of change (i.e., V/ns) for a waveform that is changing from one defined logic level to
another defined logic level
ta
Access time
The time interval between the application of a specified input pulse and the availability of valid signals
at an output
tc
Clock cycle time
Clock cycle time is 1 / fmax
tdis
Disable time (of a 3-state or open-collector output)
The propagation time between the specified reference points on the input and output voltage
waveforms with the output changing from either of the defined active levels (high or low) to the
high-impedance (off) state
NOTE: For 3-state outputs, tdis = tPHZ or tPLZ. Open-collector outputs change only if they are low at
the time of disabling, so tdis = tPLH.
ten
Enable time (of a 3-state or open-collector output)
The propagation time between the specified reference points on the input and output voltage
waveforms with the output changing from the high-impedance (off) state to either of the defined active
levels (high or low)
NOTE: In the case of memories, this is the access time from an enable input (e.g., OE). For 3-state
outputs, ten = tPZH or tPZL. Open-collector outputs change only if they are responding to data
that would cause the output to go low, so ten = tPHL.
tf
Fall time
The time interval between two reference points (90% and 10%, unless otherwise specified) on a
waveform that is changing from the defined high level to the defined low level
th
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal
NOTES: 1. The hold time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which correct operation of the digital circuit is to be expected.
2. The hold time may have a negative value, in which case, the minimum limit defines the
longest interval (between the release of the signal and the active transition) for which correct
operation of the digital circuit is to be expected.
tpd
Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with the
output changing from one defined level (high or low) to the other defined level (tpd = tPHL or tPLH)
tPHL
Propagation delay time, high-to-low level output
The time between the specified reference points on the input and output voltage waveforms with the
output changing from the defined high level to the defined low level
tPHZ
Disable time (of a 3-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms
with the 3-state output changing from the defined high level to the high-impedance (off) state
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1–7
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
tPLH
Propagation delay time, low-to-high level output
The time between the specified reference points on the input and output voltage waveforms with the
output changing from the defined low level to the defined high level
tPLZ
Disable time (of a 3-state output) from low level
The time interval between the specified reference points on the input and the output voltage waveforms
with the 3-state output changing from the defined low level to the high-impedance (off) state
tPZH
Enable time (of a 3-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms
with the 3-state output changing from the high-impedance (off) state to the defined high level
tPZL
Enable time (of a 3-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms
with the 3-state output changing from the high-impedance (off) state to the defined low level
tr
Rise time
The time interval between two reference points (10% and 90%, unless otherwise specified) on a
waveform that is changing from the defined low level to the defined high level
tsk(i)
Input skew
The difference between any two propagation delay times that originate at different inputs and terminate
at a single output. Input skew describes the ability of a device to manipulate (stretch, shrink, or chop)
a clock signal. This is typically accomplished with a multiple-input gate wherein one of the inputs acts
as a controlling signal to pass the clock through. tsk(i) describes the ability of the gate to shape the pulse
to the same duration, regardless of the input used as the controlling input.
tsk(l)
Limit skew
The difference between 1) the greater of the maximum specified values of tPLH and tPHL and 2) the
lesser of the minimum specified values of tPLH and tPHL. Limit skew is not directly observed on a device.
It is calculated from the data-sheet limits for tPLH and tPHL. tsk(l) quantifies for the designer how much
variation in propagation delay time is induced by operation over the entire ranges of supply voltage,
temperature, output load, and other specified operating conditions. Specified as such, tsk(l) also
accounts for process variation. In fact, all other skew specifications [tsk(o), tsk(i), tsk(p), and tsk(pr)] are
subsets of tsk(l); they are never greater than tsk(l).
tsk(o)
Output skew
The skew between specified outputs of a single logic device with all driving inputs connected together
and the outputs switching in the same direction while driving identical specified loads
tsk(p)
Pulse skew
The magnitude of the time difference between the propagation delay times, tPHL and tPLH, when a single
switching input causes one or more outputs to switch
tsk(pr)
Process skew
The magnitude of the difference in propagation delay times between corresponding terminals of two
logic devices when both logic devices operate with the same supply voltages, operate at the same
temperature, and have identical package styles, identical specified loads, identical internal logic
functions, and the same manufacturer
1–8
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GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
tsu
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent
active transition at another specified input terminal
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which correct operation of the digital circuit is specified.
2. The setup time may have a negative value, in which case the minimum limit defines the
longest interval (between the active transition and the application of the other signal) for which
correct operation of the digital circuit is specified.
tw
Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse
waveform
VIH
High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to represent
the binary variables
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is to be expected.
VIK
Input clamp voltage
The maximum voltage developed across an input diode with test current applied
VIL
Low-level input voltage
An input voltage within the less positive (more negative) of the two ranges of values used to represent
the binary variables
NOTE: A maximum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is to be expected.
VOH
High-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
establishes a high level at the output
VOHS
Static high-level output voltage
The static and testable voltage at a DOC circuit output with input conditions applied that, according to
the product specifications, establishes a static high level at the output. The dynamic drive voltage is not
specified for devices with DOC circuit outputs because of its transient nature.
VOL
Low-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
establishes a low level at the output
VOLS
Static low-level output voltage
The static and testable voltage at a DOC circuit output with input conditions applied that, according to
the product specifications, establishes a static low level at the output. The dynamic drive voltage is not
specified for devices with DOC circuit outputs because of its transient nature.
VT+
Positive-going input threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage rises from a level below the negative-going threshold voltage, VT–
VT–
Negative-going input threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage falls from a level above the positive-going threshold voltage, VT+
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1–9
EXPLANATION OF FUNCTION TABLES
The following symbols are used in function tables on TI data sheets:
H
L
↑
↓
X
Z
a...h
Q0
Q0
=
=
=
=
=
=
=
=
=
=
=
Qn
=
=
=
Toggle
=
high level (steady state)
low level (steady state)
transition from low to high level
transition from high to low level
value/level or resulting value/level is routed to indicated destination
value/level is re-entered
irrelevant (any input, including transitions)
off (high-impedance) state of a 3-state output
the level of steady-state inputs A through H, respectively
level of Q before the indicated steady-state input conditions were established
complement of Q0 or level of Q before the indicated steady-state input
conditions were established
level of Q before the most recent active transition indicated by ↓ or ↑
one high-level pulse
one low-level pulse
each output changes to the complement of its previous level on each active
transition indicated by ↓ or ↑
If, in the input columns, a row contains only the symbols H, L, and/or X, this means the indicated output is valid
whenever the input configuration is achieved and regardless of the sequence in which it is achieved. The output
persists so long as the input configuration is maintained.
If, in the input columns, a row contains H, L, and/or X together with ↑ and/or ↓, this means the output is valid whenever
the input configuration is achieved but the transition(s) must occur following the achievement of the steady-state
levels. If the output is shown as a level (H, L, Q0, or Q0), it persists so long as the steady-state input levels and the
levels that terminate indicated transitions are maintained. Unless otherwise indicated, input transitions in the opposite
direction to those shown have no effect at the output. (If the output is shown as a pulse,
or
, the pulse follows
the indicated input transition and persists for an interval dependent on the circuit.)
1–10
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EXPLANATION OF FUNCTION TABLES
Among the most complex function tables are those of the shift registers. These embody most of the symbols used
in any of the function tables, plus more. Below is the function table of a 4-bit bidirectional universal shift register.
FUNCTION TABLE
INPUTS
CLEAR
MODE
S1
S0
CLOCK
OUTPUTS
SERIAL
PARALLEL
LEFT
RIGHT
A
B
C
D
QA
QB
QC
QD
L
X
X
X
X
X
X
X
X
X
L
L
L
L
H
X
X
L
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
H
H
↑
X
X
a
b
c
d
a
b
c
d
H
L
H
↑
X
H
H
H
H
H
H
QAn
QBn
QCn
H
L
H
↑
X
L
L
L
L
L
L
H
L
↑
H
X
X
X
X
X
QBn
QAn
QCn
QBn
QDn
QCn
H
H
H
L
↑
L
X
X
X
X
X
QBn
QCn
QDn
L
H
L
L
X
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
The first line of the table represents a synchronous clearing of the register and says that if clear is low, all four outputs
will be reset low regardless of the other inputs. In the following lines, clear is inactive (high) and so has no effect.
The second line shows that so long as the clock input remains low (while clear is high), no other input has any effect
and the outputs maintain the levels they assumed before the steady-state combination of clear high and clock low
was established. Since on other lines of the table only the rising transition of the clock is shown to be active, the second
line implicitly shows that no further change in the outputs occurs while the clock remains high or on the high-to-low
transition of the clock.
The third line of the table represents synchronous parallel loading of the register and says that if S1 and S0 are both
high then, without regard to the serial input, the data entered at A is at output QA, data entered at B is at QB, and so
forth, following a low-to-high clock transition.
The fourth and fifth lines represent the loading of high- and low-level data, respectively, from the shift-right serial input
and the shifting of previously entered data one bit; data previously at QA is now at QB, the previous levels of QB and
QC are now at QC and QD, respectively, and the data previously at QD is no longer in the register. This entry of serial
data and shift takes place on the low-to-high transition of the clock when S1 is low and S0 is high and the levels at
inputs A through D have no effect.
The sixth and seventh lines represent the loading of high- and low-level data, respectively, from the shift-left serial
input and the shifting of previously entered data one bit; data previously at QB is now at QA, the previous levels of
QC and QD are now at QB and QC, respectively, and the data previously at QA is no longer in the register. This entry
of serial data and shift takes place on the low-to-high transition of the clock when S1 is high and S0 is low and the
levels at inputs A through D have no effect.
The last line shows that as long as both inputs are low, no other input has any effect and, as in the second line, the
outputs maintain the levels they assumed before the steady-state combination of clear high and both mode inputs
low was established.
The function table functional tests do not reflect all possible combinations or sequential modes.
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1–11
D-TYPE FLIP-FLOP AND LATCH SIGNAL CONVENTIONS
It is normal TI practice to name the outputs and other inputs of a D-type flip-flop or latch and to draw its logic symbol
based on the assumption of true data (D) inputs. Outputs that produce data in phase with the data inputs are called
Q and those producing complementary data are called Q. An input that causes a Q output to go high or a Q output
to go low is called preset (PRE). An input that causes a Q output to go high or a Q output to go low is called clear
(CLR). Bars are used over these pin names (PRE and CLR) if they are active low.
The devices on several data sheets are second-source designs, and the pin-name conventions used by the original
manufacturers have been retained. That makes it necessary to designate the inputs and outputs of the inverting
circuits D and Q.
In some applications, it may be advantageous to redesignate the data input from D to D or vice versa. In that case,
all the other inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbols. Arbitrary pin numbers are shown.
1
PRE
C
D
2
3
4
CLR
5
S
1
Q
C1
CLR
C
1D
6
R
D
Q
2
3
4
PRE
R
5
C1
1D
6
S
Latch
1
PRE
CLK
D
3
4
CLR
1
Q
C1
1D
CLR
CLK
6
R
Q
Latch
5
S
2
Q
D
Q
3
4
PRE
Flip-Flop
5
R
2
Q
C1
1D
6
Q
S
Flip-Flop
The figures show that when Q and Q exchange names, the preset and clear pins also exchange names. The polarity
indicators ( ) on PRE and CLR remain, as these inputs are still active low, but the presence or absence of the polarity
indicator changes at D (or D), Q, and Q. Pin 5 (Q or Q) is still in phase with the data input (D or D); their active levels
change together.
1–12
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DEVICE NAMES AND PACKAGE DESIGNATORS
Example:
1
16
1
2
3
4
5
6
SN – Standard Prefix
SNJ – Conforms to MIL-PRF-38535 (QML)
54 – Military
74 – Commercial
245
6
Blank = No Special Features
C – Configurable VCC (LVCC)
D – Level-Shifting Diode (CBTD)
H – Bus Hold (ALVCH)
K – Undershoot-Protection Circuitry (CBTK)
R – Damping Resistor on Inputs/Outputs (LVCR)
S – Schottky Clamping Diode (CBTS)
Z – Power-Up 3-State (LVCZ)
Bit Width
Examples:
Blank = Gates, MSI, and Octals
1G – Single Gate
2G – Dual Gate
3G – Triple Gate
8 – Octal IEEE 1149.1 (JTAG)
16 – Widebus (16, 18, and 20 bit)
18 – Widebus IEEE 1149.1 (JTAG)
32 – Widebus+ (32 and 36 bit)
9
10
Blank = No Options
2 – Series Damping Resistor on Outputs
4 – Level Shifter
25 – 25-Ω Line Driver
244 – Noninverting Buffer/Driver
374 – D-Type Flip-Flop
573 – D-Type Transparent Latch
640 – Inverting Transceiver
Device Revision
Examples:
9
8
R
Function
Examples:
8
7
GQL
Options
Examples:
7
Blank = Transistor-Transistor Logic (TTL)
ABT – Advanced BiCMOS Technology
ABTE/ETL – Advanced BiCMOS Technology/
Enhanced Transceiver Logic
AC/ACT – Advanced CMOS Logic
AHC/AHCT – Advanced High-Speed CMOS Logic
ALB – Advanced Low-Voltage BiCMOS
ALS – Advanced Low-Power Schottky Logic
ALVC – Advanced Low-Voltage CMOS Technology
ALVT – Advanced Low-Voltage BiCMOS Technology
AS – Advanced Schottky Logic
AUC – Advanced Ultra Low-Voltage CMOS Logic
AVC – Advanced Very Low-Voltage CMOS Logic
BCT – BiCMOS Bus-Interface Technology
CBT – Crossbar Technology
CBTLV – Low-Voltage Crossbar Technology
CD4000 – CMOS B-Series Integrated Circuits
F – F Logic
FB – Backplane Transceiver Logic/Futurebus+
FCT – Fast CMOS TTL Logic
GTL – Gunning Transceiver Logic
GTLP – Gunning Transceiver Logic Plus
HC/HCT – High-Speed CMOS Logic
HSTL – High-Speed Transceiver Logic
LS – Low-Power Schottky Logic
LV – Low-Voltage CMOS Technology
LVC – Low-Voltage CMOS Technology
LVT – Low-Voltage BiCMOS Technology
PCA/PCF – I2C Inter-Integrated Circuit Applications
S – Schottky Logic
SSTL/SSTV – Stub Series-Terminated Logic
TVC – Translation Voltage Clamp Logic
VME – VERSAmodule Eurocard Bus Technology
Special Features
Examples:
5
H
Family
Examples:
4
AUC
Temperature Range
Examples:
3
74
Standard Prefix
Examples:
2
SN
Blank = No Revision
Letter Designator A–Z
Packages
Commercial: D, DW – Small-Outline Integrated Circuit (SOIC)
DB, DBQ, DCT, DL – Shrink Small-Outline Package
(SSOP)
DBB, DGV – Thin Very Small-Outline Package (TVSOP)
DBQ – Quarter-Size Small-Outline Package (QSOP)
DBV, DCK, DCY, PK – Small-Outline Transistor (SOT)
DCU – Very Thin Shrink Small-Outline Package (VSSOP)
DGG, PW – Thin Shrink Small-Outline Package (TSSOP)
FN – Plastic Leaded Chip Carrier (PLCC)
GGM, GKE, GKF, ZKE, ZKF – MicroStar BGA
Low-Profile Fine-Pitch Ball Grid Array (LFBGA)
GQL, GQN, ZQL, ZQN – MicroStar Jr.
Very-Thin-Profile Fine-Pitch Ball Grid Array (VFBGA)
N, NT, P – Plastic Dual-In-Line Package (PDIP)
NS, PS – Small-Outline Package (SOP)
PAG, PAH, PCA, PCB, PM, PN, PZ – Thin Quad
Flatpack (TQFP)
PH, PQ, RC – Quad Flatpack (QFP)
PZA – Low-Profile Quad Flatpack (LQFP)
RGY – Quad Flatpack No Lead (QFN)
YEA, YZA – NanoStar and NanoFree
Die-Size Ball Grid Array (DSBGA†)
Military:
FK – Leadless Ceramic Chip Carrier (LCCC)
GB – Ceramic Pin Grid Array (CPGA)
HFP, HS, HT, HV – Ceramic Quad Flatpack (CQFP)
J, JT – Ceramic Dual-In-Line Package (CDIP)
W, WA, WD – Ceramic Flatpack (CFP)
10 Tape and Reel
Devices in the DB and PW package types include the R designation
for reeled product. Existing product inventory designated LE may
remain, but all products are being converted to the R designation.
Examples:
Old Nomenclature – SN74LVTxxxDBLE
New Nomenclature – SN74LVTxxxADBR
LE – Left Embossed (valid for DB and PW packages only)
R – Standard (valid for all surface-mount packages)
There is no functional difference between LE and R designated
products, with respect to the carrier tape, cover tape, or reels used.
† DSBGA is the JEDEC reference for wafer chip scale package (WCSP).
POST OFFICE BOX 655303
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1–13
DEVICE NAMES AND PACKAGE DESIGNATORS
SPECIAL FEATURES
Special features of TI standard logic devices are designated in the device name by using abbreviations that are listed
below and are defined in the following paragraphs.
Blank – No special features
C – Configurable VCC
D – Level-shifting diode
H – Bus hold
K – Undershoot protection circuitry
R – Damping resistor on inputs/outputs
S – Schottky clamping diode
Z – Power-up 3-state
configurable VCC (C)
Configurable VCC is a feature of devices that are designed as dual-supply-level shifters, e.g., SN74LVCC3245
and SN74LVCC4245. Using these devices allows the user to select the voltage to be applied to VCC on the
B-port side (VCCB) and/or A-port side (VCCA) (see Figure 1).
’4245 Pinning
VCCA
DIR
A1
•
•
•
•
•
•
•
GND
GND
’245 Pinning
’424
VCCB
VCCB
OE
B1
•
•
•
•
•
•
•
GND
’LVCC3245
’LVCC4245
No Internal Connection
VCCA
A PORT
VCCB
B PORT
TRANSLATION
(BIDIRECTIONAL FLOW)
SN74LVCC3245A
2.3 V–3.6 V
3 V–5.5 V
2.5 V to 3.3 V or 3.3 V to 5 V
SN74LVCC4245A
5V
3 V–5 V
5 V to 3.3 V
Figure 1
Designers can use these devices in existing single-voltage systems. When systems become mixed-voltage
systems, these devices do not need to be replaced, allowing for quicker time to market.
1–14
POST OFFICE BOX 655303
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DEVICE NAMES AND PACKAGE DESIGNATORS
level-shifting diode (D)
Devices with D as part of the device name have an integrated diode in the VCC line. Examples are crossbar
switches SN74CBT3306 (without the integrated diode) and SN74CBTD3306 (with integrated diode). These
devices allow 5-V to 3.3-V translation if no drive is required. Bidirectional data transmission is allowed between
5-V TLL and 3.3-V LVTTL, whereas only unidirectional level translation is allowed from 5-V CMOS to 3.3-V
LVTTL (see Figure 2). The integrated diode saves designers both board space and component cost.
VCC = 5 V
CBTD
CBT
IN/OUT
3-V
System
5-V
System
– µP
– µC
– DSP
– ASIC
– RAM
5-V to 3-V Translation
5
SN74CBT
VO – V
4
SN74CBTD
3
2
1
0
1
2
3
VI – V
4
5
Figure 2
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1–15
DEVICE NAMES AND PACKAGE DESIGNATORS
bus hold (H)
A bus-hold circuit is implemented in selected logic families to help solve the floating-input problem. The bus-hold
circuit maintains the last known input state into the device and, as an additional benefit, pullup or pulldown
resistors are no longer needed (see Figure 3). The advantages of devices with this circuit are board space
savings and reduced component costs.
Device
VCC
Bus-Hold Circuit
Local
TTL
Figure 3
damping resistor on inputs/outputs (R)
Series damping resistors (SDR), denoted R in the device name, are included at all input and output ports of
designated devices (see Figure 4). The SDRs limit the current, thereby reducing noise from signal undershoot
and overshoot. Additionally, SDRs make line termination easier, which improves signal quality by reducing
ringing and line reflections.
VCC
SDR
Output
Figure 4
schottky clamping diode (S)
Schottky diodes are incorporated in inputs and outputs to clamp undershoot (see Figure 5). The Schottky diodes
prevent undershoot signals from dropping below a specified level, reducing the possibility of damage to
connected devices by large undershoots that can occur without the Schottky diodes.
1A
1B
1OE
Figure 5
1–16
POST OFFICE BOX 655303
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DEVICE NAMES AND PACKAGE DESIGNATORS
undershoot-protection circuitry (K)
TI undershoot-protection circuitry (UPC) functions similarly to Schottky clamping diodes, with one major
difference. UPC is an active clamping structure. UPC can greatly reduce undershoot duration, increasing
protection to connected devices that otherwise can be damaged (see Figure 6).
VCC
VCC
UC†
UC†
1A1
1B1
VCC
VCC
UC†
UC†
1A8
1B8
1OE
† Undershoot control circuit
Undershoot Clamping
Voltage
Input
Schottky Output
UPC Output
Time
Figure 6
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1–17
DEVICE NAMES AND PACKAGE DESIGNATORS
power-up 3-state (Z)
The power-up 3-state feature ensures valid output levels during power up and the valid high-impedance state
during power down. OE must be tied high (to VCC) through an external pullup resistor (see Figure 7).
VCC
OE
PU3
OE
Control
Output
Figure 7
1–18
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DEVICE NAMES AND PACKAGE DESIGNATORS
NOTIFICATION OF PACKAGE NOMENCLATURE ALIAS
(for Standard Linear and Logic device names of more than 18 characters)
TI is converting from its current order-entry system to a more advanced system. This conversion requires
modifications, both internal and external, to TI’s current business processes. This new system will ultimately provide
significant improvements to all facets of TI’s business – from production, to order entry, to logistics. One change
required is a limitation of TI part numbers to no more than 18 characters in length. Based on customer inputs, Standard
Linear and Logic determined the least disruptive implementations as outlined below:
1. Package alias
TI will use a package alias to denote specific package types for devices currently exceeding 18 characters in
length. Table 1 shows a mapping of package codes to an alias single-character representation.
Table 1
CURRENT
PACKAGE CODE
ALIAS
DL
L
DGG/DBB
G
DGV
V
GKE/GKF/GQL
K
DLR
LR – tape/reel packing
DGGR/DBBR
GR – tape/reel packing
DGVR
VR – tape/reel packing
GKER/GKFR/GQLR
KR – tape/reel packing
Current: SN74 ALVCH 162269A DGGR
New:
SN74 ALVCH 162269A GR1
2. Resistor-option nomenclature
For devices with names of more than 18 characters with input and output resistors, TI will adopt a simplified
nomenclature to designate the resistor option. This will eliminate the redundant “2” (designating output
resistors) when the part number also contains an “R” (designating input/output resistors).
Input/Output Resistor
Output Resistor
Current: SN74 ALVCH R 16 2 245 A
New:
SN74 ALVCH R 16 245 A
There is no change to the device or data-sheet electrical parameters. The packages involved and the changes in
nomenclature are noted in Table 1.
These nomenclature changes are being gradually implemented. The first customer-visible conversions for TI logic
devices will be made to data sheets. Over the next few months, TI logic data sheets will be updated. These changes
in device nomenclature do not reflect a change in device performance or process characteristics.
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1–19
THERMAL INFORMATION
In digital-system design, consideration must be given to thermal management of components. The small size of
packages makes this more critical. Figures 8–16 show the high-effect (high-K) thermal resistance for the
5-, 14-, 16-, 20-, 24-, 48-, 56-, 64-, and 80-pin packages for various rates of airflow calculated in accordance with
JESD 51-7.
The thermal resistances in Figures 8–16 can be used to approximate typical and maximum virtual junction
temperatures. In general, the junction temperature for any device can be calculated using the following equation:
T J + R qJA
PT ) TA
Where:
TJ
RθJA
PT
TA
= virtual junction temperature (°C)
= thermal resistance, junction to free air (°C/W)
= total power dissipation of the device (W)
= free-air temperature (°C)
DCK
240
220
200
180
DBV
160
140
120
100
80
60
40
20
0
R JA – Junction-to-Ambient Thermal Resistance – °C/W
5-Pin Packages
260
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
θ
θ
R JA – Junction-to-Ambient Thermal Resistance – °C/W
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
0
100
200
300
400
500
14-Pin Packages
130
120
110
DGV
PW
100
90
80
DB
70
D
60
50
40
30
20
10
0
0
200
300
Air Velocity – ft/min
Air Velocity – ft/min
Figure 8
1–20
100
Figure 9
POST OFFICE BOX 655303
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400
500
THERMAL INFORMATION
120
110
DGV
PW
100
90
80
70
DB
D
60
50
40
30
20
10
0
R JA – Junction-to-Ambient Thermal Resistance – °C/W
16-Pin Packages
130
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
θ
θ
R JA – Junction-to-Ambient Thermal Resistance – °C/W
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
0
100
200
300
400
500
20-Pin Packages
130
120
110
100
90
80
70
DGV
PW
60
DB
50
DW
40
30
20
10
0
0
100
Air Velocity – ft/min
110
100
90
80
PW
DGV
70
60
DB
50
40
DW
30
20
10
0
R JA – Junction-to-Ambient Thermal Resistance – °C/W
120
300
500
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
θ
θ
R JA – Junction-to-Ambient Thermal Resistance – °C/W
24-Pin Packages
130
200
400
Figure 11
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
100
300
Air Velocity – ft/min
Figure 10
0
200
400
500
48-Pin Packages
190
180
170
160
150
140
130
120
110
100
90
80
70
DGG
DL
DGV
60
50
40
30
0
Air Velocity – ft/min
100
200
300
400
500
Air Velocity – ft/min
Figure 12
Figure 13
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1–21
THERMAL INFORMATION
60
55
DGG
50
45
DL
40
DGV
35
30
25
20
15
10
5
0
R JA – Junction-to-Ambient Thermal Resistance – °C/W
56-Pin Packages
65
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
64-Pin Packages
65
60
55
50
0
100
200
300
400
500
DGG
45
40
35
30
25
20
15
10
θ
θ
R JA – Junction-to-Ambient Thermal Resistance – °C/W
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
5
0
0
100
200
Air Velocity – ft/min
Air Velocity – ft/min
Figure 14
Figure 15
θ
R JA – Junction-to-Ambient Thermal Resistance – °C/W
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
80-Pin Packages
65
60
55
DBB
50
45
40
35
30
25
20
15
10
5
0
0
100
200
300
400
Air Velocity – ft/min
Figure 16
1–22
300
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
500
400
500
General Information
AUC Single Gates
AUC Widebus
AUC Widebus+
Application Reports
Mechanical Data
2–1
Contents
Page
AUC Single Gates
2–2
SN74AUC1G00
Single 2-Input Positive-NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
SN74AUC1G02
Single 2-Input Positive-NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
SN74AUC1G04
Single Inverter Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
SN74AUC1GU04
Single Inverter Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
SN74AUC1G06
Single Inverter Buffer/Driver With Open-Drain Output . . . . . . . . . . . . . . . . . . . . . 2–25
SN74AUC1G07
Single Buffer/Driver With Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
SN74AUC1G08
Single 2-Input Positive-AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
SN74AUC1G14
Single Schmitt-Trigger Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41
SN74AUC1G17
Single Schmitt-Trigger Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47
SN74AUC1G32
Single 2-Input Positive-OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53
SN74AUC1G66
Single Bilateral Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59
SN74AUC1G79
Single Positive-Edge-Triggered D-Type Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . 2–69
SN74AUC1G80
Single Positive-Edge-Triggered D-Type Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . 2–75
SN74AUC1G86
Single 2-Input Exclusive-OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–81
SN74AUC1G125
Single Bus Buffer Gate With 3-State Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–87
SN74AUC1G126
Single Bus Buffer Gate With 3-State Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–93
SN74AUC1G240
Single Buffer/Driver With 3-State Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–99
SN74AUC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES368J – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.2 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
A
B
GND
1
5
VCC
4
Y
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
B
A
3 4
Y
2
1 5
VCC
description /ordering information
This single 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G00YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G00YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G00DBVR
U00_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G00DCKR
UA_
_ _ _UA_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–3
SN74AUC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES368J – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
logic diagram (positive logic)
A
B
1
4
2
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES368J – SEPTEMBER 2001 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
MIN
MAX
0.8
2.7
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
Low-level input voltage
VI
VO
Input voltage
V
1.7
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.7
Output voltage
IOL
∆ ∆
∆t/∆v
High-level output current
Low-level output current
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
mA
5
9
VCC = 0.8 V to 1.95 V
VCC = 2.3 V to 2.7 V
Input transition rise or fall rate
V
0
VCC = 0.8 V
VCC = 1.1 V
IOH
V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
UNIT
20
ns/V
10
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
ICC
Ci
A or B input
VCC
0.8 V to 2.7 V
MIN
MAX
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
VCC–0.1
0.8 V
0.8 V
TYP†
V
0 to 2.7 V
±5
µA
0
±10
µA
10
µA
0.8 V to 2.7 V
2.5 V
3
pF
† All typical values are at TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
SN74AUC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES368J – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
TYP
tpd
A or B
4.7
Y
† This information was not available at the time of publication.
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
0.9
3.2
0.5
2.2
†
†
†
†
†
UNIT
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.7
1.3
2.2
0.5
2
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–6
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
15
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
15
• DALLAS, TEXAS 75265
15
VCC = 1.8 V
TYP
15
VCC = 2.5 V
TYP
19
UNIT
pF
SN74AUC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES368J – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–7
SN74AUC1G02
SINGLE 2-INPUT POSITIVE-NOR GATE
SCES369J – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.4 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
A
B
GND
1
5
VCC
4
Y
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
B
A
3 4
Y
2
1 5
VCC
description /ordering information
This single 2-input positive-NOR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC1G02 performs the Boolean function Y = A + B or Y = A • B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G02YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G02YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G02DBVR
U02_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G02DCKR
UB_
_ _ _UB_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–9
SN74AUC1G02
SINGLE 2-INPUT POSITIVE-NOR GATE
SCES369J – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUTS
A
B
OUTPUT
Y
H
X
L
X
H
L
L
L
H
logic diagram (positive logic)
1
4
A
B
2
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G02
SINGLE 2-INPUT POSITIVE-NOR GATE
SCES369J – SEPTEMBER 2001 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
MIN
MAX
0.8
2.7
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
Low-level input voltage
VI
VO
Input voltage
V
1.7
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.7
Output voltage
IOL
∆ ∆
∆t/∆v
High-level output current
Low-level output current
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
mA
5
9
VCC = 0.8 V to 1.95 V
VCC = 2.3 V to 2.7 V
Input transition rise or fall rate
V
0
VCC = 0.8 V
VCC = 1.1 V
IOH
V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
UNIT
20
ns/V
10
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
ICC
Ci
A or B input
VCC
0.8 V to 2.7 V
MIN
MAX
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
VCC–0.1
0.8 V
0.8 V
TYP†
V
0 to 2.7 V
±5
µA
0
±10
µA
10
µA
0.8 V to 2.7 V
2.5 V
3
pF
† All typical values are at TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–11
SN74AUC1G02
SINGLE 2-INPUT POSITIVE-NOR GATE
SCES369J – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
TYP
tpd
A or B
4.6
Y
† This information was not available at the time of publication.
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
0.9
3.2
0.5
2.2
†
†
†
†
†
UNIT
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.7
1.3
2.4
0.5
2.1
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–12
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
15
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
15
• DALLAS, TEXAS 75265
15
VCC = 1.8 V
TYP
15
VCC = 2.5 V
TYP
19
UNIT
pF
SN74AUC1G02
SINGLE 2-INPUT POSITIVE-NOR GATE
SCES369J – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–13
SN74AUC1G04
SINGLE INVERTER GATE
SCES370J – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.2 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
NC
A
GND
1
5
VCC
4
Y
2
3
NC – No internal connection
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
A
DNU
3 4
Y
2
1 5
VCC
DNU – Do not use
description/ordering information
This single inverter gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The SN74AUC1G04 performs the Boolean function Y = A.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G04YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G04YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G04DBVR
U04_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G04DCKR
UC_
_ _ _UC_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–15
SN74AUC1G04
SINGLE INVERTER GATE
SCES370J – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
A
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G04
SINGLE INVERTER GATE
SCES370J – SEPTEMBER 2001 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
MIN
MAX
0.8
2.7
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
Low-level input voltage
VI
VO
Input voltage
V
1.7
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.7
Output voltage
IOL
∆ ∆
∆t/∆v
High-level output current
Low-level output current
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
mA
5
9
VCC = 0.8 V to 1.95 V
VCC = 2.3 V to 2.7 V
Input transition rise or fall rate
V
0
VCC = 0.8 V
VCC = 1.1 V
IOH
V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
UNIT
20
ns/V
5
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
ICC
Ci
A input
VCC
0.8 V to 2.7 V
MIN
MAX
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
VCC–0.1
0.8 V
0.8 V
TYP†
V
0 to 2.7 V
±5
µA
0
±10
µA
10
µA
0.8 V to 2.7 V
2.5 V
3
pF
† All typical values are at TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–17
SN74AUC1G04
SINGLE INVERTER GATE
SCES370J – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 0.8 V
TO
(OUTPUT)
VCC = 1.2 V
± 0.1 V
TYP
tpd
A
4.4
Y
† This information was not available at the time of publication.
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
0.8
3
0.5
2
†
†
†
†
†
UNIT
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.6
1.2
2.2
0.5
1.9
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–18
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
14
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
14
• DALLAS, TEXAS 75265
14
VCC = 1.8 V
TYP
14
VCC = 2.5 V
TYP
19
UNIT
pF
SN74AUC1G04
SINGLE INVERTER GATE
SCES370J – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–19
SN74AUC1GU04
SINGLE INVERTER GATE
SCES371G – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Sub 1-V Operable
Max tpd of 2.4 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Unbuffered Output
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
NC
A
GND
1
5
VCC
4
Y
2
3
NC – No internal connection
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
A
DNU
3 4
Y
2
1 5
VCC
DNU – Do not use
description/ordering information
This single inverter gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The SN74AUC1GU04 contains one inverter with an unbuffered output and performs the Boolean function Y = A.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1GU04YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1GU04YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1GU04DBVR
UU4_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1GU04DCKR
UD_
_ _ _UD_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–21
SN74AUC1GU04
SINGLE INVERTER GATE
SCES371G – SEPTEMBER 2001 – REVISED DECEMBER 2002
logic diagram (positive logic)
A
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
VO
Output voltage
IO = –100 mA
IO = 100 mA
High-level input voltage
Input voltage
VCC = 0.8 V
VCC = 1.1 V
IOH
IOL
∆t/∆v
High-level output current
Low-level output current
MIN
MAX
0.8
2.7
0.65 × VCC
V
V
0.35 × VCC
V
0
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
UNIT
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2–22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1GU04
SINGLE INVERTER GATE
SCES371G – SEPTEMBER 2001 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
ICC
A input
TYP†
MIN
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI = VCC or GND,
IO = 0
Ci
VI = VCC or GND
† All typical values are at TA = 25°C.
UNIT
V
0 to 2.7 V
±5
µA
0.8 V to 2.7 V
10
µA
2.5 V
3
pF
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
A
Y
1.9
0.6
2.5
0.6
1.7
‡
‡
‡
‡
‡
tpd
UNIT
ns
‡ This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.6
1.1
2.4
0.5
2.1
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
4
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
4
• DALLAS, TEXAS 75265
4
VCC = 1.8 V
TYP
4
VCC = 2.5 V
TYP
5
UNIT
pF
2–23
SN74AUC1GU04
SINGLE INVERTER GATE
SCES371G – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
2–24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES372G – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
NC
A
GND
1
5
VCC
4
Y
2
3
NC – No internal connection
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
A
DNU
3 4
Y
2
1 5
VCC
DNU – Do not use
description/ordering information
This single inverter buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to
1.95-V VCC operation.
The output of the SN74AUC1G06 is open drain and can be connected to other open-drain outputs to implement
active-low wired-OR or active-high wired-AND functions.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G06YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G06YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G06DBVR
U06_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G06DCKR
UT_
_ _ _UT_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–25
SN74AUC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES372G – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
A
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES372G – SEPTEMBER 2001 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
Low-level input voltage
VI
VO
Input voltage
MAX
0.8
2.7
V
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
∆t/∆v
Input transition rise or fall rate
V
0.7
0
3.6
V
0
2.7
V
VCC = 0.8 V
VCC = 1.1 V
Low-level output current
V
1.7
Output voltage
IOL
UNIT
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
MIN
0.7
3
VCC = 1.4 V
VCC = 1.65 V
5
VCC = 2.3 V
VCC = 0.8 V to 1.6 V
9
mA
8
20
ns/V
10
VCC = 1.65 V
VCC = 2.3 V
5
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOL = 100 µA
IOL = 0.7 mA
VOL
II
Ioff
A input
MAX
UNIT
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
0 to 2.7 V
±5
µA
0
±10
µA
0.8 V to 2.7 V
10
µA
VI = VCC or GND
VI or VO = 2.7 V
ICC
Ci
TYP†
MIN
VCC
0.8 V to 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
2.5 V
3
V
pF
† All typical values are at TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 0.8 V
TYP
5
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
0.3
3.1
0.2
2.4
‡
‡
‡
‡
‡
UNIT
ns
‡ This information was not available at the time of publication.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–27
SN74AUC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES372G – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.5
1.6
2.5
0.2
1.8
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–28
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
2
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
2
• DALLAS, TEXAS 75265
2
VCC = 1.8 V
TYP
2
VCC = 2.5 V
TYP
7
UNIT
pF
SN74AUC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES372G – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–29
SN74AUC1G07
SINGLE BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES373J– SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
NC
A
GND
1
5
VCC
4
Y
2
3
NC – No internal connection
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
A
DNU
3 4
Y
2
1 5
VCC
DNU – Do not use
description/ordering information
This single buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The output of the SN74AUC1G07 is open drain and can be connected to other open-drain outputs to implement
active-low wired-OR or active-high wired-AND functions.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G07YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G07YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G07DBVR
U07_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G07DCKR
UV_
_ _ _UV_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–31
SN74AUC1G07
SINGLE BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES373J– SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
H
L
L
logic diagram (positive logic)
A
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
VI
VO
Low-level input voltage
2.7
VCC
0.65 × VCC
UNIT
V
V
1.7
0
0.35 × VCC
V
0.7
Input voltage
0
3.6
V
Output voltage
0
2.7
V
Low-level output current
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
∆t/∆v
MAX
0.8
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOL
MIN
Input transition rise or fall rate
0.7
3
5
mA
8
9
15
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2–32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G07
SINGLE BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES373J– SEPTEMBER 2001 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOL = 100 µA
IOL = 0.7 mA
VOL
II
Ioff
A input
MAX
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
0.2
0.8 V
V
0 to 2.7 V
±5
µA
0
±10
µA
0.8 V to 2.7 V
10
µA
VI = VCC or GND
VI or VO = 2.7 V
ICC
Ci
TYP†
MIN
VCC
0.8 V to 2.7 V
Co
VO = VCC or GND
† All typical values are at TA = 25°C.
2.5 V
3
pF
2.5 V
3.5
pF
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
Y
tpd
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
4.7
0.3
3.3
0.2
2.4
‡
‡
‡
‡
‡
UNIT
ns
‡ This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.8
1.9
2.5
0.2
1.8
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
2
• DALLAS, TEXAS 75265
3
VCC = 1.8 V
TYP
3
VCC = 2.5 V
TYP
5
UNIT
pF
2–33
SN74AUC1G07
SINGLE BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES373J– SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
2–34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
SCES374I – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.4 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
A
B
GND
1
5
VCC
4
Y
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
B
A
3 4
Y
2
1 5
VCC
description/ordering information
This single 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC1G08 performs the Boolean function Y + A • B or Y + A ) B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G08YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G08YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G08DBVR
U08_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G08DCKR
UE_
_ _ _UE_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–35
SN74AUC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
SCES374I – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUTS
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
logic diagram (positive logic)
A
B
1
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
SCES374I – SEPTEMBER 2001 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
MIN
MAX
0.8
2.7
Supply voltage
VIH
High-level input voltage
VCC = 0.8 V to 1.95 V
VCC = 2.3 V to 2.7 V
VIL
Low-level input voltage
VCC = 0.8 V to 1.95 V
VCC = 2.3 V to 2.7 V
VI
VO
Input voltage
V
1.7
0.35 × VCC
0.7
Output voltage
High-level output current
3.6
V
0
VCC
–0.7
V
–3
∆ ∆
∆t/∆v
–8
–9
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
mA
5
9
VCC = 0.8 V to 1.95 V
VCC = 2.3 V to 2.7 V
Input transition rise or fall rate
mA
–5
VCC = 1.4 V
VCC = 1.65 V
Low-level output current
V
0
VCC = 2.3 V
VCC = 0.8 V
IOL
V
0.65 × VCC
VCC = 0.8 V
VCC = 1.1 V
IOH
UNIT
20
ns/V
10
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
ICC
Ci
A or B input
VCC
0.8 V to 2.7 V
MIN
MAX
UNIT
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
0.8 V
TYP†
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
0 to 2.7 V
±5
µA
0
±10
µA
0.8 V to 2.7 V
10
µA
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
2.5 V
3
V
pF
† All typical values are at TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–37
SN74AUC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
SCES374I – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
TYP
tpd
A or B
4.7
Y
† This information was not available at the time of publication.
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
0.9
3.3
0.6
2.3
†
†
†
†
†
UNIT
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.7
1.3
2.4
0.5
2
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–38
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
15
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
15
• DALLAS, TEXAS 75265
15
VCC = 1.8 V
TYP
15
VCC = 2.5 V
TYP
19
UNIT
pF
SN74AUC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
SCES374I – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–39
SN74AUC1G14
SINGLE SCHMITT-TRIGGER INVERTER
SCES375H – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
NC
A
GND
1
5
VCC
4
Y
2
3
NC – No internal connection
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
A
DNU
3 4
Y
2
1 5
VCC
DNU – Do not use
description/ordering information
This single Schmitt-trigger inverter is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC1G14 contains one inverter and performs the Boolean function Y = A. The device functions as
an independent inverter, but because of Schmitt action, it may have different input threshold levels for
positive-going (VT+) and negative-going (VT–) signals.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G14YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G14YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G14DBVR
U14_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G14DCKR
UF_
_ _ _UF_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–41
SN74AUC1G14
SINGLE SCHMITT-TRIGGER INVERTER
SCES375H – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
2
4
A
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G14
SINGLE SCHMITT-TRIGGER INVERTER
SCES375H – SEPTEMBER 2001 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
VI
Supply voltage
0.8
2.7
V
Input voltage
0
3.6
V
VO
Output voltage
0
VCC
–0.7
V
VCC = 0.8 V
VCC = 1.1 V
IOH
IOL
∆t/∆v
High-level output current
Low-level output current
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
mA
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–43
SN74AUC1G14
SINGLE SCHMITT-TRIGGER INVERTER
SCES375H – SEPTEMBER 2001 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
Positive-going input
threshold voltage
TYP†
MIN
VCC
0.8 V
0.51
0.86
1.4 V
0.65
1
1.65 V
0.79
1.16
2.3 V
1.11
1.56
1.1 V
0.22
0.53
1.4 V
0.3
0.58
1.65 V
0.39
0.62
2.3 V
0.58
VOH
VOL
II
Ioff
A input
ICC
Ci
V
0.87
0.21
1.1 V
0.25
1.4 V
0.31
0.5
1.65 V
0.37
0.62
0.48
0.77
2.3 V
IOH = –100 µA
IOH = –0.7 mA
V
0.3
0.8 V
∆VT
∆
Hysteresis
(VT+ – VT–)
UNIT
0.5
1.1 V
0.8 V
VT–
Negative-going input
threshold voltage
MAX
0.8 V to 2.7 V
0.38
V
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
0 to 2.7 V
±5
µA
0
±10
µA
0.8 V to 2.7 V
10
µA
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
2.5 V
3.5
V
pF
† All typical values are at TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
tpd
A
5.8
Y
‡ This information was not available at the time of publication.
2–44
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
0.7
4
0.6
2.3
‡
‡
‡
‡
‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
SN74AUC1G14
SINGLE SCHMITT-TRIGGER INVERTER
SCES375H – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.7
1.6
2.5
0.5
2.5
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
14
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
15
• DALLAS, TEXAS 75265
15
VCC = 1.8 V
TYP
16
VCC = 2.5 V
TYP
19
UNIT
pF
2–45
SN74AUC1G14
SINGLE SCHMITT-TRIGGER INVERTER
SCES375H – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
2–46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G17
SINGLE SCHMITT-TRIGGER BUFFER
SCES376H – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.4 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
NC
A
GND
1
5
VCC
4
Y
2
3
NC – No internal connection
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
A
DNU
3 4
Y
2
1 5
VCC
DNU – Do not use
description/ordering information
This single Schmitt-trigger buffer is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to
1.95-V VCC operation.
The SN74AUC1G17 contains one buffer and performs the Boolean function Y = A. The device functions as an
independent buffer, but because of Schmitt action, it may have different input threshold levels for positive-going
(VT+) and negative-going (VT–) signals.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G17YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G17YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G17DBVR
U17_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G17DCKR
U7_
_ _ _U7_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–47
SN74AUC1G17
SINGLE SCHMITT-TRIGGER BUFFER
SCES376H – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
H
L
L
logic diagram (positive logic)
2
4
A
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G17
SINGLE SCHMITT-TRIGGER BUFFER
SCES376H – SEPTEMBER 2001 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
VI
Supply voltage
0.8
2.7
V
Input voltage
0
3.6
V
VO
Output voltage
0
VCC
–0.7
V
VCC = 0.8 V
VCC = 1.1 V
IOH
IOL
∆t/∆v
High-level output current
Low-level output current
Input transition rise or fall rate
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–49
SN74AUC1G17
SINGLE SCHMITT-TRIGGER BUFFER
SCES376H – SEPTEMBER 2001 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
Positive-going input
threshold voltage
TYP†
VCC
0.8 V
MIN
1.1 V
0.51
0.86
1.4 V
0.65
1
1.65 V
0.79
1.16
2.3 V
1.11
1.56
1.1 V
0.22
0.53
1.4 V
0.3
0.58
1.65 V
0.39
0.62
2.3 V
0.58
VOH
VOL
II
Ioff
A input
ICC
Ci
V
0.87
0.21
1.1 V
0.25
1.4 V
0.31
0.5
1.65 V
0.37
0.62
0.48
0.77
2.3 V
IOH = –100 µA
IOH = –0.7 mA
V
0.3
0.8 V
∆VT
∆
Hysteresis
(VT+ – VT–)
UNIT
0.5
0.8 V
VT–
Negative-going input
threshold voltage
MAX
0.8 V to 2.7 V
0.38
V
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
0 to 2.7 V
±5
µA
0
±10
µA
0.8 V to 2.7 V
10
µA
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
2.5 V
3
V
pF
† All typical values are at TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
tpd
A
5.7
Y
‡ This information was not available at the time of publication.
2–50
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
0.8
3.9
0.7
2.1
‡
‡
‡
‡
‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
SN74AUC1G17
SINGLE SCHMITT-TRIGGER BUFFER
SCES376H – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.8
1.4
2.4
0.7
2.5
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
15
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
15
• DALLAS, TEXAS 75265
16
VCC = 1.8 V
TYP
16
VCC = 2.5 V
TYP
20
UNIT
pF
2–51
SN74AUC1G17
SINGLE SCHMITT-TRIGGER BUFFER
SCES376H – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
2–52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES377H – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.4 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
A
B
GND
1
5
VCC
4
Y
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
B
A
3 4
Y
2
1 5
VCC
description/ordering information
This single 2-input positive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC1G32 performs the Boolean function Y + A ) B or Y + A • B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G32YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G32YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G32DBVR
U32_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G32DCKR
UG_
_ _ _UG_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–53
SN74AUC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES377H – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUTS
B
OUTPUT
Y
H
X
H
X
H
H
L
L
L
A
logic diagram (positive logic)
A
B
1
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES377H – SEPTEMBER 2001 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
MIN
MAX
0.8
2.7
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
Low-level input voltage
VI
VO
Input voltage
V
1.7
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0
3.6
V
0
VCC
–0.7
V
VCC = 0.8 V
VCC = 1.1 V
High-level output current
IOL
Low-level output current
∆t/∆v
V
0.7
Output voltage
IOH
V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
UNIT
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
mA
5
9
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
ICC
Ci
A or B input
VCC
0.8 V to 2.7 V
MIN
MAX
0.8 V
0.55
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
VCC–0.1
IOH = –3 mA
IOH = –5 mA
0.8 V
TYP†
V
0 to 2.7 V
±5
µA
0
±10
µA
10
µA
0.8 V to 2.7 V
2.5 V
4
pF
† All typical values are at TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–55
SN74AUC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES377H – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
TYP
tpd
A or B
4.8
Y
† This information was not available at the time of publication.
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
1
3.5
0.6
2.3
†
†
†
†
†
UNIT
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.8
1.4
2.4
0.6
2.1
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–56
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
14
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
14
• DALLAS, TEXAS 75265
15
VCC = 1.8 V
TYP
15
VCC = 2.5 V
TYP
20
UNIT
pF
SN74AUC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES377H – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–57
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Sub 1-V Operable
Max tpd of 0.2 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
High On-Off Output Voltage Ratio
D High Degree of Linearity
D High Speed – Typically 0.5 ns (VCC = 3 V,
CL = 50 pF)
D Low On-State Impedance – Typically ≈9 Ω
D
D
(VCC = 2.3 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
DBV OR DCK PACKAGE
(TOP VIEW)
This single analog switch is operational at 0.8-V to
2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
A
B
GND
The SN74AUC1G66 can handle both analog and
digital signals. It permits signals with amplitudes
of up to 3.6-V (peak) to be transmitted in either
direction.
1
5
VCC
4
C
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
NanoStar and NanoFree package technology
is a major breakthrough in IC packaging concepts,
using the die as the package.
GND
B
A
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing
for
analog-to-digital
and
digital-to-analog conversion systems.
3 4
C
2
1 5
VCC
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G66YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G66YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G66DBVR
U66_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G66DCKR
U6_
_ _ _U6_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–59
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
FUNCTION TABLE
CONTROL
INPUT
(C)
SWITCH
L
OFF
H
ON
logic diagram (positive logic)
1
2
A
B
4
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Switch I/O voltage range, VI/O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Control input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
I/O port diode current, IIOK (VI/O < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
On-state switch current, IT (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2–60
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
MIN
MAX
0.8
2.7
UNIT
V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
V
1.7
0
0.35 × VCC
VIL
Low-level input voltage
VI/O
VI
I/O port voltage
0
Control input voltage
0
∆t/∆v
Input transition rise or fall rate
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
V
0.7
VCC
3.6
V
V
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP†
MAX
VI = VCC or GND,
VC = VIH
(see Figure 1)
IS = 4 mA
1.65 V
10
20
IS = 8 mA
2.3 V
9
15
VI = VCC to GND,
VC = VIH
(see Figure 1)
IS = 4 mA
1.65 V
32
80
IS = 8 mA
2.3 V
15
20
UNIT
Ω
ron
On-state switch resistance
ron(p)
Peak on resistance
IS(off)
Off-state switch leakage current
VI = VCC and VO = GND, or
VI = GND and VO = VCC,
VC = VIL (see Figure 2)
2.7 V
IS(on)
On-state switch leakage current
VI = VCC or GND, VC = VIH, VO = Open
(see Figure 3)
2.7 V
II
Control input current
VI = VCC or GND
ICC
Supply current
VI = VCC or GND,
Cic
Control input capacitance
2.5 V
2
pF
Cio(off)
Switch input/output capacitance
2.5 V
3.5
pF
Cio(on)
Switch input/output capacitance
2.5 V
7
pF
±1
IO = 0
±0.1†
Ω
µ
µA
±1
±0.1†
µ
µA
0 to 2.7 V
±5
µA
0.8 V to
2.7 V
10
µA
† All typical values are at TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 4)
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
tpd‡
A or B
B or A
0.9
ten
C
A or B
4.1
PARAMETER
TYP
VCC = 1.2 V
± 0.1 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
0.3
0.5
2.6
MAX
VCC = 1.8 V
± 0.15 V
MIN
TYP
0.2
0.5
1.7
VCC = 2.5 V
± 0.2 V
MAX
MIN
0.2
0.5
0.8
1.1
0.5
UNIT
MAX
0.1
ns
1
ns
tdis
C
5
0.7
3.6
0.5
2.6
0.5
1.7
2.9
0.5
2.2
ns
A or B
‡ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–61
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 4)
FROM
(INPUT)
TO
(OUTPUT)
tpd†
A or B
B or A
ten
C
A or B
PARAMETER
VCC = 1.8 V
± 0.15 V
MIN
TYP
VCC = 2.5 V
± 0.2 V
MAX
MIN
0.3
0.5
1.4
2.3
0.8
UNIT
MAX
0.3
ns
1.4
ns
tdis
C
0.5
1.7
2.9
0.5
1.5
ns
A or B
† The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
2–62
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
analog switch characteristics, TA = 25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
CL = 50 pF, RL = 600 Ω,
Ω
fin = sine wave
(see Figure 5)
Frequency response†
(switch ON)
A or B
Crosstalk
(control input to signal output)
C
CL = 50 pF, RL = 600 Ω,
Ω
fin = 1 MHz (square wave)
(see Figure 6)
A or B
CL = 50 pF, RL = 600 Ω,
Ω
fin = 1 MHz (sine wave)
(see Figure 7)
Feed-through attenuation‡
(switch OFF)
A or B
A or B
CL = 50 pF, RL = 10 kΩ,
Ω
fin = 1 kHz (sine wave)
(see Figure 8)
B or A
A or B
B or A
60
1.1 V
60
80
120
2.3 V
170
0.8 V
>500
1.1 V
>500
1.4 V
>500
1.65 V
>500
2.3 V
>500
0.8 V
9
1.1 V
14
1.4 V
15
1.65 V
16
2.3 V
20
0.8 V
–60
1.1 V
–60
1.4 V
–60
1.65 V
–60
2.3 V
–60
0.8 V
–55
1.1 V
–55
1.4 V
–55
1.65 V
–55
2.3 V
–55
0.8 V
7.5
1.1 V
0.16
1.4 V
0.04
1.65 V
0.03
2.3 V
0.02
0.8 V
4.2
1.1 V
0.2
Sine-wave distortion
CL = 50 pF, RL = 10 kΩ,
Ω
fin = 10 kHz (sine wave)
(see Figure 8)
0.8 V
1.65 V
B or A
CL = 5 pF, RL = 50 Ω,
Ω
fin = 1 MHz (sine wave)
(see Figure 7)
TYP
1.4 V
B or A
CL = 5 pF, RL = 50 Ω,
Ω
fin = sine wave
(see Figure 5)
VCC
1.4 V
0.03
1.65 V
0.02
2.3 V
0.02
UNIT
MHz
mV
dB
%
† Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
‡ Adjust fin voltage to obtain 0 dBm at input.
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
3
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
3
• DALLAS, TEXAS 75265
3
VCC = 1.8 V
TYP
3
VCC = 2.5 V
TYP
3
UNIT
pF
2–63
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
B or A
A or B
VI = VCC or GND
VIH
VO
C
VC
(ON)
GND
IS
r on +
V
VI – VO
Figure 1. On-State Resistance Test Circuit
VCC
VCC
VI
A
VIL
B or A
A or B
C
VC
(OFF)
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 2. Off-State Switch Leakage-Current Test Circuit
2–64
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VO
VI * VO
W
IS
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
VI = VCC or GND
A
VIH
B or A
A or B
VO
VO = Open
C
VC
(ON)
GND
Figure 3. On-State Leakage-Current Test Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–65
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
INPUTS
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
VI
tr/tf
VCC
VCC
VCC
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
2–66
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
0.1 µF
50 Ω
fin
VIH
B or A
A or B
VO
C
VC
RL
(ON)
GND
CL
VCC/2
RL/CL: 600 Ω / 50 pF
RL/CL: 50 Ω / 5 pF
Figure 5. Frequency Response (Switch ON)
VCC
VCC
Rin
600 Ω
VCC/2
A or B
B or A
VO
RL
600 Ω
C
VC
GND
50 Ω
CL
50 pF
VCC/2
Figure 6. Crosstalk (Control Input – Switch Output)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–67
SN74AUC1G66
SINGLE BILATERAL ANALOG SWITCH
SCES386E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
0.1 µF
RL
50 Ω
fin
B or A
A or B
VO
C
VC
VIL
CL
RL
(OFF)
GND
VCC/2
VCC/2
RL/CL: 600 Ω / 50 pF
RL/CL: 50 Ω / 5 pF
Figure 7. Feed Through, Switch Off
VCC
VCC
10 µF
fin
600 Ω
VIH
VO
RL
10 kΩ
C
VC
(ON)
GND
VCC = 0.8 V, VI = __ VP-P
VCC = 1.1 V, VI = __ VP-P
VCC = 1.4 V, VI = __ VP-P
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2.5 VP-P
Figure 8. Sine-Wave Distortion
2–68
10 µF
B or A
A or B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC/2
CL
50 pF
SN74AUC1G79
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES387F – MARCH 2002 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
CLK
GND
1
5
VCC
4
Q
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
CLK
D
3 4
Q
2
1 5
VCC
description/ordering information
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G79YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G79YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G79DBVR
U79_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G79DCKR
UR_
_ _ _UR_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–69
SN74AUC1G79
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES387F – MARCH 2002 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUTS
CLK
D
OUTPUT
Q
↑
H
H
↑
L
L
L
X
Q0
logic diagram (positive logic)
CLK
CLK
Q
D
D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–70
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G79
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES387F – MARCH 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
MIN
MAX
0.8
2.7
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
Low-level input voltage
VI
VO
Input voltage
V
1.7
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.7
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
V
0
3.6
V
0
VCC
–0.7
V
VCC = 0.8 V
VCC = 1.1 V
IOH
V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
UNIT
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
mA
5
9
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
ICC
Ci
D or CLK input
VCC
0.8 V to 2.7 V
MIN
MAX
0.8 V
0.55
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
VCC–0.1
IOH = –3 mA
IOH = –5 mA
0.8 V
TYP†
V
0 to 2.7 V
±5
µA
0
±10
µA
10
µA
0.8 V to 2.7 V
2.5 V
2.5
pF
† All typical values are at TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–71
SN74AUC1G79
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES387F – MARCH 2002 – REVISED DECEMBER 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 0.8 V
TYP
VCC = 1.2 V
± 0.1 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
200
VCC = 1.8 V
± 0.15 V
MIN
MAX
225
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
50
250
275
MHz
Pulse duration, CLK high or low
4.6
1.7
1.7
1.7
1.7
ns
tsu
Setup time before CLK↑, Data high or low
1.5
1.1
0.7
0.7
0.5
ns
th
Hold time, data after CLK↑
0
0
0
0
0.1
ns
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 0.8 V
TO
(OUTPUT)
TYP
MIN
50
200
5
1
fmax
tpd
CLK
VCC = 1.2 V
± 0.1 V
Q
VCC = 1.5 V
± 0.1 V
MAX
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
225
3.9
0.8
TYP
VCC = 2.5 V
± 0.2 V
MAX
250
2.5
0.3
MIN
275
1
1.9
UNIT
MAX
MHz
0.3
1.3
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
MIN
fmax
tpd
TYP
VCC = 2.5 V
± 0.2 V
MAX
250
CLK
0.8
Q
MIN
275
1.5
2.4
UNIT
MAX
0.6
ns
1.8
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–72
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
18
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
18
• DALLAS, TEXAS 75265
18
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
18.5
20.5
pF
SN74AUC1G79
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES387F – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–73
SN74AUC1G80
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES388F – MARCH 2002 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 3.3 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
CLK
GND
1
5
VCC
4
Q
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
CLK
D
3 4
Q
2
1 5
VCC
description/ordering information
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G80YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G80YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G80DBVR
U80_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G80DCKR
UX_
_ _ _UX_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–75
SN74AUC1G80
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES388F – MARCH 2002 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUTS
OUTPUT
Q
CLK
D
↑
H
L
↑
L
H
L
X
Q0
logic diagram (positive logic)
CLK
CLK
Q
D
D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–76
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G80
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES388F – MARCH 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
MIN
MAX
0.8
2.7
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
Low-level input voltage
VI
VO
Input voltage
V
1.7
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.7
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
V
0
3.6
V
0
VCC
–0.7
V
VCC = 0.8 V
VCC = 1.1 V
IOH
V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
UNIT
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
mA
5
9
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
ICC
Ci
D or CLK input
VCC
0.8 V to 2.7 V
MIN
MAX
0.8 V
0.55
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
VCC–0.1
IOH = –3 mA
IOH = –5 mA
0.8 V
TYP†
V
0 to 2.7 V
±5
µA
0
±10
µA
10
µA
0.8 V to 2.7 V
2.5 V
2.5
pF
† All typical values are at TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–77
SN74AUC1G80
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES388F – MARCH 2002 – REVISED DECEMBER 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 0.8 V
TYP
VCC = 1.2 V
± 0.1 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
200
VCC = 1.8 V
± 0.15 V
MIN
MAX
225
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
50
250
275
MHz
Pulse duration, CLK high or low
4.6
1.7
1.7
1.7
1.7
ns
tsu
Setup time before CLK↑, Data high or low
1.6
1.1
0.8
0.6
0.5
ns
th
Hold time, data after CLK↑
0
0
0.1
0.1
0.1
ns
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 0.8 V
TO
(OUTPUT)
TYP
MIN
50
200
5
1
fmax
tpd
CLK
VCC = 1.2 V
± 0.1 V
Q
VCC = 1.5 V
± 0.1 V
MAX
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
225
3.9
0.8
TYP
VCC = 2.5 V
± 0.2 V
MAX
250
2.5
0.3
MIN
275
1
1.9
UNIT
MAX
MHz
0.3
1.3
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
MIN
fmax
tpd
TYP
VCC = 2.5 V
± 0.2 V
MAX
250
CLK
0.8
Q
MIN
275
1.5
2.4
UNIT
MAX
0.6
ns
1.8
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–78
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
18
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
18
• DALLAS, TEXAS 75265
18
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
18.5
20.5
pF
SN74AUC1G80
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES388F – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–79
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES389E – MARCH 2002 – REVISED JANUARY 2003
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
A
B
GND
1
5
VCC
4
Y
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
B
A
3 4
Y
2
1 5
VCC
description/ordering information
This single 2-input exclusive - OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC1G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G86YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G86YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G86DBVR
U86_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G86DCKR
UH_
_ _ _UH_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–81
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES389E – MARCH 2002 – REVISED JANUARY 2003
FUNCTION TABLE
INPUTS
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AUC1G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
EVEN-PARITY ELEMENT
2k
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
ODD-PARITY ELEMENT
2k + 1
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–82
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES389E – MARCH 2002 – REVISED JANUARY 2003
recommended operating conditions (see Note 3)
VCC
VIH
MIN
MAX
0.8
2.7
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
Low-level input voltage
VI
VO
Input voltage
V
1.7
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.7
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
V
0
3.6
V
0
VCC
–0.7
V
VCC = 0.8 V
VCC = 1.1 V
IOH
V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
UNIT
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
mA
5
9
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
ICC
Ci
A or B input
VCC
0.8 V to 2.7 V
MIN
MAX
0.8 V
0.55
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
VCC–0.1
IOH = –3 mA
IOH = –5 mA
0.8 V
TYP†
V
0 to 2.7 V
±5
µA
0
±10
µA
10
µA
0.8 V to 2.7 V
2.5 V
2.5
pF
† All typical values are at TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–83
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES389E – MARCH 2002 – REVISED JANUARY 2003
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 0.8 V
TO
(OUTPUT)
B
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
5.5
0.8
3.8
0.5
2.4
0.4
1
1.7
0.3
1.3
5
0.8
3.6
0.5
2.2
0.4
1
1.7
0.3
1.2
A
tpd
VCC = 1.2 V
± 0.1 V
Y
UNIT
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
A
tpd
Y
B
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
0.8
1.5
2.3
0.7
1.8
0.8
1.5
2.3
0.7
1.7
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–84
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
16
POST OFFICE BOX 655303
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
16
• DALLAS, TEXAS 75265
16.5
VCC = 1.8 V
TYP
17
VCC = 2.5 V
TYP
UNIT
18.5
pF
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES389E – MARCH 2002 – REVISED JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–85
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382E – MARCH 2002 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
OE
A
GND
1
5
VCC
4
Y
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
A
OE
3 4
Y
2
1 5
VCC
description/ordering information
This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G125YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G125YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G125DBVR
U25_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G125DCKR
UM_
_ _ _UM_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2-87
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382E – MARCH 2002 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
logic diagram (positive logic)
OE
A
1
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2-88
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382E – MARCH 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
Input transition rise or fall rate
MAX
0.8
2.7
VCC
0.65 × VCC
V
V
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
VCC = 0.8 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
10
ns/V
3
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2-89
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382E – MARCH 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
A or OE input
TYP†
VCC
MIN
0.8 V to 2.7 V
VCC–0.1
0.8 V
MAX
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
IOZ
ICC
VO = VCC or GND
VI = VCC or GND,
Ci
VI = VCC or GND
IO = 0
UNIT
V
0 to 2.7 V
±5
µA
0
±10
µA
2.7 V
±10
µA
0.8 V to 2.7 V
10
µA
Co
VO = VCC or GND
† All typical values are at TA = 25°C.
2.5 V
2.5
pF
2.5 V
5.5
pF
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 0.8 V
TO
(OUTPUT)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
UNIT
tpd
A
Y
4.7
0.8
3.6
0.4
2.3
‡
‡
‡
‡
‡
ns
ten
OE
Y
5.4
0.7
4.1
0.5
2.6
‡
‡
‡
‡
‡
ns
1.4
4.3
1.4
4
‡
‡
‡
‡
‡
ns
tdis
OE
4.8
Y
‡ This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
2-90
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
TYP
MAX
MIN
MAX
UNIT
tpd
A
Y
0.7
1.5
2.5
0.9
1.7
ns
ten
OE
Y
1
1.6
2.6
1.1
1.9
ns
tdis
OE
Y
1.8
2.2
3.1
0.8
1.7
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382E – MARCH 2002 – REVISED DECEMBER 2002
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
14
14
14
15
16
1.5
1.5
1.5
2
2.5
f = 10 MHz
UNIT
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2-91
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
VCC/2
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
2-92
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES383E – MARCH 2002 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
OE
A
GND
1
5
VCC
4
Y
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
A
OE
3 4
Y
2
1 5
VCC
description/ordering information
This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G126YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G126YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G126DBVR
U26_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G126DCKR
UN_
_ _ _UN_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–93
SN74AUC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES383E – MARCH 2002 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
logic diagram (positive logic)
1
OE
A
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–94
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES383E – MARCH 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
Input transition rise or fall rate
MAX
0.8
2.7
VCC
0.65 × VCC
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
VCC = 2.3 V to 2.7 V
V
V
VCC = 1.4 V
VCC = 1.65 V
VCC = 0.8 V to 1.6 V
VCC = 1.65 V to 1.95 V
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
10
ns/V
3
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–95
SN74AUC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES383E – MARCH 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
A or OE input
TYP†
MIN
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
IOZ
ICC
VO = VCC or GND
VI = VCC or GND,
Ci
VI = VCC or GND
IO = 0
UNIT
V
0 to 2.7 V
±5
µA
0
±10
µA
2.7 V
±10
µA
0.8 V to 2.7 V
10
µA
Co
VO = VCC or GND
† All typical values are at TA = 25°C.
2.5 V
2.5
pF
2.5 V
5.5
pF
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
A
Y
4.5
0.8
3.6
0.6
2.3
‡
‡
‡
‡
‡
ns
2.5
‡
‡
‡
‡
‡
ns
4.1
‡
‡
‡
‡
‡
ns
tpd
ten
OE
4.9
Y
tdis
OE
4.9
Y
‡ This information was not available at the time of publication.
0.7
2.2
3.8
4.7
0.7
1.8
UNIT
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
tdis
PARAMETER
2–96
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
UNIT
MIN
TYP
MAX
MIN
MAX
Y
1
1.5
2.5
0.9
1.7
ns
OE
Y
1.1
1.6
2.5
0.9
1.9
ns
OE
Y
1.3
2.6
3.1
1
2.1
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES383E – MARCH 2002 – REVISED DECEMBER 2002
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
14
14
14
15
16
1.5
1.5
1.5
2
2.5
f = 10 MHz
UNIT
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–97
SN74AUC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES383E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
2–98
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G240
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
SCES384E – MARCH 2002 – REVISED DECEMBER 2002
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
OE
A
GND
1
5
VCC
4
Y
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
A
OE
3 4
Y
2
1 5
VCC
description/ordering information
This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC1G240 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) – YEA
Tape and reel
SN74AUC1G240YEAR
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
SN74AUC1G240YZAR
SOT (SOT-23) – DBV
Tape and reel
SN74AUC1G240DBVR
U40_
SOT (SC-70) – DCK
Tape and reel
SN74AUC1G240DCKR
UK_
_ _ _UK_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–99
SN74AUC1G240
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
SCES384E – MARCH 2002 – REVISED DECEMBER 2002
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
L
H
L
L
L
H
H
X
Z
logic diagram (positive logic)
OE
A
1
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2–100
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G240
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
SCES384E – MARCH 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
Input transition rise or fall rate
MAX
0.8
2.7
VCC
0.65 × VCC
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
VCC = 2.3 V to 2.7 V
V
V
VCC = 1.4 V
VCC = 1.65 V
VCC = 0.8 V to 1.6 V
VCC = 1.65 V to 1.95 V
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
10
ns/V
3
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–101
SN74AUC1G240
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
SCES384E – MARCH 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
A or OE input
TYP†
MIN
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
IOZ
ICC
VO = VCC or GND
VI = VCC or GND,
Ci
VI = VCC or GND
IO = 0
UNIT
V
0 to 2.7 V
±5
µA
0
±10
µA
2.7 V
±10
µA
0.8 V to 2.7 V
10
µA
Co
VO = VCC or GND
† All typical values are at TA = 25°C.
2.5 V
2.5
pF
2.5 V
5.5
pF
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
A
Y
4.5
0.6
3.3
0.7
2.2
‡
‡
‡
‡
‡
ns
2.6
‡
‡
‡
‡
‡
ns
4.1
‡
‡
‡
‡
‡
ns
tpd
ten
OE
5.5
Y
tdis
OE
5
Y
‡ This information was not available at the time of publication.
0.7
1.5
4.1
4.3
0.5
0.9
UNIT
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
tdis
PARAMETER
2–102
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
UNIT
MIN
TYP
MAX
MIN
MAX
Y
0.5
1.5
2.5
0.8
1.7
ns
OE
Y
0.7
1.6
2.6
0.6
1.9
ns
OE
Y
2
2.4
3.1
0.8
1.7
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC1G240
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
SCES384E – MARCH 2002 – REVISED DECEMBER 2002
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
14
14
14
14
15
1
1
1
1
2
f = 10 MHz
UNIT
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–103
SN74AUC1G240
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
SCES384E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
2–104
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
General Information
AUC Single Gates
AUC Widebus
AUC Widebus+
Application Reports
Mechanical Data
3–1
Contents
Page
SN74AUC16240
16-Bit Buffer/Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
SN74AUCH16240 16-Bit Buffer/Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
SN74AUC16244
16-Bit Buffer/Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
SN74AUCH16244 16-Bit Buffer/Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
AUC Widebus
SN74AUC16245
16-Bit Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31
SN74AUCH16245 16-Bit Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–37
SN74AUC16373
16-Bit Transparent D-Type Latch With 3-State Outputs . . . . . . . . . . . . . . . . . . . . 3–43
SN74AUCH16373 16-Bit Transparent D-Type Latch With 3-State Outputs . . . . . . . . . . . . . . . . . . . . 3–49
SN74AUC16374
16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs . . . . . . . . . . . . . . 3–55
SN74AUCH16374 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs . . . . . . . . . . . . . . 3–61
3–2
SN74AUC16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES390E – MARCH 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
DGG OR DGV PACKAGE
(TOP VIEW)
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
description/ordering information
This 16-bit buffer/driver is operational at 0.8-V to
2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC16240 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides inverting outputs
and symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
PACKAGE†
TA
–40°C to 85°C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74AUC16240DGGR
AUC16240
TVSOP – DGV
Tape and reel
SN74AUC16240DGVR
MH240
VFBGA – GQL
Tape and reel
SN74AUC16240GQLR
MH240
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–3
SN74AUC16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES390E – MARCH 2002 – REVISED DECEMBER 2002
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1OE
NC
NC
NC
NC
2OE
B
B
1Y2
1Y1
GND
GND
1A1
1A2
C
C
1Y4
1Y3
1A4
D
2Y2
2Y1
VCC
GND
1A3
D
VCC
GND
2A1
2A2
E
2Y4
2Y3
2A3
2A4
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
GND
3A4
3A3
H
4Y1
4Y2
4A1
4Y3
4Y4
VCC
GND
4A2
J
VCC
GND
4A4
4A3
K
4OE
NC
NC
NC
NC
3OE
E
F
G
H
J
K
NC – No internal connection
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
3–4
OE
A
OUTPUT
Y
L
H
L
L
L
H
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES390E – MARCH 2002 – REVISED DECEMBER 2002
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Pin numbers shown are for the DGG and DGV packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–5
SN74AUC16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES390E – MARCH 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
IOL
∆t/∆v
MAX
0.8
2.7
VCC
0.65 × VCC
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
VCC = 2.7 V
V
V
VCC = 1.4 V
VCC = 1.65 V
VCC = 0.8 V, 1.3 V
VCC = 1.6 V, 1.95 V
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
10
ns/V
5
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES390E – MARCH 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
A or OE inputs
TYP†
MIN
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
IOZ
ICC
VO = VCC or GND
VI = VCC or GND,
Ci
VI = VCC or GND
V
±5
µA
0
±10
µA
2.7 V
±10
µA
0.8 V to 2.7 V
20
µA
0 to 2.7 V
IO = 0
UNIT
Co
VO = VCC or GND
† All typical values are at TA = 25°C.
2.5 V
3
4
pF
2.5 V
5.5
6
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
tpd
A
Y
5.9
0.9
2.6
0.7
1.8
0.6
1.4
2
0.4
1.6
ns
ten
OE
Y
7.9
1.2
3.8
0.8
2.5
0.7
1.5
2.5
0.7
2
ns
tdis
OE
Y
9.3
2.1
6
1.5
4.8
1.8
2.7
4.5
0.6
2.3
ns
PARAMETER
UNIT
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
24
24
25
26
30
2
2
2
3
4
f = 10 MHz
UNIT
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–7
SN74AUC16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES390E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
3–8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES398C – JULY 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
description/ordering information
This 16-bit buffer/driver is operational at 0.8-V to
2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUCH16240 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two
8-bit buffers, or one 16-bit buffer. It provides
inverting outputs and symmetrical active-low
output-enable (OE) inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP – DGG
Tape and reel
SN74AUCH16240DGGR
TVSOP – DGV
Tape and reel
SN74AUCH16240DGVR
VFBGA – GQL
Tape and reel
SN74AUCH16240GQLR
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–9
PRODUCT PREVIEW
D
DGG OR DGV PACKAGE
(TOP VIEW)
SN74AUCH16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES398C – JULY 2002 – REVISED DECEMBER 2002
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1OE
NC
NC
NC
NC
2OE
B
B
1Y2
1Y1
GND
GND
1A1
1A2
C
C
1Y4
1Y3
1A4
D
2Y2
2Y1
VCC
GND
1A3
D
VCC
GND
2A1
2A2
E
2Y4
2Y3
2A3
2A4
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
GND
3A4
3A3
H
4Y1
4Y2
4A1
4Y3
4Y4
VCC
GND
4A2
J
VCC
GND
4A4
4A3
K
4OE
NC
NC
NC
NC
3OE
E
F
G
H
J
K
NC – No internal connection
PRODUCT PREVIEW
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
3–10
OE
A
OUTPUT
Y
L
H
L
L
L
H
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES398C – JULY 2002 – REVISED DECEMBER 2002
logic diagram (positive logic)
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Pin numbers shown are for the DGG and DGV packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–11
PRODUCT PREVIEW
1OE
SN74AUCH16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES398C – JULY 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
PRODUCT PREVIEW
IOL
∆t/∆v
MAX
0.8
2.7
VCC
0.65 × VCC
Output voltage
High-level output current
Low-level output current
V
V
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3–12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES398C – JULY 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
IBHL‡
IBHH§
IBHLO¶
A or OE inputs
MIN
TYP†
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI = 0.35 V
±5
0 to 2.7 V
VI = 0.47 V
VI = 0.57 V
1.1 V
10
1.4 V
15
1.65 V
20
VI = 0.7 V
VI = 0.8 V
2.3 V
40
1.1 V
–10
VI = 0.9 V
VI = 1.07 V
1.4 V
–15
1.65 V
–20
VI = 1.7 V
2.3 V
–40
1.3 V
75
VI = 0 to VCC
IBHHO#
VI = 0 to VCC
Ioff
IOZ
VI or VO = 2.7 V
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
1.6 V
125
1.95 V
175
2.7 V
275
1.3 V
–75
1.6 V
–125
1.95 V
–175
2.7 V
–275
0
2.7 V
IO = 0
0.8 V to 2.7 V
2.5 V
UNIT
V
µA
µ
µA
µ
µA
µ
µA
µ
µA
±10
µA
±10
µA
20
µA
pF
Co
VO = VCC or GND
2.5 V
pF
† All typical values are at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–13
PRODUCT PREVIEW
PARAMETER
SN74AUCH16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES398C – JULY 2002 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ns
ten
OE
Y
ns
tdis
OE
Y
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
UNIT
MAX
operating characteristics, TA = 25°C
PARAMETER
Outputs
enabled
Outputs
disabled
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
f = 10 MHz
3–14
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
pF
PRODUCT PREVIEW
Cpd
Power
dissipation
capacitance
TEST
CONDITIONS
• DALLAS, TEXAS 75265
SN74AUCH16240
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES398C – JULY 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–15
PRODUCT PREVIEW
0V
tw
SN74AUC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES399C – JULY 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
description/ordering information
This 16-bit buffer/driver is operational at 0.8-V to
2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC16244 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two
8-bit buffers, or one 16-bit buffer. It provides true
outputs
and
symmetrical
active-low
output-enable (OE) inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP – DGG
Tape and reel
SN74AUC16244DGGR
TVSOP – DGV
Tape and reel
SN74AUC16244DGVR
VFBGA – GQL
Tape and reel
SN74AUC16244GQLR
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–17
PRODUCT PREVIEW
D
DGG OR DGV PACKAGE
(TOP VIEW)
SN74AUC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES399C – JULY 2002 – REVISED DECEMBER 2002
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1OE
NC
NC
NC
NC
2OE
B
B
1Y2
1Y1
GND
GND
1A1
1A2
C
C
1Y4
1Y3
1A4
D
2Y2
2Y1
VCC
GND
1A3
D
VCC
GND
2A1
2A2
E
2Y4
2Y3
2A3
2A4
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
GND
3A4
3A3
H
4Y1
4Y2
4A1
4Y3
4Y4
VCC
GND
4A2
J
VCC
GND
4A4
4A3
K
4OE
NC
NC
NC
NC
3OE
E
F
G
H
J
K
NC – No internal connection
PRODUCT PREVIEW
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
3–18
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES399C – JULY 2002 – REVISED DECEMBER 2002
logic diagram (positive logic)
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Pin numbers shown are for the DGG and DGV packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–19
PRODUCT PREVIEW
1OE
SN74AUC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES399C – JULY 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
PRODUCT PREVIEW
IOL
∆t/∆v
MAX
0.8
2.7
VCC
0.65 × VCC
Output voltage
High-level output current
Low-level output current
V
V
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3–20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES399C – JULY 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
A or OE inputs
MIN
TYP†
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
IOZ
ICC
VO = VCC or GND
VI = VCC or GND,
Ci
VI = VCC or GND
0 to 2.7 V
0
2.7 V
IO = 0
0.8 V to 2.7 V
Co
VO = VCC or GND
† All typical values are at TA = 25°C.
UNIT
V
±5
µA
±10
µA
±10
µA
20
µA
2.5 V
pF
2.5 V
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ns
ten
OE
Y
ns
tdis
OE
Y
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
UNIT
MAX
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
f = 10 MHz
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
pF
• DALLAS, TEXAS 75265
3–21
PRODUCT PREVIEW
PARAMETER
SN74AUC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES399C – JULY 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
PRODUCT PREVIEW
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
3–22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
D
DGG OR DGV PACKAGE
(TOP VIEW)
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 1.8 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
description/ordering information
This 16-bit buffer/driver is operational at 0.8-V to
2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
The SN74AUCH16244 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
PACKAGE†
TA
–40°C to 85°C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74AUCH16244DGGR
AUCH16244
TVSOP – DGV
Tape and reel
SN74AUCH16244DGVR
MJ244
VFBGA – GQL
Tape and reel
SN74AUCH16244GQLR
MJ244
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–23
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
description/ordering information (continued)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
2OE
B
1Y2
1Y1
GND
GND
1A1
1A2
B
C
1Y4
1Y3
2Y2
2Y1
VCC
GND
1A4
D
VCC
GND
1A3
C
2A1
2A2
D
E
2Y4
2Y3
2A3
2A4
A
E
F
3Y1
3Y2
3A2
3A1
F
G
3Y3
3Y4
GND
GND
3A4
3A3
G
H
4Y1
4Y2
VCC
GND
4A2
4A1
4A4
4A3
NC
NC
3OE
H
J
4Y3
4Y4
VCC
GND
J
K
4OE
NC
NC
K
NC – No internal connection
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
3–24
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Pin numbers shown are for the DGG and DGV packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–25
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
IOL
∆t/∆v
MAX
0.8
2.7
VCC
0.65 × VCC
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
UNIT
V
V
1.7
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
VCC = 0.8 V
VCC = 1.3 V
20
VCC = 1.6 V, 1.95 V, and 2.7 V
10
5
mA
9
15
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3–26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
IBHL‡
IBHH§
IBHLO¶
A or OE inputs
MIN
TYP†
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI = 0.35 V
±5
0 to 2.7 V
VI = 0.47 V
VI = 0.57 V
1.1 V
10
1.4 V
15
1.65 V
20
VI = 0.7 V
VI = 0.8 V
2.3 V
40
1.1 V
–10
VI = 0.9 V
VI = 1.07 V
1.4 V
–15
1.65 V
–20
VI = 1.7 V
2.3 V
–40
1.3 V
75
VI = 0 to VCC
IBHHO#
VI = 0 to VCC
Ioff
IOZ
VI or VO = 2.7 V
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
1.6 V
125
1.95 V
175
2.7 V
275
1.3 V
–75
1.6 V
–125
1.95 V
–175
2.7 V
–275
V
µA
µ
µA
µ
µA
µ
µA
µ
µA
0
±10
µA
2.7 V
±10
µA
20
µA
4.5
pF
0.8 V to 2.7 V
2.5 V
3
Co
VO = VCC or GND
2.5 V
4
7
pF
† All typical values are at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–27
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
tpd
A
Y
5.4
0.8
2.8
0.6
1.9
0.7
1.3
1.8
0.5
1.8
ns
ten
OE
Y
8
1
4.4
0.7
2.6
0.8
1.4
2.5
0.6
1.9
ns
tdis
OE
Y
12
1.9
4.9
1
4.6
1.5
2.6
4
0.5
2
ns
PARAMETER
UNIT
operating characteristics, TA = 25°C
PARAMETER
Cpd
3–28
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
21
22
23
25
30
1
1
1
1
1
f = 10 MHz
UNIT
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–29
SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E – MARCH 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
DGG OR DGV PACKAGE
(TOP VIEW)
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
description/ordering information
This 16-bit (dual-octal) noninverting bus
transceiver is operational at 0.8-V to 2.7-V VCC,
but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The
SN74AUC16245
is
designed
for
asynchronous communication between data
buses. The control-function implementation
minimizes external timing requirements.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
PACKAGE†
TA
–40°C to 85°C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74AUC16245DGGR
AUC16245
TVSOP – DGV
Tape and reel
SN74AUC16245DGVR
MH245
VFBGA – GQL
Tape and reel
SN74AUC16245GQLR
MH245
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–31
SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E – MARCH 2002 – REVISED DECEMBER 2002
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1DIR
NC
NC
NC
NC
1OE
B
B
1B2
1B1
GND
GND
1A1
1A2
C
C
1B4
1B3
1A4
D
1B6
1B5
VCC
GND
1A3
D
VCC
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
2A5
2B7
2B8
VCC
GND
2A6
J
VCC
GND
2A8
2A7
K
2DIR
NC
NC
NC
NC
2OE
E
F
G
H
J
K
NC – No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
logic diagram (positive logic)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
36
13
1B1
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
3–32
POST OFFICE BOX 655303
2OE
• DALLAS, TEXAS 75265
2B1
SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E – MARCH 2002 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
High-level output current
∆t/∆v
Low-level output current
0.8
2.7
VCC
0.65 × VCC
UNIT
V
V
1.7
0
0.35 × VCC
V
0.7
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
IOL
MAX
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
–0.7
–3
–5
–9
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
mA
–8
5
mA
9
5
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–33
SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E – MARCH 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
All inputs
TYP†
MIN
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VO = VCC or GND
VI = VCC or GND,
±5
µA
±10
µA
2.7 V
±10
µA
0.8 V to 2.7 V
20
Ci
VI = VCC or GND
µA
0 to 2.7 V
IO = 0
V
0
VI = VCC or GND
VI or VO = 2.7 V
IOZ‡
ICC
UNIT
Cio
VO = VCC or GND
† All typical values are at TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
2.5 V
3
pF
2.5 V
7
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
tpd
A or B
B or A
5.6
0.5
3.1
0.5
2
0.5
1.5
2
0.4
1.9
ns
ten
OE
A or B
10
0.7
4.6
0.7
3.1
0.7
2.1
3.1
0.7
2.6
ns
tdis
OE
A or B
12.8
0.8
6.8
0.8
5
0.8
3.4
4.8
0.5
2.9
ns
PARAMETER
UNIT
operating characteristics, TA = 25°C
PARAMETER
Cpd
3–34
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
22
23
24
25
29
1
1
1
1
1
f = 10 MHz
UNIT
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E – MARCH 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–35
SN74AUCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES400C – JULY 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
description/ordering information
This 16-bit (dual-octal) noninverting bus
transceiver is operational at 0.8-V to 2.7-V VCC,
but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The SN74AUCH16245 is designed for
asynchronous communication between data
buses. The control-function implementation
minimizes external timing requirements.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
This device can be used as two 8-bit transceivers
or one 16-bit transceiver. It allows data
transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP – DGG
Tape and reel
SN74AUCH16245DGGR
TVSOP – DGV
Tape and reel
SN74AUCH16245DGVR
VFBGA – GQL
Tape and reel
SN74AUCH16245GQLR
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–37
PRODUCT PREVIEW
D
DGG OR DGV PACKAGE
(TOP VIEW)
SN74AUCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES400C – JULY 2002 – REVISED DECEMBER 2002
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
3
4
5
6
A
A
1DIR
NC
NC
NC
NC
1OE
B
B
1B2
1B1
GND
GND
1A1
1A2
C
C
1B4
1B3
1A4
D
1B6
1B5
VCC
GND
1A3
D
VCC
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
2A5
2B7
2B8
VCC
GND
2A6
J
VCC
GND
2A8
2A7
K
2DIR
NC
NC
NC
NC
2OE
E
F
G
H
J
K
PRODUCT PREVIEW
2
NC – No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
logic diagram (positive logic)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
36
13
1B1
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
3–38
POST OFFICE BOX 655303
2OE
• DALLAS, TEXAS 75265
2B1
SN74AUCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES400C – JULY 2002 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
High-level output current
∆t/∆v
Low-level output current
0.8
2.7
VCC
0.65 × VCC
UNIT
V
V
1.7
0
0.35 × VCC
V
0.7
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
IOL
MAX
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
–0.7
–3
–5
–9
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
mA
–8
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–39
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
SN74AUCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES400C – JULY 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
PRODUCT PREVIEW
II
IBHL‡
IBHH§
IBHLO¶
All inputs
MIN
TYP†
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI = 0.35 V
±5
0 to 2.7 V
VI = 0.47 V
VI = 0.57 V
1.1 V
10
1.4 V
15
1.65 V
20
VI = 0.7 V
VI = 0.8 V
2.3 V
40
1.1 V
–10
VI = 0.9 V
VI = 1.07 V
1.4 V
–15
1.65 V
–20
VI = 1.7 V
2.3 V
–40
1.3 V
75
VI = 0 to VCC
IBHHO#
VI = 0 to VCC
Ioff
IOZ||
VI or VO = 2.7 V
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
1.6 V
125
1.95 V
175
2.7 V
275
1.3 V
–75
1.6 V
–125
1.95 V
–175
2.7 V
–275
0
2.7 V
IO = 0
0.8 V to 2.7 V
2.5 V
UNIT
V
µA
µ
µA
µ
µA
µ
µA
µ
µA
±10
µA
±10
µA
20
µA
pF
Cio
VO = VCC or GND
2.5 V
pF
† All typical values are at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| For I/O ports, the parameter IOZ includes the input leakage current.
3–40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES400C – JULY 2002 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ns
ten
OE
A or B
ns
tdis
OE
A or B
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
UNIT
MAX
operating characteristics, TA = 25°C
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
f = 10 MHz
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
pF
PRODUCT PREVIEW
PARAMETER
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–41
SN74AUCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES400C – JULY 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
PRODUCT PREVIEW
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
3–42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES401C – JULY 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
DGG OR DGV PACKAGE
(TOP VIEW)
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description/ordering information
This 16-bit transparent D-type latch is operational
at 0.8-V to 2.7-V VCC, but is designed specifically
for 1.65-V to 1.95-V VCC operation.
The SN74AUC16373 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The device can be used as two 8-bit latches or one
16-bit latch. When the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels set up at the D inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
PACKAGE†
TA
–40°C to 85°C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74AUC16373DGGR
AUC16373
TVSOP – DGV
Tape and reel
SN74AUC16373DGVR
MH373
VFBGA – GQL
Tape and reel
SN74AUC16373GQLR
MH373
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–43
SN74AUC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES401C – JULY 2002 – REVISED DECEMBER 2002
description/ordering information (continued)
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
A
1OE
NC
NC
NC
NC
1LE
B
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
1D4
1Q6
1Q5
VCC
GND
1D3
D
VCC
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
C
D
E
F
G
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
GND
2D6
2D5
2D8
2D7
NC
NC
2LE
H
J
2Q7
2Q8
VCC
GND
J
K
2OE
NC
NC
K
NC – No internal connection
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
1OE
1LE
1
2OE
48
2LE
C1
1D1
47
2
1D
24
25
C1
1Q1
2D1
36
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
3–44
POST OFFICE BOX 655303
1D
• DALLAS, TEXAS 75265
13
2Q1
SN74AUC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES401C – JULY 2002 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
MAX
0.8
2.7
VCC
0.65 × VCC
V
V
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–45
SN74AUC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES401C – JULY 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
All inputs
MIN
VCC
0.8 V to 2.7 V
TYP†
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
IOZ
ICC
VO = VCC or GND
VI = VCC or GND,
Ci
VI = VCC or GND
0 to 2.7 V
0
2.7 V
IO = 0
0.8 V to 2.7 V
Co
VO = VCC or GND
† All typical values are at TA = 25°C.
UNIT
V
±5
µA
±10
µA
±10
µA
20
µA
2.5 V
3
4
pF
2.5 V
5.5
6.5
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
TYP
MIN
VCC = 1.5 V
± 0.1 V
MAX
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
tw
tsu
Pulse duration, LE high
4.2
2.9
2.3
2.1
1.7
ns
Setup time, data before LE↓
1.7
0.7
0.5
0.4
0.4
ns
th
Hold time, data after LE↓
–
1.2
0.8
0.7
0.6
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
tpd
3–46
FROM
(INPUT)
TO
(OUTPUT)
D
LE
Q
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
8
1.1
3.8
0.6
2.4
0.7
1.5
2.4
0.6
1.9
10.6
1.4
4.9
0.7
3.2
0.7
1.6
2.8
0.6
2.1
UNIT
ns
ten
OE
Q
9
1.3
4.5
0.6
2.9
0.8
1.7
2.9
0.7
2.2
ns
tdis
OE
Q
13
2.4
7
0.8
4.8
1.1
2.7
4.6
0.4
2.5
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES401C – JULY 2002 – REVISED DECEMBER 2002
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
21
22
23
25
29
5
5
6
7
10
f = 10 MHz
UNIT
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–47
SN74AUC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES401C – JULY 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
3–48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description/ordering information
This 16-bit transparent D-type latch is operational
at 0.8-V to 2.7-V VCC, but is designed specifically
for 1.65-V to 1.95-V VCC operation.
The SN74AUCH16373 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The device can be used as two 8-bit latches or one
16-bit latch. When the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels set up at the D inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP – DGG
Tape and reel
SN74AUCH16373DGGR
TVSOP – DGV
Tape and reel
SN74AUCH16373DGVR
VFBGA – GQL
Tape and reel
SN74AUCH16373GQLR
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–49
PRODUCT PREVIEW
D
DGG OR DGV PACKAGE
(TOP VIEW)
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
description/ordering information (continued)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1LE
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
1D4
1Q6
1Q5
VCC
GND
1D3
D
VCC
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
2D5
J
2Q7
2Q8
VCC
GND
2D6
H
VCC
GND
2D8
2D7
J
K
2OE
NC
NC
NC
NC
2LE
A
B
C
D
E
F
PRODUCT PREVIEW
G
K
NC – No internal connection
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
1OE
1LE
1
2OE
48
2LE
C1
1D1
47
2
1D
24
25
C1
1Q1
2D1
36
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
3–50
POST OFFICE BOX 655303
1D
• DALLAS, TEXAS 75265
13
2Q1
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
MAX
0.8
2.7
VCC
0.65 × VCC
V
V
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–51
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
PRODUCT PREVIEW
II
IBHL‡
IBHH§
IBHLO¶
All inputs
MIN
TYP†
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI = 0.35 V
±5
0 to 2.7 V
VI = 0.47 V
VI = 0.57 V
1.1 V
10
1.4 V
15
1.65 V
20
VI = 0.7 V
VI = 0.8 V
2.3 V
40
1.1 V
–10
VI = 0.9 V
VI = 1.07 V
1.4 V
–15
1.65 V
–20
VI = 1.7 V
2.3 V
–40
1.3 V
75
VI = 0 to VCC
IBHHO#
VI = 0 to VCC
Ioff
IOZ
VI or VO = 2.7 V
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
1.6 V
125
1.95 V
175
2.7 V
275
1.3 V
–75
1.6 V
–125
1.95 V
–175
2.7 V
–275
0
2.7 V
IO = 0
0.8 V to 2.7 V
2.5 V
UNIT
V
µA
µ
µA
µ
µA
µ
µA
µ
µA
±10
µA
±10
µA
20
µA
pF
Co
VO = VCC or GND
2.5 V
pF
† All typical values are at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
3–52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 0.8 V
TYP
VCC = 1.2 V
± 0.1 V
MIN
VCC = 1.5 V
± 0.1 V
MAX
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
tw
tsu
Pulse duration, LE high
ns
Setup time, data before LE↓
ns
th
Hold time, data after LE↓
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
VCC = 1.2 V
± 0.1 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
TYP
MAX
VCC = 2.5 V
± 0.2 V
MIN
D
tpd
LE
UNIT
MAX
Q
ns
ten
OE
Q
ns
tdis
OE
Q
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
f = 10 MHz
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
pF
• DALLAS, TEXAS 75265
3–53
PRODUCT PREVIEW
PARAMETER
SN74AUCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES402C – JULY 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
PRODUCT PREVIEW
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
3–54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403C – JULY 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
DGG OR DGV PACKAGE
(TOP VIEW)
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description/ordering information
This 16-bit edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC16374 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit flip-flops or one 16-bit
flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on
the logic levels set up at the data (D) inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
PACKAGE†
TA
–40°C to 85°C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74AUC16374DGGR
AUC16374
TVSOP – DGV
Tape and reel
SN74AUC16374DGVR
MH374
VFBGA – GQL
Tape and reel
SN74AUC16374GQLR
MH374
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–55
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403C – JULY 2002 – REVISED DECEMBER 2002
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1CLK
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
1D4
1Q6
1Q5
VCC
GND
1D3
D
VCC
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
2D5
J
2Q7
2Q8
VCC
GND
2D6
H
VCC
GND
2D8
2D7
J
K
2OE
NC
NC
NC
NC
2CLK
A
B
C
D
E
F
G
K
NC – No internal connection
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
logic diagram (positive logic)
1OE
1CLK
1D1
1
2OE
48
47
2CLK
C1
2
1D
1Q1
24
25
C1
2D1
36
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
3–56
POST OFFICE BOX 655303
1D
• DALLAS, TEXAS 75265
13
2Q1
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403C – JULY 2002 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
MAX
0.8
2.7
VCC
0.65 × VCC
V
V
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–57
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403C – JULY 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
All inputs
MIN
VCC
0.8 V to 2.7 V
TYP†
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
IOZ
ICC
VO = VCC or GND
VI = VCC or GND,
Ci
VI = VCC or GND
0 to 2.7 V
0
2.7 V
IO = 0
0.8 V to 2.7 V
Co
VO = VCC or GND
† All typical values are at TA = 25°C.
UNIT
V
±5
µA
±10
µA
±10
µA
20
µA
2.5 V
3
pF
2.5 V
5
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 0.8 V
TYP
VCC = 1.2 V
± 0.1 V
MIN
VCC = 1.5 V
± 0.1 V
MAX
MIN
fclock
tw
Clock frequency
85
Pulse duration, CLK high or low
5.9
tsu
th
Setup time, data before CLK↑
1.4
1
1
Hold time, data after CLK↑
0.1
0.9
0.9
VCC = 1.8 V
± 0.15 V
MAX
250
MIN
250
1.9
MAX
VCC = 2.5 V
± 0.2 V
MIN
250
1.9
1.9
UNIT
MAX
250
MHz
1.9
ns
1
1
ns
0.9
0.9
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
3–58
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
TYP
MIN
85
250
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
250
VCC = 1.8 V
± 0.15 V
MIN
TYP
VCC = 2.5 V
± 0.2 V
MAX
250
MIN
UNIT
MAX
250
MHz
tpd
CLK
Q
7.3
1
4.5
0.8
2.9
0.7
1.5
2.8
0.7
2.2
ns
ten
OE
Q
7
1.2
5.3
0.8
3.6
0.8
1.5
2.9
0.7
2.2
ns
tdis
OE
Q
8.2
2
7.1
1
4.8
1.4
2.7
4.5
0.5
2.2
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403C – JULY 2002 – REVISED DECEMBER 2002
operating characteristics, TA = 25°C†
TEST
CONDITIONS
PARAMETER
Cpd‡
(each
output)
Cpd
(Z)
Cpd§
(each
clock)
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
Power
dissipation
capacitance
Outputs
enabled,
1 output
switching
1 fdata = 5 MHz
1 fclk = 10 MHz
1 fout = 5 MHz
OE = GND
CL = 0 pF
24
24
24.1
26.2
31.2
pF
Power
dissipation
capacitance
Outputs
disabled,
1 clock
and 1
data
switching
1 fdata = 5 MHz
1 fclk = 10 MHz
fout = not
switching
OE = VCC
CL = 0 pF
7.5
7.5
8
9.4
13.2
pF
Power
dissipation
capacitance
Outputs
disabled,
clock
only
switching
1 fdata = 0 MHz
1 fclk = 10 MHz
fout = not
switching
OE = VCC
CL = 0 pF
13.8
13.8
14
14.7
17.5
pF
† Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)}.
‡ Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz in this
test, but its ICC component has been subtracted out).
§ Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–59
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403C – JULY 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
3–60
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404C – JULY 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description/ordering information
This 16-bit edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUCH16374 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit flip-flops or one 16-bit
flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on
the logic levels set up at the data (D) inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP – DGG
Tape and reel
SN74AUCH16374DGGR
TVSOP – DGV
Tape and reel
SN74AUCH16374DGVR
VFBGA – GQL
Tape and reel
SN74AUCH16374GQLR
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–61
PRODUCT PREVIEW
D
DGG OR DGV PACKAGE
(TOP VIEW)
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404C – JULY 2002 – REVISED DECEMBER 2002
description/ordering information (continued)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1CLK
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
1D4
1Q6
1Q5
VCC
GND
1D3
D
VCC
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
2D5
J
2Q7
2Q8
VCC
GND
2D6
H
VCC
GND
2D8
2D7
J
K
2OE
NC
NC
NC
NC
2CLK
A
B
C
D
E
F
PRODUCT PREVIEW
G
K
NC – No internal connection
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
logic diagram (positive logic)
1OE
1CLK
1D1
1
2OE
48
47
2CLK
C1
2
1D
1Q1
24
25
C1
2D1
36
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
3–62
POST OFFICE BOX 655303
1D
• DALLAS, TEXAS 75265
13
2Q1
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404C – JULY 2002 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
VO
Input voltage
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
MAX
0.8
2.7
VCC
0.65 × VCC
V
V
0
0.35 × VCC
V
0.7
0
3.6
V
0
VCC
–0.7
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
UNIT
1.7
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–63
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404C – JULY 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
PRODUCT PREVIEW
II
IBHL‡
IBHH§
IBHLO¶
All inputs
MIN
TYP†
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI = 0.35 V
±5
0 to 2.7 V
VI = 0.47 V
VI = 0.57 V
1.1 V
10
1.4 V
15
1.65 V
20
VI = 0.7 V
VI = 0.8 V
2.3 V
40
1.1 V
–10
VI = 0.9 V
VI = 1.07 V
1.4 V
–15
1.65 V
–20
VI = 1.7 V
2.3 V
–40
1.3 V
75
VI = 0 to VCC
IBHHO#
VI = 0 to VCC
Ioff
IOZ
VI or VO = 2.7 V
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
1.6 V
125
1.95 V
175
2.7 V
275
1.3 V
–75
1.6 V
–125
1.95 V
–175
2.7 V
–275
0
2.7 V
IO = 0
0.8 V to 2.7 V
2.5 V
UNIT
V
µA
µ
µA
µ
µA
µ
µA
µ
µA
±10
µA
±10
µA
20
µA
pF
Co
VO = VCC or GND
2.5 V
pF
† All typical values are at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
3–64
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404C – JULY 2002 – REVISED DECEMBER 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 0.8 V
TYP
VCC = 1.2 V
± 0.1 V
MIN
VCC = 1.5 V
± 0.1 V
MAX
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
MHz
Pulse duration, CLK high or low
ns
tsu
th
Setup time, data before CLK↑
ns
Hold time, data after CLK↑
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
VCC = 1.2 V
± 0.1 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
TYP
MAX
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
MHz
tpd
CLK
Q
ns
ten
OE
Q
ns
tdis
OE
Q
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
f = 10 MHz
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
pF
• DALLAS, TEXAS 75265
3–65
PRODUCT PREVIEW
fmax
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404C – JULY 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
PRODUCT PREVIEW
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
3–66
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
General Information
AUC Single Gates
AUC Widebus
AUC Widebus+
Application Reports
Mechanical Data
4–1
Contents
Page
SN74AUCH32244 32-Bit Buffer/Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
SN74AUC32245
AUC Widebus+ 
4–2
32-Bit Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
SN74AUCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
Widebus+ Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 1.8 ns at 1.8 V
Low Power Consumption, 40-µA Max ICC
D ±8-mA Output Drive at 1.8 V
D Bus Hold on Data Inputs Eliminates the
D
D
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 32-bit buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The SN74AUCH32244 is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides
true outputs and symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C LFBGA – GKE
Tape and reel
SN74AUCH32244GKER
MK244
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus+ is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4–3
SN74AUCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1Y2
1Y1
1OE
2OE
1A1
1A2
B
B
1Y4
1Y3
GND
GND
1A3
1A4
C
C
2Y2
2Y1
2A2
D
2Y4
2Y3
VCC
GND
2A1
D
VCC
GND
2A3
2A4
E
3Y2
3Y1
GND
GND
3A1
3A2
F
3Y4
3Y3
3A4
4Y2
4Y1
VCC
GND
3A3
G
VCC
GND
4A1
4A2
H
4Y3
4Y4
4OE
3OE
4A4
4A3
E
F
G
H
J
K
L
M
J
5Y2
5Y1
5OE
6OE
5A1
5A2
K
5Y4
5Y3
GND
GND
5A3
5A4
L
6Y2
6Y1
6A2
6Y4
6Y3
VCC
GND
6A1
M
VCC
GND
6A3
6A4
N
7Y2
7Y1
GND
GND
7A1
7A2
N
P
7Y4
7Y3
8Y2
8Y1
VCC
GND
7A4
R
VCC
GND
7A3
P
8A1
8A2
R
T
8Y3
8Y4
8OE
7OE
8A4
8A3
T
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
4–4
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
5OE
5A1
5A2
5A3
5A4
6OE
6A1
6A2
6A3
6A4
A3
3OE
A5
A2
A6
A1
B5
B2
B6
B1
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
A4
4OE
C5
C2
C6
C1
D5
D2
D6
D1
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
J3
7OE
J5
J2
J6
J1
K5
K2
K6
K1
5Y1
7A1
5Y2
7A2
5Y3
7A3
5Y4
7A4
J4
8OE
L5
L2
L6
L1
M5
M2
M6
M1
6Y1
8A1
6Y2
8A2
6Y3
8A3
6Y4
8A4
POST OFFICE BOX 655303
H4
E5
E2
E6
E1
F5
F2
F6
F1
3Y1
3Y2
3Y3
3Y4
H3
G5
G2
G6
G1
H6
H1
H5
H2
4Y1
4Y2
4Y3
4Y4
T4
N5
N2
N6
N1
P5
P2
P6
P1
7Y1
7Y2
7Y3
7Y4
T3
R5
R2
R6
R1
T6
T1
T5
T2
• DALLAS, TEXAS 75265
8Y1
8Y2
8Y3
8Y4
4–5
SN74AUCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
∆t/∆v
0.8
2.7
VCC
0.65 × VCC
High-level output current
Input transition rise or fall rate
V
V
1.7
0
0.35 × VCC
V
0.7
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V
VCC = 1.65 V
Low-level output current
UNIT
0
VCC = 2.3 V
VCC = 0.8 V
IOL
MAX
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
–0.7
–3
–5
mA
–8
–9
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
VCC = 0.8 V
VCC = 1.3 V
20
5
mA
9
15
ns/V
VCC = 1.6 V, 1.95 V, and 2.7 V
10
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
IBHL‡
IBHH§
IBHLO¶
A or OE inputs
MIN
TYP†
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI = 0.35 V
±5
0 to 2.7 V
VI = 0.47 V
VI = 0.57 V
1.1 V
10
1.4 V
15
1.65 V
20
VI = 0.7 V
VI = 0.8 V
2.3 V
40
1.1 V
–10
VI = 0.9 V
VI = 1.07 V
1.4 V
–15
1.65 V
–20
VI = 1.7 V
2.3 V
–40
1.3 V
75
VI = 0 to VCC
IBHHO#
VI = 0 to VCC
Ioff
IOZ
VI or VO = 2.7 V
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
1.6 V
125
1.95 V
175
2.7 V
275
1.3 V
–75
1.6 V
–125
1.95 V
–175
2.7 V
–275
V
µA
µ
µA
µ
µA
µ
µA
µ
µA
0
±10
µA
2.7 V
±10
µA
40
µA
4.5
pF
0.8 V to 2.7 V
2.5 V
3
Co
VO = VCC or GND
2.5 V
4
7
pF
† All typical values are at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4–7
SN74AUCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
tpd
A
Y
5.4
0.8
2.8
0.6
1.9
0.7
1.3
1.8
0.5
1.8
ns
ten
OE
Y
8
1
4.4
0.7
2.6
0.8
1.4
2.5
0.6
1.9
ns
tdis
OE
Y
12
1.9
4.9
1
4.6
1.5
2.6
4
0.5
2
ns
PARAMETER
UNIT
operating characteristics, TA = 25°C
PARAMETER
Cpd
4–8
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
21
22
23
25
30
1
1
1
1
1
f = 10 MHz
UNIT
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4–9
SN74AUC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES410C – AUGUST 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
D
D
D
D
Widebus+ Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2 ns at 1.8 V
D Low Power Consumption, 40-µA Max ICC
D ±8-mA Output Drive at 1.8 V
D Latch-Up Performance Exceeds 100 mA Per
D
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 32-bit noninverting bus transceiver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC32245 is designed for asynchronous communication between data buses. The control-function
implementation minimizes external timing requirements.
This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows
data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at
the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the
buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C LFBGA – GKE
Tape and reel
SN74AUC32245GKER
MM245
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Widebus+ is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4–11
SN74AUC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES410C – AUGUST 2002 – REVISED DECEMBER 2002
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1B2
1B1
1DIR
1OE
1A1
1A2
B
B
1B4
1B3
GND
GND
1A3
1A4
C
C
1B6
1B5
1A6
D
1B8
1B7
VCC
GND
1A5
D
VCC
GND
1A7
1A8
E
2B2
2B1
GND
GND
2A1
2A2
F
2B4
2B3
2A4
2B6
2B5
VCC
GND
2A3
G
VCC
GND
2A5
2A6
H
2B7
2B8
2DIR
2OE
2A8
2A7
E
F
G
H
J
K
L
M
J
3B2
3B1
3DIR
3OE
3A1
3A2
K
3B4
3B3
GND
GND
3A3
3A4
L
3B6
3B5
3A6
3B8
3B7
VCC
GND
3A5
M
VCC
GND
3A7
3A8
N
4B2
4B1
GND
GND
4A1
4A2
N
P
4B4
4B3
4B6
4B5
VCC
GND
4A4
R
VCC
GND
4A3
P
4A5
4A6
R
T
4B7
4B8
4DIR
4OE
4A8
4A7
T
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
4–12
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES410C – AUGUST 2002 – REVISED DECEMBER 2002
logic diagram (positive logic)
1DIR
A3
2DIR
A4
1A1
H4
1OE
A5
2A1
A2
H3
E5
E2
1B1
To Seven Other Channels
3DIR
2B1
To Seven Other Channels
J3
4DIR
J4
3A1
2OE
T4
3OE
J5
4A1
J2
T3
4OE
N5
N2
3B1
To Seven Other Channels
4B1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
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4–13
SN74AUC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES410C – AUGUST 2002 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
Input voltage
VO
∆t/∆v
0.8
2.7
VCC
0.65 × VCC
Output voltage
High-level output current
V
V
1.7
0
0.35 × VCC
V
0.7
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V
VCC = 1.65 V
Low-level output current
UNIT
0
VCC = 2.3 V
VCC = 0.8 V
IOL
MAX
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
–0.7
–3
–5
–9
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
mA
–8
5
mA
9
5
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4–14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES410C – AUGUST 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
Ioff
All inputs
TYP†
MIN
MAX
VCC–0.1
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VO = VCC or GND
VI = VCC or GND,
±5
µA
±10
µA
2.7 V
±10
µA
0.8 V to 2.7 V
40
Ci
VI = VCC or GND
µA
0 to 2.7 V
IO = 0
V
0
VI = VCC or GND
VI or VO = 2.7 V
IOZ‡
ICC
UNIT
Cio
VO = VCC or GND
† All typical values are at TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
2.5 V
3
pF
2.5 V
7
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
tpd
A or B
B or A
5.6
0.5
3.1
0.5
2
0.5
1.5
2
0.4
1.9
ns
ten
OE
A or B
10
0.7
4.6
0.7
3.1
0.7
2.1
3.1
0.7
2.6
ns
tdis
OE
A or B
12.8
0.8
6.8
0.8
5
0.8
3.4
4.8
0.5
2.9
ns
PARAMETER
UNIT
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
TEST
CONDITIONS
VCC = 0.8 V
TYP
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
22
23
24
25
29
1
1
1
1
1
f = 10 MHz
UNIT
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4–15
SN74AUC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES410C – AUGUST 2002 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
CL
15 pF
15 pF
15 pF
30 pF
30 pF
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4–16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
General Information
AUC Single Gates
AUC Widebus
AUC Widebus+
Application Reports
Mechanical Data
5–1
Contents
Page
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices . . . . . . . . . . . . . . . . . . 5–3
Application Reports
5–2
Application Report
SCEA027A - September 2002
Application of the Texas Instruments
AUC Sub-1-V Little Logic Devices
Chris Maxwell and Tomdio Nana
Standard Linear & Logic
ABSTRACT
Power consumption and speed are always concerns in electronic system logic design. Texas
Instruments (TI) announces the industry’s first sub-1-V logic family that provides significant
benefits to portable consumer electronics by operating at low power and high speed, while
maintaining overall system signal integrity. TI’s next-generation logic family is the advanced
ultra-low-voltage CMOS (AUC) family. Although optimized for 1.8-V operation, AUC logic
supports mixed-voltage systems because it is compatible with 0.8-V, 1.2-V, 1.5-V and 2.5-V
devices. The AUC logic inputs tolerate 3.6-V signals, thus enabling level-translation down
from 3.3-V nodes to lower-voltage nodes. Further, AUC logic has the Ioff feature, which
supports the partial-power-down mode of operation. This application report discusses AUC
Little Logic device features, characteristics, and applications.
Keywords: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3-V tolerant, AUC, electrical performance, Ioff,
level translation, Little Logic, open drain, overvoltage protection, partial power down, signal
integrity, ULTTL
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
2
AUC Little Logic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
2.1 Novel Output Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
2.2 Level-Translation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
2.3 Power-Off Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
3
AUC Little Logic Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Input Voltage Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Slow-Input-Edge-Rate Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 AC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 DC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11
5–11
5–11
5–11
5–12
5–15
5–15
5–17
5–19
4
Design Issues and AUC Little Logic Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Mixed-Voltage-Mode Data Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Partial Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Low Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–21
5–21
5–24
5–26
5–26
TI and Widebus are trademarks of Texas Instruments.
5–3
SCEA027A
5
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28
6
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29
7
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30
8
Frequently Asked Questions (FAQs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30
9
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32
10
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32
Appendix A. Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34
Appendix B. Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–36
List of Figures
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
5–4
ULTTL Output Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
Output Drive Currents of UOP During Low-to-High Transition . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
SN74AUC1G00 Slow-Input Transition-Time Plot, ∆t/∆V = 11.69 ns/V . . . . . . . . . . . . . . . . . . 5–13
SN74AUC1G00 Slow-Input Transition-Time Plot, ∆t/∆V = 23.19 ns/V . . . . . . . . . . . . . . . . . . 5–14
tpd vs Capacitive Load at 2.5-V, 1.8-V, and 1.5-V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
tpd vs Capacitive Load at 1.2-V and 0.8-V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
VOH vs IOH for AUC1G Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
VOL vs IOL for AUC1G Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Relative Power Efficiency of Selected Little Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
Transmission-Line Test Points for Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21
Output Impedance, Output Voltage, and Receiver Voltage of AUC Single-Gate
Transmission-Line Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22
Simulation of 65-Ω Transmission Line Across Supply Voltage and Temperature . . . . . . . . . 5–22
Simulation of Low-to-High Transition into 30-Ω to 70-Ω Transmission Line . . . . . . . . . . . . . . 5–23
Simulation of High-to-Low Transition into 30-Ω to 70-Ω Transmission Line . . . . . . . . . . . . . . 5–23
Device at 1.8-V VCC, With 2.5-V or 3.3-V Inputs, Showing Switching Levels . . . . . . . . . . . . 5–24
Circuit for Voltage Translation Using the SN74AUC1G07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–25
ICC vs Frequency for Different AUC Little Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27
ICC vs Frequency for SN74AUC1G06 and SN74LVC1G06 Devices . . . . . . . . . . . . . . . . . . . 5–27
AUC Little Logic (with ULTTL Outputs) Load Circuit and Voltage Waveforms . . . . . . . . . . . . 5–34
AUC Little Logic (with Open-Drain Outputs) Load Circuit and Voltage Waveforms . . . . . . . 5–35
Plastic Small Outline Package (DBV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–36
Plastic Small Outline Package (DCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–37
Die-Size Ball Grid Array (YEA or YZA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–38
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
List of Tables
1.
2.
3.
4.
5.
6.
Input Capacitance and Speed Comparison for Comparable Families . . . . . . . . . . . . . . . . . .
Input Transition for Some AUC Little Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics of AUC Little Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption and Speed of Selected Little Logic Devices at Their
Optimized Supply-Voltage Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements for Voltage Translation Between Devices A and B . . . . . . . . . . . . . . . . . . . . . .
Features and Benefits of AUC Little Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11
5–14
5–15
5–20
5–25
5–29
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
5–5
SCEA027A
1
Introduction
Many electronic applications have shifted from the legacy bipolar TTL interface to CMOS
rail-to-rail interface. The CMOS technology has facilitated supply-voltage migration from 5 V to
3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 0.8 V. These lower-voltage nodes allow decreased power
consumption in the system. To facilitate migration to lower-voltage nodes, TI has released the
advanced ultra-low-voltage CMOS (AUC) family, which is optimized for 1.8-V operation and is
compatible with 0.8-V, 1.2-V, 1.5-V, 1.8-V, and 2.5-V devices.
TI offers the AUC functions in Widebus, octal, gates, and Little Logic (single, double, and triple
gate) options. The widebus, octal, and gate AUC devices are designed for high-speed data
throughput and enhanced signal integrity to target bus applications in telecommunications and
computing systems. The Little Logic AUC devices have high speed, low power consumption,
and low-noise characteristics, which make them suitable for portable consumer electronics
applications.
This application report discusses AUC Little Logic device features, characteristics, and
applications.
5–6
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
2
AUC Little Logic Features
The AUC Little Logic devices are designed for use in battery-operated portable consumer
electronics or to fix design bugs in electronic systems. The characteristic output structure,
level-translation support capability, and partial-power-down support features of the AUC Little
Logic facilitate the use of these devices in their targeted applications.
2.1
Novel Output Structure
The AUC Little Logic features the ultra-low-voltage transistor-transistor logic (ULTTL) output
driver. The ULTTL is a new CMOS-technology interface driver designed for applications
requiring high-speed, low power consumption, and optimal signal integrity, while maintaining the
bipolar TTL output characteristic of reduced line-reflection noise. With the migration from bipolar
TTL technology to CMOS technology for lower-operating-voltage nodes, the ULTTL output driver
was developed to minimize switching noise, which is inherent in high-speed applications.
The ULTTL output driver of the AUC Little Logic changes impedance during transition. Three
basic output features are critical for optimal performance in low-voltage high-speed applications.
First, the device must provide low-impedance (i.e., high dynamic current) drive during the initial
phase of the transition through the ac threshold (i.e., VCC/2). This initial high drive provides the
quick transition to the desired logic level and ensures that system timing is preserved. During the
second phase of the transition, the impedance must be equal to that of the transmission-line
medium it is driving, to minimize ringing and optimize signal integrity. A major cause of ringing in
point-to-point applications is the result of a mismatch or discontinuity between the output
impedance of the driver and the impedance of the transmission line (i.e., PCB trace). AUC Little
Logic devices have been optimized for transmission lines of 50 Ω to 65 Ω, which is typical of
most portable PCB applications. Finally, the output should stabilize at an impedance low enough
to provide the required dc drive. For most portable applications, 4-mA dc drive is sufficient;
however, for nonportable applications, more drive current might be required.
The majority of application loads targeted for the AUC Little Logic family can be represented as
a transmission line rather than a dc load. Thus, ac operation is dominated by the inductance and
capacitance of the load and, in most cases, heavy drive capabilities are not required, although
they are provided up to 8 mA at 1.8-V VCC.
AUC Little Logic devices provide 8-mA dc drive current at the 1.8-V VCC node for nonportable
applications, while maintaining the signal-integrity performance of a 4-mA dc driver. The ULTTL
output used in the AUC Little Logic family is designed to address each of the three critical
performance requirements previously noted. Figure 1 shows a schematic of the ULTTL output
structure.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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ACB
TLB
DCB
Control
Feedback
Internal
Node
VOUT
Control
Feedback
Figure 1. ULTTL Output Structure
To achieve the three impedance phases, the ULTTL output utilizes a three-branch p-channel
upper-output (UOP) and three-branch n-channel lower-output (LOP) structure (see Figure 1).
For the purpose of illustration, the three branches are referred to in this application report as the
ac branch (ACB), the transmission-line branch (TLB), and the dc branch (DCB). The first branch,
which uses the diode in the output structure, provides the high dynamic current required to drive
through the ac threshold. The second branch, which contains a series resistor, provides
optimized impedance matching into the transmission line. The third branch provides the
additional dc current drive for applications requiring more than 4 mA of output drive current at
1.8-V VCC.
Each independent branch posses a unique on-state resistance (ron). As the output transitions
from a low to high (or high to low), the equivalent resistance of all branches varies in a controlled
manner by adjusting the individual resistance of each branch. The low-to-high transition
functions similarly to the high-to-low transition. The output impedance is controlled during the
low-to-high transition sequential action outlined below and shown in Figure 2.
1. During the initial phase of the transition, all three legs are turned on. The parallel ron of all
three legs provides very low combined impedance.
2. During the second phase of the transition, the ACB and DCB are turned off, and the
output transitions to a higher impedance. As the output voltage level approaches VCC, the
series diode begins to saturate and, eventually, becomes reverse biased, causing the
current through the ACB to be reduced to less than 1 mA (basically, turned off). A
threshold-controlled feedback circuit turns off the DCB. The thresholds are adjusted, to
minimize the effect of oscillations directly at the output of the driver before entering the
transmission line. (NOTE: A major advantage for the DCB being turned on in the initial
stage is to provide support for the ACB at lower VCC ranges where speed often is
sacrificed.) The TLB ron is 50 Ω to 65 Ω and, because it is the last branch remaining on, it
provides the impedance matching to the transmission line.
3. In the final phase of the transition, the DCB is turned on by the threshold-controlled
feedback circuit to provide a combined DCB and TLB equivalent resistance that is
satisfactory for driving applications requiring more than 4 mA of output drive current at
1.8-V VCC.
5–8
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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2.0
TLB
1.8
0
1.6
1.4
–5
VOUT
–10
VOUT – V
Current – mA
1.2
1.0
VCC = 1.8 V
TJ = 25°C
Nominal Process
0.8
ACB
–15
0.6
0.4
–20
0.2
DCB
0.0
Stg 1
–25
Stg 2
Stg 3
–0.2
211
212
213
214
215
216
217
218
219
220
Time – ns
Figure 2. Output Drive Current of UOP During Low-to-High Transition
2.2
Level-Translation Support
Because the AUC Little Logic family uses a 0.8-V to 2.5-V power supply, interfacing AUC Little
Logic devices with other components that use a 3.3-V power supply becomes a concern. If an
AUC Little Logic device is subjected to 3.3-V at its inputs, it is critical that the device not be
damaged. The term 3.3-V tolerance implies that the presence of 3.3-V at either the input or the
output of the AUC device will not damage it. This feature enables AUC Little Logic devices to be
used for level-translation support from higher-voltage nodes to lower-voltage nodes within the
0.8-V and 3.3-V nodes.
Whether a device can tolerate 3.3-V only at the input, only at the output, or at both the input and
output must be considered. Every AUC Little Logic device TI produces can be subjected to 3.3-V
at its input and not be damaged. Thus, all TI AUC Little Logic devices are 3.3-V input tolerant.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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Whether or not an AUC Little Logic device can be subjected to 3.3-V at its output requires
consideration. For the term 3.3-V output tolerant to be meaningful, the outputs of the device
must be capable of being placed in the high-impedance state. Only the SN74AUC1G06,
SN74AUC1G07, SN74AUC1G125, SN74AUC1G126, and SN74AUC1G240 have
high-impedance outputs, and it is to these devices only that the term 3.3-V output tolerant
applies. For those devices with outputs capable of being placed in the high-impedance state,
3.3-V output tolerance means that 3.3 V at its output does not damage the device.
The AUC Little Logic functions that do not have high-impedance-state outputs should not be
connected to 3.3-V. This means that 3.3-V output tolerance does not make sense for these
devices because their outputs cannot be placed in the high-impedance state.
2.3
Power-Off Support
The inputs and outputs of the AUC family have a blocking diode in the reversed-current paths to
VCC. In this configuration, the maximum leakage current into or out of the input or output
transistors is negligible when forcing the input or output to 3.3 V and VCC = 0 V. This off-state
leakage current (Ioff) is small enough to allow the device to remain electrically connected to a
bus during partial power down without loading the remaining live circuits. This feature also
allows the use of this family in a mixed-voltage environment.
5–10
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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3
AUC Little Logic Device Characteristics
3.1
Input Characteristics
3.1.1
Input Capacitance
The AUC Little Logic devices provide a low input capacitance-to-speed ratio relative to similar
products (see Table 1). Two major design factors influence input capacitance: speed and
capacitive-load-driving requirements. As speed requirements become more critical, the number
of internal stages for a given integrated circuit must be reduced to minimize propagation delay.
In addition to a reduction in stages, unless the requirement to drive large capacitive loads is
reduced (especially for nonportable applications), the output stage must be large enough to
drive these loads. In most cases, the combination of these two factors results in a higher input
capacitance because the large input capacitance of the output stage is transferred to the input
stage. Simply placing a small (low input capacitance) input stage in front of the large output
stage does not result in less propagation delay.
Table 1. Input Capacitance and Speed Comparison for Comparable Families
Device
Input Capacitance
(pF)
tpd at 1.8-V VCC
(ns)
SN74AUC1G00
3.0
2.5
SN74LVC1G00
4.0
8.0
SN74ALVC00
4.5
4.4
The AUC Little Logic devices can maintain a comparable low input capacitance of 3 pF (typical),
while providing high dynamic drive capability for larger loads and providing a propagation delay
less than 2.5 ns at 1.8-V VCC (see Table 1).
3.1.2
Input Voltage Tolerance
As previously mentioned, AUC Little Logic devices operate with a 0.8-V to 2.7-V VCC. Therefore,
interfacing AUC Little Logic with other components that use 3.3-V VCC might be a concern. In
such systems, AUC Little Logic devices must have tolerance for input levels up to and
exceeding 3.3 V, as well as below 0 V, without causing damage to the inputs. The AUC Little
Logic devices allow input voltages to exceed 3.3 V, up to 3.6 V, to allow extra protection for the
following reasons:
•
The 3.3-V system power supply might not stabilize at 3.3 V, but reach 3.6 V. Consequently,
the output of the device driving the AUC Little Logic device could reach 3.6 V as well.
•
The 3.3-V system power supply may stabilize at 3.3 V, but overshoots and undershoots can
cause the input voltage into the AUC Little Logic devices to exceed the 0-V to 3.3-V range.
The AUC Little Logic devices support input voltages up to 3.6 V and must be operated within the
following guidelines:
•
The recommended operating conditions specified in the data sheets restrict the input voltage
to 0 V to 3.6 V, while the absolute maximum ratings specify the input voltage to be –0.5 V to
4.1 V. As the data sheet indicates, stresses beyond those listed under absolute maximum
ratings may cause permanent damage to the device. The absolute maximum ratings are
stress ratings only, and functional operation of the device at those or any other conditions
beyond those indicated under recommended operating conditions is not implied. Exposure to
absolute-maximum-rated conditions may affect device reliability.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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•
3.1.3
Because the input-voltage range is limited from 0 V to 3.6 V, for 3.3-V systems, proper
termination must be used on the inputs of AUC Little Logic devices to ensure that overshoot
does not exceed 3.6 V.
Slow-Input-Edge-Rate Compatibility
The AUC Little Logic devices are designed and tested for high-speed systems (i.e., systems
requiring a fast input edge rate) with input transition signals less than 1 ns/V. However, there
may be several applications where it is desired to operate the device at a low frequency. In such
applications, an input edge rate greater than 1 ns/V might be required. AUC Little Logic devices
support such low-frequency applications.
A slow-input test sheds light on the integrity of the device, specifically, how the device responds
when the input voltage is slowly ramped from 0 V to VCC and, conversely, when the input voltage
is ramped slowly from VCC to 0 V. As the input voltage is ramping, the output voltage is
monitored and, when it begins to switch, the waveform is observed. If nonmonotonic behavior is
observed as the output traverses the threshold region, the device may be sensitive to a slow
input, which can cause the output to oscillate or cause false triggering.
Figure 3 shows a passing case of slow-input-transition-rate tests. The test was done in the
laboratory using the SN74AUC1G00 with VCC = 2.7 V and the device at –40°C, with both inputs
tied together for the worst-case condition. In Figure 3, the input transition rate is fast enough
(11.69 ns/V) to not cause any oscillation at the output.
5–12
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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3.5
3.0
Output
2.5
Voltage – V
2.0
1.5
1
0.5
Input
0
–0.5
0
10
20
30
40
50
60
70
80
90
100
Time – ns
Figure 3. SN74AUC1G00 Slow-Input-Transition-Time Plot, ∆t/∆V = 11.69 ns/V
Figure 4 shows a failure case of slow-input-transition-rate tests. The test was done in the
laboratory using the SN74AUC1G00 with VCC = 2.7 V and the device at –40°C, with both inputs
tied together for the worst-case condition. In Figure 4, the input transition rate is too slow
(23.19 ns/V) and causes oscillations at the output.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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3.5
3.0
Output
2.5
Voltage – V
2.0
1.5
1
0.5
Input
0
–0.5
0
10
20
30
40
50
60
70
80
90
100
Time – ns
Figure 4. SN74AUC1G00 Slow-Input-Transition-Time Plot, ∆t/∆V = 23.19 ns/V
Table 2 shows the maximum input transition rise or fall rate for some AUC Little Logic devices at
different voltage nodes. At the optimized voltage node, all AUC Little Logic devices show
noncritical responses to the slow-input test.
Table 2. Input Transition for Some AUC Little Logic Devices
Maximum Input Transition Rise or Fall Rate, ∆t/∆V
(ns/V)
Device
SN74AUC1G00
VCC = 0.8 V
20
VCC = 1.3 V
20
VCC = 1.6 V
20
VCC = 1.95 V
20
VCC = 2.7 V
10
SN74AUC1G04
20
20
20
20
5
SN74AUC1G07
20
20
20
20
15
SN74AUC1G14
20
20
20
20
20
SN74AUC1G17
20
20
20
20
20
SN74AUC1G32
20
20
20
20
20
Table 2 shows that the AUC Little Logic devices can operate with slow signals (∆t/∆V > 1 ns/V)
at the inputs. However, power consumption increases significantly with increased input transition
rise or fall rates.
5–14
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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3.2
Electrical Characteristics
In most electronic-system applications, it is important for the integrated circuit drivers to provide
balanced high and low drive during ac transition, which ensures balanced output edge rates and
improved signal integrity. Also, balanced high and low drive ensures that the difference between
the low-to-high transition time (tPLH) and the high-to-low transition time (tPHL) is minimized. In
general, as the supply voltage lowers, the p-channel becomes weaker at a faster rate than the
n-channel transistor, due to their respective positive and negative carrier-mobility-degradation
characteristics. For devices with active p-channel pullups, this causes tPLH to increase at a
faster rate than tPHL; consequently, the |tPLH – tPHL| increases respectively. The three-branch
ULTTL output mentioned previously works to minimize this effect across VCC by distributing the
high drive across the ron of the transistor with that of the resistor (i.e., resistor in the TLB). The
resistance of the resistor does not vary with supply voltage, thus reducing the effective variation
in ron of the high and low drives.
As the supply voltage lowers, the ACB output branch provides less support for the ac transition
due to the series diode. The propagation delay performance is then affected primarily by the
TLB and DCB. Again, by inserting the series resistance, the balance between the high-drive
transistor and low-drive transistor is preserved better at lower VCC nodes.
The electrical characteristics of the AUC family are critical aspects of a successful system
design. The following sections discuss the ac and dc performance of the devices.
3.2.1
AC Performance
Table 3 shows a comparison of the propagation delay for different AUC Little Logic devices
operating at different voltage nodes. These results are from laboratory tests using the standard
load specifications in the parameter measurement information (see Appendix A).
Table 3. Timing Characteristics of AUC Little Logic Devices
Device
VCC = 0.8 V
VCC = 1.2
± 0.1 V
tpd (ns)
VCC = 1.5
± 0.1 V
VCC = 1.8
± 0.15 V
VCC = 2.5
± 0.2 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
SN74AUC1G00
4.7
0.9
3.5
0.5
2.3
0.7
1.3
2.5
0.5
2.1
SN74AUC1G02
4.6
0.9
3.4
0.5
2.2
0.7
1.3
2.5
0.5
2.1
SN74AUC1G04
4.4
0.8
3.3
0.5
2.2
0.6
1.2
2.5
0.5
1.9
SN74AUC1G06
5.0
0.3
3.1
0.2
2.5
0.5
1.6
2.9
0.2
1.9
SN74AUC1G07
4.7
0.3
3.3
0.2
2.4
0.8
1.9
2.5
0.2
1.8
SN74AUC1G08
4.7
0.9
3.5
0.6
2.6
0.7
1.3
2.5
0.5
2.1
SN74AUC1G14
5.8
0.7
4.2
0.6
2.7
0.7
1.6
2.8
0.5
2.5
SN74AUC1G17
5.7
0.8
4.0
0.7
2.4
0.8
1.4
2.5
0.7
2.6
SN74AUC1G32
4.8
1.0
3.5
0.6
2.3
0.8
1.4
2.5
0.6
2.1
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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Table 3 shows that the AUC Little Logic devices have very low propagation delay. The devices
appear to be optimized at the 1.5-V node because the tpd is lowest when VCC = 1.5 V. However,
the tpd values are measured under different load conditions (see Appendix A). The AUC Little
Logic devices are optimized at the 1.8-V node but, because the 1.8-V node test load
(RL = 1 kΩ; CL = 30 pF) is heavier than the 1.5-V test load (RL = 2 kΩ; CL = 15 pF), the devices
appear to be slower at the 1.8-V node than they are at the 1.5-V node. The test loads used for
characterizing the devices are the standard JEDEC test loads at the respective voltage nodes.
A true comparison of the propagation delays of the AUC Little Logic devices at different voltage
nodes is obtained by measuring the propagation delays at different voltage nodes when the
device is under the same loading condition. Figure 5 shows typical variations of propagation
delay with respect to capacitive loading for 1.5-V, 1.8-V, and 2.5-V VCC. In all three cases, a
resistive load of 1 MΩ was connected between the output and ground. The data were collected
under nominal-process conditions from the SN74AUC1G00 at 25°C. Similarly, Figure 6 shows
typical variations of propagation delay with respect to capacitive loading for 0.8-V and 1.2-V
VCC. The data also were collected under the same conditions as for Figure 5.
3
VCC = 1.5 V
2.5
VCC = 1.8 V
tpd – ns
2
VCC = 2.5 V
1.5
1
0.5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
CL – Capactive Load – pF
Figure 5. tpd vs Capacitive Load at 2.5-V, 1.8-V, and 1.5-V VCC
5–16
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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12
11
10
VCC = 0.8 V
9
tpd – ns
8
7
6
5
VCC = 1.2 V
4
3
2
1
0
5
10
15
20
25
30
35
40
45
50
CL – Capactive Load – pF
55
60
65
70
75
Figure 6. tpd vs Capacitive Load at 1.2-V and 0.8-V VCC
3.2.2
DC Performance
The VOH vs IOH and VOL vs IOL characteristics are unique for the ULTTL output used in the AUC
Little Logic devices. Figures 7 and 8 show the typical VO vs IO performance of the AUC1G
devices. These curves can be used to determine an approximate output resistance at each
supply-voltage node. These figures are provided to demonstrate the dc drive performance of the
integrated circuit, but do not relate directly to the ac performance.
It is common to use the VO vs IO curves to generate Bergeron plots for analyzing the effective
signal integrity of the driver (see The Bergeron Method: A Graphical Method for Determining
Line Reflections in Transient Phenomena).[1] A simple VO vs IO plot is not accurate for this
purpose unless the device is biased in an ac mode before generating the curve. For a
low-to-high transition, the ac mode is defined as biasing the input so as to generate a high logic
level on the output, then sweeping the load current from high current (between 70 mA and 80
mA) to 0 mA and monitoring the corresponding output waveform. Sweeping the current from a
high to low represents the actual operation during ac operation because the current is highest at
the beginning of the transition and reduces as the output reaches the desired logic level. The
same concept applies for a high-to-low transition.
As previously mentioned, the AUC Little Logic devices are optimized to drive a 50-Ω to 65-Ω
transmission line, and provide 8-mA output current at 1.8-V VCC. The majority of application
loads targeted for the AUC Little Logic family can be represented as a transmission line rather
than a dc load. Therefore, 4 mA (~70 Ω) of dc drive current should be sufficient.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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2.4
2.2
2.0
1.8
1.6
VOH– V
1.4
TJ = 25°C
Nominal Process
VCC = 2.5 V
1.2
1.0
0.8
VCC = 1.8 V
0.6
VCC = 1.5 V
0.4
0.2
VCC = 1.2 V
0.0
0
20
40
60
80
100
IOH – mA
Figure 7. VOH vs IOH for AUC1G Devices
2.4
2.2
VCC = 1.2 V
2.0
VCC = 1.5 V
VCC = 1.8 V
1.8
1.6
VCC = 2.5 V
VOL – V
1.4
TJ = 25°C
Nominal Process
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
20
40
60
80
100
IOL – mA
Figure 8. VOL vs IOL for AUC1G Devices
5–18
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With each trace on the VOH vs IOH and VOL vs IOL plots, a small step function is present outside
the drive conditions of the data sheet. This step in the waveform should not cause any problems
in performance because it occurs at the point when the ACB and DCB are both turned off, and
affects only the ac-signal-integrity performance, for which it is designed (refer to the Novel
Output Structure section for more detailed operation).
3.3
Power Consumption
System designers, especially of portable applications, are becoming more concerned with the
power consumption of each integrated circuit. The power consumption of an integrated circuit
determines how much energy is consumed during operation (especially important for
battery-powered systems), and how much heat the integrated circuit dissipates (especially
important in personal-computer applications). The AUC Little Logic devices are designed for
optimum efficiency in power consumption.
Two components establish the level of power consumption in a CMOS circuit:
1. Static dissipation caused by continuous leakage current from the power supply while the
output is in a static (nonswitching) state
2. Dynamic dissipation caused by switching-transient current, which is a combination of the
short-circuit current (current pulse from VCC to GND during a transition) and load current
(current required to charge the capacitive load on the output)
Although system designers desire integrated circuits with minimal power consumption, lower
power often results in slower propagation delays. For CMOS designs, the propagation delay and
the power consumption of an integrated circuit are related. For a given gate topology, the
product of power consumption and propagation delay usually is a constant. This is referred to as
the power-delay product (PDP) and is a quality measure for analyzing the speed vs power
efficiency of a given device. The AUC Little Logic devices provide a low-power solution, without
sacrificing speed. Figure 9 shows the relative power efficiency of the AUC Little Logic devices
compared with other Little Logic devices. The data represented in Figure 9 were measured at
the supply-voltage node at which the different devices are optimized (see Table 4).
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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30
SN74LVC1G00
Cpd – pF
20
SN74AHCT1G00
SN74AUC1G00
10
SN74AHC1G00
0
10
20
30
40
Supply-Voltage Delay Product, VCC × tpd – V • ns
Figure 9. Relative Power Efficiency of Selected Little Logic Devices
Table 4. Power Consumption and Speed of Selected Little Logic Devices
at Their Optimized Supply-Voltage Nodes
Device
5–20
Typical Cpd
1.8 V
CL
30 pF
Maximum tpd
SN74AUC1G00
Optimized VCC
2.5 ns
15 pF
SN74LVC1G00
3.3 V
30 pF
4.7 ns
23 pF
SN74AHC1G00
5.0 V
50 pF
8.5 ns
9.5 pF
SN74AHCT1G00
5.0 V
50 pF
9.0 ns
10.5 pF
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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4
Design Issues and AUC Little Logic Solutions
4.1
Signal Integrity
As power-supply voltages decrease, signal integrity becomes a major issue. The noise margin
required for a device to be considered operable reduces proportionately with a reduction in
power-supply voltage. In addition to the requirement for better signal integrity and smaller noise
margins, system designers, especially for portable applications, need a solution that requires no
external termination (i.e., damping resistors, clamping diodes, etc.). Additional components use
valuable board space, and space also is at a premium in portable applications. The AUC Little
Logic devices provide the best possible solution for systems with these design constraints.
The ULTTL output provides great signal integrity without the need for external termination when
driving traces of moderate length (less than 15 cm). Figure 10 shows a typical application
environment. The driver represents an AUC Little Logic device and the receiver represents a
CMOS device whose interface is compatible with the AUC logic levels. The transmission line
corresponds to a PCB trace of 50 Ω to 65 Ω for a portable system application, consisting of short
trace length (less than 15 cm). During the second phase of the three distinctive transitional
phases of the ULTTL output (see Section 2.1), the AUC output impedance changes to a level
close to that of the transmission line (see Figure 11), thus minimizing overshoots and
undershoots.
Output Impedance
Ω
Transmission Line
Receiver
Driver
Output Voltage
Receiver Voltage
Figure 10. Transmission-Line Test Points for Simulations
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100.0
2.5
Phase 1
Phase 2
Phase 3
90.0
2.0
Output Impedance – Ω
70.0
60.0
50.0
40.0
30.0
Output Voltage and Receiver Voltage – V
80.0
RTOTAL
212.84 ns; 65.03 Ω
1.5
YOUT
Zo = 65 Ω
Lg = 10 cm
Ld = 5 pF
Flight Time = 0.64 ns
1.0
0.5
20.0
213.41 ns; 25.04 Ω
211.56 ns; 24.15 Ω
Receiver
10.0
0.0
0.0
212
211.5
212.5
213
213.5
Time – ns
Figure 11. Output Impedance, Output Voltage, and Receiver Voltage
of AUC Single-Gate Transmission-Line Simulation
The simulation results in Figure 12 show typical operation into a 10-cm PCB trace, with a line
impedance of 65 Ω and a 5-pF capacitive load at the receiver end. The simulation was
completed at 10 MHz, with an input edge rate of 1 ns/V.
2.6
2.4
VCC = 1.95 V
TJ = –40°C to 85°C
2.2
VCC = 1.8 V
TJ = 25°C
2.0
1.8
1.6
VO – V
1.4
VCC = 1.65 V
TJ = –40°C to 85°C
1.2
Zo = 65 Ω
Lg = 10 cm
Ld = 5 pF
Nominal Process
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
100
110
120
130
140
150
160
170
180
Time – ns
Figure 12. Simulation of 65-Ω Transmission Line Across Supply Voltage and Temperature
5–22
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
Although the AUC Little Logic devices are optimized for 50-Ω to 65-Ω loads, some applications
might require operation into 30-Ω to 75-Ω loads. The unique characteristic of the ULTTL output
provides adequate performance into these wider-range loads (see Figures 13 and 14).
2.2
Zo = 70 Ω
2.0
1.8
1.6
1.4
Zo = 30 Ω
Zo = 30 Ω to 70 Ω
Lg = 10 cm
Ld = 5 pF
TJ = 25°C
Nominal Process
VO – V
1.2
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
110
111
112
113
114
115
116
117
118
119
120
Time – ns
Figure 13. Simulation of Low-to-High Transition into 30-Ω to 70-Ω Transmission Line
2.0
1.8
1.6
1.4
1.2
VO – V
1.0
Zo = 30 Ω to 70 Ω
Lg = 10 cm
Ld = 5 pF
TJ = 25°C
Nominal Process
0.8
0.6
Zo = 30 Ω
0.4
0.2
0.0
–0.2
Zo = 70 Ω
–04
260
261
262
263
264
265
266
267
268
Time – ns
Figure 14. Simulation of High-to-Low Transition into 30-Ω to 70-Ω Transmission Line
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
5–23
SCEA027A
4.2
Mixed-Voltage-Mode Data Communication
In designing electronic systems, proper interfaces between buses with incompatible logic levels
must be provided. Voltage-level translation is necessary to allow the interconnection with
flexibility to provide a future migration path to lower-voltage input/output (I/O) levels.
Voltage translation between buses with incompatible logic levels can be accomplished using
AUC Little Logic devices. With a unidirectional AUC driver powered with 1.8-V VCC, data
communication from 2.5-V or 3.3-V devices can occur (see Figure 15). In this case, the inputs of
the AUC devices are tolerant of the higher voltages and accept the higher switching levels.
Likewise, the outputs of the AUC driver are valid 1.8-V signal levels.
VCC = 1.8 V
3.3 V
VCC
2.4
VOH
2.0
VIH
1.5
2.5 V
VCC
2.3
VOH
1.7
VIH
1.2
Vt
0.7
VIL
0.2
VOL
GND
Vt
0.8
VIL
0.4
VOL
0
GND
0
2.5 V or 3.3 V
AUC
Little
Logic
Device
1.8 V
1.8 V
1.35
1.17
0.9
0.63
0.45
0
GND
Figure 15. Device at 1.8-V VCC, With 2.5-V or 3.3-V Inputs, Showing Switching Levels
Generally, a unidirectional AUC driver powered with 0.8-V, 1.2-V, 1.5-V, or 1.8-V VCC can be
used to down-translate from a higher voltage node to the voltage node of the supply voltage.
Similarly, up-translation and down-translation can be achieved by using the SN74AUC1G06 or
the SN74AUC1G07. The SN74AUC1G07 is a noninverting buffer with an open-drain output, and
the SN74AUC1G06 is the inverting buffer (the SN74AUC1G07 plus an extra stage of inversion).
These buffers are designed to operate in the 0.8-V to 2.7-V VCC range; however, inputs and
outputs can interface with 3.3-V signals.
This section focuses on the application of the SN74AUC1G07 in voltage-level translation.
However, the SN74AUC1G06 can be used in such applications as well, only with an extra
inversion.
5–24
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
The open-drain feature of the SN74AUC1G07 is useful in voltage translation. The fact that the
input and output structure of this device can accept voltages from 0.8-V to 3.3-V enables the
device to support voltage translation from a lower voltage to a higher voltage, or vice versa.
Without the p-channel pullup on the output structure of the SN74AUC1G07, the entire output
voltage drops across the n-channel transistor (see Figure 16). With the help of a pullup resistor
that is connected to the designer’s choice of voltage (not exceeding 3.6 V), voltage translation is
achieved.
VPULLUP
VCC
RPULLUP
VCC
SN74AUC1G07
Device A
OUT
Device B
IN
GND
Figure 16. Circuit for Voltage Translation Using the SN74AUC1G07
The voltage translation provided by the SN74AUC1G07 can be used between wide CMOS
voltage nodes. Table 5 illustrates parameters necessary for some example voltage translations
between devices A and B.
Table 5. Requirements for Voltage Translation Between Devices A and B
3.3-V CMOS
Device A
1.2-V LVCMOS
Device B
VCC
0.8 V to 2.5 V
VPULLUP
1.2 V
Function
3.3-V CMOS
1.8-V LVCMOS
0.8 V to 2.5 V
1.8 V
Down translation
2.5-V LVCMOS
1.8-V LVCMOS
0.8 V to 2.5 V
1.8 V
Down translation
3.3-V CMOS
3.3-V CMOS
0.8 V to 2.5 V
3.3 V
Buffer
1.8-V LVCMOS
1.8-V LVCMOS
0.8 V to 1.8 V
1.8 V
Buffer
1.2-V LVCMOS
1.2-V LVCMOS
0.8 V to 1.2 V
1.2 V
Buffer
1.8-V LVCMOS
3.3-V CMOS
0.8 V to 1.8 V
3.3 V
Up translation
1.8-V LVCMOS
2.5-V LVCMOS
0.8 V to 1.8 V
2.5 V
Up translation
1.2-V LVCMOS
3.3-V CMOS
0.8 V to 1.2 V
3.3 V
Up translation
Down translation
In Table 5, note that the SN74AUC1G07 also can be used as a buffer in some applications. In
such configurations, the device can be used as an active-high wired-AND or for active-low
wired-OR functions. This is achieved by tying outputs of two or more open-drain devices.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
5–25
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4.3
Partial Power Down
Electronic systems usually have power-saving or suspended modes of operation, whereby some
circuitry in the system is powered down to reduce power consumption. During such modes of
operation, the supply voltage of the circuitry is turned off. This mode of operation is known as
partial-power-down mode, as part of the system is powered down. The AUC Little Logic devices
support partial-power-down applications and it is important that the designer understands the
data-sheet-specified parameters related to this feature.
To partially power down a device, no direct path from the input to VCC or from the output to VCC
can exist. Consequently, when the device is powered down (VCC = 0 V), independent of the logic
level at the I/O terminal, no current can flow from the I/O terminal to the power-supply pin, which
is at 0 V. In the partial-powered-down mode, therefore, other devices interfacing with the
powered-down device may be powered up with valid logic levels at the I/O terminals.
With the AUC Little Logic, there is no direct path from the I/O terminal to VCC. Consequently,
these devices support partial-power-down modes of operation. This feature is specified on the
data sheet with the Ioff parameter. The Ioff parameter is the maximum leakage current into (or out
of) the input (or output) transistors when forcing the input (or output) to 2.7 V and VCC = 0 V.
With the AUC Little Logic, Ioff is specified at ±10 µA. This is a very small current and represents
leakage current at the I/O terminal.
4.4
Low Power Consumption
The migration to lower voltage nodes is becoming increasingly important in digital electronics,
especially with portable and consumer electronics, because of the benefits of reduced power
consumption. If power consumption is reduced, these electronics can use smaller batteries, thus
reducing form factors, while getting the maximum life of the power supply between charges.
The AUC Little Logic devices enable low-power, high-performance designs. The power
consumption reduction decreases heat dissipation in compact designs. This reduced heat
dissipation simplifies heat removal and decreases the amount of package space needed, thus
saving valuable board space in compact designs.
Figure 17 shows plots of supply current vs frequency for different AUC Little Logic devices. For
each of the devices, the test was done with only one input switching from 0 V to 1.8 V at 1 ns/V.
Note that the supply current increases with increased input transition. A 1.8-V power supply was
used, and the tests were done at 25°C.
5–26
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
7
6
AUC1G14
AUC1G00
AUC1G04
ICC – mA
5
4
3
2
1
AUC1G06
0
1
5
10
15
20
30
40
50
60
70
80
90
100 125
150 175
Frequency – MHz
Figure 17. ICC vs Frequency for Different AUC Little Logic Devices
Generally, the AUC Little Logic devices consume less power than the corresponding Little Logic
devices of other families. Figure 18 provides a comparison of the supply current vs frequency for
the SN74LVC1G06 and the SN74AUC1G06. Both devices were tested under the same
conditions as those used to obtain the results in Figure 17.
0.60
LVC1G06
0.50
ICC – mA
0.40
0.30
AUC1G06
0.20
0.10
0.00
1
5
10
15
20
30
40
50
60
70
80
Frequency – MHz
Figure 18. ICC vs Frequency for SN74AUC1G06 and SN74LVC1G06 Devices
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
5–27
SCEA027A
5
Package Information
The devices discussed in this application report are available in a variety of packages, including
SOT-23 (DBV), SC-70 (DCK), tin-lead (SnPb) NanoStart (YEA), and lead-free NanoFreet
(YZA). TI’s Little Logic Data Book, literature number SCED010, lists devices and packages in
which they are available. The mechanical data information for these packages is provided in
Appendix B of this application report.
The mechanical data for the YEA and YZA packages are the same. The only difference between
the two packages is that the YEA package is leaded, while the YZA package is lead-free. The
NanoStar and NanoFree packages comply with JEDEC MO-211.
5–28
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
6
Features and Benefits
Table 6 summarizes the features and benefits of AUC Little Logic devices.
Table 6. Features and Benefits of AUC Little Logic Devices
FEATURES
BENEFITS
Low power consumption
Use in portable electronics and battery-operated systems
Supports Ioff at inputs
Use in applications that require partial power-down modes
3.6-V I/O tolerant
Use in level-translation applications. Eases migration to lower-voltage nodes. Enhances system
safety.
Sub-1-V operable
Flexibility for future migration. Operable at lower-voltage nodes means less power consumption.
Small low-profile packages
Saves board space. Simplify large PCB routing. Use as quick fix for design errors.
Cost effective
Inexpensive compared to redesign. Used as quick fix for design errors. Reduces time-to-market
and maximized design investment in all types of electronic systems.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
5–29
SCEA027A
7
Conclusion
The AUC Little Logic devices provide simple cost-effective solutions for portable electronics and
battery-operated systems and facilitates quick fixes in system design errors. The devices are
optimized at 1.8 V and are compatible with 2.5-V, 1.5-V, 1.2-V, and 0.8-V systems. The AUC
family features TI’s ULTTL output circuitry, 3.6-V I/O tolerance, low power consumption
capability, and partial power-down support. Features, electrical characteristics, and applications
of the AUC Little Logic devices are presented in this application report.
8
5–30
Frequently Asked Questions (FAQs)
Question 1:
What is AUC?
Answer:
The advanced ultra-low-voltage CMOS (AUC) is the new logic family that is
optimized at 1.8 V, has an operating voltage range from 0.8 V to 2.5 V, and is
tolerant of 3.3-V input and output voltages.
Question 2:
What is ULTTL?
Answer:
The ultra-low-voltage transistor-transistor logic (ULTTL) is a new interface driver
designed for high-speed with low EMI noise, low power consumption, and optimal
signal integrity.
Question 3:
How do I get copies of the AUC family data sheets and samples?
Answer:
The AUC family data sheets can be obtained by accessing http://www.ti.com.
Samples of the AUC devices can be obtained by contacting your local TI sales
representative.
Question 4:
How do I get copies of AUC family SPICE and IBIS models?
Answer:
The SPICE models for AUC devices can be obtained by contacting your local TI
sales representative. The IBIS model can be obtained by accessing
http://www.ti.com.
Question 5:
What are the advantages of migrating to the AUC family?
Answer:
The advantages of migrating to the AUC family include:
•
Lowered power consumption enables use in portable electronics and
battery-operated systems.
•
Partial-power-down mode is supported.
•
Level-translation is feasible and migration to lower-voltage nodes is easy.
•
Future migration to sub-1-V applications is possible.
•
Board space is saved and large-PCB routing is simplified.
•
Capability for fixing design errors is flexible and redesign cost is lower.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
Question 6:
What should I do if it appears that the device is producing a noisy signal?
Answer:
The most common reason an AUC device may appear to be producing a noisy
signal is that the outputs have not been terminated properly. To reduce or
eliminate reflections that are inherent with long trace lengths and transmission
lines, one of five techniques must be used to match the impedance of the
transmission line and thereby properly terminate the output. These five
techniques are: single-resistor termination, parallel split-resistor termination,
series-resistor termination, resistor-and-capacitor termination, and diode
termination. For a detailed explanation of the techniques and the advantages and
disadvantages of each method, refer to the Advanced Schottky Load
Management Application Report.[3]
Question 7:
What is the maximum voltage the input pin of an AUC Little Logic can sustain
when the device is powered down or when the device is powered up?
Answer:
The AUC Little Logic devices are 3.6-V tolerant at the inputs. Therefore, within
the supply-voltage operational range (0.8 V = VCC = 2.7 V), the input voltage can
be as high as 3.6 V. Further, the AUC Little Logic devices have the Ioff feature.
Therefore, if VCC = 0 V, the inputs can tolerate a 3.6-V signal.
Question 8:
What is the maximum voltage the output pin of an AUC Little Logic device can
sustain when the device is powered down, and how can this information be
inferred from the data sheet?
Answer:
With older family devices, there is a parasitic diode connected from the output to
VCC. With those devices, if VCC = 0 V and the output is driven about 1 V above
VCC, the diode is forward biased and conducts current from the output pin to the
VCC pin. Under this condition, the device can be damaged. Therefore, the data
sheet of a device with a power-clamp diode has a positive limit on the output
clamp current (IOK).
The AUC Little Logic, however, have no parasitic diode from the output to VCC.
The data sheets specify an absolute maximum rating IOK of –50 mA, with no
positive limit for this specification. Therefore, the output can be driven above
VCC, but caution should be taken to ensure that the IOK limit is not exceeded
when the output is driven below GND.
The above explanation applies only for the absolute maximum rating of the
device. Under the recommended operating conditions, the AUC Little Logic
devices with outputs incapable of being placed in the high-impedance state are
recommended to be between 0 V and VCC.
Question 9:
What is the maximum operating frequency of the AUC Little Logic devices?
Answer:
The maximum operating frequency of a device depends upon the load that the
AUC device is driving. Using the specified data sheet load, the AUC Little Logic
devices have been tested in the laboratory to operate at frequencies greater than
175 MHz.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
5–31
SCEA027A
9
References
1. The Bergeron Method: A Graphical Method for Determining Line Reflections in Transient
Phenomena, application report, literature number SDYA014.
2. Little Logic Data Book (SCED010), November 2001.
3. Advanced Schottky Load Management, application report, literature number SDYA016.
10
Glossary
ac
Alternating current
ACB
ac branch
AUC
Advanced ultra-low-voltage CMOS
CMOS
Complementary metal-oxide silicon; a device technology that has balanced drive
outputs and low power consumption
dc
Direct current
DCB
dc branch
EMI
Electromagnetic interference
IBIS
I/O buffer information specification
Ioff
The maximum leakage current into/out of the input/output transistors when forcing
the input/output to 2.7 V and VCC = 0 V
IOH
High-level output current. The current out of an output with input conditions applied
that, according to the product specification, establishes a high level at the output.
IOK
Output clamp current. The absolute maximum current that can be sourced from an
output pin when the voltage is taken below 0 V
IOL
Low-level output current. The current into an output with input conditions applied that,
according to the product specification, establishes a low level at the output.
JEDEC
Joint Electron Device Engineering Council
LOP
Lower-output transistor
LVCMOS Low-voltage complementary metal-oxide silicon
5–32
PCB
Printed circuit board
PDP
Power-delay product
ron
On-channel resistance
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
SPICE
Simulation program with integrated circuit emphasis
TI
Texas Instruments
TLB
Transmission-line branch
tpd
Propagation delay time. The time between the specified reference points on the input
and output voltage waveforms with the output changing from one defined level (high
or low) to the other defined level (tpd = tPHL or tPLH).
tPHL
Propagation delay time, high-to-low level output. The time between the specified
reference points on the input and output voltage waveforms, with the output changing
from the defined high level to the defined low level.
tPLH
Propagation delay time, low-to-high level output. The time between the specified
reference points on the input and output voltage waveforms, with the output changing
from the defined low level to the defined high level
TTL
Transistor-transistor logic
ULTTL
Ultra-low-voltage transistor-transistor logic
UOP
Upper-output transistor
VOH
High-level output voltage. The voltage at an output terminal with input conditions
applied such that, according to product specification, it establishes a high level at the
output.
VOL
Low-level output voltage. The voltage at an output terminal with input conditions
applied such that, according to product specification, it establishes a low level at the
output.
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
5–33
SCEA027A
Appendix A. Parameter Measurement Information
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
CL
RL
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VCC/2
VCC/2
VOL
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES:
VCC/2
0V
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VOH
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
I. CL includes probe and jig capacitance.
J. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
K. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
L. The outputs are measured one at a time with one transition per measurement.
M. tPLZ and tPHZ are the same as tdis.
N. tPZL and tPZH are the same as ten.
O. tPLH and tPHL are the same as tpd.
P. All parameters and waveforms are not applicable to all devices.
Figure 19. AUC Little Logic (with ULTTL Outputs) Load Circuit and Voltage Waveforms
5–34
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
PARAMETER MEASUREMENT INFORMATION
(OPEN DRAIN)
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tPZL
(see Note F)
tPLZ
(see Note G)
tPHZ/tPZH
2 × VCC
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
CL
15 pF
15 pF
15 pF
30 pF
30 pF
2 × VCC
2 × VCC
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
RL
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLZ
VCC
VCC/2
VOL + V∆
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at 2 × VCC
(see Note B)
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: Q. CL includes probe and jig capacitance.
R. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
S. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
T. The outputs are measured one at a time with one transition per measurement.
U. For open-drain outputs, tPLZ and tPZL are the same as tpd.
V. tPZL is measured at VCC/2.
W. tPLZ is measured at VOL + V∆.
X. All parameters and waveforms are not applicable to all devices.
Figure 20. AUC Little Logic (with Open-Drain Outputs) Load Circuit and Voltage Waveforms
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
5–35
SCEA027A
Appendix B. Mechanical Data
DBV (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,50
0,30
0,95
5
0,20 M
4
1,70
1,50
1
0,15 NOM
3,00
2,60
3
Gage Plane
3,00
2,80
0,25
0°–8°
0,55
0,35
Seating Plane
1,45
0,95
0,05 MIN
0,10
4073253-4/G 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-178
Figure 21. Plastic Small Outline (DBV)
5–36
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
SCEA027A
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
5
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-2/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
Figure 22. Plastic Small Outline (DCK)
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
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SCEA027A
YEA (R-XBGA-N5)
A
DIE-SIZE BALL GRID ARRAY
0,95
0,85
0,50
B
0.25
C
1.00
1,45
1,35
B
0.50
A
1
2
Pin A1 Index Area
5X
0.19
0.15
0.05 M C A B
0.05 M C
0.35 MAX
0.05 C
0,50 MAX
Seating Plane
0.15
0.10
C
4203167-2/B 11/2001
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
NanoStart package configuration.
Package complies to JEDEC MO-211.
Figure 23. Die-Size Ball Grid Array (YEA or YZA)
NanoStar is a trademark of Texas Instruments.
5–38
Application of the Texas Instruments AUC Sub-1-V Little Logic Devices
General Information
AUC Single Gates
AUC Widebus
AUC Widebus+
Application Reports
Mechanical Data
6–1
Contents
Page
Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DBV (R-PDSO-G5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK (R-PDSO-G5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGG (R-PDSO-G**) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV (R-PDSO-G**) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GKE (R-PBGA-N96) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL (R-PBGA-N56) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEA (R-XBGA-N5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YZA (R-XBGA-N5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data
6–2
6–3
6–7
6–7
6–8
6–9
6–10
6–11
6–12
6–13
6–14
ORDERING INSTRUCTIONS
Electrical characteristics presented in this data book, unless otherwise noted, apply for the circuit type(s) listed in the
page heading regardless of package. The availability of a circuit function in a particular package is denoted by an
alphabetical reference above the pin-connection diagram(s). These alphabetical references refer to mechanical
outline drawings shown in this section.
Factory orders for circuits described in this data book should include a four-part type number as explained in the
following example.
EXAMPLE:
SN
AUC16244
DGV
R
Prefix
SN = Standard prefix
SNJ = Compliant to MIL-PRF-38535 (QML)
Unique Circuit Description
MUST CONTAIN SEVEN TO NINE CHARACTERS
Examples: AUC1G17
AUCH16374
Package
MUST CONTAIN ONE TO THREE LETTERS
DBV, DCK
= plastic small-outline transistor
DGG
= plastic thin shrink small-outline package
DGV
= plastic thin very small-outline package
GQL, YEA, YZA = ball grid array
Tape and Reel Packaging
Valid for surface-mount packages only. All orders for tape and reel must be for whole reels.
MUST CONTAIN ONE LETTER
R = Standard tape and reel (required for DBV, DCK, DGG, DGV, GQL, YEA, and YZA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6–3
ORDERING INSTRUCTIONS
Table 1. Normal Dimensions of Packing Materials
CARRIER-TAPE
WIDTH
(mm)
COVER-TAPE
WIDTH
(mm)
REEL
WIDTH
(mm)
REEL
DIAMETER
(mm)
8
5.4
9.0
178
12
9.2
12.4
330
16
13.3
16.4
330
24
21.0
24.4
330
32
25.5
32.4
330
44
37.5
44.4
330
56
49.5
56.4
330
All material meets or exceeds industry guidelines for ESD protection.
Dimensions are selected based on package size and design configurations. All dimensions are established to be
within the recommendations of the Electronics Industry Association Standard EIA-481-1,2,3.
Common dimensions of particular interest to the end user are carrier-tape width, pocket pitch, and quantity per reel
(see Figure 1 and Table 2).
1
Direction
of Feed
Width
Pocket/Component Pitch
(Center to Center of Pocket)
Trailer
(No Components)
400
340
Components
Leader
(No Components)
As Required
for Component Count
Figure 1. Typical Carrier-Tape Design
6–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
560
500
ORDERING INSTRUCTIONS
Table 2. Selected Tape-and-Reel Specifications
NO. OF
PINS
CARRIER-TAPE
WIDTH
(mm)
POCKET
PITCH
(mm)
QTY/REEL
YEA
5
8.00
4.00
3000
YZA
5
8.00
4.00
3000
GKE
96
24.00
8.00
1000
DBV
5
8.00
4.00
3000
DCK
5
8.00
4.00
3000
48
24.00
12.00
2000
56
24.00
12.00
2000
64
24.00
12.00
2000
14
16.00
8.00
2000
16
16.00
8.00
2000
20
16.00
8.00
2000
24
16.00
8.00
2000
48
16.00
8.00
2000
56
24.00
8.00
2000
56
16.00
8.00
1000
PACKAGE
DSBGA
LFBGA
SOT
TSSOP
TVSOP
VFBGA
DGG
DGV
GQL
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6–5
MECHANICAL DATA
DBV (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,95
5X
5
0,50
0,20 M
0,30
4
1,70
1,50
1
0,15 NOM
3,00
2,60
3
Gage Plane
3,00
2,80
0,25
0°–8°
0,55
0,35
Seating Plane
1,45
0,95
0,05 MIN
0,10
4073253-4/G 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-178
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6–7
MECHANICAL DATA
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
5
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-2/D 01/02
NOTES: A.
B.
C.
D.
6–8
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6–9
MECHANICAL DATA
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
6–10
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
GKE (R-PBGA-N96)
PLASTIC BALL GRID ARRAY
5,60
5,40
4,00 TYP
0,80
0,40
12,00
0,40
13,60
13,40
0,80
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6
Bottom View
A1 Corner
0,95
0,85
0,10
Seating Plane
1,40 MAX
96×
0,45
0,35
0,55
0,45
0,08 M
4188953/D 07/2002
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar BGA configuration
Falls within JEDEC MO-205 variation CC.
This package is tin-lead (SnPb). Refer to the 96 ZKE package (drawing 4204493) for lead-free.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6–11
MECHANICAL DATA
GQL (R-PBGA-N56)
PLASTIC BALL GRID ARRAY
4,60
4,40
3,25
0,65
0,325
K
J
3X Via Hole
Without
Ball
0,65
G
F
5,85
E
Missing Via
Hole Indicates
Pin A1
Quadrant
D
0,325
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
7,10
6,90
H
C
B
A
1
A1 Corner
2
3
4
5
6
Bottom View
1,00 MAX
0,08
Seating Plane
0,45
56× ∅
0,35
0,25
0,15
0,05 M
4200583/D 06/2002
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Junior BGA configuration
Falls within JEDEC MO-225 variation BA.
This package is tin-lead (SnPb). Refer to the 56 ZQL package ( drawing 4204437) for lead-free.
MicroStar Junior is a trademark of Texas Instruments.
6–12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
YEA (R–XBGA–N5)
DIE–SIZE BALL GRID ARRAY
0,50
A
0,95
0,85
B
0,25
C
1,45
1,35
1,00
B
ÉÉ
ÉÉ
0,50
A
1
2
PIN A1 INDEX AREA
5X
0,19
0,15
0,05 M C A B
0,05 M C
0,35 MAX
0,05 C
0,50 MAX
SEATING PLANE
0,15
0,10
C
4203167–2/C 04/2002
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
NanoStar package configuration.
Package complies to JEDEC MO–211 variation EA.
This package is tin–lead (SnPb). Refer to the 5 YZA package (drawing 4204151) for lead–free.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6–13
MECHANICAL DATA
YZA (R-XBGA-N5)
DIE-SIZE BALL GRID ARRAY
0,50
A
0,95
0,85
B
0,25
C
1,00
1,45
1,35
B
0,50
A
1
2
Pin A1 Index Area
5X
0,19
0,15
0,05 M C A B
0,05 M C
0,35 MAX
0,05 C
0,50 MAX
Seating Plane
0,15
0,10
C
4204151-2/B 03/2002
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
NanoFree package configuration.
Package complies to JEDEC MO-211 variation EA.
This package is lead-free. Refer to the 5 YEA package (drawing 4203167) for tin-lead (SnPb).
NanoFree is a trademark of Texas Instruments.
6–14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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