Texas Instruments | AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) | User Guides | Texas Instruments AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) User guides

Texas Instruments AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) User guides
AVC
Advanced VeryĆLowĆVoltage CMOS Logic
Data Book
1999
Product News
new products for prototype design
PRODUCTS OF
THE YEAR
AWARD
March 2000
Logic Products
General Information
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Widebus+
Application Reports
Mechanical Data
AVC
Advanced Very-Low-Voltage
CMOS Logic
Data Book
Printed on Recycled Paper
IMPORTANT NOTICE
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or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
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In order to minimize risks associated with the customer’s applications, adequate design and
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TI assumes no liability for applications assistance or customer product design. TI does not
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not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated
INTRODUCTION
The new Texas Instruments (TI) AVC (Advanced Very-Low-Voltage CMOS) logic family
provides designers the tools to create tomorrow’s advanced high-speed systems with
propagation delays of less than 2 ns. Although optimized for 2.5-V systems, AVC logic
supports operating voltages between 1.2 V and 3.6 V. The AVC family features TI’s new
Dynamic Output Control (DOC) circuitry, which dynamically lowers circuit output impedance
during signal transition for fast rise and fall times, then raises the impedance after signal
transition to reduce ringing.
Trends in digital electronics design emphasize lower power consumption, lower supply
voltages, faster operating speeds, smaller timing budgets, and heavier loads. Many designs
are making the transition from 3.3 V to 2.5 V, with bus speeds increasing beyond 100 MHz.
Signal integrity need not be compromised to meet these design requirements. The TI AVC
family is designed to meet the needs of these high-speed, low-voltage systems, including
next-generation high-performance workstations, PCs, networking servers, and
telecommunications switching equipment.
Key features are:
•
•
•
•
•
•
•
Sub-2-ns maximum tpd at 2.5 V for AVC16245
Designed for next-generation, high-performance PCs, workstations, and servers
DOC circuitry enhances high-speed, low-noise operation.
Supports mixed-voltage systems
Optimized for 2.5 V; operable from 1.2 V to 3.6 V
Bus-hold option eliminates need for external resistors on unused input pins.
Ioff supports partial power down.
For more information on these or other TI products, please consult the TI Worldwide Technical
Support list in the back of this data book, or visit the TI logic web site at
http://www.ti.com/sc/logic.
DOC and TI are trademarks of Texas Instruments Incorporated.
v
PRODUCT STAGE STATEMENTS
Product stage statements are used on Texas Instruments data sheets to indicate the
development stage(s) of the product(s) specified in the data sheets.
If all products specified in a data sheet are at the same development stage, the appropriate
statement from the following list is placed in the lower left corner of the first page of the
data sheet.
PRODUCTION DATA information is current as of publication date. Products conform
to specifications per the terms of Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction
phase of development. Characteristic data and other specifications are subject to
change without notice.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these products
without notice.
If not all products specified in a data sheet are at the PRODUCTION DATA stage, then the first
statement below is placed in the lower left corner of the first page of the data sheet.
Subsequent pages of the data sheet containing PRODUCT PREVIEW information or
ADVANCE INFORMATION are then marked in the lower left-hand corner with the appropriate
statement given below:
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA
information current as of publication date. Products conform to specifications per the
terms of Texas Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction
phase of development. Characteristic data and other specifications are subject to
change without notice.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these products
without notice.
vi
General Information
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Mechanical Data
1–1
Contents
Page
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
General Information
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Explanation of Function Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
D Flip-Flop and Latch Signal Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
Device Names and Package Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
1–2
ALPHANUMERIC INDEX
DEVICE
SN74AVC16244
SN74AVC16245
SN74AVC16269
SN74AVC16334
SN74AVC16373
SN74AVC16374
SN74AVC16501
SN74AVC16601
SN74AVC16646
SN74AVC16721
SN74AVC16722
SN74AVC16820
PAGE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–71
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–93
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–115
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–127
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–139
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–153
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–163
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–173
POST OFFICE BOX 655303
DEVICE
PAGE
SN74AVC16821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–183
SN74AVC16827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–195
SN74AVC16831 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–205
SN74AVC16834 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–217
SN74AVC16835 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–229
SN74AVC16836 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–241
SN74AVC32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
SN74AVC32501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
SN74AVCH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
SN74AVCH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
SN74AVCH16373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–81
SN74AVCH16374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–103
• DALLAS, TEXAS 75265
1–3
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC Council
of the Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission
(IEC) for international use.
operating conditions and characteristics (in sequence by letter symbols)
Ci
Input capacitance
The capacitance of an input terminal of the device
Cio
Input/output capacitance
The capacitance of an input/output (I/O) terminal of the device with the input conditions applied that,
according to the product specification, establishes the high-impedance state at the output
Co
Output capacitance
The capacitance of an output terminal of the device with the input conditions applied that, according
to the product specification, establishes the high-impedance state at the output
Cpd
Power dissipation capacitance
Used to determine the no-load dynamic power dissipation per logic function (see individual circuit
pages): PD = Cpd VCC2 f + ICC VCC
fmax
Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required sequence
while maintaining stable transitions of logic level at the output with input conditions established that
should cause changes of output logic level in accordance with the specification
IBHH
Bus-hold high sustaining current
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should
be measured after raising VIN to VCC and then lowering it to VIH min.
IBHL
Bus-hold low sustaining current
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be
measured after lowering VIN to GND and then raising it to VIL max.
IBHHO
Bus-hold high overdrive current
An external driver must sink at least IBHHO to switch this node from high to low.
IBHLO
Bus-hold low overdrive current
An external driver must source at least IBHLO to switch this node from low to high.
ICC
Supply current
The current into* the VCC supply terminal of an integrated circuit
∆ICC
Supply current change
The increase in supply current for each input that is at one of the specified TTL voltage levels rather
than 0 V or VCC
ICEX
Output high leakage current
The maximum leakage current into* an output that is in a high state and VO = VCC
II(hold)
Input hold current
The input current that holds the input at the previous state when the driving device goes to the
high-impedance state
*Current out of a terminal is given as a negative value.
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GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
IIH
High-level input current
The current into* an input when a high-level voltage is applied to that input
IIL
Low-level input current
The current into* an input when a low-level voltage is applied to that input
Ioff
Input/output power-off leakage current
The maximum leakage current into* an input or output terminal of the device with the specified voltage
applied to the terminal and VCC = 0 V
IOH
High-level output current
The current into* an output with input conditions applied that, according to the product specification,
establishes a high level at the output
IOHS
Static high-level output current
The static and testable current into* a Dynamic Output Control (DOC) output with input conditions
applied that, according to the product specifications, establishes a static high level at the output. The
dynamic drive current is not specified for devices with DOC outputs because of its transient nature;
however, it is similar to the dynamic drive current that is available from a high-drive (nondamping
resistor) standard-output device.
IOL
Low-level output current
The current into* an output with input conditions applied that, according to the product specification,
establishes a low level at the output
IOLS
Static low-level output current
The static and testable current into* a Dynamic Output Control (DOC) output with input conditions
applied that, according to the product specifications, establishes a static low level at the output. The
dynamic drive current is not specified for devices with DOC outputs because of its transient nature;
however, it is similar to the dynamic drive current that is available from a high-drive (nondamping
resistor) standard-output device.
IOZ
Off-state (high-impedance state) output current (of a 3-state output)
The current flowing into* an output with the input conditions applied that, according to the product
specification, establishes the high-impedance state at the output
IOZPD
Power-down off-state (high-impedance state) output current (of a 3-state output)
The current flowing into* an output that is switched to or held in the high-impedance state as the device
is being powered down to VCC = 0 V
IOZPU
Power-up off-state (high-impedance state) output current (of a 3-state output)
The current flowing into* an output that is switched to or held in the high-impedance state as the device
is being powered up from VCC = 0 V
jitter
Jitter
Dispersion of a time parameter of the pulse waveforms in a pulse train with respect to a reference time,
interval, or duration. Unless otherwise specified by a mathematical adjective, peak-to-peak jitter is
assumed.
jitter(RMS) RMS jitter
The root mean square jitter, one-sixth of the maximum peak-to-peak jitter
*Current out of a terminal is given as a negative value.
DOC is a trademark of Texas Instruments Incorporated.
1–6
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GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
SR
Slew rate
The average rate of change (i.e., V/ns) for a waveform that is changing from one defined logic level to
another defined logic level
ta
Access time
The time interval between the application of a specified input pulse and the availability of valid signals
at an output
tc
Clock cycle time
Clock cycle time is 1 / fmax
tdis
Disable time (of a 3-state or open-collector output)
The propagation time between the specified reference points on the input and output voltage
waveforms with the output changing from either of the defined active levels (high or low) to the
high-impedance (off) state
NOTE: For 3-state outputs, tdis = tPHZ or tPLZ. Open-collector outputs change only if they are low at
the time of disabling, so tdis = tPLH.
ten
Enable time (of a 3-state or open-collector output)
The propagation time between the specified reference points on the input and output voltage
waveforms with the output changing from the high-impedance (off) state to either of the defined active
levels (high or low)
NOTE: In the case of memories, this is the access time from an enable input (e.g., OE). For 3-state
outputs, ten = tPZH or tPZL. Open-collector outputs change only if they are responding to data
that would cause the output to go low, so ten = tPHL.
tf
Fall time
The time interval between two reference points (90% and 10%, unless otherwise specified) on a
waveform that is changing from the defined high level to the defined low level
th
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal
NOTES: 1. The hold time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which correct operation of the digital circuit is to be expected.
2. The hold time may have a negative value, in which case, the minimum limit defines the
longest interval (between the release of the signal and the active transition) for which correct
operation of the digital circuit is to be expected.
tpd
Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with the
output changing from one defined level (high or low) to the other defined level (tpd = tPHL or tPLH)
tPHL
Propagation delay time, high-to-low level output
The time between the specified reference points on the input and output voltage waveforms with the
output changing from the defined high level to the defined low level
tPHZ
Disable time (of a 3-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms
with the 3-state output changing from the defined high level to the high-impedance (off) state
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GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
tPLH
Propagation delay time, low-to-high level output
The time between the specified reference points on the input and output voltage waveforms with the
output changing from the defined low level to the defined high level
tPLZ
Disable time (of a 3-state output) from low level
The time interval between the specified reference points on the input and the output voltage waveforms
with the 3-state output changing from the defined low level to the high-impedance (off) state
tPZH
Enable time (of a 3-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms
with the 3-state output changing from the high-impedance (off) state to the defined high level
tPZL
Enable time (of a 3-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms
with the 3-state output changing from the high-impedance (off) state to the defined low level
tr
Rise time
The time interval between two reference points (10% and 90%, unless otherwise specified) on a
waveform that is changing from the defined low level to the defined high level
tsk(i)
Input skew
The difference between any two propagation delay times that originate at different inputs and terminate
at a single output. Input skew describes the ability of a device to manipulate (stretch, shrink, or chop)
a clock signal. This is typically accomplished with a multiple-input gate wherein one of the inputs acts
as a controlling signal to pass the clock through. tsk(i) describes the ability of the gate to shape the pulse
to the same duration, regardless of the input used as the controlling input.
tsk(l)
Limit skew
The difference between 1) the greater of the maximum specified values of tPLH and tPHL and 2) the
lesser of the minimum specified values of tPLH and tPHL. Limit skew is not directly observed on a device.
It is calculated from the data-sheet limits for tPLH and tPHL. tsk(l) quantifies for the designer how much
variation in propagation delay time is induced by operation over the entire ranges of supply voltage,
temperature, output load, and other specified operating conditions. Specified as such, tsk(l) also
accounts for process variation. In fact, all other skew specifications [tsk(o), tsk(i), tsk(p), and tsk(pr)] are
subsets of tsk(l); they are never greater than tsk(l).
tsk(o)
Output skew
The skew between specified outputs of a single logic device with all driving inputs connected together
and the outputs switching in the same direction while driving identical specified loads
tsk(p)
Pulse skew
The magnitude of the time difference between the propagation delay times, tPHL and tPLH, when a single
switching input causes one or more outputs to switch
tsk(pr)
Process skew
The magnitude of the difference in propagation delay times between corresponding terminals of two
logic devices when both logic devices operate with the same supply voltages, operate at the same
temperature, and have identical package styles, identical specified loads, identical internal logic
functions, and the same manufacturer
1–8
POST OFFICE BOX 655303
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GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
tsu
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent
active transition at another specified input terminal
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which correct operation of the digital circuit is specified.
2. The setup time may have a negative value, in which case the minimum limit defines the
longest interval (between the active transition and the application of the other signal) for which
correct operation of the digital circuit is specified.
tw
Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse
waveform
VIH
High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to represent
the binary variables
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is to be expected.
VIL
Low-level input voltage
An input voltage within the less positive (more negative) of the two ranges of values used to represent
the binary variables
NOTE: A maximum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is to be expected.
VOH
High-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
establishes a high level at the output
VOHS
Static high-level output voltage
The static and testable voltage at a Dynamic Output Control (DOC) output with input conditions applied
that, according to the product specifications, establishes a static high level at the output. The dynamic
drive voltage is not specified for devices with DOC outputs because of its transient nature.
VOL
Low-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
establishes a low level at the output
VOLS
Static low-level output voltage
The static and testable voltage at a Dynamic Output Control (DOC) output with input conditions applied
that, according to the product specifications, establishes a static low level at the output. The dynamic
drive voltage is not specified for devices with DOC outputs because of its transient nature.
VT+
Positive-going input threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage rises from a level below the negative-going threshold voltage, VT–
VT–
Negative-going input threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage falls from a level above the positive-going threshold voltage, VT+
POST OFFICE BOX 655303
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1–9
EXPLANATION OF FUNCTION TABLES
The following symbols are used in function tables on TI data sheets:
H
L
↑
↓
X
Z
a...h
Q0
Q0
=
=
=
=
=
=
=
=
=
=
=
Qn
=
=
=
Toggle
=
high level (steady state)
low level (steady state)
transition from low to high level
transition from high to low level
value/level or resulting value/level is routed to indicated destination
value/level is re-entered
irrelevant (any input, including transitions)
off (high-impedance) state of a 3-state output
the level of steady-state inputs A through H, respectively
level of Q before the indicated steady-state input conditions were established
complement of Q0 or level of Q before the indicated steady-state input
conditions were established
level of Q before the most recent active transition indicated by ↓ or ↑
one high-level pulse
one low-level pulse
each output changes to the complement of its previous level on each active
transition indicated by ↓ or ↑
If, in the input columns, a row contains only the symbols H, L, and/or X, this means the indicated output is valid
whenever the input configuration is achieved and regardless of the sequence in which it is achieved. The output
persists so long as the input configuration is maintained.
If, in the input columns, a row contains H, L, and/or X together with ↑ and/or ↓, this means the output is valid whenever
the input configuration is achieved but the transition(s) must occur following the achievement of the steady-state
levels. If the output is shown as a level (H, L, Q0, or Q0), it persists so long as the steady-state input levels and the
levels that terminate indicated transitions are maintained. Unless otherwise indicated, input transitions in the opposite
direction to those shown have no effect at the output. (If the output is shown as a pulse,
or
, the pulse follows
the indicated input transition and persists for an interval dependent on the circuit.)
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• DALLAS, TEXAS 75265
1–11
EXPLANATION OF FUNCTION TABLES
Among the most complex function tables are those of the shift registers. These embody most of the symbols used
in any of the function tables, plus more. Below is the function table of a 4-bit bidirectional universal shift register.
FUNCTION TABLE
INPUTS
CLEAR
MODE
S1
S0
CLOCK
OUTPUTS
SERIAL
PARALLEL
LEFT
RIGHT
A
B
C
D
QA
QB
QC
QD
L
X
X
X
X
X
X
X
X
X
L
L
L
L
H
X
X
L
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
H
H
↑
X
X
a
b
c
d
a
b
c
d
H
L
H
↑
X
H
H
H
H
H
H
QAn
QBn
QCn
H
L
H
↑
X
L
L
L
L
L
L
H
L
↑
H
X
X
X
X
X
QBn
QAn
QCn
QBn
QDn
QCn
H
H
H
L
↑
L
X
X
X
X
X
QBn
QCn
QDn
L
H
L
L
X
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
The first line of the table represents a synchronous clearing of the register and says that if clear is low, all four outputs
will be reset low regardless of the other inputs. In the following lines, clear is inactive (high) and so has no effect.
The second line shows that so long as the clock input remains low (while clear is high), no other input has any effect
and the outputs maintain the levels they assumed before the steady-state combination of clear high and clock low
was established. Since on other lines of the table only the rising transition of the clock is shown to be active, the second
line implicitly shows that no further change in the outputs occurs while the clock remains high or on the high-to-low
transition of the clock.
The third line of the table represents synchronous parallel loading of the register and says that if S1 and S0 are both
high then, without regard to the serial input, the data entered at A is at output QA, data entered at B is at QB, and so
forth, following a low-to-high clock transition.
The fourth and fifth lines represent the loading of high- and low-level data, respectively, from the shift-right serial input
and the shifting of previously entered data one bit; data previously at QA is now at QB, the previous levels of QB and
QC are now at QC and QD, respectively, and the data previously at QD is no longer in the register. This entry of serial
data and shift takes place on the low-to-high transition of the clock when S1 is low and S0 is high and the levels at
inputs A through D have no effect.
The sixth and seventh lines represent the loading of high- and low-level data, respectively, from the shift-left serial
input and the shifting of previously entered data one bit; data previously at QB is now at QA, the previous levels of
QC and QD are now at QB and QC, respectively, and the data previously at QA is no longer in the register. This entry
of serial data and shift takes place on the low-to-high transition of the clock when S1 is high and S0 is low and the
levels at inputs A through D have no effect.
The last line shows that as long as both inputs are low, no other input has any effect and, as in the second line, the
outputs maintain the levels they assumed before the steady-state combination of clear high and both mode inputs
low was established.
The function table functional tests do not reflect all possible combinations or sequential modes.
1–12
POST OFFICE BOX 655303
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D FLIP-FLOP AND LATCH SIGNAL CONVENTIONS
It is normal TI practice to name the outputs and other inputs of a D-type flip-flop or latch and to draw its logic symbol
based on the assumption of true data (D) inputs. Outputs that produce data in phase with the data inputs are called
Q and those producing complementary data are called Q. An input that causes a Q output to go high or a Q output
to go low is called preset (PRE). An input that causes a Q output to go high or a Q output to go low is called clear
(CLR). Bars are used over these pin names (PRE and CLR) if they are active low.
The devices on several data sheets are second-source designs, and the pin-name conventions used by the original
manufacturers have been retained. That makes it necessary to designate the inputs and outputs of the inverting
circuits D and Q.
In some applications, it may be advantageous to redesignate the data input from D to D or vice versa. In that case,
all the other inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbols. Arbitrary pin numbers are shown.
1
PRE
C
D
2
3
4
CLR
5
S
1
Q
C1
CLR
C
1D
6
R
D
Q
2
3
4
PRE
R
5
C1
1D
6
S
Latch
1
PRE
CLK
D
3
4
CLR
1
Q
C1
1D
CLR
CLK
6
R
Q
Latch
5
S
2
Q
D
Q
3
4
PRE
Flip-Flop
5
R
2
Q
C1
1D
6
Q
S
Flip-Flop
The figures show that when Q and Q exchange names, the preset and clear pins also exchange names. The polarity
indicators ( ) on PRE and CLR remain, as these inputs are still active low, but the presence or absence of the polarity
indicator changes at D (or D), Q, and Q. Pin 5 (Q or Q) is still in phase with the data input (D or D); their active levels
change together.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1–13
THERMAL INFORMATION
In digital-system design, consideration must be given to thermal management of components. The small size of the
small-outline packages makes this even more critical. Figures 1–5 show the high-effect (High-K) thermal resistance
for the small-outline 14-, 16-, 20-, 24-, and 48-pin packages for various rates of airflow calculated in accordance with
JESD 51-7.
The thermal resistances in Figures 1–5 can be used to approximate typical and maximum virtual junction
temperatures. In general, the junction temperature for any device can be calculated using the following equation:
T J + R qJA
PT ) TA
where:
TJ
RθJA
PT
TA
= virtual junction temperature (°C)
= thermal resistance, junction to free air (°C/W)
= total power dissipation of the device (W)
= free-air temperature (°C)
θ
R JA – Junction-to-Ambient Thermal Resistance – °C/W
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
14-Pin Packages
130
120
110
DGV
PW
100
90
80
DB
70
D
60
50
40
30
20
10
0
0
100
200
300
400
Air Velocity – ft/min
Figure 1
1–14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
500
THERMAL INFORMATION
120
110
DGV
PW
100
90
80
70
DB
D
60
50
40
30
20
10
0
R JA – Junction-to-Ambient Thermal Resistance – °C/W
16-Pin Packages
130
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
θ
θ
R JA – Junction-to-Ambient Thermal Resistance – °C/W
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
0
100
200
300
400
500
20-Pin Packages
130
120
110
100
90
80
70
DGV
PW
60
DB
50
DW
40
30
20
10
0
0
100
Air Velocity – ft/min
110
100
90
80
PW
DGV
70
60
DB
50
40
DW
30
20
10
0
R JA – Junction-to-Ambient Thermal Resistance – °C/W
120
300
500
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
θ
θ
R JA – Junction-to-Ambient Thermal Resistance – °C/W
24-Pin Packages
130
200
400
Figure 3
JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
AIR VELOCITY
100
300
Air Velocity – ft/min
Figure 2
0
200
400
500
48-Pin Packages
190
180
170
160
150
140
130
120
110
100
90
80
70
DGG
DL
DGV
60
50
40
30
0
Air Velocity – ft/min
100
200
300
400
500
Air Velocity – ft/min
Figure 4
Figure 5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1–15
DEVICE NAMES AND PACKAGE DESIGNATORS
Example:
SN
74
1
2
1
H
16
3
4
5
SNJ – Conforms to MIL-PRF-38535 (QML)
Temperature Range
Examples: 54 – Military
74 – Commercial
3
Special Features
Examples: Blank = No Special Features
D – Level-Shifting Diode (CBTD)
H – Bus Hold (ALVCH)
R – Damping Resistor on Inputs/Outputs (LVCR)
S – Schottky Clamping Diode (CBTS)
5
6
Bit Width
7
R
9
10
8
Options
Function
Examples: 244 – Noninverting Buffer/Driver
374 – D-Type Flip-Flop
573 – D-Type Transparent Latch
640 – Inverting Transceiver
8
Device Revision
Examples: Blank = No Revision
Letter Designator A–Z
9
Packages
Examples: D, DW – Small-Outline Integrated Circuit (SOIC)
DB, DL – Shrink Small-Outline Package (SSOP)
DBB, DGV – Thin Very Small-Outline Package (TVSOP)
DBQ – Quarter-Size Outline Package (QSOP)
DBV, DCK – Small-Outline Transistor Package (SOT)
DGG, PW – Thin Shrink Small-Outline Package (TSSOP)
FN – Plastic Leaded Chip Carrier (PLCC)
GKE, GKF – MicroStar BGA Low-Profile Fine-Pitch
Ball Grid Array (LFBGA)
N, NP, NT – Plastic Dual-In-Line Package (PDIP)
NS, PS – Small-Outline Package (SOP)
PAG, PAH, PCA, PCB, PM, PN, PZ –
Thin Quad Flatpack (TQFP)
PH, PQ, RC – Quad Flatpack (QFP)
10 Tape and Reel
Devices in the DB and PW package types include the R designation
for reeled product. Existing product inventory designated LE may
remain, but all products are being converted to the R designation.
Examples:
Existing Nomenclature – SN74LVTxxxDBLE
New Nomenclature – SN74LVTxxxADBR
LE – Left Embossed (valid for DB and PW packages only)
R – Standard (valid for all surface-mount packages)
There is no functional difference between LE and R designated
products, with respect to the carrier tape, cover tape, or reels used.
Examples: Blank = Gates, MSI, and Octals
1G – Single Gate
8 – Octal IEEE 1149.1 (JTAG)
16 – Widebus (16, 18, and 20 bit)
18 – Widebus IEEE 1149.1 (JTAG)
32 – Widebus+ (32 and 36 bit)
MicroStar BGA, Widebus, and Widebus+ are trademarks of Texas Instruments Incorporated.
1–16
DGG
Examples: Blank = No Options
2 – Series-Damping Resistor on Outputs
4 – Level Shifter
25 – 25-Ω Line Driver
7
Family
Examples: Blank – Transistor-Transistor Logic
ABT – Advanced BiCMOS Technology
ABTE – Advanced BiCMOS Technology/
Enhanced Transceiver Logic
AC/ACT – Advanced CMOS Logic
AHC/AHCT – Advanced High-Speed CMOS Logic
ALB – Advanced Low-Voltage BiCMOS
ALS – Advanced Low-Power Schottky Logic
ALVC – Advanced Low-Voltage CMOS Technology
AS – Advanced Schottky Logic
AVC – Advanced Very-Low-Voltage CMOS Logic
BCT – BiCMOS Bus-Interface Technology
CBT – Crossbar Technology
CBTLV – Low-Voltage Crossbar Technology
F – F Logic
FB – Backplane Transceiver Logic/Futurebus+
GTL – Gunning Transceiver Logic
HC/HCT – High-Speed CMOS Logic
HSTL – High-Speed Transceiver Logic
LS – Low-Power Schottky Logic
LV – Low-Voltage CMOS Technology
LVC – Low-Voltage CMOS Technology
LVT – Low-Voltage BiCMOS Technology
S – Schottky Logic
SSTL – Stub Series-Terminated Logic
TVC – Translation Voltage Clamp Logic
4
244
6
Standard Prefix
Example:
2
AVC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DEVICE NAMES AND PACKAGE DESIGNATORS
NOTIFICATION OF PACKAGE NOMENCLATURE ALIAS
(for Standard Linear and Logic device names of greater than 18 characters)
TI is converting from its current order-entry system to a more advanced system. This conversion requires
modifications, both internal and external, to TI’s current business processes. This new system will ultimately provide
significant improvements to all facets of TI’s business – from production, to order entry, to logistics. One change
required is a limitation of TI part numbers to no more than 18 characters in length. Based on customer inputs, Standard
Linear and Logic determined the least disruptive implementations as outlined below:
1. Package alias
TI will use a package alias to denote specific package types for devices currently exceeding 18 characters in
length. Table 1 shows a mapping of package codes to an alias single-character representation.
Table 1
CURRENT
PACKAGE
CODE
ALIAS
DL
L
DGG/DBB
G
DGV
V
DLR
LR – tape/reel packing
DGGR/DBBR
GR – tape/reel packing
DGVR
VR – tape/reel packing
Current: SN74 ALVCH 162269A DGGR
New:
SN74 ALVCH 162269A GR1
2. Resistor-option nomenclature
For devices greater than 18 characters with input and output resistors, TI will adopt a simplified
nomenclature to designate the resistor option. This will eliminate the redundant “2” (designating output
resistors) when the part number also contains an “R” (designating input/output resistors).
Input/Output Resistor
Output Resistor
Current: SN74 ALVCH R 16 2 245 A
New:
SN74 ALVCH R 16 245 A
There is no change to the device or data-sheet electrical parameters. The packages involved and the changes in
nomenclature are noted in Table 1.
These nomenclature changes are being gradually implemented. The first customer-visible conversions for TI logic
devices will be made to data sheets. Over the next few months, TI logic data sheets will be updated. These changes
in device nomenclature do not reflect a change in device performance or process characteristics.
POST OFFICE BOX 655303
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1–17
General Information
Widebus
Widebus+
Application Reports
Mechanical Data
2–1
Contents
Widebus
2–2
SN74AVC16244
Page
16-Bit Buffer/Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
SN74AVCH16244
16-Bit Buffer/Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
SN74AVC16245
16-Bit Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
SN74AVCH16245
16-Bit Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
SN74AVC16269
12-Bit to 24-Bit Registered Bus Exchanger With 3-State Outputs . . . . . . . . . . 2–47
SN74AVC16334
16-Bit Universal Bus Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . 2–59
SN74AVC16373
16-Bit Transparent D-Type Latch With 3-State Outputs . . . . . . . . . . . . . . . . . . . 2–71
SN74AVCH16373
16-Bit Transparent D-Type Latch With 3-State Outputs . . . . . . . . . . . . . . . . . . . 2–81
SN74AVC16374
16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs . . . . . . . . . . . . . 2–93
SN74AVCH16374
16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs . . . . . . . . . . . . . 2–103
SN74AVC16501
18-Bit Universal Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . 2–115
SN74AVC16601
18-Bit Universal Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . 2–127
SN74AVC16646
16-Bit Bus Transceiver and Register With 3-State Outputs . . . . . . . . . . . . . . . . 2–139
SN74AVC16721
20-Bit Flip-Flop With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–153
SN74AVC16722
22-Bit Flip-Flop With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–163
SN74AVC16820
10-Bit Flip-Flop With Dual Outputs and 3-State Outputs . . . . . . . . . . . . . . . . . . 2–173
SN74AVC16821
20-Bit Bus-Interface Flip-Flop With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . 2–183
SN74AVC16827
20-Bit Buffer/Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–195
SN74AVC16831
9-Bit 1-to-4 Address Register/Driver With 3-State Outputs . . . . . . . . . . . . . . . . 2–205
SN74AVC16834
18-Bit Universal Bus Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . 2–217
SN74AVC16835
18-Bit Universal Bus Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . 2–229
SN74AVC16836
20-Bit Universal Bus Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . 2–241
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D
D Overvoltage-Tolerant Inputs/Outputs Allow
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Less Than 2-ns Maximum Propagation
Delay at 2.5-V and 3.3-V VCC
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
D
D
D
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC
operation.
The SN74AVC16244 is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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2–3
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16244 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE
2–4
A
OUTPUT
Y
L
L
L
L
H
H
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
logic symbol†
1OE
2OE
1
EN1
48
25
3OE
4OE
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
24
47
EN2
EN3
EN4
1
1
2
46
3
44
5
43
6
41
1
2
8
40
9
38
11
37
12
36
13
1
3
35
14
33
16
32
17
30
1
4
19
29
20
27
22
26
23
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
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2–5
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–7
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ
ICC
Control inputs
VCC
1.4 V to 3.6 V
Co
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
MAX
UNIT
V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
VI = VCC or GND
VI = VCC or GND
Outputs
TYP†
1.4 V to 3.6 V
Ci
Data inputs
MIN
VO = VCC or GND
2.5 V
3.5
3.3 V
3.5
2.5 V
6
3.3 V
6
2.5 V
6.5
3.3 V
6.5
pF
pF
† Typical values are measured at TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
tdis
PARAMETER
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Y
3.1
0.6
3.3
0.7
2.9
0.6
1.9
0.5
1.7
ns
OE
Y
7.6
1.4
8
1.3
6.8
0.9
4
0.7
3.5
ns
OE
Y
7.2
1.7
7.3
1.6
6.2
1
4.3
1
3.5
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–8
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
23
27
33
0.1
0.1
0.1
UNIT
pF
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–9
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–11
SN74AVC16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES141K – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC
Timing
Input
Input
VCC/2
VCC/2
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D
D Overvoltage-Tolerant Inputs/Outputs Allow
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Less Than 2-ns Maximum Propagation
Delay at 2.5-V and 3.3-V VCC
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
D
D
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup / Pulldown
Resistors
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC
operation.
The SN74AVCH16244 is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–13
PRODUCT PREVIEW
description
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVCH16244 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
2–14
OE
A
OUTPUT
Y
L
L
L
L
H
H
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
logic symbol†
2OE
1
EN1
48
25
3OE
4OE
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
24
47
EN2
EN3
EN4
1
1
2
46
3
44
5
43
6
41
1
2
8
40
9
38
11
37
12
36
13
1
3
35
14
33
16
32
17
30
1
4
19
29
20
27
22
26
23
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
PRODUCT PREVIEW
1OE
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–15
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
PRODUCT PREVIEW
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–17
PRODUCT PREVIEW
VCC
MIN
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
IOHS = –4 mA,
IOHS = –8 mA,
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Control inputs
PRODUCT PREVIEW
IBHL‡
IBHH§
VIH = 0.91 V
VIH = 1.07 V
VIH = 1.7 V
VIH = 2 V
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
VI = VCC or GND
VI = 0.57 V
1.2
2.3 V
1.75
3V
2.3
1.4 V
0.4
0.45
2.3 V
0.55
3V
0.7
3.6 V
±2.5
45
75
VI = 1.07 V
VI = 1.7 V
1.65 V
–25
2.3 V
–45
3V
–75
1.95 V
200
2.7 V
300
3.6 V
500
1.95 V
–200
2.7 V
–300
3.6 V
–500
ICC
VI = VCC or GND,
IO = 0
UNIT
V
1.65 V
3V
VI or VO = 3.6 V
VO = VCC or GND
MAX
0.2
25
Ioff
IOZ
V
µA
µA
µA
µA
µA
0
±10
µA
3.6 V
±10
µA
3.6 V
40
µA
2.5 V
Control inputs
3.3 V
VI = VCC or GND
2.5 V
Data inputs
Outputs
1.65 V
2.3 V
VI = 0 to VCC
Co
VCC–0.2
1.05
1.65 V
IBHHO#
TYP†
1.4 V
VI = 0.7 V
VI = 0.8 V
VI = 0 to VCC
Ci
MIN
1.4 V to 3.6 V
VI = 2 V
IBHLO¶
VCC
1.4 V to 3.6 V
pF
3.3 V
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
2–18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ns
ten
OE
Y
ns
tdis
OE
Y
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
operating characteristics, TA = 25°C
PARAMETER
Power dissipation
capacitance
Outputs enabled
Outputs disabled
CL = 0,
VCC = 1.8 V
TYP
f = 10 MHz
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
PRODUCT PREVIEW
Cpd
TEST CONDITIONS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–19
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–21
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES150E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Input
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–23
PRODUCT PREVIEW
Timing
Input
VCC/2
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D
D Overvoltage-Tolerant Inputs/Outputs Allow
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Less Than 2-ns Maximum Propagation
Delay at 2.5-V and 3.3-V VCC
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
D
D
D
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 250 mA Per
JESD 78
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed
specifically for 1.65-V to 3.6-V VCC operation.
The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function
implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–25
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16245 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
FUNCTION TABLE
(each 8-bit transceiver)
INPUTS
2–26
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
logic symbol†
48
1OE
1DIR
G3
1
3 EN1 [BA]
3 EN2 [AB]
25
2OE
2DIR
G6
24
6 EN4 [BA]
6 EN5 [AB]
1A1
47
2
1
1B1
2
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
4
5
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
36
13
1B1
2B1
To Seven Other Channels
To Seven Other Channels
POST OFFICE BOX 655303
2OE
• DALLAS, TEXAS 75265
2–27
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output
when the output is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output
when the output is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–29
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ‡
ICC
VCC
1.4 V to 3.6 V
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
VI = VCC or GND
VI or VO = 3.6 V
VO = VCC or GND,
VI = VCC or GND,
Control inputs
VI = VCC or GND
Cio
A or B ports
VO = VCC or GND
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
MAX
VI (OE)= VCC
IO = 0
UNIT
V
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
Ci
MIN
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
3.6 V
±2.5
µA
0
±10
µA
3.6 V
±12.5
µA
3.6 V
40
µA
2.5 V
3
3.3 V
3
2.5 V
9
3.3 V
9
pF
pF
† Typical values are measured at TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
ten
tdis
PARAMETER
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B or A
3.9
0.8
4
0.7
3
0.6
1.9
0.5
1.7
ns
OE
A or B
8.4
1.5
9.2
1.4
7
1
4.3
0.7
3.7
ns
OE
A or B
8.4
2.3
9.3
2.2
7
1.1
4
1.2
3.9
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–30
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
35
38
44
6
6
7
UNIT
pF
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–31
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–33
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
From Output
Under Test
2 × VCC
S1
500 Ω
GND
CL = 30 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
500 Ω
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
Input
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
tPLZ
VCC
VCC/2
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VOL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D
D Overvoltage-Tolerant Inputs/Outputs Allow
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Less Than 2-ns Maximum Propagation
Delay at 2.5-V and 3.3-V VCC
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
D
D
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup / Pulldown
Resistors
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit (dual-octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed
specifically for 1.65-V to 3.6-V VCC operation.
The SN74AVCH16245 is designed for asynchronous communication between data buses. The control-function
implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–35
PRODUCT PREVIEW
description
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVCH16245 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
FUNCTION TABLE
(each 8-bit transceiver)
INPUTS
OE
2–36
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
logic symbol†
48
1OE
1DIR
G3
1
3 EN1 [BA]
3 EN2 [AB]
25
2OE
2DIR
G6
24
6 EN4 [BA]
6 EN5 [AB]
1A1
47
2
1
1B1
2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
4
1B2
1B3
1B4
1B5
1B6
1B7
PRODUCT PREVIEW
1A2
1B8
2B1
5
2A2
2A3
2A4
2A5
2A6
2A7
2A8
35
14
33
16
32
17
30
19
29
20
27
22
26
23
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
36
13
1B1
2B1
To Seven Other Channels
To Seven Other Channels
POST OFFICE BOX 655303
2OE
• DALLAS, TEXAS 75265
2–37
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Voltage range applied to any input/output
when the output is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output
when the output is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–39
PRODUCT PREVIEW
VCC
MIN
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
IOHS = –4 mA,
IOHS = –8 mA,
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Control inputs
PRODUCT PREVIEW
IBHL‡
IBHH§
VIH = 0.91 V
VIH = 1.07 V
VIH = 1.7 V
VIH = 2 V
MIN
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
VI = VCC or GND
VI = 0.57 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
1.4 V
0.4
0.45
2.3 V
0.55
3V
0.7
3.6 V
±2.5
25
2.3 V
45
3V
75
VI = 1.07 V
VI = 1.7 V
1.65 V
–25
2.3 V
–45
3V
–75
1.95 V
200
2.7 V
300
3.6 V
500
1.95 V
–200
2.7 V
–300
3.6 V
–500
VI = 0 to VCC
Ioff
IOZ||
VI or VO = 3.6 V
VO = VCC or GND
ICC
VI = VCC or GND,
Ci
Control inputs
VI = VCC or GND
Cio
A or B ports
VO = VCC or GND
IO = 0
UNIT
V
1.65 V
1.65 V
IBHHO#
MAX
0.2
VI = 0.7 V
VI = 0.8 V
VI = 0 to VCC
TYP†
1.4 V
1.4 V to 3.6 V
VI = 2 V
IBHLO¶
VCC
1.4 V to 3.6 V
V
µA
µA
µA
µA
µA
0
±10
µA
3.6 V
±12.5
µA
3.6 V
40
µA
2.5 V
3.3 V
2.5 V
pF
pF
3.3 V
† Typical values are measured at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| For I/O ports, the parameter IOZ includes the input leakage current.
2–40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ns
ten
OE
A or B
ns
tdis
OE
A or B
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
operating characteristics, TA = 25°C
PARAMETER
Power dissipation
capacitance
Outputs enabled
Outputs disabled
CL = 0,
VCC = 1.8 V
TYP
f = 10 MHz
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
PRODUCT PREVIEW
Cpd
TEST CONDITIONS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–41
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–43
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES151E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Input
VCC/2
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–45
PRODUCT PREVIEW
Timing
Input
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 12-bit to 24-bit registered bus exchanger is operational at 1.2-V to 3.6-V VCC, but is designed specifically
for 1.65-V to 3.6-V VCC operation.
The SN74AVC16269 is used in applications in which two separate ports must be multiplexed onto, or
demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous
DRAMs and high-speed microprocessors.
Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the
appropriate clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit
words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage
register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–47
PRODUCT PREVIEW
description
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled
by the active-low output enables (OEA, OEB1, OEB2).
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon
as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the first clock pulse.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16269 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
OEA
OEB1
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
NC
SEL
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OEB2
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
NC – No internal connection
2–48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
Function Tables
OUTPUT ENABLE
OUTPUTS
INPUTS
CLK
OEA
OEB
A
1B, 2B
↑
H
H
Z
Z
↑
H
L
Z
Active
↑
L
H
Active
Z
↑
L
L
Active
Active
A-TO-B STORAGE (OEB = L)
INPUTS
OUTPUTS
CLKENA1
CLKENA2
CLK
A
1B
1B0†
2B
2B0†
H
H
X
X
L
X
↑
L
X
↑
L
L
X
H
H
X
X
L
↑
L
X
X
L
↑
H
L
H
PRODUCT PREVIEW
X
† Output level before the indicated steady-state input
conditions were established
B-TO-A STORAGE (OEA = L)
INPUTS
1B
2B
OUTPUT
A
CLK
SEL
X
H
X
X
X
L
X
X
↑
H
L
X
A0†
A0†
L
↑
H
H
X
H
↑
L
X
L
L
↑
L
X
H
H
† Output level before the indicated steady-state
input conditions were established
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–49
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
logic diagram (positive logic)
CLK
OEB1
29
C1
2
1D
C1
OEB2
CLKENA1
CLKENA2
56
1D
30
55
C1
SEL
PRODUCT PREVIEW
OEA
28
1D
1
1D
1 of 12 Channels
C1
G1
A1
8
C1
1
1D
23
1B1
1
CE
C1
1D
6
CE
C1
1D
2–50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2B1
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–51
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output when the output
is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output when the output
is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
PRODUCT PREVIEW
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2–52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ‡
ICC
VCC
1.4 V to 3.6 V
MIN
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
UNIT
V
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
MAX
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±12.5
µA
3.6 V
40
µA
Ci
Control inputs
VI = VCC or GND
Cio
A or B ports
VO = VCC or GND
IO = 0
2.5 V
pF
3.3 V
2.5 V
pF
3.3 V
† Typical values are measured at TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
fclock Clock frequency
tw
Pulse duration, CLK high or low
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
MHz
ns
A data before CLK↑
B data before CLK↑
tsu
Setup
time
SEL before CLK↑
ns
CLKENA1 or CLKENA2
before CLK↑
OE before CLK↑
A data after CLK↑
B data after CLK↑
th
Hold
time
SEL after CLK↑
ns
CLKENA1 or CLKENA2
after CLK↑
OE after CLK↑
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–53
PRODUCT PREVIEW
PARAMETER
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
VCC = 2.5 V
± 0.2 V
MAX
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fmax
MHz
tpd
CLK
ten
CLK
tdis
CLK
B
ns
A
B
ns
A
B
ns
A
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
FROM
(INPUT)
PRODUCT PREVIEW
PARAMETER
tpd
VCC = 3.3 V
± 0.15 V
TO
(OUTPUT)
MIN
B
CLK
UNIT
MAX
ns
A
† Texas Instruments SPICE simulation data
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–54
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–55
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–56
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–57
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES152F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
VCC/2
0V
0V
tsu
PRODUCT PREVIEW
Input
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–58
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D Ioff Supports Partial-Power-Down Mode
D
D
D
D
Operation
Ideal for Use in PC133 Registered DIMM
Applications
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition
of CLK. When OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–59
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16334 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y11
Y12
VCC
Y13
Y14
GND
Y15
Y16
NC
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
CLK
A1
A2
GND
A3
A4
VCC
A5
A6
GND
A7
A8
A9
A10
GND
A11
A12
VCC
A13
A14
GND
A15
A16
LE
NC – No internal connection
FUNCTION TABLE
(each universal bus driver)
INPUTS
OE
LE
CLK
A
OUTPUT
Y
H
X
X
X
Z
L
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
Y0†
† Output level before the indicated steady-state
input conditions were established
L
2–60
H
L or H
POST OFFICE BOX 655303
X
• DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
logic symbol†
OE
CLK
LE
1
EN1
48
25
2C3
C3
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
2
1
1
3D
47
3
46
5
44
6
43
1
8
41
9
40
11
38
12
37
13
36
14
35
16
33
17
32
19
30
20
29
22
27
23
26
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
48
CLK
LE
25
47
A1
1D
C1
2
Y1
CLK
To 15 Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–61
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–62
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–63
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ
ICC
CLK input
Ci
Co
VCC
1.4 V to 3.6 V
MIN
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
UNIT
V
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
MAX
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
VI = VCC or GND
Control inputs
VI = VCC or GND
Data inputs
VI = VCC or GND
Outputs
VO = VCC or GND
2.5 V
4
3.3 V
4
2.5 V
4
3.3 V
4
2.5 V
2.5
3.3 V
2.5
2.5 V
6.5
3.3 V
6.5
pF
pF
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
Clock frequency
tw
Pulse
duration
tsu
Setup
time
MAX
VCC = 2.5 V
± 0.2 V
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
Data
before LE↑
UNIT
MAX
150
LE low
Data before CLK↑
MHz
ns
1
0.8
0.7
0.7
0.7
CLK high
1.5
1.4
0.9
0.9
0.9
CLK low
2.7
1.6
1.2
1
1
1.3
1.1
0.9
0.8
0.7
ns
CLK high
2.2
1.9
1.7
1.5
1.5
ns
CLK low
2.4
1.8
1.6
1.4
1.3
ns
th
Hold
time
Data after CLK↑
th
Hold
time
Data
↑
after LE↑
2–64
MAX
VCC = 1.5 V
± 0.1 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
fmax
VCC = 2.5 V
± 0.2 V
MAX
150
A
tpd
LE
MAX
150
MIN
UNIT
MAX
150
MHz
5.3
1.2
6.2
1.5
4.9
1
3.2
0.9
7
2.2
9.7
1.8
7.5
1.5
4.9
0.8
4
6
1.9
7.8
1.6
6
1.1
3.7
1
3.1
Y
CLK
ten
tdis
MIN
VCC = 3.3 V
± 0.3 V
2.5
ns
OE
Y
7.9
2.4
10.2
1.6
8.8
1.5
6.7
1
6.2
ns
OE
Y
7.7
2.1
10.3
1.5
8.4
1.2
5.3
1
5.3
ns
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
FROM
(INPUT)
PARAMETER
A
tpd
VCC = 3.3 V
± 0.15 V
TO
(OUTPUT)
Y
CLK
MIN
MAX
0.6
1.3
0.7
1.5
UNIT
ns
† Texas Instruments SPICE simulation data
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
45
48
52
23
25
28
UNIT
pF
2–65
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–66
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VOH
VCC/2
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–67
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–68
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
Input
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–69
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D Ioff Supports Partial-Power-Down Mode
D
D
D
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V
to 3.6-V VCC operation.
The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the
latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the levels set up at the D inputs.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
2–71
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16373 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
2–72
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
POST OFFICE BOX 655303
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
• DALLAS, TEXAS 75265
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each 8-bit latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic symbol†
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
1EN
48
C3
24
2EN
25
C4
47
3D
2
1
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
4D
2
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE
1LE
1D1
1
2OE
48
47
2LE
C1
2
1D
1Q1
24
25
C1
2D1
36
13
2Q1
To Seven Other Channels
To Seven Other Channels
POST OFFICE BOX 655303
1D
• DALLAS, TEXAS 75265
2–73
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–74
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–75
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
II
Ioff
Control inputs
IOZ
ICC
Control inputs
1.4 V
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
VCC
1.4 V to 3.6 V
Co
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
MAX
UNIT
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
2.5 V
VI = VCC or GND
VI = VCC or GND
Outputs
TYP†
1.4 V to 3.6 V
Ci
Data inputs
MIN
VO = VCC or GND
3
3.3 V
3
2.5 V
2.5
3.3 V
2.5
2.5 V
6.5
3.3 V
6.5
pF
pF
† Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
tw
tsu
Pulse duration, LE high
th
Hold time, data after LE↓
Setup time, data before LE↓
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
2.2
2
1.8
ns
1.7
1.2
1.1
0.9
0.8
ns
2
1.1
1.1
1.1
1
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
tpd
2–76
FROM
(INPUT)
D
LE
TO
(OUTPUT)
Q
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
5.8
1.2
6.8
1
5.7
0.8
3.3
0.7
2.8
7.2
1.4
8.3
1.1
6.6
0.8
4
0.7
3.2
UNIT
ns
ten
OE
Q
7.4
1.6
8.8
1.6
6.7
1.4
4.3
0.7
3.4
ns
tdis
OE
Q
8.4
2.5
9.4
2.3
7.8
1.3
4.2
1.2
3.9
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Power dissipation
capacitance
Cpd
Outputs disabled
CL = 0,
VCC = 1.8 V
TYP
f = 10 MHz
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
40
43
47
20
22
24
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–77
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–78
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–79
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
Input
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC/2
VCC
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–80
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D Overvoltage-Tolerant Inputs/Outputs Allow
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
D
D
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup / Pulldown
Resistors
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V
to 3.6-V VCC operation.
The SN74AVCH16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the
latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the levels set up at the D inputs.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–81
PRODUCT PREVIEW
description
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVCH16373 is characterized for operation from –40°C to 85°C.
terminal assignments
PRODUCT PREVIEW
DGG OR DGV PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
2–82
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
POST OFFICE BOX 655303
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
• DALLAS, TEXAS 75265
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each 8-bit latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic symbol†
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
1EN
48
C3
24
2EN
25
C4
47
3D
2
1
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
4D
2
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q1
PRODUCT PREVIEW
1OE
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE
1LE
1D1
1
2OE
48
47
2LE
C1
2
1D
1Q1
24
25
C1
2D1
36
13
2Q1
To Seven Other Channels
To Seven Other Channels
POST OFFICE BOX 655303
1D
• DALLAS, TEXAS 75265
2–83
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–84
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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2–85
PRODUCT PREVIEW
VCC
MIN
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
IOHS = –4 mA,
IOHS = –8 mA,
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Control inputs
PRODUCT PREVIEW
IBHL‡
IBHH§
VIH = 0.91 V
VIH = 1.07 V
VIH = 1.7 V
VIH = 2 V
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
VI = VCC or GND
VI = 0.57 V
2.3 V
1.75
3V
2.3
1.4 V
0.4
0.45
2.3 V
0.55
3V
0.7
3.6 V
±2.5
75
VI = 1.07 V
VI = 1.7 V
1.65 V
–25
2.3 V
–45
3V
–75
1.95 V
200
2.7 V
300
3.6 V
500
1.95 V
–200
2.7 V
–300
3.6 V
–500
IO = 0
UNIT
V
1.65 V
45
VI = VCC or GND,
MAX
0.2
3V
ICC
V
µA
µA
µA
µA
µA
0
±10
µA
3.6 V
±10
µA
3.6 V
40
µA
2.5 V
Control inputs
3.3 V
VI = VCC or GND
2.5 V
Data inputs
Outputs
1.2
25
VI or VO = 3.6 V
VO = VCC or GND
Co
1.65 V
2.3 V
Ioff
IOZ
Ci
VCC–0.2
1.05
1.65 V
VI = 0 to VCC
TYP†
1.4 V
VI = 0.7 V
VI = 0.8 V
VI = 0 to VCC
IBHHO#
MIN
1.4 V to 3.6 V
VI = 2 V
IBHLO¶
VCC
1.4 V to 3.6 V
pF
3.3 V
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
2–86
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
tw
tsu
Pulse duration, LE high or low
ns
Setup time, data before LE↓
ns
th
Hold time, data after LE↓
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
tpd
FROM
(INPUT)
TO
(OUTPUT)
D
LE
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
Q
ns
ten
OE
Q
ns
tdis
OE
Q
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
2–87
PRODUCT PREVIEW
PARAMETER
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–88
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–89
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–90
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES157E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
0V
VCC/2
0V
tsu
Data
Input
Input
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
VCC/2
VCC/2
tPLZ
VCC
VCC/2
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
tPLH
VOL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
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2–91
PRODUCT PREVIEW
Timing
Input
VCC/2
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D Ioff Supports Partial-Power-Down Mode
D
D
D
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit edge-triggered D-type flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for
1.65-V to 3.6-V VCC operation.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–93
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
The SN74AVC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive
transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs.
OE can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and the increased drive provide the capability to drive bus lines without need for
interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16374 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
2–94
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
POST OFFICE BOX 655303
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
• DALLAS, TEXAS 75265
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each 8-bit flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
logic symbol†
1OE
1CLK
2OE
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
1EN
48
C1
24
2EN
25
C2
47
1D
2
1
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
2D
2
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE
1CLK
1D1
1
2OE
48
47
2CLK
C1
2
1D
1Q1
24
25
C1
2D1
36
13
2Q1
To Seven Other Channels
To Seven Other Channels
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1D
• DALLAS, TEXAS 75265
2–95
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–96
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• DALLAS, TEXAS 75265
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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2–97
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
II
Control inputs
Ioff
IOZ
ICC
Control inputs
1.4 V
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
VCC
1.4 V to 3.6 V
Co
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
MAX
UNIT
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
2.5 V
VI = VCC or GND
VI = VCC or GND
Outputs
TYP†
1.4 V to 3.6 V
Ci
Data inputs
MIN
VO = VCC or GND
3
3.3 V
3
2.5 V
2.5
3.3 V
2.5
2.5 V
6.5
3.3 V
6.5
pF
pF
† Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
160
MAX
VCC = 3.3 V
± 0.3 V
MIN
fclock
tw
Clock frequency
3.1
2.5
2.5
ns
tsu
th
Setup time, data before CLK↑
4.1
2.7
1.9
1.4
1.4
ns
Hold time, data after CLK↑
1.7
1.3
1.2
1.1
1.1
ns
Pulse duration, CLK high or low
200
UNIT
MAX
200
MHz
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
ten
tdis
PARAMETER
2–98
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
Q
7.3
1.5
8.4
1.2
6.7
0.8
4.1
0.7
3.3
ns
OE
Q
7.4
1.6
8.5
1.6
6.7
0.9
4.3
0.7
3.4
ns
OE
Q
8.4
2.5
9.4
2.3
7.8
1
4.2
1.5
3.9
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
200
MIN
UNIT
TYP
160
MIN
VCC = 3.3 V
± 0.3 V
MAX
200
MHz
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Power dissipation
capacitance
Cpd
Outputs disabled
CL = 0,
VCC = 1.8 V
TYP
f = 10 MHz
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
74
81
89
52
57
63
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–99
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–100
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–101
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
Input
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
VCC/2
VCC/2
VCC
VCC/2
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
tPLH
VOL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–102
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D Overvoltage-Tolerant Inputs/Outputs Allow
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
D
D
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup / Pulldown
Resistors
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit edge-triggered D-type flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for
1.65-V to 3.6-V VCC operation.
The SN74AVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive
transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs.
OE can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and the increased drive provide the capability to drive bus lines without need for
interface or pullup components.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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2–103
PRODUCT PREVIEW
description
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVCH16374 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
FUNCTION TABLE
(each 8-bit flip-flop)
INPUTS
2–104
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
logic symbol†
1CLK
2OE
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
1EN
48
C1
24
2EN
25
C2
47
1D
2
1
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
2D
13
2
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
PRODUCT PREVIEW
1OE
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE
1CLK
1D1
1
2OE
48
47
2CLK
C1
2
1D
1Q1
24
25
C1
2D1
36
13
2Q1
To Seven Other Channels
To Seven Other Channels
POST OFFICE BOX 655303
1D
• DALLAS, TEXAS 75265
2–105
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–106
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–107
PRODUCT PREVIEW
VCC
MIN
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
IOHS = –4 mA,
IOHS = –8 mA,
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Control inputs
PRODUCT PREVIEW
IBHL‡
IBHH§
VIH = 0.91 V
VIH = 1.07 V
VIH = 1.7 V
VIH = 2 V
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
VI = VCC or GND
VI = 0.57 V
1.2
2.3 V
1.75
3V
2.3
1.4 V
0.4
0.45
2.3 V
0.55
3V
0.7
3.6 V
±2.5
45
75
VI = 1.07 V
VI = 1.7 V
1.65 V
–25
2.3 V
–45
3V
–75
1.95 V
200
2.7 V
300
3.6 V
500
1.95 V
–200
2.7 V
–300
3.6 V
–500
ICC
VI = VCC or GND,
IO = 0
UNIT
V
1.65 V
3V
VI or VO = 3.6 V
VO = VCC or GND
MAX
0.2
25
Ioff
IOZ
V
µA
µA
µA
µA
µA
0
±10
µA
3.6 V
±10
µA
3.6 V
40
µA
2.5 V
Control inputs
3.3 V
VI = VCC or GND
2.5 V
Data inputs
Outputs
1.65 V
2.3 V
VI = 0 to VCC
Co
VCC–0.2
1.05
1.65 V
IBHHO#
TYP†
1.4 V
VI = 0.7 V
VI = 0.8 V
VI = 0 to VCC
Ci
MIN
1.4 V to 3.6 V
VI = 2 V
IBHLO¶
VCC
1.4 V to 3.6 V
pF
3.3 V
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
2–108
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
MHz
Pulse duration, CLK high or low
ns
tsu
th
Setup time, data before CLK↑
ns
Hold time, data after CLK↑
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
ns
ten
OE
Q
ns
tdis
OE
Q
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
2–109
PRODUCT PREVIEW
MHz
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–110
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–111
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–112
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES159E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Input
VCC/2
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
VOL
VCC/2
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VCC/2
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–113
PRODUCT PREVIEW
Timing
Input
VCC/2
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 18-bit universal bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V
to 3.6-V VCC operation.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the
outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
DOC, EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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2–115
PRODUCT PREVIEW
description
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16501 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
2–116
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
POST OFFICE BOX 655303
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
• DALLAS, TEXAS 75265
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE†
(each universal bus transceiver)
INPUTS
OEAB
LEAB
CLKAB
A
OUTPUT
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
B0‡
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established, provided that CLKAB is
high before LEAB goes low
H
L
L or H
X
logic symbol§
CLKAB
LEAB
1
55
2
CLKBA
LEBA
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
2C3
C3
G2
27
OEBA
EN1
PRODUCT PREVIEW
OEAB
30
28
3
EN4
5C6
C6
G5
3D
1
1
4
1
6D
54
5
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–117
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
logic diagram (positive logic)
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
PRODUCT PREVIEW
A1
1
55
2
28
30
27
3
1D
C1
CLK
54
B1
1D
C1
CLK
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output when the output
is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output when the output
is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–119
PRODUCT PREVIEW
VCC
MIN
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
PRODUCT PREVIEW
II
Ioff
Control inputs
IOZ‡
ICC
VCC
1.4 V to 3.6 V
MIN
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
UNIT
V
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
MAX
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±12.5
µA
3.6 V
40
µA
Ci
Control inputs
VI = VCC or GND
Cio
A or B ports
VO = VCC or GND
IO = 0
2.5 V
pF
3.3 V
2.5 V
pF
3.3 V
† Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
Clock frequency
tw
Pulse
duration
tsu
Setup
time
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
MHz
LE high
ns
CLK high or low
Data before CLK↑
th
2–120
Hold
time
Data
before LE↓
ns
CLK high
CLK low
Data after CLK↑
Data
after LE↓
ns
CLK high
or low
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
fmax
MHz
A or B
tpd
UNIT
MAX
LE
CLK
B or A
ns
A or B
ten
tdis
OEAB
B
ns
OEAB
B
ns
ten
tdis
OEBA
A
ns
OEBA
A
ns
operating characteristics, TA = 25°C
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
2–121
PRODUCT PREVIEW
PARAMETER
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–122
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–123
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–124
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES160E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
Input
VCC/2
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
tPLZ
VCC
VCC/2
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VOL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–125
PRODUCT PREVIEW
VCC
Timing
Input
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 18-bit universal bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V
to 3.6-V VCC operation.
The SN74AVC16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched,
and clocked modes.
DOC, EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–127
PRODUCT PREVIEW
description
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is
low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16601 is characterized for operation from –40°C to 85°C.
terminal assignments
PRODUCT PREVIEW
DGG OR DGV PACKAGE
(TOP VIEW)
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
2–128
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
POST OFFICE BOX 655303
CLKENAB
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
• DALLAS, TEXAS 75265
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE†
(each universal bus transceiver)
INPUTS
CLKENAB
OEAB
LEAB
CLKAB
A
OUTPUT
B
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
L
L
X
X
H
B0‡
H
L
L
X
X
L
L
L
↑
L
B0‡
L
L
L
L
↑
H
H
B0‡
† A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA,
LEBA, CLKBA, and CLKENBA.
‡ Output level before the indicated steady-state input conditions were
established
L
L
L
L or H
X
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
PRODUCT PREVIEW
logic diagram (positive logic)
1
56
55
2
28
30
29
27
CE
3
1D
C1
CLK
54
B1
CE
1D
C1
CLK
To 17 Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–129
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output when the output
is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output when the output
is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–130
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–131
PRODUCT PREVIEW
VCC
MIN
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
PRODUCT PREVIEW
II
Ioff
Control inputs
IOZ‡
ICC
VCC
1.4 V to 3.6 V
MIN
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
UNIT
V
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
MAX
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±12.5
µA
3.6 V
40
µA
Ci
Control inputs
VI = VCC or GND
Cio
A or B ports
VO = VCC or GND
IO = 0
2.5 V
pF
3.3 V
2.5 V
pF
3.3 V
† Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
Clock frequency
tw
Pulse
duration
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
MHz
LE high
ns
CLK high or low
Data before CLK↑
tsu
Setup
time
Data
before LE↓
CLK high
ns
CLK low
CLKEN before CLK↑
Data after CLK↑
th
Hold
time
Data
after LE↓
CLK high
ns
CLK low
CLKEN after CLK↑
2–132
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
fmax
MHz
A or B
tpd
ten
tdis
UNIT
MAX
B or A
LEAB or LEBA
ns
CLKAB or
CLKBA
A or B
OEAB or OEBA
A or B
ns
OEAB or OEBA
A or B
ns
operating characteristics, TA = 25°C
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
2–133
PRODUCT PREVIEW
PARAMETER
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–134
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–135
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–136
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES162F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Input
VCC/2
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–137
PRODUCT PREVIEW
Timing
Input
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 16-bit bus transceiver and register is operational at 1.2-V to 3.6-V VCC, but is designed specifically for
1.65-V to 3.6-V VCC operation.
The SN74AVC16646 can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus
is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.
Figure 2 illustrates the four fundamental bus-management functions that can be performed with the
SN74AVC16646.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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2–139
PRODUCT PREVIEW
description
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the
transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the
isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16646 is characterized for operation from –40°C to 85°C.
terminal assignments
PRODUCT PREVIEW
DGG OR DGV PACKAGE
(TOP VIEW)
1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
2–140
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
POST OFFICE BOX 655303
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
• DALLAS, TEXAS 75265
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each 8-bit transceiver/register)
DATA I/Os
INPUTS
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
X
X
↑
X
X
X
Input
Unspecified†
Input
OPERATION OR FUNCTION
Store A, B unspecified†
Store B, A unspecified†
X
X
X
↑
X
X
Unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
PRODUCT PREVIEW
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
† The data-output functions may be enabled or disabled by various signals at OE and DIR. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–141
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
PRODUCT PREVIEW
OE
L
DIR
L
CLKAB CLKBA
X
X
SAB
X
BUS B
BUS A
BUS A
BUS B
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
SBA
L
OE
L
DIR
H
DIR
X
X
X
CLKAB CLKBA
X
↑
X
↑
↑
↑
SAB
X
X
X
SBA
X
X
X
OE
L
L
SBA
X
BUS B
DIR
L
H
CLKAB
X
H or L
CLKBA
H or L
X
SAB
X
H
TRANSFER STORED DATA
TO A AND/OR B
STORAGE FROM
A, B, OR A AND B
Figure 2. Bus-Management Functions
2–142
SAB
L
BUS A
BUS A
OE
X
X
H
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
CLKAB
X
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SBA
H
X
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
logic symbol†
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
1A1
56
1
55
54
2
3
29
28
30
31
27
26
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
C13
G14
≥1
5
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
7
1
2A3
2A4
2A5
2A6
2A7
2A8
≥1
7
51
49
9
48
10
47
12
45
13
44
14
43
15
16
1B1
2
8
≥1
8
12 11D
42
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
12 1
13D 14
2A2
52
5 1
6D
6
4D
5
PRODUCT PREVIEW
1OE
1 14
≥1
9
41
17
40
19
38
20
37
21
36
23
34
24
33
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–143
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
logic diagram (positive logic)
56
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
1
55
54
2
3
One of Eight Channels
1D
C1
PRODUCT PREVIEW
1A1
5
52
1B1
1D
C1
2OE
To Seven Other Channels
29
28
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
30
31
27
26
One of Eight Channels
1D
C1
2A1
15
42
1D
C1
To Seven Other Channels
2–144
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2B1
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–145
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output when the output
is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any input/output when the output
is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
PRODUCT PREVIEW
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2–146
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ‡
ICC
VCC
1.4 V to 3.6 V
MIN
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
UNIT
V
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
MAX
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±12.5
µA
3.6 V
40
µA
Ci
Control inputs
VI = VCC or GND
Cio
A or B ports
VO = VCC or GND
IO = 0
2.5 V
pF
3.3 V
2.5 V
pF
3.3 V
† Typical values are measured at TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 3 through 6)
VCC = 1.2 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fclock
Clock frequency
MHz
tw
Pulse
duration
CLKAB or CLKBA
high or low
ns
tsu
Setup
time
A before CLKAB↑ or
B before CLKBA↑
ns
th
Hold
time
A after CLKAB↑ or
B after CLKBA↑
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–147
PRODUCT PREVIEW
PARAMETER
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 3 through 6)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
fmax
tpd
UNIT
MAX
MHz
A or B
B or A
CLKAB or
CLKBA
A or B
ns
SAB or SBA
ten
OE
A or B
ns
tdis
OE
A or B
ns
ten
DIR
A or B
ns
DIR
A or B
ns
tdis
PRODUCT PREVIEW
operating characteristics, TA = 25°C
PARAMETER
Cpd
2–148
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–149
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–151
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181E – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
VCC/2
0V
0V
tsu
PRODUCT PREVIEW
Input
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
tPLZ
VCC
VCC/2
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VOL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 6. Load Circuit and Voltage Waveforms
2–152
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 20-bit flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC
operation.
The 20 flip-flops of the AVC16721 are edge-triggered D-type flip-flops with clock-enable (CLKEN) input. On the
positive transition of the clock (CLK) input, the device provides true data at the Q outputs if CLKEN is low. If
CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or the
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and increased drive provide the capability to drive bus lines without need for interface
or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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2–153
PRODUCT PREVIEW
description
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16721 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
OE
Q1
Q2
GND
Q3
Q4
VCC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
VCC
Q17
Q18
GND
Q19
Q20
NC
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLK
D1
D2
GND
D3
D4
VCC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
D18
GND
D19
D20
CLKEN
NC – No internal connection
2–154
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLKEN
CLK
D
OUTPUT
Q
L
H
X
X
Q0
L
L
↑
H
H
L
L
↑
L
L
L
L
L or H
X
Q0
H
X
X
X
Z
logic diagram (positive logic)
1
OE
56
CLK
CE
C1
55
D1
1D
2
Q1
To 19 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
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2–155
PRODUCT PREVIEW
29
CLKEN
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
PRODUCT PREVIEW
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2–156
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ
ICC
VCC
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
MAX
UNIT
V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
2.5 V
3.3 V
VI = VCC or GND
pF
2.5 V
Data inputs
Co
TYP†
1.4 V to 3.6 V
Control inputs
Ci
MIN
3.3 V
Outputs
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
tw
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
Clock frequency
MHz
Pulse duration, CLK high or low
tsu
Setup time
th
Hold time
UNIT
MAX
ns
Data before CLK↑
ns
CLKEN before CLK↑
Data after CLK↑
ns
CLKEN after CLK↑
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fmax
tpd
MHz
CLK
Q
ns
ten
OE
Q
ns
tdis
OE
Q
ns
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2–157
PRODUCT PREVIEW
PARAMETER
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CLK
Q
tpd
† Texas Instruments SPICE simulation data
VCC = 3.3 V
± 0.15 V
MIN
UNIT
MAX
ns
operating characteristics, TA = 25°C
PARAMETER
Power dissipation
capacitance
Outputs enabled
Outputs disabled
CL = 0,
VCC = 1.8 V
TYP
f = 10 MHz
PRODUCT PREVIEW
Cpd
TEST CONDITIONS
2–158
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–159
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–160
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–161
PRODUCT PREVIEW
Timing
Input
SN74AVC16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES164F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
Input
VCC/2
0V
VCC/2
0V
tsu
PRODUCT PREVIEW
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
VOL
VCC/2
VCC
VCC/2
tPZH
tPHL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–162
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Packaged in Thin Shrink Small-Outline
Package
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 22-bit flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC
operation.
The 22 flip-flops of the SN74AVC16722 are edge-triggered D-type flip-flops with clock-enable (CLKEN) input.
On the positive transition of the clock (CLK) input, the device stores data into the flip-flops if CLKEN is low. If
CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the 22 outputs in either a normal logic state (high or low) or the
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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2–163
PRODUCT PREVIEW
description
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16722 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
OE
Q1
Q2
GND
Q3
Q4
VCC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
VCC
Q17
Q18
GND
Q19
Q20
VCC
Q21
Q22
GND
NC
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
CLK
D1
D2
GND
D3
D4
VCC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
D18
GND
D19
D20
VCC
D21
D22
GND
CLKEN
NC – No internal connection
2–164
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLKEN
CLK
D
OUTPUT
Q
L
H
X
X
Q0
L
L
↑
H
H
L
L
↑
L
L
L
L
L or H
X
Q0
H
X
X
X
Z
logic diagram (positive logic)
1
OE
64
CLK
CE
C1
63
D1
1D
2
Q1
To 21 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
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2–165
PRODUCT PREVIEW
33
CLKEN
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
PRODUCT PREVIEW
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2–166
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ
ICC
VCC
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
MAX
UNIT
V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
2.5 V
3.3 V
VI = VCC or GND
pF
2.5 V
Data inputs
Co
TYP†
1.4 V to 3.6 V
Control inputs
Ci
MIN
3.3 V
Outputs
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
tw
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
Clock frequency
MHz
Pulse duration, CLK high or low
tsu
Setup time
th
Hold time
UNIT
MAX
ns
Data before CLK↑
ns
CLKEN before CLK↑
Data after CLK↑
ns
CLKEN after CLK↑
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fmax
tpd
MHz
CLK
Q
ns
ten
OE
Q
ns
tdis
OE
Q
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–167
PRODUCT PREVIEW
PARAMETER
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CLK
Q
tpd
† Texas Instruments SPICE simulation data
VCC = 3.3 V
± 0.15 V
MIN
UNIT
MAX
ns
operating characteristics, TA = 25°C
PARAMETER
Power dissipation
capacitance
Outputs enabled
Outputs disabled
CL = 0,
VCC = 1.8 V
TYP
f = 10 MHz
PRODUCT PREVIEW
Cpd
TEST CONDITIONS
2–168
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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2–169
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–170
POST OFFICE BOX 655303
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SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–171
PRODUCT PREVIEW
Timing
Input
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
Input
VCC/2
0V
VCC/2
0V
tsu
PRODUCT PREVIEW
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
VOL
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–172
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 10-bit flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC
operation.
The flip-flops of the SN74AVC16820 are edge-triggered D-type flip-flops. On the positive transition of the clock
(CLK) input, the device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high
or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be
entered while the outputs are in the high-impedance state.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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2–173
PRODUCT PREVIEW
description
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16820 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
1OE
1Q1
1Q2
GND
2Q1
2Q2
VCC
3Q1
3Q2
4Q1
GND
4Q2
5Q1
5Q2
6Q1
6Q2
7Q1
GND
7Q2
8Q1
8Q2
VCC
9Q1
9Q2
GND
10Q1
10Q2
2OE
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLK
D1
NC
GND
D2
NC
VCC
D3
NC
D4
GND
NC
D5
NC
D6
NC
D7
GND
NC
D8
NC
VCC
D9
NC
GND
D10
NC
NC
NC – No internal connection
2–174
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each flip-flop)
INPUTS
OEn†
L
CLK
D
OUTPUT
Qn†
↑
H
H
L
↑
L
L
L
L
X
Q0
H
† n = 1, 2
X
X
Z
logic diagram (positive logic)
1
1OE
28
2OE
C1
D1
55
1Q1
3
1Q2
1D
To Nine Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
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2–175
PRODUCT PREVIEW
2
56
CLK
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
PRODUCT PREVIEW
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2–176
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
II
Ioff
Control inputs
IOZ
ICC
1.65 V
1.2
2.3 V
1.75
3V
2.3
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
MAX
UNIT
V
1.4 V to 3.6 V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
2.5 V
3.3 V
VI = VCC or GND
pF
2.5 V
Data inputs
Co
TYP†
VCC–0.2
1.05
Control inputs
Ci
MIN
1.4 V
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
VCC
1.4 V to 3.6 V
3.3 V
Outputs
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
MHz
Pulse duration, CLK high or low
ns
tsu
th
Setup time, data before CLK↑
ns
Hold time, data after CLK↑
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
ns
ten
OE
Q
ns
tdis
OE
Q
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
MHz
POST OFFICE BOX 655303
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2–177
PRODUCT PREVIEW
PARAMETER
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CLK
Q
tpd
† Texas Instruments SPICE simulation data
VCC = 3.3 V
± 0.15 V
MIN
UNIT
MAX
ns
operating characteristics, TA = 25°C
PARAMETER
Power dissipation
capacitance
Outputs enabled
Outputs disabled
CL = 0,
VCC = 1.8 V
TYP
f = 10 MHz
PRODUCT PREVIEW
Cpd
TEST CONDITIONS
2–178
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–179
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–180
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC
VCC/2
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–181
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16820
10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
SCES173F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–182
POST OFFICE BOX 655303
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SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 20-bit bus-interface flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
The SN74AVC16821 can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20 flip-flops are
edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data
at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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2–183
PRODUCT PREVIEW
description
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16821 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2CLK
FUNCTION TABLE
(each 10-bit flip-flop)
INPUTS
2–184
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
logic symbol†
1CLK
2OE
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1D10
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2D10
1
EN2
56
28
C1
EN4
29
C3
55
1D
2
2
54
3
52
5
51
6
49
8
48
9
47
10
45
12
44
13
43
14
42
15
3D
4
41
16
40
17
38
19
37
20
36
21
34
23
33
24
31
26
30
27
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
PRODUCT PREVIEW
1OE
1Q10
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2Q10
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–185
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
logic diagram (positive logic)
1
1OE
56
1CLK
One of Ten
Channels
C1
55
1D1
2
1D
1Q1
To Nine Other Channels
PRODUCT PREVIEW
28
2OE
29
2CLK
One of Ten
Channels
C1
42
2D1
1D
To Nine Other Channels
2–186
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
2Q1
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–187
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
PRODUCT PREVIEW
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2–188
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ
ICC
VCC
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
MAX
UNIT
V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
2.5 V
3.3 V
VI = VCC or GND
pF
2.5 V
Data inputs
Co
TYP†
1.4 V to 3.6 V
Control inputs
Ci
MIN
3.3 V
Outputs
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
MHz
Pulse duration, CLK high or low
ns
tsu
th
Setup time, data before CLK↑
ns
Hold time, data after CLK↑
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
ns
ten
OE
Q
ns
tdis
OE
Q
ns
PARAMETER
MIN
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
MHz
POST OFFICE BOX 655303
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2–189
PRODUCT PREVIEW
PARAMETER
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CLK
Q
tpd
† Texas Instruments SPICE simulation data
VCC = 3.3 V
± 0.15 V
MIN
UNIT
MAX
ns
operating characteristics, TA = 25°C
PARAMETER
Power dissipation
capacitance
Outputs enabled
Outputs disabled
CL = 0,
VCC = 1.8 V
TYP
f = 10 MHz
PRODUCT PREVIEW
Cpd
TEST CONDITIONS
2–190
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–191
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–192
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–193
PRODUCT PREVIEW
Timing
Input
SN74AVC16821
20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES175F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Less Than 2-ns Maximum Propagation
Delay at 2.5-V and 3.3-V VCC
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 20-bit non-inverting buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V
to 3.6-V VCC operation.
The SN74AVC16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit
buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the
corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section
are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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2–195
PRODUCT PREVIEW
description
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
The SN74AVC16827 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
1OE1
1Y1
1Y2
GND
1Y3
1Y4
VCC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GND
2Y4
2Y5
2Y6
VCC
2Y7
2Y8
GND
2Y9
2Y10
2OE1
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
2A10
2OE2
FUNCTION TABLE
(each 10-bit buffer/driver)
INPUTS
2–196
A
OUTPUT
Y
OE1
OE2
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
logic symbol†
1OE2
2OE1
2OE2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1
&
1OE1
56
28
1OE2
EN2
1A1
&
29
55
EN1
1
1
2
54
3
52
5
51
6
49
8
48
9
47
10
45
12
44
13
43
14
42
15
1
2
41
16
40
17
38
19
37
20
36
21
34
23
33
24
31
26
30
27
1
56
55
2
1Y1
1Y1
To Nine Other Channels
1Y2
1Y3
1Y4
28
2OE1
29
2OE2
1Y5
1Y6
1Y7
2A1
42
15
2Y1
1Y8
PRODUCT PREVIEW
1OE1
logic diagram (positive logic)
1Y9
To Nine Other Channels
1Y10
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
2Y9
2Y10
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–197
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–198
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–199
PRODUCT PREVIEW
VCC
MIN
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
PRODUCT PREVIEW
II
Ioff
Control inputs
IOZ
ICC
VCC
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
MAX
UNIT
V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
2.5 V
3.3 V
VI = VCC or GND
pF
2.5 V
Data inputs
Co
TYP†
1.4 V to 3.6 V
Control inputs
Ci
MIN
3.3 V
Outputs
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ns
ten
OE
Y
ns
tdis
OE
Y
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
switching characteristics, TA = 0°C to 85°C, CL = 0 pF‡
PARAMETER
tpd
‡ Texas Instruments SPICE simulation data
2–200
FROM
(INPUT)
TO
(OUTPUT)
A
Y
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 3.3 V
± 0.15 V
MIN
UNIT
MAX
ns
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Power dissipation
capacitance
Cpd
Outputs disabled
CL = 0,
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
TYP
f = 10 MHz
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–201
PRODUCT PREVIEW
2 kΩ
From Output
Under Test
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
2–202
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC
VCC/2
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–203
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
PRODUCT PREVIEW
Input
VCC/2
0V
VCC/2
0V
tsu
Data
Input
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
VCC/2
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VCC/2
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2–204
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Packaged in Thin Very Small-Outline
Package
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 9-bit 1-to-4 address register/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for
1.65-V to 3.6-V VCC operation.
The device is ideal for use in applications in which a single address bus is driving four separate memory
locations. The SN74AVC16831 can be used as a buffer or a register, depending on the logic level of the select
(SEL) input.
When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by
the two output-enable (OE) controls. Each OE controls two groups of nine outputs.
When SEL is logic low, the device is in the register mode. The register is an edge-triggered D-type flip-flop. On
the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers. OE
controls operate the same as in buffer mode.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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2–205
PRODUCT PREVIEW
description
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
When OE is logic low, the outputs are in a normal logic state (high or low logic level). When OE is logic high,
the outputs are in the high-impedance state.
SEL and OE do not affect the internal operation of the flip-flops. Old data can be retained or new data can be
entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
PRODUCT PREVIEW
The SN74AVC16831 is characterized for operation from –40°C to 85°C.
2–206
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
terminal assignments
DBB PACKAGE
(TOP VIEW)
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
39
42
40
41
1Y2
2Y2
GND
3Y2
4Y2
VCC
1Y3
2Y3
GND
3Y3
4Y3
GND
1Y4
2Y4
VCC
3Y4
4Y4
GND
1Y5
2Y5
3Y5
4Y5
GND
1Y6
2Y6
VCC
3Y6
4Y6
GND
1Y7
2Y7
GND
3Y7
4Y7
VCC
1Y8
2Y8
GND
3Y8
4Y8
PRODUCT PREVIEW
4Y1
3Y1
GND
2Y1
1Y1
VCC
NC
A1
GND
NC
A2
GND
NC
A3
VCC
NC
A4
GND
CLK
OE1
OE2
SEL
GND
A5
A6
VCC
A7
NC
GND
A8
NC
GND
A9
NC
VCC
4Y9
3Y9
GND
2Y9
1Y9
NC – No internal connection
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–207
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
INPUTS
SEL
CLK
A
OUTPUT
Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
OE
logic diagram (positive logic)
OE1
OE2
20
5
4
PRODUCT PREVIEW
CLK
19
A1
2Y1
CLK
2
8
D
3Y1
Q
1
SEL
1Y1
21
4Y1
22
To Eight Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–208
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–209
PRODUCT PREVIEW
VCC
MIN
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
PRODUCT PREVIEW
II
Ioff
Control inputs
IOZ
ICC
1.65 V
1.2
2.3 V
1.75
3V
2.3
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
MAX
UNIT
V
1.4 V to 3.6 V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
2.5 V
3.3 V
VI = VCC or GND
pF
2.5 V
Data inputs
Co
TYP†
VCC–0.2
1.05
Control inputs
Ci
MIN
1.4 V
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
VCC
1.4 V to 3.6 V
3.3 V
Outputs
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
MHz
Pulse duration, CLK high or low
ns
tsu
th
Setup time, A data before CLK↑
ns
Hold time, A data after CLK↑
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
fmax
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
MHz
A
tpd
CLK
Y
ns
SEL
ten
OE
Y
ns
tdis
OE
Y
ns
2–210
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
FROM
(INPUT)
PARAMETER
VCC = 3.3 V
± 0.15 V
TO
(OUTPUT)
MIN
UNIT
MAX
A
tpd
Y
CLK
ns
† Texas Instruments SPICE simulation data
operating characteristics, TA = 25°C
PARAMETER
Power dissipation
capacitance
Outputs enabled
Outputs disabled
CL = 0,
VCC = 1.8 V
TYP
f = 10 MHz
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
PRODUCT PREVIEW
Cpd
TEST CONDITIONS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–211
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–212
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VOH
VCC/2
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–213
PRODUCT PREVIEW
Timing
Input
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–214
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Input
VCC/2
0V
VCC/2
0V
tsu
th
VCC
Data
Input
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
VOL
VCC/2
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VCC/2
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–215
PRODUCT PREVIEW
Timing
Input
VCC/2
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D Ioff Supports Partial-Power-Down Mode
D
D
D
D
Operation
Ideal for Use in PC133 Registered DIMM
Applications
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 18-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low
logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE
is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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2–217
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16834 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
NC – No internal connection
2–218
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each universal bus driver)
INPUTS
OE
LE
CLK
A
OUTPUT
Y
H
X
X
X
Z
L
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
L
H
H
X
Y0†
Y0‡
L
H
L
X
† Output level before the indicated steady-state
input conditions were established, provided
that CLK is high before LE goes high
‡ Output level before the indicated steady-state
input conditions were established
logic symbol§
OE
CLK
27
EN1
30
2C3
28
LE
C3
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
3
1
5
1
3D
54
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
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2–219
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
logic diagram (positive logic)
OE
CLK
LE
A1
27
30
28
54
1D
C1
3
Y1
CLK
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–220
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ
ICC
CLK input
Ci
Co
VCC
1.4 V to 3.6 V
MIN
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
UNIT
V
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
MAX
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
VI = VCC or GND
Control inputs
VI = VCC or GND
Data inputs
VI = VCC or GND
Outputs
VO = VCC or GND
2.5 V
4
3.3 V
4
2.5 V
4
3.3 V
4
2.5 V
2.5
3.3 V
2.5
2.5 V
6.5
3.3 V
6.5
pF
pF
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
Pulse
duration
tsu
Setup
time
MAX
MIN
Hold
time
MAX
VCC = 2.5 V
± 0.2 V
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
0.7
0.7
0.7
1
0.9
CLK high
1.6
1.5
1
1
1
CLK low
3.1
1.7
1.3
1
1
Data after CLK↑
1.5
1.3
1
0.9
0.9
Data
after LE↑
CLK high
2.5
2
1.8
1.5
1.4
Data
after LE↑
CLK low
2
1.7
1.5
1.3
1.3
Data
before LE↑
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
150
LE low
Data before CLK↑
2–222
MIN
VCC = 1.8 V
± 0.15 V
Clock frequency
tw
th
MAX
VCC = 1.5 V
± 0.1 V
MHz
ns
ns
ns
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
fmax
VCC = 2.5 V
± 0.2 V
MAX
150
A
tpd
LE
MAX
150
MIN
UNIT
MAX
150
MHz
5.3
1.2
6.2
1.5
4.9
1
3.2
0.9
7
2.2
9.7
1.8
7.5
1.5
4.9
0.8
4
6
1.9
7.8
1.6
6
1.1
3.7
1
3.1
Y
CLK
ten
tdis
MIN
VCC = 3.3 V
± 0.3 V
2.5
ns
OE
Y
7.9
2.4
10.2
1.6
8.8
1.5
6.7
1
6.2
ns
OE
Y
7.7
2.1
10.3
1.5
8.4
1.2
5.3
1
5.3
ns
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
FROM
(INPUT)
PARAMETER
A
tpd
VCC = 3.3 V
± 0.15 V
TO
(OUTPUT)
Y
CLK
MIN
MAX
0.6
1.3
0.7
1.5
UNIT
ns
† Texas Instruments SPICE simulation data
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
45
48
52
23
25
28
UNIT
pF
2–223
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–224
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VOH
VCC/2
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–225
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–226
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
Input
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
VOL
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–227
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D Ioff Supports Partial-Power-Down Mode
D
D
D
D
Operation
Ideal for Use in PC133 Registered DIMM
Applications
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to TI application reports AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 18-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low
logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE
is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–229
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16835 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
NC – No internal connection
2–230
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each universal bus driver)
INPUTS
OE
LE
CLK
A
OUTPUT
Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
Y0†
† Output level before the indicated steady-state
input conditions were established, provided
that CLK is high before LE goes low
L
L
L or H
X
logic symbol‡
OE
CLK
LE
27
EN1
30
2C3
28
C3
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
3
1
1
3D
54
5
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–231
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
logic diagram (positive logic)
OE
CLK
LE
A1
27
30
28
54
1D
C1
3
Y1
CLK
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–232
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to TI application reports AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic
Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–233
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA,
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ
ICC
Ci
Co
MIN
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
VI = VCC or GND
VI or VO = 3.6 V
VI = VCC or GND
Data inputs
VI = VCC or GND
Outputs
VO = VCC or GND
UNIT
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
3.6 V
±2.5
µA
0
±10
µA
OE = VCC
3.6 V
±10
µA
IO = 0
3.6 V
40
µA
VI = VCC or GND
Control inputs
MAX
V
1.4 V to 3.6 V
VO = VCC or GND,
VI = VCC or GND,
CLK input
VCC
1.4 V to 3.6 V
2.5 V
4
3.3 V
4
2.5 V
4
3.3 V
4
2.5 V
2.5
3.3 V
2.5
2.5 V
6.5
3.3 V
6.5
pF
pF
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
Pulse
duration
tsu
Setup
time
MAX
MIN
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
3.3
3.3
CLK high or low
3.3
3.3
3.3
Data
before LE↓
1
0.9
0.7
0.7
0.7
1.7
1.6
1.2
0.8
0.8
2
0.9
0.7
0.5
0.5
1.5
1.3
1
0.9
1.3
CLK high
3.2
2.4
2
1.7
1.6
CLK low
2.8
2.1
1.7
1.5
1.4
CLK high
CLK low
Data
after LE↓
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
150
3.3
Data after CLK↑
Hold
time
MAX
VCC = 2.5 V
± 0.2 V
LE high
Data before CLK↑
2–234
MIN
VCC = 1.8 V
± 0.15 V
Clock frequency
tw
th
MAX
VCC = 1.5 V
± 0.1 V
MHz
ns
ns
ns
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
fmax
VCC = 2.5 V
± 0.2 V
MAX
150
A
tpd
LE
Y
CLK
ten
tdis
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
4.5
1.2
6.2
1.3
5.5
1
3.1
0.9
2.5
6.2
1.6
9.4
1.3
7.2
1.1
4.7
0.9
3.8
5.2
1.6
7.8
1.5
6
1
3.7
0.8
3.1
ns
OE
Y
7.1
2.4
10.2
2.2
8.8
1.5
6.7
1.2
6.2
ns
OE
Y
6.9
2.2
10.3
2
8.4
1.2
5.3
1.1
5.3
ns
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
FROM
(INPUT)
PARAMETER
A
tpd
VCC = 3.3 V
± 0.15 V
TO
(OUTPUT)
Y
CLK
MIN
MAX
0.6
1.3
0.7
1.5
UNIT
ns
† Texas Instruments SPICE simulation data
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
45
48
52
23
25
28
UNIT
pF
2–235
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–236
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VOH
VCC/2
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–237
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–238
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168H – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
Input
VCC/2
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VCC/2
tPLZ
VCC
VCC/2
VOL + 0.3 V
VOL
tPZH
tPHL
VOH
Output
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–239
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D Overvoltage-Tolerant Inputs/Outputs Allow
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
D
D
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Ideal for Use in PC133 Registered DIMM
Applications
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 20-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition
of CLK. When OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–241
PRODUCT PREVIEW
description
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
The SN74AVC16836 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
Y7
GND
Y8
Y9
Y10
Y11
Y12
Y13
GND
Y14
Y15
Y16
VCC
Y17
Y18
GND
Y19
Y20
NC
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLK
A1
A2
GND
A3
A4
VCC
A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
GND
A14
A15
A16
VCC
A17
A18
GND
A19
A20
LE
NC – No internal connection
FUNCTION TABLE
(each universal bus driver)
INPUTS
CLK
A
OUTPUT
Y
X
X
X
Z
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
OE
LE
H
L
Y0†
† Output level before the indicated steady-state
input conditions were established
L
2–242
H
L or H
POST OFFICE BOX 655303
X
• DALLAS, TEXAS 75265
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
logic symbol†
OE
CLK
LE
1
EN1
56
29
2C3
C3
G2
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
2
1
1
3D
55
3
54
5
52
6
51
1
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
27
30
A1
A2
A3
A4
A5
A6
A7
A8
A9
PRODUCT PREVIEW
Y1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
56
CLK
LE
29
55
A1
1D
C1
2
Y1
CLK
To 19 Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–243
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
PRODUCT PREVIEW
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
2–244
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and
VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
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2–245
PRODUCT PREVIEW
VCC
MIN
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
PRODUCT PREVIEW
II
Ioff
Control inputs
IOZ
ICC
VCC
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
UNIT
V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
IO = 0
2.5 V
3.3 V
VI = VCC or GND
Outputs
1.4 V
MAX
VI = VCC or GND
VI or VO = 3.6 V
pF
2.5 V
Data inputs
Co
TYP†
1.4 V to 3.6 V
Control inputs
Ci
MIN
3.3 V
2.5 V
VO = VCC or GND
pF
3.3 V
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
Clock frequency
tw
Pulse
duration
tsu
Setup
time
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
MHz
LE low
ns
CLK high or low
Data before CLK↑
th
2–246
Hold
time
Data
before LE↑
ns
CLK high
CLK low
Data after CLK↑
Data
after LE↑
ns
CLK high
or low
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
VCC = 2.5 V
± 0.2 V
MAX
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fmax
MHz
A
tpd
Y
ns
OE
Y
ns
OE
Y
ns
LE
CLK
ten
tdis
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
A
tpd
VCC = 3.3 V
± 0.15 V
TO
(OUTPUT)
MIN
Y
CLK
UNIT
MAX
ns
† Texas Instruments SPICE simulation data
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
2–247
PRODUCT PREVIEW
FROM
(INPUT)
PARAMETER
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
2–248
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VOH
VCC/2
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–249
PRODUCT PREVIEW
Timing
Input
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
2–250
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES170F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
Input
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
VOL
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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2–251
PRODUCT PREVIEW
VCC
Timing
Input
VCC/2
General Information
Widebus
Widebus+
Application Reports
Mechanical Data
3–1
Contents
Widebus+
3–2
SN74AVC32245
Page
32-Bit Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
SN74AVC32501
36-Bit Universal Bus Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . 3–13
SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191D – MARCH 1999 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D Dynamic Drive Capability Is Equivalent to
Widebus  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Packaged in Plastic Fine-Pitch Ball Grid
Array Package
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 32-bit (dual-octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed
specifically for 1.65-V to 3.6-V VCC operation.
The SN74AVC32245 is designed for asynchronous communication between data buses. The control-function
implementation minimizes external timing requirements.
This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows
data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at
the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the
buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–3
PRODUCT PREVIEW
description
SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191D – MARCH 1999 – REVISED FEBRUARY 2000
description (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC32245 is characterized for operation from –40°C to 85°C.
GKE PACKAGE
(TOP VIEW)
6
5
4
3
2
1
PRODUCT PREVIEW
A B
C D E F
G H J
K
L M N P
R T
terminal assignments
6
1A2
1A4
1A6
1A8
2A2
2A4
2A6
2A7
3A2
3A4
3A6
3A8
4A2
4A4
4A6
4A7
5
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A8
3A1
3A3
3A5
3A7
4A1
4A3
4A5
4A8
4
1OE
GND
GND
2OE
3OE
GND
GND
4OE
GND
GND
2DIR
3DIR
GND
GND
GND
VCC
VCC
GND
GND
VCC
VCC
GND
GND
VCC
VCC
GND
1DIR
VCC
VCC
GND
3
GND
4DIR
2
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B8
3B1
3B3
3B5
3B7
4B1
4B3
4B5
4B8
1
1B2
1B4
1B6
1B8
2B2
2B4
2B6
2B7
3B2
3B4
3B6
3B8
4B2
4B4
4B6
4B7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
FUNCTION TABLE
(each 8-bit transceiver)
INPUTS
3–4
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191D – MARCH 1999 – REVISED FEBRUARY 2000
logic diagram (positive logic)
A3
2DIR
A4
1A1
H4
1OE
A5
2A1
A2
H3
E5
E2
1B1
To Seven Other Channels
3DIR
2B1
To Seven Other Channels
J3
4DIR
J4
3A1
2OE
T4
3OE
J5
4A1
J2
T3
4OE
N5
N2
3B1
To Seven Other Channels
4B1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–5
PRODUCT PREVIEW
1DIR
SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191D – MARCH 1999 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
PRODUCT PREVIEW
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191D – MARCH 1999 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
II
Ioff
Control inputs
IOZ‡
ICC
VCC
1.4 V to 3.6 V
MIN
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
UNIT
V
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
MAX
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±12.5
µA
3.6 V
40
µA
Ci
Control inputs
VI = VCC or GND
Cio
A or B ports
VO = VCC or GND
IO = 0
2.5 V
pF
3.3 V
2.5 V
pF
3.3 V
† Typical values are measured at TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ns
ten
OE
A or B
ns
tdis
OE
A or B
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
3–7
PRODUCT PREVIEW
PARAMETER
SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191D – MARCH 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
3–8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191D – MARCH 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–9
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191D – MARCH 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
3–10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191D – MARCH 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
From Output
Under Test
2 × VCC
S1
500 Ω
GND
CL = 30 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
500 Ω
tw
LOAD CIRCUIT
VCC
VCC
Input
VCC/2
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
tPLZ
VCC
VCC/2
VOL + 0.3 V
VOL
tPZH
tPHL
VOH
Output
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–11
PRODUCT PREVIEW
Timing
Input
VCC/2
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
D Member of the Texas Instruments
D
D
D
D Less Than 2-ns Maximum Propagation
Widebus+  Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
D
Delay at 2.5-V and 3.3-V VCC
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Packaged in Plastic Fine-Pitch Ball Grid
Array Package
A Dynamic Output Control (DOC) circuit is implemented that, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 36-bit universal bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V
to 3.6-V VCC operation.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the
outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
DOC, EPIC, UBT, and Widebus+ are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–13
PRODUCT PREVIEW
description
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC32501 is characterized for operation from –40°C to 85°C.
terminal assignments
GKF PACKAGE
(TOP VIEW)
1
A
PRODUCT PREVIEW
B
2
3
4
5
6
1
2
3
4
5
6
A
1A2
B
1A4
1A1
1LEAB
1CLKAB
1B1
1B2
1A3
1OEAB
1GND
1B3
C
1B4
1A6
1A5
1GND
1GND
1B5
1B6
1B7
1B8
1B9
1B10
D
1A8
1A7
C
E
1A10
1A9
1VCC
1GND
1VCC
1GND
D
E
F
1A12
1A11
1GND
1GND
1B11
1B12
G
1A14
1A13
1B14
H
1A15
1A16
1VCC
1GND
1B13
F
G
1VCC
1GND
1B16
1B15
J
1A17
1A18
1OEBA
1CLKBA
1B18
1B17
H
K
NC
2LEAB
1LEBA
1GND
2CLKAB
NC
J
K
L
2A2
2A1
2OEAB
2GND
2B1
2B2
M
2A4
2A3
2GND
2GND
2B3
2B4
N
2A6
2A5
2VCC
2GND
2B5
2B6
L
M
N
P
R
T
U
P
2A8
2A7
2VCC
2GND
2B7
2B8
R
2A10
2A9
2GND
2GND
2B9
2B10
T
2A12
2A11
2A13
2VCC
2GND
2B12
2A14
2VCC
2GND
2B11
U
2B13
2B14
V
2A15
2A16
2OEBA
2CLKBA
2B16
2B15
W
2A17
2A18
2LEBA
2GND
2B18
2B17
NC – No internal connection
V
W
3–14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
FUNCTION TABLE†
(each 18-bit universal bus transceiver)
INPUTS
OEAB
LEAB
CLKAB
A
OUTPUT
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
B0‡
† A-to-B data flow is shown. B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established, provided that CLKAB is
high before LEAB goes low
H
L
L or H
X
logic diagram (positive logic)
1CLKAB
1LEAB
1LEBA
1CLKBA
1OEBA
1A1
B3
PRODUCT PREVIEW
1OEAB
A4
A3
K3
J4
J3
A2
1D
C1
CLK
A5
1B1
1D
C1
CLK
To 17 Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–15
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
logic diagram (positive logic) (continued)
2OEAB
2CLKAB
2LEAB
2LEBA
2CLKBA
2OEBA
PRODUCT PREVIEW
2A1
L3
K5
K2
W3
V4
V3
L2
1D
C1
CLK
L5
2B1
1D
C1
CLK
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
3–16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
VIH
Supply voltage
High-level input voltage
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
Low-level input voltage
Output voltage
Static high-level output current†
IOLS
Static low-level output current†
∆t/∆v
Input transition rise or fall rate
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
12
VCC = 1.4 V to 3.6 V
5
4
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–17
PRODUCT PREVIEW
VCC
MIN
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
IOHS = –2 mA,
VOH
IOHS = –4 mA,
IOHS = –8 mA,
IOHS = –12 mA,
IOLS = 100 µA
VOL
PRODUCT PREVIEW
II
Ioff
Control inputs
IOZ‡
ICC
VCC
1.4 V to 3.6 V
VIH = 0.91 V
VIH = 1.07 V
VIH = 1.7 V
VIH = 2 V
MIN
TYP†
1.4 V
VCC–0.2
1.05
1.65 V
1.2
2.3 V
1.75
3V
2.3
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
UNIT
V
1.4 V to 3.6 V
IOLS = 2 mA,
IOLS = 4 mA,
MAX
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
VI = VCC or GND
VI or VO = 3.6 V
3.6 V
±2.5
µA
0
±10
µA
VO = VCC or GND
VI = VCC or GND,
3.6 V
±12.5
µA
3.6 V
40
µA
Ci
Control inputs
VI = VCC or GND
Cio
A or B ports
VO = VCC or GND
IO = 0
2.5 V
pF
3.3 V
2.5 V
pF
3.3 V
† Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
Clock frequency
tw
Pulse
duration
tsu
Setup
time
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
MHz
LE high
ns
CLK high or low
Data before CLK↑
Data
before LE↓
ns
CLK high
CLK low
Data after CLK↑
th
3–18
Hold time
Data
after LE↓
ns
CLK high
or low
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
fmax
MHz
A or B
tpd
UNIT
MAX
LE
CLK
B or A
ns
A or B
ten
tdis
OEAB
B
ns
OEAB
B
ns
ten
tdis
OEBA
A
ns
OEBA
A
ns
operating characteristics, TA = 25°C
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
pF
3–19
PRODUCT PREVIEW
PARAMETER
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
3–20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
tPLZ
VCC
VCC/2
tPZH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VOH
Output
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–21
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
PRODUCT PREVIEW
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
3–22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES272E – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
S1
500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Input
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–23
PRODUCT PREVIEW
Timing
Input
VCC/2
General Information
Widebus
Widebus+
Application Reports
Mechanical Data
4–1
Contents
Page
AVC Logic Family Technology and Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Dynamic Output Control (DOC) Circuitry Technology and Applications . . . . . . . . . . . . . . . . . 4–29
Implications of Slow or Floating CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53
Application Reports
4–2
AVC Logic Family
Technology and Applications
SCEA006A
August 1998
4–3
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time
of sale in accordance with TI’s standard warranty. Testing and other quality control techniques
are utilized to the extent TI deems necessary to support this warranty. Specific testing of all
parameters of each device is not necessarily performed, except those mandated by government
requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated
4–4
Contents
Title
Page
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
AVC Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unparalleled Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Novel Output Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mixed-Voltage Mode and Power Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7
4–8
4–8
4–9
Design Issues and AVC Family Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
Low Power (Optimized for 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
Unused and Undriven Inputs (Bus Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
Partial Power-Down and Mixed-Voltage-Mode Data Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Characteristics With DOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–12
4–12
4–13
4–15
4–18
4–20
4–21
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
Appendix A – Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
4–5
List of Illustrations
Figure
Title
Page
1
Low-Voltage Logic Family Performance Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
2
Impedance Changes Through Switching Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
3
Totem-Pole Input Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4
Typical Bus-Hold Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
5
Bus Hold Across VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
6
Device at 2.5-V VCC With 3.3-V I/Os on One Side and 2.5-V I/Os on the Other,
Showing Switching Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
7
Device at 1.8-V VCC With 2.5-V Inputs or 3.3-V Inputs, Showing Switching Levels . . . . . . . . . . . . . . . . . . 4–12
8
ICC vs Frequency With 1, 8, or 16 Outputs Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
9
ICC vs VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
10
VO vs VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
11
tPHL vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
12
tPLH vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
13
tPHL vs Load Capacitance, One Output Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16
14
tPLH vs Load Capacitance, One Output Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16
15
tPHL vs Load Capacitance, 16 Outputs Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
16
tPLH vs Load Capacitance, 16 Outputs Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
17
Simultaneous-Switching Voltage (VOLP, VOLV) vs Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
18
Simultaneous-Switching Voltage (VOHP, VOHV) vs Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
19
Slow Input-Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
20
Pin-to-Pin Skew (tPHL, tPLH) (<100 ps nominal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
21
VOL vs IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
22
VOH vs IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
A-1
AVC Parameter Measurement Information (1.8 V ± 0.15 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
A-2
AVC Parameter Measurement Information (VCC = 2.5 V ± 0.2 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
A-3
AVC Parameter Measurement Information (VCC = 3.3 V ± 0.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
List of Tables
Table
4–6
Title
Page
1
Cpd for Various Conditions, One Output Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
2
Selected AVC Family Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
Abstract
Texas Instruments (TI) announces the industry’s first logic family to achieve maximum propagation delays of less than 2 ns
at 2.5 V. TI’s next-generation logic is the Advanced Very-low-voltage CMOS (AVC) family. Although optimized for 2.5-V
systems, AVC logic supports mixed-voltage systems because it is compatible with 3.3-V and 1.8-V devices. The AVC family
features TI’s Dynamic Output Control (DOC) circuit (patent pending). The DOC circuit provides enough current to achieve
high signaling speeds, but automatically lowers the output impedance of the circuit during a signal transition and subsequently
increases the impedance to reduce the overshoot and undershoot noise that is often found in high-speed logic. This feature of
AVC logic eliminates the need for series damping resistors. AVC logic also has a power-off feature that disables outputs from
the device when no power is applied.
Introduction
Current trends in advanced digital electronics design continue to include lower power consumption, lower supply voltages,
faster operating speeds, smaller timing budgets, and heavier loads. Many designs are making the transition from 3.3 V to 2.5 V,
and bus speeds are increasing beyond 100 MHz. Encompassing all these goals makes the requirement of signal integrity more
difficult to achieve. For designs that require very-low-voltage logic and bus-interface functions, TI produces a new logic family
that designers of next-generation high-performance workstations, PCs, networking, and telecommunications equipment find
particularly useful.
AVC Family
TI’s next-generation logic family is AVC (see Figure 1). As part of TI’s Widebus and Widebus+ families, these devices
give designers an easy migration path to higher performance and lower voltages. Also offered in the AVC family are a broad
line of logic gates and octal bus-interface functions. The devices in TI’s AVC family are available in multiple JEDEC-standard
advanced packages to provide maximum flexibility in board layout and cost.
DOC, TI, Widebus, and Widebus+ are trademarks of Texas Instruments Incorporated.
4–7
64
LVT
ALVT
3.3 V
I OL – Drive Current – mA
2.5 V
24
ALB
ALVC
LVC
12
8
LV
AVC
5
10
15
20
Speed – Maximum tpd – ns
Figure 1. Low-Voltage Logic Family Performance Positioning
Unparalleled Performance
TI’s AVC family is the industry’s first logic family to achieve maximum propagation delays of less than 2 ns at 2.5 V. This
premier performance is achieved through a combination of advances. The family was designed for high performance,
incorporating several novel circuit structures and changes to conventional logic-circuit designs. TI’s advanced 0.5-micron
Enhanced-Performance Implanted CMOS (EPIC) fabrication process is used to produce the new devices.
Novel Output Structure
The AVC family features TI’s DOC circuit, which changes output impedance during switching (see Figure 2). The DOC circuit
allows a single device to have the desirable characteristics of reduced noise, similar to damping-resistor outputs during static
conditions, and high drive similar to a low-impedance output during dynamic conditions. The DOC circuit controls overshoots
and undershoots and limits noise, which are inherent in high-speed, high-current devices.
EPIC is a trademark of Texas Instruments Incorporated.
4–8
2.32
2.01
V O – Output Voltage – V
1.81
High Impedance
1.55
1.29
1.03
0.77
Low Impedance
0.52
0.25
0
High Impedance
20.7
21.4
22.1
22.8
23.5
24.2
24.9
25.6
26.3
Switching Time – ns
Figure 2. Impedance Changes Through Switching Transitions
Mixed-Voltage Mode and Power Off
The AVC family is optimized for low-power 2.5-V systems and effectively supports mixed-voltage systems because it is
compatible with 3.3-V and 1.8-V devices. AVC device inputs and outputs are 3.6-V tolerant at 2.5-V and 1.8-V VCC. This
provides a bidirectional data path between 3.3-V LVTTL and 2.5-V CMOS, and a one-way data path from 3.3-V LVTTL or
2.5-V CMOS to 1.8-V CMOS. AVC logic also has a power-off isolation feature that disables outputs from the device during
system partial power down.
Design Issues and AVC Family Solutions
Low Power (Optimized for 2.5 V)
Perhaps one of the most pervasive trends in advanced digital-electronics design is lower power consumption. Lower power
consumption is especially important to extend battery life of portable equipment. Reduced heat dissipation from lower power
consumption simplifies the measures necessary to remove heat and decrease the necessary packaging area, leading to
production of smaller and less expensive products. One of the most effective ways to reduce power dissipation is to decrease
integrated-circuit operating voltages. The AVC family, designed to operate at 2.5-V VCC, enables high-performance,
low-power, and advanced designs. Not simply a scaled-down 3.3-V family, AVC is the first logic family conceived and
designed for optimized performance at 2.5 V.
Unused and Undriven Inputs (Bus Hold)
A circuit element that must be addressed when designing with a CMOS family, such as AVC, is circuit inputs. With the
totem-pole structure (see Figure 3) that characterizes the inputs of CMOS devices, the input node must be held as close to the
VCC or GND rails as possible.
4–9
VCC
Qp
VI
Qn
Figure 3. Totem-Pole Input Structure
Precautions should be taken to prevent the input voltage from floating near the threshold voltage because this biases both input
transistors on and creates undesirably high ICC currents at the VCC pin of the device. Under certain conditions, this can damage
the device. One way to address this concern is to place external pullup resistors at any input that might be in a high-impedance,
undriven state. This is costly in terms of component count, reliability, and board area. An alternative solution is to employ the
devices in the AVC family that utilize the optional bus-hold circuit at the inputs (see Figure 4). AVC devices with bus-hold
circuitry are designated as AVCH.
Input
Inverter
Stage
I/O Pin
Bus-Hold
Input Cell
Figure 4. Typical Bus-Hold Cell
The bus-hold circuit consists of two series inverters with the output fed back to the input through a resistor. This provides a
weak positive feedback by sinking or sourcing current to the input node. The bus-hold cell holds the input at its last-known
valid logic state until forcibly changed by a driving circuit. Figure 5 shows the input characteristics of bus hold as the input
voltage is swept from 0 V to 2.5 V. These characteristics are similar to a weak bistable latch. The bus-hold cell sinks current
when the input is low, and sources current when the input is high. When the input voltage is near the threshold, the circuit sinks
or sources maximum current to force the input node toward either the VCC or GND rail.
4–10
VCC = 3.3 V
TJ = 40°C
Process = Nominal
0.15
VCC = 2.5 V
I I – Input Current – mA
0.10
VCC = 1.8 V
0.05
0
–0.05
–0.10
–0.15
–0.20
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VI – Input Voltage – V
Figure 5. Bus Hold Across VCC
Generally, pullup and pulldown resistors should not be used on the inputs of devices with bus hold. In applications that require
pullup or pulldown resistors to hold the inputs at a specific logic level, the II(hold) maximum specification should be considered.
The resistor value should be chosen to overcome bus hold under worst-case conditions. The resistor must supply enough
current so that the input is pulled through the threshold to the desired logic level. If the current supplied is too weak, the input
node could be held near the threshold, causing a high ICC that could damage the part.
Partial Power-Down and Mixed-Voltage-Mode Data Communication
The inputs and outputs of the AVC family have been designed with all reverse-current paths to VCC blocked. This low IOFF
current feature allows the device to remain electrically connected to a bus during partial power down without loading the
remaining live circuits. This feature also allows the use of this family in a mixed-voltage environment. If the inputs or outputs
are at a voltage greater than the VCC of the device, there is no current sourcing back through the device from the higher voltage
node to the lower-voltage VCC supply.
With a bidirectional AVC transceiver powered with 2.5-V VCC, two-way data communication between 3.3-V LVTTL devices
and 2.5-V CMOS devices can occur (see Figure 6). The inputs of the AVC part are 3.6-V tolerant and accept the LVTTL
switching levels. The outputs of the AVC part, when powered at 2.5-V VCC under worst-case conditions, are accepted as valid
switching levels at the input of a 3.3-V LVTTL device.
With a unidirectional AVC driver powered with 1.8-V VCC, data communication from 2.5-V or 3.3-V signal levels to 1.8-V
devices can occur (see Figure 7). The inputs of the AVC part are tolerant of the higher voltages and accept the higher switching
levels. The outputs of the AVC driver are valid 1.8-V signal levels.
4–11
2.5 V
VCC
3.3 V
VCC
2.4
2
1.5
VOH
VIH
Vt
0.8
VIL
0.7
Vt
VIL
0.4
0
VOL
GND
0.2
0
VOL
GND
VCC
VOH
VIH
2.5
2.3
1.7
3.3 V
AVC
2.5 V
1.2
Figure 6. Device at 2.5-V VCC With 3.3-V I/Os on One Side and 2.5-V I/Os on the Other,
Showing Switching Levels
1.8 V
VCC
3.3 V
VCC
2.4
2
1.5
VOH
VIH
Vt
0.8
VIL
0.7
Vt
VIL
0.4
0
VOL
GND
0.2
0
VOL
GND
2.5
2.3
1.7
1.2
VCC
VOH
VIH
2.5 V or 3.3 V
AVC
1.8 V
0.63
0.45
VCC
VOH
VIH
Vt
VIL
VOL
0
GND
1.8
1.35
1.17
0.9
Figure 7. Device at 1.8-V VCC With 2.5-V Inputs or 3.3-V Inputs, Showing Switching Levels
Device Characteristics
To facilitate a preliminary analysis of the characteristics of the AVC family, SPICE analysis graphs from TI’s initial
AVC-family device, the SN74AVC16245 16-bit bus transceiver with 3-state outputs are shown in Figures 8 through 22. These
analyses are the outputs of SPICE simulations using standard loads specified in the parameter measurement information
illustrations in Appendix A, unless otherwise noted.
Power Consumption
Figure 8 presents SPICE information about the device dynamic power consumption across the operating frequencies. Table 1
shows modeled values of power dissipation capacitance (Cpd). The Cpd data were obtained using an input edge rate of 1 ns
(0%–100%), open-circuit load on the output, and one output switching with a 48-pin TSSOP (DGG) package.
4–12
200
Process = Nominal
VCC = 2.5 V
TJ = 40°C
48-pin TSSOP (DGG) Package
180
I CC – Supply Current – mA
160
16 Outputs
Switching
140
120
8 Outputs
Switching
100
80
60
40
1 Output
Switching
20
29
48
67
86
105
124
143
162
181
Operating Frequency – MHz
Figure 8. ICC vs Frequency With 1, 8, or 16 Outputs Switching
Table 1. Cpd for Various Conditions, One Output Switching
PARAMETER
TEST CONDITIONS
CL = 0, f = 10 MHz
VCC = 1.8 V
± 0.15 V TYP
VCC = 2.5 V
± 0.2 V TYP
VCC = 3.3 V
± 0.3 V TYP
Cpd
Outputs enabled
15.9 pF
18.1 pF
21.1 pF
Cpd
Outputs disabled
∼1 pF
∼1 pF
∼1 pF
Input Characteristics
Figures 9 and 10 present SPICE information about the device static behavior. Figure 9 shows the device supply-current
requirements across input voltage and Figure 10 shows the output-voltage versus input-voltage transfer curves.
4–13
50
TJ = 40°C
Process = Nominal
45
40
I CC – Supply Current – mA
VCC = 3.3 V
35
30
25
20
15
VCC = 2.5 V
10
5
VCC = 1.8 V
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
2.4
2.7
3.0
VI – Input Voltage – V
Figure 9. ICC vs VI
3.2
TJ = 40°C
Process = Nominal
VCC = 3.3 V
2.8
V O – Output Voltage – V
2.4
VCC = 2.5 V
2.0
VCC = 1.8 V
1.6
1.2
0.8
0.4
0.3
0.6
0.9
1.2
1.5
1.8
VI – Input Voltage – V
Figure 10. VO vs VI
4–14
2.1
Switching Performance
Figures 11 through 16 present SPICE models of the device dynamic behavior. Propagation delay times across various
conditions of ambient temperature, load capacitance with one output switching, and load capacitance with 16 outputs switching
are shown.
1.28
1.26
t PHL – Propagation Delay Time – ns
VCC = 2.3 V
1.24
1.22
1.20
VCC = 2.5 V
1.18
1.16
1.14
VCC = 2.7 V
One Output Switching
Nominal Process
VCC = 2.5 V
RL = 500 Ω, CL = 30 pF
48-pin TSSOP (DGG) Package
1.12
1.10
–26
–12
2
16
30
44
TJ – Junction Temperature – °C
58
72
86
Figure 11. tPHL vs TJ
1.17
VCC = 2.3 V
t PLH – Propagation Delay Time – ns
1.14
1.11
1.08
VCC = 2.5 V
1.05
1.02
VCC = 2.7 V
One Output Switching
Nominal Process
VCC = 2.5 V
RL = 500 Ω, CL = 30 pF
48-pin TSSOP (DGG) Package
0.99
0.96
–26
–12
2
16
30
44
58
72
86
TJ – Junction Temperature – °C
Figure 12. tPLH vs TJ
4–15
t PHL – Propagation Delay Time – ns
2.4
2.2
Weak: VCC = 2.3 V, Weak Process, TJ = 100°C
Nominal: VCC = 2.5 V, Nominal Process, TJ = 40°C
Strong: VCC = 2.7 V, Strong Process, TJ = –40°C
RL = 500 Ω to GND
48-pin TSSOP (DGG) Package
2.0
1.8
Weak
1.6
Nominal
1.4
Strong
1.2
1.0
0.8
11
21
31
41
51
61
71
81
91
CL – Load Capacitance – pF
Figure 13. tPHL vs Load Capacitance, One Output Switching
t PLH – Propagation Delay Time – ns
3.0
2.7
Weak: VCC = 2.3 V, Weak Process, TJ = 100°C
Nominal: VCC = 2.5 V, Nominal Process, TJ = 40°C
Strong: VCC = 2.7 V, Strong Process, TJ = –40°C
RL = 500 Ω to GND
48-pin TSSOP (DGG) Package
2.4
2.1
Weak
1.8
1.5
Nominal
Strong
1.2
0.9
0.6
11
21
31
41
51
61
71
81
CL – Load Capacitance – pF
Figure 14. tPLH vs Load Capacitance, One Output Switching
4–16
91
t PHL – Propagation Delay Time – ns
2.6
2.4
2.2
Weak: VCC = 2.3 V, Weak Process, TJ = 100°C
Nominal: VCC = 2.5 V, Nominal Process, TJ = 40°C
Strong: VCC = 2.7 V, Strong Process, TJ = –40°C
RL = 500 Ω to GND
48-pin TSSOP (DGG) Package
2.0
Weak
1.8
Nominal
1.6
Strong
1.4
1.2
1.0
0.8
11
21
31
41
51
61
71
81
91
CL – Load Capacitance – pF
Figure 15. tPHL vs Load Capacitance, 16 Outputs Switching
t PLH – Propagation Delay Time – ns
3.2
2.8
Weak: VCC = 2.3 V, Weak Process, TJ = 100°C
Nominal: VCC = 2.5 V, Nominal Process, TJ = 40°C
Strong: VCC = 2.7 V, Strong Process, TJ = –40°C
RL = 500 Ω to GND
48-pin TSSOP (DGG) Package
2.4
Weak
2.0
Strong
Nominal
1.6
1.2
0.8
0.4
11
21
31
41
51
61
71
81
91
CL – Load Capacitance – pF
Figure 16. tPLH vs Load Capacitance, 16 Outputs Switching
4–17
Signal Integrity
Perhaps the most important measure of a device’s performance in the dynamic domain is the effect of varying conditions upon
signal integrity. Figures 17 through 20 show SPICE simulations of the device dynamic behavior. The effect of multiple outputs
switching simultaneously on one that is held at a valid logic level is shown (see Figures 17 and 18). The effects of slow
input-transition time (see Figure 19), and pin-to-pin skew (see Figure 20) are shown.
3.2
15 Outputs Switching
1 Quiet Low
Process = Nominal
TJ = 40°C
RL = 500 Ω
CL = 30 pF
VCC = 3.3 V
V O – Output Voltage – V
2.8
2.4
2.0
1.6
VCC = 2.5 V
1.2
0.8
VOLP at 2.5 V
VOLP at 3.3 V
VOLV Are Approximately Equal
0.4
0
41
42
43
44
45
46
47
48
49
Time – ns
Figure 17. Simultaneous-Switching Voltage (VOLP , VOLV) vs Time
3.2
VCC = 3.3 V
V O – Output Voltage – V
2.8
2.4
VCC = 2.5 V
2.0
1.6
1.2
15 Outputs Switching
1 Quiet High
Process = Nominal
TJ = 40°C
RL = 500 Ω
CL = 30 pF
0.8
0.4
0
19
20
21
22
23
24
25
26
27
28
29
Time – ns
Figure 18. Simultaneous-Switching Voltage (VOHP , VOHV) vs Time
4–18
2.4
VCC = 2.5 V
Process = Nominal
TJ = 40°C
RL = 500 Ω
CL = 30 pF
V O – Output Voltage – V
2.1
1.8
1.5
1.2
0.9
0.6
16 Outputs Switching
0.3
0
53
61
69
77
85
93
101
109
117
Time – ns
Figure 19. Slow Input-Transition Time
2.4
VCC = 2.5 V
Process = Nominal
TJ = 40°C
16 Outputs Switching
V O – Output Voltage – V
2.1
1.8
1.5
1.2
<100 ps Nominal
0.9
0.6
0.3
0
22
26
30
34
38
42
46
50
Time – ns
Figure 20. Pin-to-Pin Skew (tPHL, tPLH) (<100 ps nominal)
4–19
Output Characteristics With DOC
Selecting a component with improved output drive characteristics simplifies the design engineer’s job of ensuring signal
integrity and meeting timing requirements. For signal integrity, the output must have an output impedance that minimizes
overshoots and undershoots. A component with 26-Ω series damping resistors on the output ports was sometimes necessary
to improve the match of the impedance with the transmission-line load on the output of the buffer. The opposing characteristic
that must be considered is having sufficient drive to meet the timing requirements. The AVC family features TI’s DOC circuit
that automatically lowers the output impedance of the circuit during a signal transition and subsequently raises the impedance
to reduce overshoot and undershoot. Figures 21 and 22 contain typical voltage and current curves that illustrate the operation
of the circuit as it transitions from one state to another.
3.2
TJ = 40°C
Process = Nominal
V OL– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
VCC = 1.8 V
0.8
0.4
0
17
34
51
68
85
102
IOL – Output Current – mA
Figure 21. VOL vs IOL
4–20
119
136
153
170
2.8
TJ = 40°C
Process = Nominal
V OH – Output Voltage – V
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
–160
VCC = 1.8 V
–144
–128
–112
–96
–80
–64
–48
–32
–16
0
IOH – Output Current – mA
Figure 22. VOH vs IOH
The DOC circuitry provides enough drive current to achieve faster slew rates and meet timing requirements, but quickly
switches the impedance level to reduce the overshoot and undershoot noise that is often found in high-speed logic. This feature
of AVC logic eliminates the need for damping resistors in the output circuit, which are often used in series, and sometimes
integrated with logic devices, to limit electrical noise. Damping resistors reduce the noise, but increase propagation delay due
to the decreased drive current.
Because of the excellent signal integrity characteristics of the DOC output, transmission-line termination typically is
unnecessary. Due to the high-impedance drive characteristics of the output in the static state, the use of dc termination is
specifically discouraged. The output current that is required to bias a dc termination network could exceed the static-state
output-drive capabilities of the device. AVC with DOC circuitry is ideally suited for any high-speed, point-to-point application
or unterminated distributed load, such as high-speed memory interfacing.
Design Support
Examination of the characteristics of the device is a critical portion of a successful design. To aid the design engineer in analysis
of device characteristics, the latest versions of IBIS models can be obtained from TI’s website at http://www.ti.com. SPICE
models are also available from TI. Please contact your local TI field sales representative for more information.
4–21
Features and Benefits
Table 2 provides selected AVC family features and benefits.
Table 2. Selected AVC Family Features and Benefits
FEATURES
BENEFITS
Optimized for 2.5-V VCC
Enables low-power designs
Broad product offerings
Simplifies component choice
Advanced EPIC fabrication process; turbo-circuit design
Sub-2-ns (maximum) speeds at 2.5 V.
Easier to meet timing windows
in advanced high-speed designs
DOC outputs do not require series damping resistors internally or externally
Reduced ringing without series output resistors,
increased performance and cost savings
Bus-hold option
Eliminates pullup or pulldown resistors on inputs
IOFF – reverse-current paths to VCC blocked on the inputs and outputs
Outputs disabled during power off for use in
partial power down and mixed-voltage designs
Conclusion
For designs that require 1.8-V, 2.5-V, and 3.3-V logic functions with the highest performance, the AVC family provides the
fastest, quietest logic devices optimized for 2.5-V and unterminated load conditions. AVC offers a broad line of Widebus and
Widebus+ functions, logic gates, and octal bus-interface functions.
Acknowledgment
The authors of this application report are Stephen M. Nolan and Tim Ten Eyck.
4–22
Glossary
A
AVC
Advanced very-low-voltage CMOS
C
CMOS
Complementary metal-oxide semiconductor
D
DOC
Dynamic output control (patent pending)
E
EPIC
Enhanced-performance implanted CMOS
I
IBIS
I/O buffer information specification
II
Input current
II(hold)
Input current (bus hold)
IOH
High-level output current
IOL
Low-level output current
L
LVTTL
Low-voltage TTL (3.3-V power supply and interface levels)
P
PC
Personal computer
S
SPICE
Simulation program with integrated-circuit emphasis
4–23
T
tpd
Propagation delay time
tPHL
Propagation delay time, high- to low-level output
tPLH
Propagation delay time, low- to high-level output
TSSOP
Thin shrink small-outline package
TTL
Transistor-transistor logic
V
VOH
High-level output voltage
VOL
Low-level output voltage
VOHP
High-level output voltage peak
VOHV
High-level output voltage valley
VOLP
Low-level output voltage peak
VOLV
Low-level output voltage valley
4–24
Appendix A – Parameter Measurement Information
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VOH
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure A–1. AVC Parameter Measurement Information (1.8 V ± 0.15 V)
4–25
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure A–2. AVC Parameter Measurement Information (VCC = 2.5 V ± 0.2 V)
4–26
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC
Timing
Input
VCC/2
VCC/2
0V
0V
tsu
Data
Input
VCC/2
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
Output
Control
(low-level
enabling)
VCC/2
VCC/2
0V
tPLZ
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure A–3. AVC Parameter Measurement Information (VCC = 3.3 V ± 0.3 V)
4–27
Dynamic Output Control (DOC)
Circuitry
Technology and Applications
SCEA009B
July 1999
4–29
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time
of sale in accordance with TI’s standard warranty. Testing and other quality control techniques
are utilized to the extent TI deems necessary to support this warranty. Specific testing of all
parameters of each device is not necessarily performed, except those mandated by government
requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated
4–30
Contents
Title
Page
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What Happens at the Output in the Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DOC Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Dynamic Drive vs DC Static Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination (AC vs DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Waveforms – Comparison of ALVCH Standard and Resistor Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–36
4–36
4–37
4–40
4–42
4–43
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–46
Frequently Asked Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–46
Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–47
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–47
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–48
Appendix A – Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–51
4–31
List of Illustrations
Figure
Title
Page
1
VOL vs IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
2
VOH vs IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35
3
DOC Output Curve Superimposed on Resistor-Output and High-Drive-Output Curves . . . . . . . . . . . . . . . . . 4–35
4
Switching Transition of a Fixed Low-Impedance Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–36
5
Impedance Through Switching Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37
6
Simplified Totem-Pole Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37
7
25-Ω Driver Driving Transmission-Line Load and Waveform at the Load . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–38
8
25-Ω Driver and 26-Ω Series Resistor Driving Transmission-Line Load and Waveform at the Load . . . . . . . 4–38
9
50-Ω Driver Driving Transmission-Line Load and Waveform at the Load . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–39
10
Two 50-Ω Drivers In Parallel, Driving Transmission-Line Load and Waveform at the Load . . . . . . . . . . . . . 4–39
11
DOC Circuit Driving Transmission-Line Load and Waveform at the Load . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40
12
DOC Device Output Current Through the Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41
13
Output Current Through the Transition, ±24-mA High-Drive Standard-Output Device . . . . . . . . . . . . . . . . . 4–42
14
Outputs Driving a Standard Lumped Load, VCC = 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–43
15
Outputs Driving a Standard Lumped Load, VCC = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–43
16
Outputs Driving a PC100 Load Network, VCC = 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–44
17
Outputs Driving a PC100 Load Network, VCC = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45
18
SDRAM Load Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45
A-1
AVC Load Circuit and Voltage Waveforms (VCC = 2.5 V ± 0.2 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–51
List of Tables
Table
Title
Page
1
Recommended Static Output Current for DOC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41
2
Recommended Output Current for ALVC Device With Damping Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41
3
Output Voltage Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . 4–42
4
Features and Benefits of DOC Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45
4–32
Abstract
Texas Instruments (TI) next-generation logic is called the Advanced Very-low-voltage CMOS (AVC) family. The AVC
family features TI’s Dynamic Output Control (DOC) circuit (patent pending). DOC circuitry automatically lowers the output
impedance of the circuit at the beginning of a signal transition, providing enough current to achieve high signaling speeds, then
subsequently raises the impedance to limit the overshoot and undershoot noise inherent in high-speed, high-current devices.
This allows a single device to have characteristics similar to both series-damping-resistor outputs during static conditions and
to high-current outputs during dynamic conditions, eliminating the need for series damping resistors. Due to the characteristics
of the DOC output, the dc drive-current specifications for DOC devices are not useable as a relative indicator of the dynamic
performance. A thorough understanding of static and dynamic drive-current conditions is required to design with the DOC
feature of AVC logic.
Introduction
Performance
Trends in advanced digital electronics design continue to include lower power consumption, lower supply voltages, faster
operating speeds, smaller timing budgets, and heavier loads. Many designs are making the transition from 3.3 V to 2.5 V, and
bus speeds are increasing beyond 100 MHz. Trying to meet all of these goals makes the requirement of signal integrity harder
to achieve. For designs that require very-low-voltage logic and bus-interface functions, TI announces the AVC family featuring
TI’s DOC circuit. The DOC circuit limits overshoot and undershoot noise inherent in high-speed, high-current devices, while
still providing propagation delays of less than 2 ns, maximum, at 2.5 V.
Impedance Matching
The design engineer must carefully consider a logic component’s output characteristics to ensure signal integrity and meet
timing requirements. The output must have an impedance that minimizes overshoots and undershoots for signal integrity. The
opposing characteristic that must be considered is having sufficient drive to meet the timing requirements. In the past, the
selection of a component with integrated 26-Ω series damping resistors on the output ports or the use of external resistors was
sometimes necessary. These resistors improve the impedance match of the driver output with the impedance of the
transmission-line load and limit overshoot and undershoot noise. Damping resistors reduce the noise, but decrease slew rate
and increase propagation delay due to the decreased drive current.
TI’s DOC circuitry provides enough drive current to achieve fast slew rates and meet timing requirements, but quickly changes
the output impedance level during the output transition to reduce the overshoot and undershoot noise that often is found in
high-speed logic. This feature of AVC logic eliminates the need for series damping resistors in the output circuit, thereby
improving the output slew rate and propagation-delay characteristics.
The dynamic drive current varies through the transition due to the dynamically changing output impedance. The static
on-resistance (RON) of the output can be calculated from the VOH vs IOH and VOL vs IOL curves (see Figure 1 and
Figure 2). At any specific point on the VOH vs IOH curves, RON = (VOH – VCC)/IOH. At any specific point on the VOL vs IOL
curves, RON = VOL/IOL. The impedance during dynamic conditions is characterized by the slope of the VO vs IO line at any
specific point on the graph.
DOC and TI are trademarks of Texas Instruments Incorporated.
4–33
The VOL vs IOL curves (see Figure 1) illustrate the impedance characteristics of the output in the low state. The curves represent
the amount of sink current available (at a given VCC) to drive the load, as the output voltage decreases from VCC to 0 V when
the output is sinking current (i.e., driving low). The VOL vs IOL curve for 2.5-V VCC has two distinct regions of sink current
availability. At the beginning of the transition from high to low, the portion of the output from 2.5-V to 1.5-V has a high amount
of sink current available. In that region, the curve has characteristics that are similar to a circuit with an output resistance of
approximately 20 Ω. Then, during the transition through 1.5 V, there is a steep drop in the drive current available. In the region
from 1.5 V to ground, the curve has characteristics that are similar to a circuit with an output resistance of approximately 50 Ω.
The VOL vs IOL curves for 1.8-V and 3.3-V VCC have similar characteristics.
3.2
TJ = 40°C
Process = Nominal
V OL– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
VCC = 1.8 V
0.8
0.4
0
17
34
51
68
85
102
119
136
153
170
IOL – Output Current – mA
Figure 1. VOL vs IOL
The VOH vs IOH curves (see Figure 2) illustrate the impedance characteristics of the output in the high state. The curves
represent the amount of source current available (at a given VCC) to drive the load, as the output voltage increases from 0 V
to VCC when the output is sourcing current (i.e., driving high). The operation of the output in the high state is similar to the
operation in the low state. There are two distinct regions of source current availability, each with an output resistance (at 2.5-V
VCC) of approximately 30 Ω and 50 Ω, respectively. The VOH vs IOH curves for 1.8-V and 3.3-V VCC have similar
characteristics.
4–34
2.8
TJ = 40°C
Process = Nominal
V OH – Output Voltage – V
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
–160
VCC = 1.8 V
–144
–128
–112
–96
–80
–64
–48
–32
–16
0
IOH – Output Current – mA
Figure 2. VOH vs IOH
The dual-impedance regions of the DOC output allow a single device to have characteristics similar to a ±24-mA high-drive
device, providing fast edge rates and propagation-delay times. During the latter portion of the transition and during static
conditions, the device has the characteristics of a series-damping-resistor part, with reduced ringing. Figure 3 illustrates the
dual-impedance nature of the DOC output as compared to the fixed-impedance outputs of both a high-drive part and a
series-damping-resistor part by showing the VOL vs IOL curves of all three.
2.4
VCC = 2.5 V
Process = Nominal
TJ = 40°C
2.1
Resistor Output
V OL– Output Voltage – V
1.8
DOC Output
1.5
1.2
0.9
High-Drive Output
0.6
0.3
0
0
10
20
30
40
50
60
70
80
90
100
IOL – Output Current – mA
Figure 3. DOC Output Curve Superimposed on Resistor-Output and High-Drive-Output Curves
4–35
Output Circuitry
What Happens at the Output in the Transition
A standard device with a fixed low-impedance output delivers high current to the load during the entire transition. At the top
of the transition from low to high, high-drive circuits can experience a tremendous overshoot and ringing due to the fast slew
rate (see Figure 4). The DOC circuit counteracts this by switching to a higher output impedance, thereby slowing the slew rate
as the output approaches the top of the transition.
3.46
3.11
Input
V O – Output Voltage – V
2.77
2.42
2.08
1.73
1.38
1.04
Output
0.69
0.35
0
0
11
13
15
17
19
21
23
25
27
29
Switching Time – ns
Figure 4. Switching Transition of a Fixed Low-Impedance Driver
Figure 5 illustrates the output of the DOC driver in the transition from low to high. Initially, the output is at a static low level.
The 2.5-V VOL vs IOL impedance-characteristic curve (see Figure 1) shows that, with an output at 0 V, the output resistance
in the low state is approximately 50 Ω. When the transition from low to high begins, the 2.5-V VOH vs IOH curve (see Figure 2)
illustrates the impedance characteristics of the output. Initially, the output resistance is approximately 30 Ω. Under typical
conditions, this low-impedance output can deliver nearly 84 mA to the load, providing a very fast slew rate. After the output
voltage passes through the threshold (1.5 V) in the transition from low to high, the output resistance is switched from
approximately 30 Ω to approximately 50 Ω. This increase in output resistance reduces the amount of drive current available.
This decreases the slew rate and rolls off the transition, producing a smooth knee at the top and reducing overshoot or ringing.
When the final output voltage is reached, due to the high output resistance, the amount of drive current available to hold the
output voltage at a valid logic level is at a minimum, providing relatively low static-state power levels.
4–36
2.32
V O – Output Voltage – V
2.01
High Impedance
1.81
1.55
1.29
1.03
0.77
Low Impedance
0.52
High Impedance
0.25
0
20.7
21.4
22.1
22.8
23.5
24.2
24.9
25.6
26.3
Switching Time – ns
Figure 5. Impedance Through Switching Transitions
A transition from high to low behaves in a similar manner and can be understood by the same principles. When the transition
from high to low begins, the 2.5-V VOL vs IOL curve (see Figure 1) illustrates the impedance characteristics of the output.
Initially, the output resistance is approximately 20 Ω. Under typical conditions, this low output impedance can deliver nearly
105-mA to the load. Then, as the output voltage passes through the threshold (1.5 V), the output resistance is switched from
approximately 20 Ω to approximately 50 Ω. This results in minimal, or no undershoot.
DOC Circuit Description
Figure 6 shows a simplified output stage of a typical logic circuit. When the input is low, the n-channel transistor (Qn) turns
off and the p-channel transistor (Qp) turns on and begins to conduct, and the output voltage VO is pulled high. Conversely, when
the input is high, Qp turns off, Qn begins to conduct, and VO is pulled low. This action is similar to an inverter, and several of
these inverting stages typically are cascaded in series to form a buffer/driver.
VCC
Qp
VO
Qn
Figure 6. Simplified Totem-Pole Output Stage
4–37
The sizes of the output transistors Qp and Qn determine the output impedance. The transistors are designed with the sizes of
the n-channel FET and p-channel FET selected to provide an output impedance of a specific design value. The sizes can be
selected so that the on-resistance of the output is, for example, characteristically approximately 25 Ω, which is the typical
output impedance of a conventional low-voltage CMOS logic device. Figure 7 illustrates a driver with the output transistors
sized to provide a 25-Ω output. The driver is shown driving a transmission-line load consisting of a length of transmission line
that is terminated into a capacitor. The waveform showing the signal incident at the capacitor depicts the fast slew rates and
small propagation delays that are characteristic of low-impedance drivers. The fast edge rates create large overshoots and
unacceptable ringing.
3.6
V – Output Voltage – V
3.0
O
25 Ω
2.4
1.8
1.2
0
–0.6
–1.2
–1.8
22
0
26
30
34
38
42
Time – ns
46
50
54
58
Figure 7. 25-Ω Driver Driving Transmission-Line Load and Waveform at the Load
One method of reducing the ringing and electrical noise is to slow down the edge rates. This can be accomplished by the
addition of a damping resistor in series with the output. This creates a high-impedance low-drive output. Figure 8 illustrates
a driver with a 25-Ω output and a series 26-Ω damping resistor driving the transmission-line load. The resultant signal is much
cleaner, but the slower edge rate increases the propagation delay time. Depending on the total timing budget available, this
could be an unacceptable solution. Series resistors also can raise the dc low-voltage level of a signal. This reduces noise
immunity of the receiving logic. Finally, series damping resistors should be used only on point-to-point nets, and never with
distributed loads, because of the half voltage that propagates down the transmission line due to incident wave switching.
26 Ω
2.0
1.6
1.2
0.8
0.4
O
25 Ω
V – Output Voltage – V
2.4
0
–0.4
0
22
26
30
34
38
42
Time – ns
46
50
54
58
Figure 8. 25-Ω Driver and 26-Ω Series Resistor Driving Transmission-Line Load and Waveform
at the Load
Another method that can be used to improve the impedance match of the output with the load is to reduce the size of the output
transistors. If their sizes are decreased, the output impedance increases. This provides a low-drive output. Figure 9 illustrates
a driver with the output transistor sizes selected to provide a 50-Ω output. The driver is shown driving the same
transmission-line load and the resultant waveform at the load exhibits similar characteristics to the series-damping-resistor
version.
4–38
O
50 Ω
V – Output Voltage – V
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
–0.4
0
22
26
30
34
38
42
Time – ns
46
50
54
58
Figure 9. 50-Ω Driver Driving Transmission-Line Load and Waveform at the Load
It is also interesting to explore the attributes of two drivers in parallel. Figure 10 represents two 50-Ω drivers in parallel. The
resultant waveform at the load exhibits characteristics similar to the single 25-Ω driver. In fact, the parallel combination of the
two has the same output impedance as a single 25-Ω impedance driver. This effectively creates a low-impedance high-drive
output.
3.6
O
50 Ω
V – Output Voltage – V
3.0
50 Ω
2.4
1.8
1.2
0
–0.6
–1.2
–1.8
0
22
26
30
34
38
42
Time – ns
46
50
54
58
Figure 10. Two 50-Ω Drivers In Parallel, Driving Transmission-Line Load and Waveform at the Load
Increasing the output impedance reduces overshoots and undershoots, but at the cost of increased propagation delays.
Decreasing the output impedance decreases propagation delays, but at the cost of increased overshoots and undershoots. A
desirable circuit would have a low output impedance for the beginning portion of the output transition and a high output
impedance for the latter portion of the output transition. This would provide fast propagation delays, with minimal, or no
overshoot or undershoot.
Figure 11 is a block diagram of the DOC circuit, which consists of a fixed driver with a nominal 50-Ω on-resistance. The
50-Ω driver functions like a typical high-impedance low-drive output, with good electrical and noise characteristics. In parallel
with the 50-Ω driver is a controllable 50-Ω nominal on-resistance driver, with an output that can be enabled or disabled similar
to the output of a 3-state device. When a device is disabled, its output is in a very high-impedance state and contributes nothing
to the drive or to the loading of the output. When it is enabled, the parallel combination of the 50-Ω drivers has the same output
characteristics as a single 25-Ω impedance driver. This effectively creates a low-impedance high-drive output. The impedance
control circuit (ZCC) enables and disables the controllable driver by controlling its ON signal. The ZCC monitors the output
and controls the controllable driver at the appropriate times during the signal transition to achieve a high-drive, fast slew-rate
transition.
4–39
2.8
V – Output Voltage – V
2.4
50 Ω
50 Ω
O
ON
2.0
1.6
1.2
0.8
0.4
0
ZCC
–0.4
0
22
26
30
34
38
42
Time – ns
46
50
54
58
Figure 11. DOC Circuit Driving Transmission-Line Load and Waveform at the Load
The operation of the DOC begins with the output in a static state, for example, at a logic low state. In the static low state, the
ZCC has the controllable 50-Ω driver disabled and the n channel of the fixed 50-Ω driver sinks current to ground from the
output. When the input transitions from low to high, the n-channel transistor in the fixed 50-Ω driver turns off, and the p channel
turns on, sourcing current to the output and beginning the output transition from low to high. Simultaneously, the ZCC enables
the p channel in the controllable 50-Ω driver. The parallel p channels of the drivers have a combined on-resistance of
approximately 25 Ω. This low impedance provides a high drive current to cause a fast slew-rate signal transition. The ZCC
senses the output voltage, and as the voltage passes through threshold in the transition from low to high, the ZCC disables the
output p channel of the controllable 50-Ω driver. The increase in output impedance decreases the slope and rolls off the output
signal, reducing the overshoot.
The operation of the high-to-low transition is similar.
AC Dynamic Drive vs DC Static Drive
The dc drive-current ratings in the recommended operating-conditions table of a device data sheet typically are selected to show
the static-drive capability of a device when the output voltage is at a worst-case valid logic level, such as VOH(MIN) or
VOL(MAX). Historically, these dc drive-current ratings were used as a relative measure of a component’s ac dynamic-drive
performance. For a device with a fixed output on-resistance, this was an acceptable method, because the dc current at a given
logic level could be extrapolated to determine the amount of ac drive current available through the transition.
With DOC circuitry, the output impedance characteristics change dynamically during a transition. The dc drive-current
specification is not a useable indicator of the devices’ dynamic performance capability. The dc output ratings of DOC devices
(see Table 1) can be used loosely as a relative comparison to the dc output ratings of devices with integral series damping
resistors (see Table 2), and this is a good indication of the DOC circuit’s excellent low-noise and low-power characteristics.
However, unlike a part with a fixed low-drive output, the DOC circuitry provides good ac performance. The DOC output
provides a very strong ac drive during dynamic conditions, capable of driving very heavily capacitive CMOS loads.
4–40
Table 1. Recommended Static Output Current for DOC Circuits1
MIN
IOHS
IOLS
Static high-level output current
Static low-level output current
MAX
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
–4
VCC = 3 V to 3.6 V
VCC = 1.65 V to 1.95 V
–12
–8
UNIT
mA
4
8
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
mA
12
Table 2. Recommended Output Current for ALVC Device With Damping Resistor2
MIN
IOH
IOL
High-level output current
Low-level output current
MAX
VCC = 2.3 V
VCC = 2.7 V
–6
VCC = 3 V
VCC = 2.3 V
–12
VCC = 2.7 V
VCC = 3 V
8
–8
UNIT
mA
6
mA
12
The DOC device performs like a high-drive part during signal transition. Under typical conditions at 2.5-V VCC , the drive
current that is available during the beginning of a transition from low to high is about 84 mA, and from high to low is about
105 mA. Figure 12 illustrates the output current of the DOC circuit driving a standard load through the low-to-high and
high-to-low transitions. Note the large peak currents during the transition.
VCC = 2.5 V
Process = Nominal
TJ = 40°C
48
1.87
24
Output Current
1.40
0
0.94
I O – Output Current – mA
V O – Output Voltage – V
Output Voltage
–24
Output Voltage
0.47
Output Current
–48
0
0
22
26
30
34
38
42
46
50
Time – ns
Figure 12. DOC Device Output Current Through the Transition
The dynamic drive current is not specified on the data sheet for devices with DOC outputs because of its transient nature, but
it is similar to the dynamic drive current that is available from a ±24-mA (at 2.5-V VCC) high-drive standard-output device
(see Figure 13).
4–41
VCC = 2.5 V
Process = Nominal
TJ = 40°C
40
Output Voltage
Output Current
20
1.2
0
0.6
I O – Output Current – mA
V O – Output Voltage – V
1.8
60
–20
Output Current
Output Voltage
–40
0
0
22
26
30
34
38
42
46
50
Time – ns
Figure 13. Output Current Through the Transition, ±24-mA High-Drive Standard-Output Device
Because a typical CMOS load is purely capacitive, with very little bias (leakage) current necessary to hold a valid static logic
level, the amount of dc drive required of most drivers is small. The dc drive is specified on the data sheet of DOC output devices.
The output parameters are static and testable values that are enumerated in terms of minimum and maximum output voltages
at specific output currents (see Table 3).
Table 3. Output Voltage Characteristics Over Recommended Operating Free-Air Temperature Range1
PARAMETER
VOH
VOL
TEST CONDITIONS
IOH = –100 µA
IOH = –4 mA,
IOH = –8 mA,
IOH = –12 mA,
IOL = 100 µA
IOL = 4 mA,
IOL = 8 mA,
IOL = 12 mA,
VIH = 1.07 V
VIH = 1.7 V
VIH = 2 V
VCC
1.65 V to 3.6 V
MIN
1.65 V
VCC–0.2
1.2
2.3 V
1.75
3V
2.3
TYP
MAX
UNIT
V
1.65 V to 3.6 V
0.2
VIL = 0.57 V
VIL = 0.7 V
1.65 V
0.45
2.3 V
0.55
VIL = 0.8 V
3V
0.7
V
Termination (AC vs DC)
Because of the excellent signal-integrity characteristics of the DOC output, transmission-line termination typically is
unnecessary. Due to the high-impedance characteristics of the output in the static state, the use of dc termination is specifically
discouraged. The output current that is required to bias a dc termination network could exceed the static-state output-drive
capabilities of the device. AVC family devices with DOC circuitry are suited ideally for any high-speed, point-to-point
application or unterminated distributed load, such as high-speed memory interfaces.
4–42
Waveforms – Comparison of ALVCH Standard and Resistor Outputs
Figures 14 and 15 show the SPICE results comparing SN74AVC16827 with SN74ALVCH16827 and SN74ALVCH162827
into a standard lumped load (see Appendix A) for VCC = 2.5 V and VCC = 3.3 V, respectively. The results show the relative
propagation delay and noise performance of the DOC circuit.
VCC = 2.5 V
Process = Nominal
TJ = 40°C
19 Bits Switching
2.4
V O – Output Voltage – V
2.0
SN74ALVCH162827
1.6
SN74ALVCH16827
1.2
SN74AVC16827
0.8
Input
0.4
0
–0.4
22
26
30
34
38
42
46
50
54
58
Time – ns
Figure 14. Outputs Driving a Standard Lumped Load, VCC = 2.5 V
3.5
VCC = 3.3 V
Process = Nominal
TJ = 40°C
19 Bits Switching
3.0
V O – Output Voltage – V
2.5
SN74ALVCH162827
2.0
SN74ALVCH16827
1.5
1.0
SN74AVC16827
0.5
Input
0
–0.5
22
26
30
34
38
42
46
50
54
58
Time – ns
Figure 15. Outputs Driving a Standard Lumped Load, VCC = 3.3 V
4–43
Figures 16 and 17 show the SPICE modeling of the SN74AVC16827 with the DOC circuit, an SN74ALVCH16827 with
low-impedance output circuit, and an SN74ALVCH162827 with series damping resistors driving a PC100 DQM load for
VCC = 2.5 V and VCC = 3.3 V, respectively. The DQM load is defined in the Intel PC SDRAM Registered DIMM Specification,
Revision 1.0, February 19983. For this example, the 256-Mbyte load was used. The transmission lines have a characteristic
impedance of 70 Ω. The lengths of the transmission lines are specified in the PC100 specification; series resistor R1 was
specified as zero. This resistor is not necessary when using the DOC circuit. The six SDRAM loads were modeled by the circuit
shown in Figure 18.
The waveforms shown in Figures 16 and 17 were measured at the input to the memory devices. The low-impedance driver
exhibits excessive overshoots and undershoots, while the DOC circuit and the driver with series damping resistors does not.
The DOC circuit is faster than the series-damping-resistor circuit. This improvement in speed is more pronounced when the
simulations are run under worst-case weak conditions.
VCC = 2.5 V
Process = Nominal
TJ = 40°C
One Bit Switching
3.0
V O – Output Voltage – V
2.5
2.0
SN74ALVCH162827
1.5
SN74ALVCH16827
1.0
SN74AVC16827
0.5
Input
0
–0.5
–1.0
–1.5
22
26
30
34
38
42
46
50
Time – ns
Figure 16. Outputs Driving a PC100 Load Network, VCC = 2.5 V
Intel is a trademark of Intel Corporation.
4–44
54
58
4.8
VCC = 3.3 V
Process = Nominal
TJ = 40°C
One Bit Switching
4.0
V O – Output Voltage – V
3.2
2.4
SN74ALVCH162827
1.6
SN74ALVCH16827
0.8
SN74AVC16827
0
Input
–0.8
–1.6
22
26
30
34
38
42
46
50
54
58
Time – ns
Figure 17. Outputs Driving a PC100 Load Network, VCC = 3.3 V
0.86 nH
0.01 Ω
0.01 Ω
1 pF
0.86 nH
Test Point
1.5 pF
Figure 18. SDRAM Load Model
Features and Benefits
Table 4 summarizes DOC circuit features and some of the benefits of those features.
Table 4. Features and Benefits of DOC Circuitry
FEATURES
BENEFITS
Optimized for 2.5-V VCC. No damping resistors
Enables low-power designs
Low-impedance, high-drive output during the beginning of a signal transition
Fast edge-rates and small propagation delays
High output impedance for the later portion of the ouput transition
Minimal, or no overshoot or undershoot
High-impedance, low-drive steady-state output after signal transition
Enables low-power designs
DOC outputs do not require series damping resistors internally or externally
Reduced ringing without series output resistors;
increased performance; cost savings
IOFF – reverse-current paths to VCC blocked
Outputs disabled during power off for use in partial
power-down designs
4–45
Conclusion
The DOC circuitry provides a low-impedance, high-drive output during the beginning of a signal transition, to provide fast
edge rates and small propagation delays. Then, as the output passes through the threshold, the DOC switches to a
high-impedance, low-drive output to roll off the signal and reduce ringing. The amount of static dc drive current specified in
the data sheets of devices with DOC features does not reflect the large amount of dynamic current that is available to drive
a typical large capacitive CMOS load.
Frequently Asked Questions
1.
Q: What is DOC?
A: DOC is the Dynamic Output Control circuit (patent pending). It is the output circuit of TI’s AVC family of devices
that changes the output impedance during the signal transition.
2.
Q: Why use DOC output?
A: During the beginning of the signal transition, DOC output provides the desirable characteristics of high drive
to supply fast edge-rates and small propagation delays. As the signal passes through the threshold, the DOC
output decreases the drive to roll off the signal and reduce ringing without the use of damping resistors.
3.
Q: How does DOC work?
A: The DOC output has an impedance-control circuit that monitors the output signal. When a transition begins, the
impedance-control circuit enables the outputs of two parallel drivers to provide a low-impedance, high-drive
output. As the output passes through the threshold, the impedance-control circuit disables the output of one of
the drivers, providing a high-impedance, low-drive output.
4.
Q: Should I use series damping resistors on the output of DOC devices?
A: It is not necessary to use series damping resistors to reduce ringing because the DOC output provides a
high-impedance, low-drive output at the end of the signal transition. Using series damping resistors would defeat
the high-drive benefit of the DOC output.
5.
Q: Can I use dc termination on the output of DOC devices?
A: Do not use dc termination. The use of dc termination could exceed the static-drive capability of the DOC output.
Due to the excellent signal-integrity characteristics of the DOC output, termination should be unnecessary.
6.
Q: What is the maximum drive-current capability of the DOC output?
A: The DOC output has ±8-mA dc static-drive current capability at 2.5-V VCC. Under typical conditions at 2.5-V
VCC, the amount of ac dynamic-drive current that the DOC output can supply varies from a maximum of about
84 mA at the beginning of the transition from low to high. At the beginning of the transition from high to low,
it varies from a maximum of about 105 mA.
7.
Q: What is the output impedance of a DOC circuit?
A: The impedance during dynamic conditions is characterized by the slope of the VO vs IO line, at any specific point
on the graph. The output RON can be calculated from the VOH vs IOH and VOL vs IOL curves (see Figure 1 and
Figure 2). At any specific point on the VOH vs IOH curves, RON = (VOH – VCC)/IOH. At any specific point on
the VOL vs IOL curves, RON = VOL/IOL. In the high state, the output RON varies from approximately 50 Ω in the
high-impedance mode to approximately 30 Ω in the low-impedance mode. In the low state, the output RON varies
from approximately 50 Ω in the high-impedance mode to approximately 20 Ω in the low-impedance mode.
8.
Q: Are devices with DOC output circuitry fast?
A: Yes, the DOC output provides a very fast edge-rate to decrease the propagation delay times, while maintaining
the excellent signal-integrity characteristics associated with the slower series-damping-resistor parts.
4–46
9.
Q: Why aren’t ac dynamic-drive specifications included in the data sheet?
A: The dynamic-drive current is not specified on the data sheet for devices with DOC outputs because of its transient
nature, but it is similar to the drive current available from a standard-output device with an IOH and IOL of ±24
mA at 2.5-V VCC.
10. Q: In data sheets for devices with DOC outputs, is the dc static-drive specification an indicator of the devices’
dynamic performance?
A: No. The devices perform like high-drive devices during signal transition. This is not reflected in the
dc static-drive specification on the data sheet.
11. Q: Since the DOC output provides high-drive, does it suffer from poor simultaneous switching performance? How
does its simultaneous switching performance compare to standard and resistor devices?
A: At 2.5-V VCC with output into a standard load, SPICE analysis shows that the SN74AVC16245 DOC outputs
have a maximum VOLV = –165 mV, standard outputs have a maximum VOLV = –574 mV, and resistor outputs
have a maximum VOLV = –36 mV (15 outputs switching, one steady-state low).
12. Q: Do DOC outputs contribute to a device’s low-power performance?
A: Compared to a damping-resistor output where a portion of the output drive is dissipated in the resistor and not
delivered to the load, the DOC output offers better low-power performance. The devices in the AVC family that
feature DOC outputs are designed for 2.5-V VCC operation, enabling low-power designs.
Acknowledgment
The authors of this application report are Stephen M. Nolan and Tim Ten Eyck.
References
1.
2.
3.
TI SN74AVC16245 16-Bit Bus Transceiver With 3-State Outputs, literature number SCES142.
TI SN74ALVC162245 16-Bit Bus Transceiver With 3-State Outputs, literature number SCES064.
Intel PC SDRAM Registered DIMM Specification, Revision 1.0, February 1998.
4–47
Glossary
A
A
Amperes
ac
Alternating current
ALVC
Advanced Low-Voltage CMOS
AVC
Advanced Very-low-voltage CMOS
B
B
Byte
C
C
Celsius
CMOS
Complementary metal-oxide semiconductor
D
dc
Direct current
DIMM
Dual-inline memory module
DOC
Dynamic output control (patent pending)
DQM
Data mask
DRAM
Dynamic random-access memory
F
F
Farad
FET
Field-effect transistor
H
H
4–48
Henry
I
IBIS
I/O buffer information specification
II
Input current
IOFF
Current into a pin when VCC = 0 V
IOH
High-level output current
IOHS
Static high-level output current
IOL
Low-level output current
IOLS
Static low-level output current
IV
Current vs voltage
M
Max
Maximum
Min
Minimum
P
PC
Personal computer
R
RON
On-state output resistance
S
s
Seconds
SDRAM
Synchronous DRAM
SPICE
Simulation program with integrated-circuit emphasis
T
TI
Texas Instruments
4–49
V
V
Volts
VCC
Supply voltage
VO
Output voltage
VOH
High-level output voltage
VOL
Low-level output voltage
VOHP
High-level output voltage peak
VOHV
High-level output voltage valley
VOLP
Low-level output voltage peak
VOLV
Low-level output voltage valley
Z
ZCC
4–50
Impedance control circuit
Appendix A – Parameter Measurement Information
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure A–1. AVC Load Circuit and Voltage Waveforms (VCC = 2.5 V ± 0.2 V)
4–51
Implications of
Slow or Floating CMOS Inputs
SCBA004C
February 1998
4–53
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current and complete.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty. Specific
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Copyright  1998, Texas Instruments Incorporated
4–54
Contents
Title
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–57
Characteristics of Slow or Floating CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–57
Slow Input Edge Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–59
Floating Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–59
Recommendations for Designing More-Reliable Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pullup or Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus-Hold Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–61
4–61
4–61
4–62
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–68
List of Illustrations
Figure
Title
Page
1
Input Structures of ABT and LVT/LVC Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–57
2
Supply Current Versus Input Voltage (One Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–58
3
Input Transition Rise or Fall Rate as Specified in Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–58
4
Input/Output Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–59
5
Examples of Supply-Current Change of the Input at TTL Level as Specified in Data Sheets . . . . . . . . . . . . . 4–60
6
Supply Current Versus Input Voltage (36 Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–60
7
Typical Bidirectional Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–60
8
Inactive-Bus Model With a Defined Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–61
9
Typical Bus-Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–62
10
Stand-Alone Bus-Hold Circuit (SN74ACT107x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–63
11
Diode Characteristics (SN74ACT107x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–63
12
Input Structure of ABT/LVT and ALVC/LVC Families With Bus-Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . 4–64
13
Bus-Hold Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65
14
Driver and Receiver System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–66
15
Output Waveforms of Driver With and Without Receiver Bus-Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 4–66
16
Bus-Hold Circuit Supply Current Versus Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–66
17
Input Power With and Without Bus Hold at Different Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–67
18
Example of Data-Sheet Minimum Specification for Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–68
4–55
Introduction
In recent years, CMOS (AC/ACT, AHC/AHCT, ALVC, CBT, CBTLV, HC/HCT, LVC, LV/LV-A) and BiCMOS (ABT, ALVT,
BCT, FB, GTL, and LVT) logic families have further strengthened their position in the semiconductor market. New designs
have adopted both technologies in almost every system that exists, whether it is a PC, a workstation, or a digital switch. The
reason is obvious: power consumption is becoming a major issue in today’s market. However, when designing systems using
CMOS and BiCMOS devices, one must understand the characteristics of these families and the way inputs and outputs behave
in systems. It is very important for the designer to follow all rules and restrictions that the manufacturer requires, as well as
to design within the data-sheet specifications. Because data sheets do not cover the input behavior of a device in detail, this
application report explains the input characteristics of CMOS and BiCMOS families in general. It also explains ways to deal
with issues when designing with families in which floating inputs are a concern. Understanding the behavior of these inputs
results in more robust designs and better reliability.
Characteristics of Slow or Floating CMOS Inputs
Both CMOS and BiCMOS families have a CMOS input structure. This structure is an inverter consisting of a p-channel to VCC
and an n-channel to GND as shown in Figure 1. With low-level input, the p-channel transistor is on and the n-channel is off,
causing current to flow from VCC and pulling the node to a high state. With high-level input, the n-channel transistor is on,
the p-channel is off, and the current flows to GND, pulling the node low. In both cases, no current flows from VCC to GND.
However, when switching from one state to another, the input crosses the threshold region, causing the n-channel and the
p-channel to turn on simultaneously, generating a current path between VCC and GND. This current surge can be damaging,
depending on the length of time that the input is in the threshold region (0.8 to 2 V). The supply current (ICC) can rise to several
milliamperes per input, peaking at approximately 1.5-V VI (see Figure 2). This is not a problem when switching states within
the data-sheet-specified input transition time limit specified in the recommended operating conditions table for the specific
devices. Examples are shown in Figure 3.
VCC
Drops
Supply
Voltage
D1
Q1
VCC
Qp
Qp
To the
Internal Stage
Input
Inverter
Qn
ABT DEVICES
To the
Internal Stage
Input
Inverter
Qn
LVT/LVC DEVICES
Figure 1. Input Structures of ABT and LVT/LVC Devices
4–57
16
VCC = 5 V
TA = 25°C
One Bit is Driven From 0 V to 6 V
I CC – Supply Current – mA
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
VI – Input Voltage – V
Figure 2. Supply Current Versus Input Voltage (One Input)
recommended operating conditions†
MIN
ABT octals
∆t/∆v
Input transition rise or fall rate
10
AHC, AHCT
20
FB
10
10
LVT, LVC, ALVC, ALVT
LV-A
HC, HCT
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
† Refer to the latest TI data sheets for device specifications.
Figure 3. Input Transition Rise or Fall Rate as Specified in Data Sheets
4–58
ns/V
100
VCC = 4.5 V to 5.5 V
Input transition (rise and fall) time
UNIT
5
ABT Widebus and Widebus+
LV
tt
MAX
200
100
20
1000
500
400
ns
Slow Input Edge Rate
With increased speed, logic devices have become more sensitive to slow input edge rates. A slow input edge rate, coupled with
the noise generated on the power rails when the output switches, can cause excessive output errors or oscillations. Similar
situations can occur if an unused input is left floating or is not actively held at a valid logic level.
These functional problems are due to voltage transients induced on the device’s power system as the output load current (IO)
flows through the parasitic lead inductances during switching (see Figure 4). Because the device’s internal power-supply nodes
are used as voltage references throughout the integrated circuit, inductive voltage spikes, VGND, affect the way signals appear
to the internal gate structures. For example, as the voltage at the device’s ground node rises, the input signal, VI′, appears to
decrease in magnitude. This undesirable phenomenon can then erroneously change the output if a threshold violation occurs.
In the case of a slowly rising input edge, if the change in voltage at GND is large enough, the apparent signal, VI′, at the device
appears to be driven back through the threshold and the output starts to switch in the opposite direction. If worst-case conditions
prevail (simultaneously switching all of the outputs with large transient load currents), the slow input edge is repeatedly driven
back through the threshold, causing the output to oscillate. Therefore, the maximum input transition time of the device should
not be violated, so no damage to the circuit or the package occurs.
VCC
VI
IO
VI′
VGND
LGND
Figure 4. Input /Output Model
Floating Inputs
If a voltage between 0.8 V and 2 V is applied to the input for a prolonged period of time, this situation becomes critical and
should not be ignored, especially with higher bit count and more dense packages (SSOP, TSSOP). For example, if an 18-bit
transceiver has 36 I/O pins floating at the threshold, the current from VCC can be as high as 150 mA to 200 mA. This is
approximately 1 W of power consumed by the device, which leads to a serious overheating problem. This continuous
overheating of the device affects its reliability. Also, because the inputs are in the threshold region, the outputs tend to oscillate,
resulting in damage to the internal circuit over a long period of time. The data sheet shows the increase in supply current (∆ICC)
when the input is at a TTL level [for ABT VI = 3.4 V, ∆ICC = 1.5 mA (see Figure 5)]. This becomes more critical when the
input is in the threshold region as shown in Figure 6.
These characteristics are typical for all CMOS input circuits, including microprocessors and memories.
For CBT or CBTLV devices, this applies to the control inputs. For FB and GTL devices, this applies to the control inputs and
the TTL ports only.
4–59
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)†
PARAMETER
∆ICC‡
∆ICC‡
∆
∆ICC‡
∆
TEST CONDITIONS
MIN
MAX
ABT, AHCT
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
1.5
CBT
Control inputs
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
2.5
CBTLV
Control inputs
VCC = 3.6 V,
One input at 3 V,
Other inputs at VCC or GND
750
VCC = 3 V to 3.6 V,
One input at VCC – 0.6 V,
Other inputs at VCC or GND
LVT
LVC, ALVC, LV
0.2
0.5
UNIT
mA
µA
µ
mA
† Refer to the latest TI data sheets for device specifications.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Figure 5. Examples of Supply-Current Change of the Input at TTL Level as Specified in Data Sheets
160
VCC = 5 V
TA = 25°C
All 36 Bits Are Driven
From 0 V to 6 V
I CC – Supply Current – mA
140
120
100
80
60
40
20
0
0
0.5
1 1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VI – Input Voltage – V
Figure 6. Supply Current Versus Input Voltage (36 Inputs)
As long as the driver is active in a transmission path or bus, the receiver’s input is always in a valid state. No input specification
is violated as long as the rise and fall times are within the data-sheet limits. However, when the driver is in a high-impedance
state, the receiver input is no longer at a defined level and tends to float. This situation can worsen when several transceivers
share the same bus. Figure 7 is an example of a typical bus system. When all transceivers are inactive, the bus-line levels are
undefined. When a voltage that is determined by the leakage currents of each component on the bus is reached, the condition
is known as a floating state. The result is a considerable increase in power consumption and a risk of damaging all components
on the bus. Holding the inputs or I/O pins at a valid logic level when they are not being used or when the part driving them
is in the high-impedance state is recommended.
Figure 7. Typical Bidirectional Bus
4–60
Recommendations for Designing More-Reliable Systems
Bus Control
The simplest way to avoid floating inputs in a bus system is to ensure that the bus always is either active or inactive for a limited
time when the voltage buildup does not exceed the maximum VIL specification (0.8 V for TTL-compatible input). At this
voltage, the corresponding ICC value is too low and the device operates without any problem or concern (see Figures 2 and 4).
To avoid damaging components, the designer must know the maximum time the bus can float. First, assuming that the
maximum leakage current is IOZ = 50 µA and the total capacitance (I/O and line capacitance) is C = 20 pF, the change in voltage
with respect to time on an inactive line that exceeds the 0.8-V level can be calculated as shown in equation 1.
DVńDt +
50 mA
I OZ
+
+ 2.5 Vńms
20 pF
C
(1)
The permissible floating time for the bus in this example should be reduced to 320 ns maximum, which ensures that the bus
does not exceed the 0.8-V level specified. The time constant does not change when multiple components are involved because
their leakage currents and capacitances are summed.
The advantage of this method is that it requires no additional cost for adding special components. Unfortunately, this method
does not always apply because buses are not always active.
Pullup or Pulldown Resistors
When buses are disabled for more than the maximum allowable time, other ways should be used to prevent components from
being damaged or overheated. A pullup or a pulldown resistor to VCC or GND, respectively, should be used to keep the bus
in a defined state. The size of the resistor plays an important role and, if its resistance is not chosen properly, a problem may
occur. Usually, a 1-kΩ to 10-kΩ resistor is recommended. The maximum input transition time must not be violated when
selecting pullup or pulldown resistors (see Figure 3). Otherwise, components may oscillate, or device reliability may be
affected.
VCC
VCC
R
R
=
BUS
V(t)
CT
Figure 8. Inactive-Bus Model With a Defined Level
Assume that an active-low bus goes to the high-impedance state as modeled in Figure 8. CT represents the device plus the
bus-line capacitance and R is a pullup resistor to VCC. The value of the required resistor can be calculated as shown in
equation 2.
V(t) + V CC – [e –tńRCT (V CC – V i)]
Where:
V(t)
Vi
VCC
CT
R
t
=
=
=
=
=
=
(2)
2 V, minimum voltage at time t
0.5 V, initial voltage
5V
total capacitance
pullup resistor
maximum input rise time as specified in the data sheets (see Figure 3).
4–61
Solving for R, the equation becomes:
R +
t
0.4
(3)
CT
For multiple transceivers on a bus:
R +
0.4
t
C
(4)
N
Where:
C = individual component and trace capacitance
N = number of components connected to the bus
Assuming that there are two components connected to the bus, each with a capacitance C = 15 pF, requiring a maximum rise
time of 10 ns/V and t = 15-ns total rise time for the input (2 V), the maximum resistor size can be calculated:
R +
0.4
15 ns
15 pF
2
+ 1.25 kW
(5)
This pullup resistor method is recommended for ac-powered systems; however, it is not recommended for battery-operated
equipment because power consumption is critical. Instead, use the bus-hold feature that is discussed in the next section. The
overall advantage of using pullup resistors is that they ensure defined levels when the bus is floating and help eliminate some
of the line reflections, because resistors also can act as bus terminations.
Bus-Hold Circuits
The most effective method to provide defined levels for a floating bus is to use Texas Instruments (TI) built-in bus-hold
feature on selected families or as an external component like the SN74ACT1071 and SN74ACT1073 (refer to Table 1).
Table 1. Devices With Bus Hold
DEVICE TYPE
BUS HOLD INCORPORATED
SN74ACT1071
10-bit bus hold with clamping diodes
SN74ACT1073
16-bit bus hold with clamping diodes
ABT Widebus+ (32 and 36 bit)
All devices
ABT Octals and Widebus
Selected devices only
AHC/AHCT Widebus
TBA (Selected devices only)
Low Voltage (LVT and ALVC)
All devices
LVC Widebus
All devices
Bus-hold circuits are used in selected TI families to help solve the floating-input problem and eliminate the need for pullup
and pulldown resistors. Bus-hold circuits consist of two back-to-back inverters with the output fed back to the input through
a resistor (see Figure 9). To understand how the bus-hold circuit operates, assume that an active driver has switched the line
to a high level. This results in no current flowing through the feedback circuit. Now, the driver goes to the high-impedance
state and the bus-hold circuit holds the high level through the feedback resistor. The current requirement of the bus-hold circuit
is determined only by the leakage current of the circuit. The same condition applies when the bus is in the low state and then
goes inactive.
Input
Figure 9. Typical Bus-Hold Circuit
4–62
As mentioned previously in this section, TI offers the bus-hold capability as stand-alone 10-bit and 16-bit devices
(SN74ACT1071 and SN74ACT1073) with clamping diodes to VCC and GND for added protection against line reflections
caused by impedance mismatch on the bus. Because purely ohmic resistors cannot be implemented easily in CMOS circuits,
a configuration known as a transmission gate is used as the feedback element (see Figure 10). An n-channel and a p-channel
are arranged in parallel between the input and the output of the buffer stage. The gate of the n-channel transistor is connected
to VCC and the gate of the p-channel is connected to GND. When the output of the buffer is high, the p-channel is on, and when
the output is low, the n-channel is on. Both channels have a relatively small surface area — the on-state resistance from drain
to source, Rdson, is about 5 kΩ.
VCC
VCC
Figure 10. Stand-Alone Bus-Hold Circuit (SN74ACT107x)
Assume that in a practical application the leakage current of a driver on a bus is IOZ = 10 µA and the voltage drop across the
5-kΩ resistance is VD = 0.8 V (this value is assumed to ensure a defined logic level). Then, the maximum number of
components that a bus-hold circuit can handle is calculated as follows:
N+
VD
I OZ
R
+
0.8 V
+ 16 components
10 mA 5 kW
(6)
The 74ACT1071 and 74ACT1073 also provide clamping diodes as an added feature to the bus-hold circuit. These diodes are
useful for clamping any overshoot or undershoot generated by line reflections. Figure 11 shows the characteristics of the diodes
when the input voltage is above VCC or below GND. At VI = –1V, the diode can source about 50 mA, which can help eliminate
undershoots. This can be very useful when noisy buses are a concern.
Upper Clamping Diode
Lower Clamping Diode
5
60
55
VCC = 5 V
0
–5
I F – Forward Current – mA
I F – Forward Current – mA
50
45
40
35
30
25
20
15
–10
–15
–20
–25
–30
–35
–40
–45
10
–50
5
–55
0
5.5
VCC = 5 V
6
6.5
7
7.5
VI – Input Voltage – V
8
8.5
9
–60
–2
–1.75 –1.5 –1.25
–1 –0.75 –0.5 –0.25
0
VI – Input Voltage – V
Figure 11. Diode Characteristics (SN74ACT107x)
4–63
TI also offers the bus-hold circuit as a feature added to some of the advanced-family drivers and receivers. This circuit is similar
to the stand-alone circuit, with a diode added to the drain of the second inverter (ABT and LVT only, see Figure 12). The diode
blocks the overshoot current when the input voltage is higher than VCC (VI > VCC), so only the leakage current is present. This
circuit uses the device’s input stage as its first inverter; a second inverter creates the feedback feature. The calculation of the
maximum number of components that the bus-hold circuit can handle is similar to the previous example. However, the
advantage of this circuit over the stand-alone bus-hold circuit is that it eliminates the need for external components or resistors
that occupy more area on the board. This becomes critical for some designs, especially when wide buses are used. Also, because
cost and board-dimension restrictions are a major concern, designers prefer the easy fix: drop-in replaceable parts. TI offers
this feature in most of the commonly used functions in several families (refer to Table 1 for more details).
ABT/LVT Family
Input
ALVC/LVC Family
Bus Hold
Bus Hold
VCC
VCC
Input
1 kΩ
1 kΩ
VCC
VCC
Input Stage
Input Stage
Figure 12. Input Structure of ABT/LVT and ALVC/LVC Families With Bus-Hold Circuit
Figure 13 shows the input characteristics of the bus-hold circuit at 3.3-V and 5-V operations, as the input voltage is swept from
0 to 5 V. These characteristics are similar in behavior to a weak driver. This driver sinks current into the part when the input
is low and sources current out of the part when the input is high. When the voltage is near the threshold, the circuit tries to switch
to the other state, always keeping the input at a valid level. This is the result of the internal feedback circuit. The plot also shows
that the current is at its maximum when the input is near the threshold. II(hold) maximum is approximately 25 µA for 3.3-V
input and 400 µA for 5-V input.
4–64
300
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
VCC = 2.7 V
250
I I(hold) – Hold Current – µ A
200
150
100
50
0
–50
–100
–150
–200
–250
–300
0
1
2
3
4
VO – Output Voltage – V
I I(hold) – Hold Current – µ A
400
VCC = 5.5 V
VCC = 5 V
VCC = 4.5 V
250
100
–50
–200
–350
–500
0
1
2
3
4
5
VI – Input Voltage – V
Figure 13. Bus-Hold Input Characteristics
When multiple devices with bus-hold circuits are driven by a single driver, there may be some concern about the ac switching
capability of the driver becoming weaker. As small drivers, bus-hold circuits require an ac current to switch them. This current
is not significant when using TI CMOS and BiCMOS families. Figure 14 shows a 4-mA buffer driving six LVTH16244
devices. The trace is a 75-Ω transmission line. The receivers are separated by 1cm, with the driver located in the center of the
trace. Figure 15 shows the bus-hold loading effect on the driver when connected to six receivers switching low or high. It also
shows the same system with the bus-hold circuit disconnected from the receivers. Both plots show the effect of bus hold on
the driver’s rise and fall times. Initially, the bus-hold circuit tries to counteract the driver, causing the rise or fall time to increase.
Then, the bus-hold circuit changes states (note the crossover point), which helps the driver switch faster, decreasing the rise
or fall time.
4–65
Figure 14. Driver and Receiver System
Driver Switching From High to Low
Driver Switching From Low to High
3
3
VCC = 3.3 V
TA = 25°C
VO – Output Voltage – V
VO – Output Voltage – V
Receivers:
With Bus Hold
Without Bus Hold
2
Bus Hold Switched
1
2
Bus Hold Switched
1
Receivers:
With Bus Hold
Without Bus Hold
VCC = 3.3 V
TA = 25°C
0
10
20
30
40
50
Time – ns
60
70
0
105
80
110
115
120
125
Time – ns
130
135
140
Figure 15. Output Waveforms of Driver With and Without Receiver Bus-Hold Circuit
Figure 16 shows the supply current (ICC) of the bus-hold circuit as the input is swept from 0 to 5 V. The spike at about 1.5-V
VI is due to both the n-channel and the p-channel conducting simultaneously. This is one of the CMOS
transistor characteristics.
5
VCC = 5 V
I CC – Supply Current – mA
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VI – Input Voltage – V
Figure 16. Bus-Hold Circuit Supply Current Versus Input Voltage
4–66
The power consumption of the bus-hold circuit is minimal when switching the input at higher frequencies. Figure 17 shows
the power consumed by the input at different frequencies, with or without bus hold. The increase in power consumption of the
bus-hold circuit at higher frequencies is not significant enough to be considered in power calculations.
Power Plot of the Input With Bus Hold
0
VCC = 5.5 V
10 MHz
20 MHz
40 MHz
50 MHz
2
Power – mW
4
100 MHz
6
8
10
12
14
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Switching Time - µs
Power Plot of the Input Without Bus Hold
0
VCC = 5.5 V
10 MHz
20 MHz
40 MHz
50 MHz
2
Power – mW
4
100 MHz
6
8
10
12
14
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Switching Time - µs
Figure 17. Input Power With and Without Bus Hold at Different Frequencies
4–67
Figure 18 shows the data-sheet dc specifications for bus hold. The first test condition is the minimum current required to hold
the bus at 0.8 V or 2 V. These voltages meet the specified low and high levels for TTL inputs. The second test condition is the
maximum current that the bus-hold circuit sources or sinks at any input voltage between 0 V and 3.6 V (for low-voltage
families) or between 0 V and 5.5 V (for ABT). The bus-hold current becomes minimal as the input voltage approaches the rail
voltage. The output leakage currents, IOZH and IOZL, are insignificant for transceivers with bus hold because a true leakage
test cannot be performed due to the existence of the bus-hold circuit. Because the bus-hold circuit behaves as a small driver,
it tends to source or sink a current that is opposite in direction to the leakage current. This situation is true for transceivers with
the bus-hold feature only and does not apply to buffers. All LVT, ABT Widebus+, and selected ABT octal and Widebus devices
have the bus-hold feature (refer to Table 1 or contact the local TI sales office for more information).
electrical characteristics over recommended operating free-air temperature range (for families
with bus-hold feature)†
PARAMETER
II(hold)
Data inputs
or I/Os
LVT, LVC, ALVC
VCC = 3 V
LVC, ALVC
VCC = 3.6 V,
ABT Widebus+ and
selected ABT
Transceivers
with bus hold
IOZH/IOZL
Buffers
with bus hold
TEST CONDITIONS
ABT
LVT, LVC, ALVC
ABT
LVT, LVC, ALVC
VCC = 4.5 V
MIN
VI = 0.8 V
VI = 2 V
–75
VI = 0 to 3.6 V
VI = 0.8 V
100
VI = 2 V
MAX
UNIT
±500
µA
75
–100
This test is not a true IOZ test because bus
hold always is active on an I/O pin. Bus hold
tends to supply a current that is opposite in
direction to the output leakage current.
This test is a true IOZ test since bus hold does
not exist on an output pin.
±
±1
µA
±10
±5
† Refer to the latest TI data sheets for device specifications.
Figure 18. Example of Data-Sheet Minimum Specification for Bus Hold
Summary
Floating inputs and slow rise and fall times are important issues to consider when designing with CMOS and advanced
BiCMOS families. It is important to understand the complications associated with floating inputs. Terminating the bus properly
plays a major role in achieving reliable systems. The three methods recommended in this application report should be
considered. If it is not possible to control the bus directly, and adding pullup or pulldown resistors is impractical due to
power-consumption and board-space limitations, bus hold is the best choice. TI designed bus hold to reduce the need for
resistors used in bus designs, thus reducing the number of components on the board and improving the overall reliability of
the system.
4–68
General Information
Widebus
Widebus+
Application Reports
Mechanical Data
5–1
Contents
Page
Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
DBB (R-PDSO-G**) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
DGG (R-PDSO-G**) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
DGV (R-PDSO-G**) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
GKE (R-PBGA-N96) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
GKF (R-PBGA-N114) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Mechanical Data
5–2
ORDERING INSTRUCTIONS
Electrical characteristics presented in this data book, unless otherwise noted, apply for the circuit type(s) listed in the
page heading, regardless of package. The availability of a circuit function in a particular package is denoted by an
alphabetical reference above the pin-connection diagram(s). These alphabetical references refer to mechanical
outline drawings shown in this section.
Factory orders for circuits described in this data book should include a three-part type number as explained in the
following example.
EXAMPLE:
Prefix
SN
SN
74AVC245
DGV
R
= Standard prefix
Unique Circuit Description
MUST CONTAIN SIX TO ELEVEN CHARACTERS
Examples: 74AVC16244
74AVCH16373
Package
MUST CONTAIN ONE TO THREE LETTERS
DBB, DGV (or V) = plastic thin very small-outline package (TVSOP)†
DGG (or G)
= plastic thin shrink small-outline package (TSSOP)†
GKE, GKF
= MicroStar BGA low-profile fine-pitch ball grid array (LFBGA)
(from pin-connection diagram on individual data sheet)
Tape-and-Reel Packaging
Valid for surface-mount packages only. All orders for tape and reel must be for whole reels.
R = Standard tape and reel [required for DGG (or G) and DGV (or V)]‡
The purpose of tape-and-reel packing is to position components so they can be placed automatically.
Components such as, but not limited to, diodes, capacitors, resistors, transistors, inductors, and integrated
circuits can be packed in this manner.
The packing materials include a carrier tape, cover tape, and a reel. The normal dimensions for these items
are listed in Table 1.
† TI is changing the nomenclature for select logic devices. For details, see Device Names and Package Designators in Section 1.
‡ All reeled material previously designated LE will continue to be reeled left embossed, but an R designator will be used.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5–3
ORDERING INSTRUCTIONS
Table 1. Normal Dimensions of Packing Materials
CARRIER-TAPE
WIDTH
(mm)
COVER-TAPE
WIDTH
(mm)
REEL
WIDTH
(mm)
REEL
DIAMETER
(mm)
8
5.4
9.0
178
12
9.2
12.4
330
16
13.3
16.4
330
24
21.0
24.4
330
32
25.5
32.4
330
44
37.5
44.4
330
56
49.5
56.4
330
All material meets or exceeds industry guidelines for ESD protection.
Dimensions are selected based on package size and design configurations. All dimensions are established to be
within the recommendations of the Electronics Industry Association Standard EIA-481-1,2,3.
Common dimensions of particular interest to the end user are carrier-tape width, pocket pitch, and quantity per reel
(see Figure 1 and Table 2).
1
Direction
of Feed
Width
Pocket/Component Pitch
(Center to Center of Pocket)
Trailer
(No Components)
400
340
Components
Leader
(No Components)
As Required
for Component Count
Figure 1. Typical Carrier-Tape Design
5–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
560
500
ORDERING INSTRUCTIONS
Table 2. Selected Tape-and-Reel Specifications
NO. OF
PINS
CARRIER-TAPE
WIDTH
(mm)
POCKET
PITCH
(mm)
QTY/REEL
GKE
96
24.00
8.00
1000
GKF
114
24.00
8.00
1000
DGG
48
24.00
12.00
2000
DBB
80
24.00
12.00
2000
14
16.00
8.00
2000
16
16.00
8.00
2000
20
16.00
8.00
2000
48
16.00
8.00
2000
PACKAGE
LFBGA
TSSOP
TVSOP
DGV
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5–5
MECHANICAL DATA
DBB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
80 PINS SHOWN
0,23
0,13
0,40
80
0,07 M
41
6,20
6,00
8,40
7,80
0,16 NOM
1
Gage Plane
40
A
0,25
0°–ā12°
0,75
0,50
Seating Plane
1,20 MAX
0,08
0,15
PINS**
80
100
A MAX
17,10
20,90
A MIN
16,90
20,70
DIM
4040212 / D 03/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. The 80-pin package falls within JEDEC MO-153 and the 100-pin package falls within JEDEC MO-194.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5–7
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
5–8
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
48
56
A MAX
3,70
3,70
5,10
5,10
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
9,60
11,20
DIM
4073251/C 08/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5–9
MECHANICAL DATA
GKE (R-PBGA-N96)
PLASTIC BALL GRID ARRAY
5,60
5,40
4,00 TYP
0,80
0,40
12,00 TYP
0,40
13,60
13,40
0,80
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08 M
0,45
0,35
0,10
4188953/A 10/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
MicroStar BGA is a trademark of Texas Instruments Incorporated.
5–10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
GKF (R-PBGA-N114)
PLASTIC BALL GRID ARRAY
4,00 TYP
5,60
5,40
0,80
0,40
16,10
15,90
0,80
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
14,40 TYP
1 2 3 4 5 6
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08 M
0,45
0,35
0,10
4188954/A 10/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
MicroStar BGA is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5–11
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2002, Texas Instruments Incorporated
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