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Texas Instruments CYFCT Parameter Measurement Information User guides
CYFCT Parameter Measurement Information
SCCU001 – APRIL 2001
features
D
D
D
D
D
D
D
Function, Pinout, Speed, and Drive
Compatible With F Logic
All Products Capable of Live Insertion
All Products Meet FCT Logic JEDEC
Standard No. 8A
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Power-Off Disable Feature on All Families
Matched Output Signal Rise and Fall Times
CMOS for Low Power Consumption:
Typically 1/3 of the Fastest Advanced
Schottky TTL Logic
D
D
D
D
D
D
Inputs and Outputs Interface Directly With
TTL, NMOS, and CMOS Devices
Typically 64-mA Sink and 32-mA Source
Drive Capability
3-State Outputs on Most Devices
Operational Over the Full Commercial and
Military Temperature Ranges (Octal)
Industrial Temperature Range of –40_C to
85_C (16-Bit Family)
Products Available to Latest Revision of
MIL-STD-833 Class B Compliance
functional description
introduction
The CYxxFCT-T logic families acquired from Cypress offer the lowest power solution for the design of
high-speed systems. All logic families are TTL compatible, which means that they conform to the
industry-standard TTL voltage levels and TTL threshold point of 1.5 V. All inputs have hysteresis. The benefit
to the user is increased static and dynamic noise immunity, as well as less sensitivity to noise superimposed
on slowly rising or falling inputs.
the original FCT
The outputs of the original (non-Cypress) FCT family swung rail-to-rail, i.e., from VOL = 0.4 V to
VOH = VCC – 0.2 V. The data sheets specify VOH minimum as 2.4 V when sourcing 15 mA and typical as 4.3 V.
The output pullup transistor is a p-channel device. Typical unloaded output signal rise and fall times are 1 ns.
CYxxFCT-T from Cypress
The new, 5-V VCC CYxxFCT-T logic families feature output buffers that use n-channel pullup transistors and
controlled rise- and fall-time edge rates. Typical unloaded output signal rise and fall times are 1 ns. The
maximum unloaded output high voltage, VOH, is VCC minus the n-channel threshold, VT. The transistor drain
is connected to VCC, so VT is approximately 1 V. The loaded VOH typically is 3.3 V when sourcing 15 mA with
a VCC of 5 V.
The reduced output voltage swing of CYxxFCT-T results in lower crosstalk. The controlled edge rates reduce
crosstalk, as well as ground bounce and, in addition, reduce output signal overshoot and undershoot.
These products have no diodes from input pins, output pins, or I/O pins to VCC. This means that they all are
capable of being inserted or withdrawn from operating systems without turning off the power.
These logic families produced by Cypress operate from a 5-V power source. The products consist of octals (8-bit
data path), either with high-drive (source 32 mA/sink 64 mA) or 25-Ω (output) series resistors, and 16-bit-wide
data-path products, either with high-drive or balanced-drive (24-mA source/sink) outputs. Some of these
products have bus-hold inputs.
Copyright  2001, Texas Instruments Incorporated
1
CYFCT Parameter Measurement Information
octal CYxxFCT; 5-V, high-drive, and 25-Ω outputs
This high-drive octal family consists of multiple logic functions. The CYxxFCT2-T logic family is identical to the
CYxxFCT-T logic family, except that the CYxxFCT2-T devices have the equivalent of a 25-Ω resistor in series
with the output. The purpose of the resistor is to provide series damping when driving a transmission line. These
products with series damping resistors should be used only when driving lumped (single) loads, and should not
be used for driving multiple or distributed loads.
16-bit CYxxFCT; 5-V, high-drive, and balanced-drive outputs
The CYxxFCT16-T logic family is a 16-bit version of the CYxxFCT-T family. The temperature range of the family
has been extended to –40_C to 85_C, and VCC tolerance has been loosened to ±10%. Multiple power and
grounds have been added to reduce typical ground bounce to below 0.6 V.
The CYxxFCT162-T logic family is a 24-mA balanced-drive version of the CYxxFCT16-T family, and is intended
for use in driving transmission lines. The dynamic output current is specified as ±60 mA at 1.5 V, which means
that the output impedance is a maximum of 25 Ω.
bus hold
Bus hold is the ability of either an input (data) pin or an I/O pin to retain the last valid logic state (voltage level)
after the source driving it either enters the high-impedance state or is removed. Bus hold is available on some
16-bit, 5-V, balanced-drive products. An example part number with bus hold is CY74FCT162H245TPA.
switching characteristics
The circuit shown in Figure 1 is used to load each output for specifying and measuring device propagation
delays. It is a de facto industry standard and does not represent device behavior in any application.
The switch is open for all measurements except those having to do with the outputs entering or leaving the
high-impedance state as a result of a control input changing.
These conditions are illustrated in Figures 7 and 8. The parameter tPZL is the amount of time it takes an output
to go from the high-impedance state to a low state. The parameter tPLZ is the amount of time it takes an output
to go from the low state to the high-impedance state; defined as 300 mV above VOL. The parameter tPZH is the
amount of time it takes an output to go from a high-impedance state to the high state. The parameter tPHZ is
the amount of time it takes an output to go from a high state to the high-impedance state, defined as 300 mV
below VOH.
Figures 2–9 illustrate the various propagation delay, setup times, and hold times that are referred to in the
switching-characteristics section of the various data sheets. Note that, except for entering the high-impedance
state, all measurements are made between the 1.5-V amplitude voltage levels.
Figure 10 shows the input waveform amplitude levels recommended for ac testing of CYFCT-T logic products.
Input signals should have maximum rise and fall times of 1 ns and signal swings of 0 to 3 V. Input signals with
rise and fall times of 1 ns should be used for testing minimum pulse width or maximum frequency.
When performing ac tests, care must be taken to ensure that the input signals do not return to the transition
region due to signal overshoot or undershoot. The load capacitor should be a leaderless chipcap. If this is not
possible, keep the leads as short as possible to avoid signal overshoot and undershoot due to lead inductance.
The same reasoning applies to the load resistors and power-supply decoupling and filtering capacitors. Solid
grounding is required, and a ground plane is recommended.
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CYFCT Parameter Measurement Information
power specifications
CYxxFCT-T logic devices do not use a substrate bias generator. As a result, the quiescent or standby current
typically is a few microamperes when the voltage at the inputs is either less than 0.2 V or greater than
VCC – 0.2 V. On the data sheet, this current is described as quiescent power supply current, given the symbol
ICC, and specified on a per-IC basis. No inputs are switching, and all outputs are open and, if possible, disabled.
When the input signal transitions between the logic levels, both the p-channel pullup transistor and the
n-channel pulldown transistor in the input TTL-to-CMOS translator are partially turned on, which creates a
low-impedance path between VCC and ground. On the data sheet, this current is described as “quiescent power
supply current (TTL inputs),” given the symbol ∆ICC, and specified on a per-input basis. One input is VIN = 3.4 V,
other inputs are at either VCC or 0 V, and all outputs are open and, if possible, disabled.
The dynamic power supply current, given the symbol ICCD, is not measured directly, but is provided so that the
user can calculate total current. It is specified in mA per MHz at 50% duty cycle, with one input toggling and one
output toggling [enabled but open (unloaded)].
The preceding three currents are specified with the outputs open. The ac CVf current required to charge and
discharge parasitic capacitances (e.g., other inputs being driven by the outputs), as well as any dc load currents,
must be calculated separately.
Total supply current, IC, is specified on the data sheet for several different conditions. The inputs are switched
between ground and either TTL (3.4 V) or CMOS (VCC – 0.2 V) levels with rise and fall times of 2.5 ns. Slow
rise and fall times can cause the dynamic current to increase, because the input signals are within the transition
region for longer times. Figure 14 shows a characterization curve of normalized (ICC/∆ICC) currents versus VIN.
Total supply current can be estimated by using the following formula. This equation implies calculating the
current associated with each input and adding them up. The same procedure must be followed to calculate the
CVf current required to charge and discharge the load capacitances.
IC = ICC + ∆ICC x DH x NT + ICCD (fcp/2 + fn x Nn)
Where:
IC
ICC
DH
NT
ICCD
fCP
fn
Nn
= Total supply current
= Power supply current for a TTL high input (VIN = 3.4 V)
= Duty cycle for TTL inputs high
= Number of TTL inputs at DH
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise 0
= Input signal frequency
= Number of inputs changing at fn
3
CYFCT Parameter Measurement Information
ESD (electrostatic discharge) precautions
Large electrical fields can damage the thin gate oxides of MOS transistors. Special input protection circuits are
used at every input pin of all CYxxFCT-T products to provide protection against ESD. This circuitry has been
designed to withstand repeated applications of high voltages without failure or performance degradation. This
is accomplished by preventing the high voltage (ESD) from reaching the thin gate oxides of the internal
transistors.
Precautions should be taken by persons handling CMOS devices. Individuals should wear a grounded wrist
strap or ankle strap when handling these devices.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Static discharge voltage (per MIL-STD-883, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2001 V
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: Unused inputs always must be connected to an appropriate logic voltage level, preferably either VCC or ground.
OPERATING RANGE CYxxFCT-T, CYxxFCT2-T
PRODUCT
SUFFIX
AMBIENT
TEMPERATURE
VCC
T, AT, BT
–40°C to 85°C
5 V ± 5%
All
–55°C to 125°C
† TA is the instant-on case temperature.
5 V ± 10%
RANGE
Industrial
Military†
OPERATING RANGE
4
PRODUCT
NAME
RANGE
AMBIENT
TEMPERATURE
VCC
CYxxFCT16-T
Industrial
–40°C to 85°C
5 V ± 5%
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CYFCT Parameter Measurement Information
7V
Open
tPZL, tPLZ
All Other
VIN
500 Ω
DUT
1.5 V
1.5 V
tPHL
tPLH
500 Ω
CL = 50 pF
1.5 V
VOUT
1.5 V
Param-2
Param-1
Figure 1. Test Load
1.5 V
VIN
1.5 V
tPLH
1.5 V
VOUT
Figure 2. Waveform for Inverting Functions
VIN
1.5 V
1.5 V
1.5 V
th(L)
tPHL
1.5 V
ts(H)
ts(L)
1.5 V
th(H)
1.5 V
CP
1.5 V
Param-3
Figure 3. Waveform for Noninverting Functions
Param-4
Figure 4. Setup and Hold Times, Rising-Edge Clock
tw
MR
1.5 V
1.5 V
MR
tPHZ
or CP
1.5 V
1.5 V
1.5 V
CP or LE
tw(H)
tPHL
VOUT
1.5 V
tPLH
1.5 V
tPLH
VIN
1.5 V
tPHL
VOUT
tPHL
1.5 V
Param-6
Figure 5. Propagation Delays From
Rising-Edge Clock or Enable
1.5 V
1.5 V
tPLH
VOUT
1.5 V
Param-10
Figure 6. Asynchronous Reset,
Active Rising-Edge Clock, or Active Low Enable
5
CYFCT Parameter Measurement Information
VE
1.5 V
1.5 V
VE
VE
1.5 V
tPZL
1.5 V
VE
tPLZ
tPZH
VOUT
tPHZ
1.5 V
VOL
0.3 V
0.3 V
Param-8
Param-5
Figure 7. Three-State Output Low
Enable and Disable Times
Figure 8. Three-State Output High
Enable and Disable Times
1.5 V
VIN
1.5 V
1.5 V
ts(L)
1.5 V
ts(H)
th(L)
th(H)
1.5 V
LE
1.5 V
Param-7
Figure 9. Setup and Hold Times to Active-High Enable or Parallel Load
5.0 V
4.0 V
AC High Level
3.0 V
DC High-Level Range
2.4 V
2.0 V
High-Level Notes Margin
Transition Area
0.8 V
0.5 V
Low-Level Notes Margin
DC Low-Level Range
0V
AC Test
DC Test
VIL = 0.8 V; VIN = 2 V
VOL = 0.5 V; VOH = 2.4 V
NoiseImmunity
Test
AC Low Level
Figure 10. Input Signal Levels
6
VOH
1.5 V
VOUT
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Param-9
CYFCT Parameter Measurement Information
–80
25°C
–70
80°C
I OH (mA)
–60
–50
–40
125°C
–30
–20
–10
0
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25 3.50
VOH(V)
Param-11
Figure 11. Output Source Current vs Output Voltage
Normalized Propagation Delay
1.20
TA = 25° C
1.15
tPLH
1.10
tPHL
1.05
1.00
0.95
0.90
0.85
0.80
4.50
4.75
5.00
VCC(V)
5.25
5.50
Param-12
Figure 12. Normalized Propagation Delay vs VCC
Normalized Propagation Delay
1.40
tPHL
VCC = 5 V
1.20
1.00
tPLH
tPLH
0.80
0.60
tPHL
0.40
0.20
0.00
0
15
30
50
Capacitive Load (pF)
100
Param-14
Figure 13. Normalized Propagation Delay vs Output Loading
7
CYFCT Parameter Measurement Information
ICC/∆ICC
1.4
Temperature
VCC = 5.5 V
TA = 25°C
1.2
I CC / ∆I CC
1.0
0.8
0.6
0.4
0.2
0.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2
VIN(V)
Param-16
Figure 14. Normalized Current vs Input Voltage
Normalized Propagation Delay
1.04
VCC = 5 V
1.03
tPLH
1.02
1.01
tPHL
tPHL
1.00
0.99
0.98
0.97
25°C
tPLH
80°C
Temperature
125°C
Param-13
Figure 15. Normalized Propagation Delay vs Temperature
140
25°C
120
I OL(mA)
100
80
80°C
60
125°C
40
20
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60
VOL(V)
Param-15
Figure 16. Output Sink Current vs Output Voltage
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Copyright  2001, Texas Instruments Incorporated
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