Texas Instruments | DRV887x-Q1 H-Bridge Motor Drivers With Integrated Current Sense and Regulation | Datasheet | Texas Instruments DRV887x-Q1 H-Bridge Motor Drivers With Integrated Current Sense and Regulation Datasheet

Texas Instruments DRV887x-Q1 H-Bridge Motor Drivers With Integrated Current Sense and Regulation Datasheet
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DRV8876-Q1
SLVSDS6 – OCTOBER 2018
1 Features
3 Description
•
•
The DRV887x-Q1 family of devices are flexible motor
drivers for a wide variety of end applications. The
devices integrate an N-channel H-bridge, charge
pump regulator, current sensing and regulation,
current proportional output, and protection circuitry.
The charge pump improves efficiency by allowing for
both high-side and low-side N-channels MOSFETs
and 100% duty cycle support. The family of devices
come in pin to pin, scalable RDS(on) options to support
different loads with minimal design changes.
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C4B
N-Channel H-Bridge Motor Driver
– Drives One Bidirectional Brushed DC Motor
– Two Unidirectional Brushed DC Motors
– Other Resistive and Inductive Loads
4.5-V to 37-V Operating Supply Voltage Range
Pin to Pin RDS(on) Variants
– DRV8876-Q1: 700-mΩ (High-Side + Low-Side)
High Output Current Capability
– DRV8876-Q1: 3.5-A Peak
Integrated Current Sensing and Regulation
Proportional Current Output (IPROPI)
Selectable Current Regulation (IMODE)
– Cycle-By-Cycle or Fixed Off Time
Selectable Input Control Modes (PMODE)
– Multiple H-Bridge Control Modes
– Independent Half-Bridge Control Mode
Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
Ultra Low-Power Sleep Mode
– <1-µA @ VVM = 24-V, TJ = 25°C
Spread Spectrum Clocking For Low
Electromagnetic Interference (EMI)
Integrated Protection Features
– Undervoltage Lockout (UVLO)
– Charge Pump Undervoltage (CPUV)
– Overcurrent Protection (OCP)
– Thermal Shutdown (TSD)
– Automatic Fault Recovery
– Fault Indicator Pin (nFAULT)
The devices support a variety of motor control
methods through the PMODE and IMODE pins.
These hardware configurable options allow the
designer to select the PWM input mode and current
regulation scheme.
Integrated current sensing allows for the motor driver
to regulate the motor current during start up and high
load events. The current limit can be set with an
external voltage reference. Additionally, the devices
provide an output current proportional to the motor
load current. This can be used to detect motor stall or
change in load conditions.
A low-power sleep mode is provided to achieve ultralow quiescent current draw by shutting down most of
the internal circuitry. Internal protection features are
provided for supply undervoltage lockout (UVLO),
charge
pump
undervoltage
(CPUV),
output
overcurrent (OCP), and device overtemperature
(TSD). Fault conditions are indicated on nFAULT.
Table 1. Device Information
PART NUMBER
DRV8876-Q1
PACKAGE
HTSSOP (16)
(1)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2 Applications
•
•
•
•
•
•
Brushed DC Motors
Servo Motors and Actuators
HVAC Damper
Siren and Piezo
Mirror Tilt and Fold
E-Shifter Adjust and Lock
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
DRV887x-Q1 H-Bridge Motor Drivers With Integrated Current Sense and Regulation
DRV8876-Q1
SLVSDS6 – OCTOBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
5
5
9
Power Supply Recommendations...................... 21
9.1 Bulk Capacitance .................................................... 21
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description .............................................. 7
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings Auto .....................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 16
Overview ................................................................... 7
Functional Block Diagram ......................................... 7
Feature Description................................................... 8
Device Functional Modes........................................ 14
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
12.1 Package Option Addendum .................................. 25
Application and Implementation ........................ 16
ADVANCE INFORMATION
4 Revision History
2
DATE
REVISION
NOTES
OCT 2018
*
Initial release.
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DRV8876-Q1
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SLVSDS6 – OCTOBER 2018
5 Pin Configuration and Functions
EN/IN1
1
16
PMODE
PH/IN2
2
15
GND
nSLEEP
3
14
CPL
nFAULT
4
13
CPH
VREF
5
12
VCP
IPROPI
6
11
VM
IMODE
7
10
OUT2
OUT1
8
9
PGND
Thermal
Pad
ADVANCE INFORMATION
DRV8876-Q1 PWP Package
16-Pin HTSSOP With Exposed Thermal Pad
Top View
Pin Functions
PIN
NAME
TYPE (1)
DESCRIPTION
RGT
PWP
CPH
n/a
13
PWR
CPL
n/a
14
PWR
EN/IN1
n/a
1
I
GND
n/a
15
PWR
IMODE
n/a
7
I
Current regulation and overcurrent protection mode. See Current Regulation. Quadlevel input.
IPROPI
n/a
6
O
Analog current output proportional to load current. See Current Sensing.
nFAULT
n/a
4
OD
nSLEEP
n/a
3
I
Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep
mode. See Device Functional Modes. Internal pulldown resistor.
OUT1
n/a
8
O
H-bridge output. Connect to the motor or other load.
OUT2
n/a
10
O
H-bridge output. Connect to the motor or other load.
PGND
n/a
9
PWR
PH/IN2
n/a
2
I
H-bridge control input. See Control Modes. Internal pulldown resistor.
PMODE
n/a
16
I
H-bridge control input mode. See Control Modes. Tri-level input.
VCP
n/a
12
PWR
Charge pump output. Connect a X5R or X7R, 100-nF, 16-V ceramic capacitor
between the VCP and VM pins.
VM
n/a
11
PWR
4.5-V to 37-V power supply input. Connect a 0.1-µF bypass capacitor to ground, as
well as sufficient bulk capacitance rated for VM.
VREF
n/a
5
I
External reference voltage input to set internal current regulation limit. See Current
Regulation.
PAD
n/a
—
—
(1)
Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic
capacitor between the CPH and CPL pins.
H-bridge control input. See Control Modes. Internal pulldown resistor.
Device ground. Connect to system ground.
Fault indicator output. Pulled low during a fault condition. Connect an external pullup
resistor for open-drain operation. See Protection Circuits.
Device power ground. Connect to system ground.
Thermal pad. Connect to system ground.
PWR = power, I = input, O = output, NC = no connection, OD = open-drain
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted) (1)
Power supply pin voltage
VM
Voltage difference between ground pins
GND, PGND
Charge pump pin voltage
CPH, VCP
Charge pump low-side pin voltage
Logic pin voltage
MIN
MAX
–0.3
40
UNIT
V
–0.3
0.3
V
VVM – 0.3
VVM + 7
V
CPL
–0.3
VVM + 0.3
V
EN/IN1, IMODE, nSLEEP, PH/IN2,
PMODE
–0.3
5.75
V
nFAULT
–0.3
5.75
V
OUT1, OUT2
–0.9
VVM + 0.9
V
Output pin current
OUT1, OUT2
Internally
Limited
Internally
Limited
A
Proportional current output pin voltage
IPROPI
–0.3
5.75
V
–0.3
VVM + 0.3
V
Reference input pin voltage
VREF
–0.3
5.75
V
Ambient temperature, TA
–40
125
°C
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Open-drain output pin voltage
Output pin voltage
ADVANCE INFORMATION
(1)
(2)
(2)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Errata: On the "P" prototype version samples, the voltage on the OUT1 and OUT2 pins should be limited to 5.5 V when the device is in
low-powered sleep mode (nSLEEP = LO). This will be corrected when the final version samples are available.
6.2 ESD Ratings Auto
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged device model (CDM), per AEC Q100-011
UNIT
±2000
Corner pins
±750
Other pins
±500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
VVM
Power supply voltage
VM
VIN
Logic input voltage
fPWM
VOD
IOD
IOUT
(1)
NOM
MAX
UNIT
4.5
37
V
EN/IN1, MODE, nSLEEP, PH/IN2
0
5.5
V
PWM frequency
EN/IN1, PH/IN2
0
100
kHz
Open drain pullup voltage
nFAULT
0
5.5
Open drain output current
nFAULT
0
5
V
mA
Peak output current
DRV8876-Q1, OUT1, OUT2
0
3.5
IIPROPI
Current sense output current
IPROPI
0
3
VVREF
Current limit reference voltage
VREF
0
3.6
V
TA
Operating ambient temperature
–40
125
°C
TJ
Operating junction temperature
–40
150
°C
(1)
4
A
mA
Power dissipation and thermal limits must be observed
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6.4 Thermal Information
DRV8876-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
44.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
38.3
°C/W
RθJB
Junction-to-board thermal resistance
20.5
°C/W
ΨJT
Junction-to-top characterization parameter
1.0
°C/W
ΨJB
Junction-to-board characterization parameter
20.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
4.5 V ≤ VVM ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.75
1
µA
5
µA
7
mA
1
ms
1
ms
IVMQ
VM sleep mode current
VVM = 13.5 V, nSLEEP = 0 V, TJ =
25°C
nSLEEP = 0 V
IVM
VM active mode current
VVM = 13.5 V, nSLEEP = 5 V, EN/IN1 =
PH/IN2 = 0 V
tWAKE
Turnon time
VVM > VUVLO, nSLEEP = 5 V to
active mode
tSLEEP
Turnoff time
nSLEEP = 0 V to sleep mode
VVCP
Charge pump regulator voltage
VCP with respect to VM, VVM = 13.5 V
fVCP
Charge pump switching frequency
4
5
ADVANCE INFORMATION
POWER SUPPLIES (VCP, VM)
V
400
kHz
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP)
VIL
Input logic low voltage
VIH
Input logic high voltage
VHYS
Input hysteresis
IIL
VVM < 5 V
0
0.7
VVM ≥ 5 V
0
0.8
1.5
5.5
150
V
V
mV
nSLEEP
35
Input logic low current
VI = 0 V
–5
mV
IIH
Input logic high current
VI = 5 V
50
RPD
Input pulldown resistance
To GND
100
5
µA
75
µA
kΩ
TRI-LEVEL INPUTS (PMODE)
VTIL
Tri-level input logic low voltage
0
VTIZ
Tri-level input Hi-Z voltage
0.9
VTIH
Tri-level input logic high voltage
1.5
VTHYS
Tri-level input hysteresis
180
ITIL
Tri-level input logic low current
VI = 0 V
ITIZ
Tri-level input Hi-Z current
VI = 1.1 V
ITIH
Tri-level input logic high current
VI = 5 V
RTPD
Tri-level pulldown resistance
RTPU
Tri-level pullup resistance
–50
1.1
0.65
V
1.2
V
5.5
V
mV
–32
–5
113
µA
5
µA
150
µA
44
kΩ
156
kΩ
QUAD-LEVEL INPUTS (IMODE)
VQI2
Quad-level input level 1
Voltage to set quad-level 1
RQI2
Quad-level input level 2
Resistance to GND to set quad-level 2
18.6
RQI3
Quad-level input level 3
Resistance to GND to set quad-level 3
57.6
VQI4
Quad-level input level 4
Voltage to set quad-level 4
Copyright © 2018, Texas Instruments Incorporated
0
2.5
0.45
V
20
21.4
kΩ
62
66.4
kΩ
5.5
V
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Electrical Characteristics (continued)
4.5 V ≤ VVM ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RQPD
Quad-level pulldown resistance
To GND
RQPU
Quad-level pullup resistance
To internal 5 V
MIN
TYP
MAX
UNIT
136
kΩ
68
kΩ
OPEN-DRAIN OUTPUTS (nFAULT)
VOL
Output logic low voltage
IOD = 5 mA
IOZ
Output logic high current
VOD = 5 V
–2
0.3
V
2
µA
DRIVER OUTPUTS (OUT1, OUT2)
RDS(on)_HS
RDS(on)_LS
High-side MOSFET on resistance
Low-side MOSFET on resistance
DRV8876-Q1, VVM = 13.5 V, IO = 1 A,
TJ = 25°C
350
420
mΩ
DRV8876-Q1, VVM = 13.5 V, IO = 1 A,
TJ = 150°C
525
660
mΩ
DRV8876-Q1, VVM = 13.5 V, IO = –1 A,
TJ = 25°C
350
420
mΩ
DRV8876-Q1, VVM = 13.5 V, IO = –1 A,
TJ = 150°C
525
660
mΩ
ADVANCE INFORMATION
VSD
Body diode forward voltage
ISD = 1 A
0.9
V
tRISE
Output rise time
VVM = 13.5 V, OUTx rising 10% to 90%
1
µs
tFALL
Output fall time
VVM = 13.5 V, OUTx falling 90% to 10%
1
µs
tPD
Input to output propagation delay
EN/IN1, PH/IN2 to OUTx
1.75
µs
tDEAD
Output dead time
Body diode conducting
750
ns
1000
µA/A
CURRENT SENSE AND REGULATION (IPROPI, VREF)
AIPROPI
Current mirror scaling factor
AERR
Current mirror scaling error
DRV8876-Q1
DRV8876-Q1, IOUT < 0.15 A
DRV8876-Q1, 0.15 A ≤ IOUT < 0.5 A
DRV8876-Q1, 0.5 A ≤ IOUT ≤ 2 A
–7.5
7.5
–5
5
–3.5
3.5
mA
%
tOFF
Current regulation off time
25
µs
tDELAY
Current sense delay time
6
µs
tDEG
Current regulation deglitch time
1.7
µs
tBLK
Current regulation blanking time
2.7
µs
PROTECTION CIRCUITS
VVM rising
4.3
4.45
4.6
V
VVM falling
4.2
4.35
4.5
V
VUVLO
Supply undervoltage lockout (UVLO)
VUVLO_HYS
Supply UVLO hysteresis
tUVLO
Supply undervoltage deglitch time
VCPUV
Charge pump undervoltage lockout
VCP with respect to VM, VVCP falling
IOCP
Overcurrent protection trip point
DRV8876-Q1
5.5
A
tOCP
Overcurrent protection deglitch time
3
µs
tRETRY
Overcurrent protection retry time
2
ms
TTSD
Thermal shutdown temperature
THYS
Thermal shutdown hysteresis
6
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3.5
160
100
mV
10
µs
2.25
V
175
20
190
°C
°C
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SLVSDS6 – OCTOBER 2018
7 Detailed Description
7.1 Overview
The DRV887x-Q1 family of device also integrate output current sensing using current mirrors on the low-side
power MOSFETs. A proportional current is then sent out on the IPROPI pin and can be converted to a
proportional voltage using an external resistor (RIPROPI). The integrated current sensing allows the DRV887x-Q1
devices to limit the output current with a fixed off-time PWM chopping scheme and provide load information to
the external controller to detect change in load or stall conditions. The integrated current sensing out performs
traditional external shunt resistor sensing by providing current information even during the off-time slow decay
recirculating period and removing the need for an external power shunt resistor. The off-time PWM current
regulation level can be configured during motor operation through the VREF pin to limit the load current
accordingly to the system demands.
A variety of integrated protection features protect the device in the case of a system fault. These include
undervoltage lockout (UVLO), charge pump undervoltage (CPUV), overcurrent protection (OCP), and
overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin.
7.2 Functional Block Diagram
VM
VM
0.1 …F
VCP
VM
Gate Driver
VVCP
VVCP
0.1 …F
VCP
Charge
Pump
CPH
0.022 …F
HS
OUT1
VDD
CPL
LS
VDD
Internal
Regulator
GND
ISEN1
Power
Digital
Core
nSLEEP
VM
Gate Driver
VVCP
EN/IN1
HS
PH/IN2
PMODE
IMODE
OUT2
VDD
Control
Inputs
LS
3-Level
PGND
4-Level
VVCC
ISEN2
VVCC
RPU
VREF
Fault Output
+
IPROPI
IPROPI
Clamp
RIPROP
nFAULT
±
Current
Sense
ISEN1
ISEN2
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7
ADVANCE INFORMATION
The DRV887x-Q1 family of devices are brushed DC motor drivers that operate from 4.5 to 37-V supporting a
wide range of output load currents for various types of motors and loads. The devices integrate an H-bridge
output power stage that can be operated in different control modes set be the PMODE pin setting. This allows for
driving a single bidirectional brushed DC motor, two unidirectional brushed DC motors, or other output load
configurations. The devices integrate a charge pump regulator to support more efficient high-side N-channel
MOSFETs and 100% duty cycle operation. The devices operate off a single power supply input (VM) which can
be directly connected to a battery or DC voltage supply. The nSLEEP pin provides an ultra low power mode to
minimize current draw during system inactivity.
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7.3 Feature Description
7.3.1 Control Modes
The DRV887x-Q1 family of devices provide three modes to support different control schemes with the EN/IN1
and PH/IN2 pins. The control mode is selected through the PMODE pin with either logic low, logic high, or setting
the pin Hi-Z as shown in Table 2. The PMODE pin state is latched when the device is enabled through the
nSLEEP pin. The PMODE state can be changed by taking the nSLEEP pin logic low, waiting the tSLEEP time,
changing the PMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high.
Table 2. PMODE Functions
PMODE STATE
CONTROL MODE
PMODE = Logic Low
PH/EN
PMODE = Logic High
PWM
PMODE = Hi-Z
Independent Half-Bridge
The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive
modes. The device input pins can be powered before VM is applied with no issues. By default, the EN/IN1 and
PH/IN2 pins have an internal pulldown resistor to ensure the outputs are Hi-Z if no inputs are present.
ADVANCE INFORMATION
The sections below show the truth table for each control mode. Note that these tables do not take into account
the internal current regulation feature. Additionally, the DRV887x-Q1 family of device automatically handles the
dead-time generation when switching between the high-side and low-side MOSFET of a half-bridge.
Figure 1 describes the naming and configuration for the various H-bridge states.
VM
VM
1
OUT1
1 Forward drive
1 Reverse drive
2 Slow decay (brake)
22 Slow decay (brake)
1
3 High-Z (coast)
OUT2
3 High-Z (coast)
OUT1
OUT2
2
2
3
3
Forward
Reverse
Figure 1. H-Bridge Configurations
7.3.1.1 PH/EN Control Mode (PMODE = Logic Low)
When the PMODE pin is logic low on power up, the device is latched into PH/EN mode. PH/EN mode allows for
the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is
shown in Table 3.
8
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Table 3. PH/EN Control Mode
nSLEEP
EN
PH
OUT1
OUT2
0
X
X
Hi-Z
Hi-Z
DESCRIPTION
1
0
X
L
L
Brake, (Low-Side Slow Decay)
1
1
0
L
H
Reverse (OUT2 → OUT1)
1
1
1
H
L
Forward (OUT1 → OUT2)
Sleep, (H-Bridge Hi-Z)
7.3.1.2 PWM Control Mode (PMODE = Logic High)
When the PMODE pin is logic high on power up, the device is latched into PWM mode. PWM mode allows for
the H-bridge to enter the Hi-Z state without taking the nSLEEP pin logic low. The truth table for PWM mode is
shown in Table 4.
Table 4. PWM Control Mode
IN1
IN2
OUT1
OUT2
0
X
X
Hi-Z
Hi-Z
Sleep, (H-Bridge Hi-Z)
DESCRIPTION
1
0
0
Hi-Z
Hi-Z
Coast, (H-Bridge Hi-Z)
1
0
1
L
H
Reverse (OUT2 → OUT1)
1
1
0
H
L
Forward (OUT1 → OUT2)
1
1
1
L
L
Brake, (Low-Side Slow Decay)
7.3.1.3 Independent Half-Bridge Control Mode (PMODE = Hi-Z)
When the PMODE pin is Hi-Z on power up, the device is latched into independent half-bridge control mode. This
mode allows for each half-bridge to be directly controlled in order to support high-side slow decay or driving two
independent loads. The truth table for independent half-bridge mode is shown in Table 5.
Table 5. Independent Half-Bridge Control Mode
nSLEEP
INx
OUTx
0
X
Hi-Z
DESCRIPTION
1
0
L
OUTx Low-Side On
1
1
H
OUTx High-Side On
Sleep, (H-Bridge Hi-Z)
7.3.2 Current Sense and Regulation
The DRV887x-Q1 family of devices integrate current sensing, regulation, and feedback. These features allow for
the device to sense the output current without an external sense resistor or sense circuitry. This also allows for
the devices to limit the output current in the case of motor stall or high torque events and give detailed feedback
to the controller about the load current through a current proportional output.
7.3.2.1 Current Sensing
The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power
MOSFETs in the H-bridge scaled by AIPROPI. The IPROPI output current can be calculated by Equation 1.
IPROPI (μA) = (ILS1 + ILS2) (A) / AIPROPI (μA/A)
(1)
The current is measured by an internal current mirror architecture that removes the needs for an external power
sense resistor. Additionally, the current mirror architecture allows for the motor winding current to be sensed in
both the drive and brake low-side slow-decay periods allowing for continuous current monitoring in typical
bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed,
but the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and
measuring the current before switching back to coast mode again. In the case of independent PWM mode and
both low-side MOSFETs are carrying current, the IPROPI output will be the sum of the two low-side MOSFET
currents.
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The IPROPI pin can be connected to an external resistor (RIPROPI) to ground in order to generate a proportional
voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be
measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The
RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the
controller ADC is utilized. Additionally, the DRV887x-Q1 devices implements an internal IPROPI voltage clamp
circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC incase of output
overcurrent or unexpected high current events.
The corresponding IPROPI voltage to the output current can be calculated by Equation 2.
VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)
(2)
OUT
Control
Inputs
VREF
+
ILOAD
LS
±
GND
ADVANCE INFORMATION
IPROPI
Clamp
Integrated
Current Sense
MCU
ADC
IPROPI
+
VPROPI
±
RIPROPI
IPROPI
AIPROPI
Copyright © 2017, Texas Instruments Incorporated
Figure 2. Integrated Current Sensing
The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the DRV887x-Q1 internal current
sensing circuit. This time is the delay from the low-side MOSFET enable command to the IPROPI output being
ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the
low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI
output.
7.3.2.2 Current Regulation
The DRV887x-Q1 family of devices integrate current regulation using either a fixed off-time or cycle-by-cycle
PWM current chopping scheme. The current chopping scheme is selectable through the IMODE quad-level input.
This allows the devices to limit the output current in case of motor stall, high torque, or other high current load
events.
The IMODE level can be set by leaving the pin floating (Hi-Z), connecting the pin to GND, or connecting a
resistor between IMODE and GND. The IMODE pin state is latched when the device is enabled through the
nSLEEP pin. The IMODE state can be changed by taking the nSLEEP pin logic low, waiting the tSLEEP time,
changing the IMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high. The
IMODE input is also used to select the device response to an overcurrent event. See more details in the
Protection Circuits section.
The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater
than GND (if current feedback isn't required) or if current feedback is required, setting VVREF and RIPROPI such
that VIPROPI never reaches the VVREF threshold. In independent half-bridge control mode (PMODE = Hi-Z), the
internal current regulation is automatically disabled since the outputs are operating independently and the current
sense and regulation is shared between half-bridges.
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Table 6. IMODE Functions
IMODE FUNCTION
IMODE STATE
Current Chopping
Mode
Overcurrent Response
Quad-Level 1
RIMODE = GND
Fixed Off-Time
Automatic Retry
Quad-Level 2
RIMODE = 20kΩ to GND
Cycle-By-Cycle
Automatic Retry
Quad-Level 3
RIMODE = 62kΩ to GND
Cycle-By-Cycle
Latched Off
Quad-Level 4
RIMODE = Hi-Z
Fixed Off-Time
Latched Off
The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI
output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF
with an internal comparator.
ITRIP (A) = (VVREF (V) / RIPROPI (Ω)) x AIPROPI (μA/A)
(3)
When the ITRIP threshold is exceeded, the outputs will enter a current chopping mode according to the IMODE
setting. The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time
helps to prevent voltage and current transients during output switching from effecting the current regulation. The
internal deglitch time ensure that transient conditions do not prematurely trigger the current regulation.
7.3.2.2.1 Fixed Off-Time Current Chopping
In the fixed off-time mode, the H-bridge enters a brake, low-side slow decay (both low-side MOSFETs ON) for
tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless
IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake, lowside slow decay for tOFF. The fixed off-time mode allows for a simple current chopping scheme without
involvement from the external controller. This is shown in Figure 3. Fixed off-time mode will support 100% duty
cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new
control input edge on the EN/IN1 or PH/IN2 pins to reset the outputs.
ITRIP
IOUT
VOUT
Control
Input
tOFF
tOFF
tOFF
Figure 3. Off-Time Current-Regulation
7.3.2.2.2 Cycle-By-Cycle Current Chopping
In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay (both low-side MOSFETs ON) after
IOUT exceeds ITRIPuntil the next control input edge on the EN/IN1 or PH/IN2 pins. This allows for additional control
of the current chopping scheme by the external controller. This is shown in Figure 4. Cycle-by-cycle mode will
not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after
the brake, low-side slow decay state has been entered.
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For example, if VVREF = 2.5 V, RIPROPI = 1500 Ω, and AIPROPI = 1000 μA/A, then ITRIP will be approximately 1.67 A
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ITRIP
IOUT
VOUT
Control
Input
Re-enable
Re-enable
Figure 4. Cycle-By-Cycle Current Regulation
In cycle-by-cycle mode, the device will also indicates whenever the H-bridge has entered internal current
chopping by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from
the control inputs or the load has reached the ITRIP threshold. This is shown in Figure 5. nFAULT will be released
whenever the next control input edge is received by the device and the outputs are reset.
ADVANCE INFORMATION
Control
Input
ITRIP
IOUT
Drive
Decay
Drive
Chop
Decay
Drive
VOUT
VIPROPI
nFAULT
Figure 5. Cycle-By-Cycle Current Regulation
No device functionality is affected when the nFAULT pin is pulled low for the current chopping indicator. The
nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish from a
device fault (outlined in the Protection Circuits section) from the current chopping indicator, the nFAULT pin can
be compared with the control inputs. The current chopping indicator can only assert when the control inputs are
commanding a forward or reverse drive state (Figure 1). If the nFAULT pin is pulled low and the control inputs
are commanding the high-Z or slow-decay states, then a device fault has occurred.
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7.3.3 Protection Circuits
The DRV887x-Q1 family of devices are fully protected against supply undervoltage, charge pump undervoltage,
output overcurrent, and device overtemperature events.
7.3.3.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the supply voltage on the VM pin falls below the undervoltage lockout threshold voltage (VUVLO), all
MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. The charge pump is disabled in this
condition. Normal operation will resume when the undervoltage condition is removed and VM rises above the
VUVLO threshold.
7.3.3.2 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the charge pump voltage on the VCP pin falls below the undervoltage lockout threshold voltage
(VCPUV), all MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. Normal operation will
resume when the undervoltage condition is removed and VCP rises above the VCPUV threshold.
An analog current limit circuit on each MOSFETs limits the peak current out of the device even in hard short
circuit events.
If the output current exceeds the overcurrent threshold, IOCP, for longer than tOCP, all MOSFETs in the H-bridge
will be disabled and the nFAULT pin driven low. The overcurrent response can be configured through the IMODE
pin as shown in Table 6.
In automatic retry mode, the MOSFETs will be disabled and nFAULT pin driven low for a duration of tRETRY. After
tRETRY, the MOSFETs are re-enabled according to the state of the EN/IN1 and PH/IN2 pins. If the overcurrent
condition is still present, the cycle repeats; otherwise normal device operation resumes.
In latched off mode, the MOSFETs will remain disabled and nFAULT pin driven low until the device is reset
through either the nSLEEP pin or by removing the VM power supply.
In Independent Half-Bridge Control Mode (PMODE = Hi-Z), the OCP behavior is slightly modified. If an
overcurrent event is detected, only the corresponding half-bridge will be disabled and the nFAULT pin driven low.
The other half-bridge will continue normal operation. This allows for the device to manage independent fault
events when driving independent loads. If an overcurrent event is detected in both half-bridges, both half-bridges
will be disabled and the nFAULT pin driven low. In automatic retry mode, both half-bridges share the same
overcurrent retry timer. If an overcurrent event occurs first in one half-bridge and then later in the secondary halfbridge, but before tRETRY has expired, the retry timer for the first half-bridge will be reset to tRETRY and both halfbridges will enable again after the retry timer expires.
7.3.3.4 Thermal Shutdown (TSD)
If the die temperature exceeds the overtemperature limit TTSD, all MOSFET in the H-bridge will be disabled and
the nFAULT pin driven low. Normal operation will resume when the overtemperature condition is removed and
the die temperature drops below the TTSD threshold.
7.3.3.5 Fault Condition Summary
Table 7. Fault Condition Summary
FAULT
REPORT
H-BRIDGE
RECOVERY
ITRIP Indicator
CBC Mode &
IOUT > ITRIP
nFAULT
Active
Low-Side Slow Decay
Control Input Edge
VM Undervoltage Lockout (UVLO)
VM < VUVLO
nFAULT
Disabled
VM > VUVLO
VCP < VCPUV
nFAULT
Disabled
VCP > VCPUV
VCP Undervoltage Lockout (CPUV)
Overcurrent (OCP)
Thermal Shutdown (TSD)
Copyright © 2018, Texas Instruments Incorporated
CONDITION
IOUT > IOCP
nFAULT
Disabled
tRETRY or Reset
(Set by IMODE)
TJ > TTSD
nFAULT
Disabled
TJ < TTSD – THYS
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7.3.3.3 OUT Overcurrent Protection (OCP)
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7.3.4 Pin Diagrams
7.3.4.1 Logic-Level Inputs
Figure 6 shows the input structure for the logic-level input pins EN/IN1, PH/IN2, and nSLEEP.
100 k
Figure 6. Logic-Level Input
7.3.4.2 Tri-Level Inputs
Figure 7 shows the input structure for the tri-level input pin PMODE.
5V
ADVANCE INFORMATION
156 k
+
±
+
44 k
±
Figure 7. PMODE Tri-Level Input
7.3.4.3 Quad-Level Inputs
Figure 8 shows the input structure for the quad-level input pin IMODE.
+
5V
68 k
±
+
±
+
136 k
±
Figure 8. Quad-Level Input
7.4 Device Functional Modes
The DRV887x-Q1 family of devices have several different modes of operation depending on the system inputs.
7.4.1 Active Mode
After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the nSLEEP pin is logic
high, and tWAKE has elapsed, the device enters its active mode. In this mode, the H-bridge, charge pump, and
internal logic are active and the device is ready to receive inputs. The input control mode (PMODE) and current
control modes (IMODE) will be latched when the device enters active mode.
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Device Functional Modes (continued)
7.4.2 Low-Power Sleep Mode
The DRV887x-Q1 family of devices support a low power mode to reduce current consumption from the VM pin
when the driver is not active. This mode is entered by setting the nSLEEP pin logic low and waiting for tSLEEP to
elapse. In sleep mode, the H-bridge, charge pump, and internal logic are disabled. The device relies on a weak
pulldown to ensure all of the internal MOSFETs remain disabled. The device will not respond to any inputs
besides nSLEEP while in low-power sleep mode.
7.4.3 Fault Standby Mode
ADVANCE INFORMATION
The DRV887x-Q1 family of devices enter a standby mode when a fault is encountered. This is utilized to protect
the device and the output load. The device behavior in the fault standby mode is described in Table 7 and
depends on the fault condition. The device will leave the standby mode and re-enter the active mode when the
recovery condition is met.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV887x-Q1 family of devices can be used in a variety of applications that require either a half-bridge or Hbridge power stage configuration. Common application examples include brushed DC motors, solenoids, and
actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive
elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current
control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two
half-bridge drivers.
8.2 Typical Application
ADVANCE INFORMATION
8.2.1 Primary Application
In the primary application example, the device is configured to drive a bidirectional current through an external
load (such as a brushed DC motor) using an H-bridge configuration. The H-bridge polarity and duty cycle are
controlled with a PWM and IO resource from the external controller to the EN/IN1 and PH/IN2 pins. The device is
configured for the PH/EN control mode by tying the PMODE pin to GND. The current limit threshold (ITRIP) is
generated with an external resistor divider from the control logic supply voltage (VCC). The device is configured
for the fixed off-time current regulation scheme by tying the IMODE pin to GND. The load current is monitored
with an ADC from the controller to detect the voltage across RIPROPI.
VCC
Controller
1
PWM
EN/IN1
DRV887x
16
PMODE
2
I/O
VCC
15
PH/IN2
GND
nSLEEP
CPL
3
I/O
10 k
14
4
I/O
13
nFAULT
VREF
5
ADC
VREF
Thermal
Pad
CPH
12
VM
11
IPROPI
VM
IMODE
OUT2
OUT1
PGND
7
10
8
VCC
0.1 …F
VCP
6
RIPROPI
0.022 …F
0.1 …F
CBulk
9
RREF1
VREF
RREF2
BDC
Figure 9. Typical Application Schematic
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Typical Application (continued)
8.2.1.1 Design Requirements
REFERENCE
DESIGN PARAMETER
EXAMPLE VALUE
VM
Motor and driver supply voltage
13.5 V
3.3 V
VCC
Controller supply voltage
IRMS
Output RMS current
0.5 A
fPWM
Switching frequency
20 kHz
ITRIP
Current regulation trip point
1A
AIPROPI
Current sense scaling factor
1000 µA/A
RIPROPI
IPROPI external resistor
2.5 kΩ
2.5 V
VREF
Current regulation reference voltage
VADC
Controller ADC reference voltage
2.5 V
RREF1
VREF external resistor
16 kΩ
RREF2
VREF external resistor
50 kΩ
TA
PCB ambient temperature
–20 to 85 °C
TJ
Device max junction temperature
150 °C
RθJA
Device junction to ambient thermal resistance
35 °C/W
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Current Sense and Regulation
The DRV887x-Q1 family of devices provide integrated regulation and sensing out the output current.
The current sense feedback is configured by scaling the RIPROPI resistor to properly sense the scaled down
output current from IPROPI within the dynamic voltage range of the controller ADC. An example of this is shown.
RIPROPI <= VADC / (ITRIP x AIPROPI)
RIPROPI = 2.5 kΩ <= 2.5 V / (1 A x 1000 µA/A)
(4)
(5)
If VADC = 2.5 V, ITRIP = 1 A, and AIPROPI = 1000 µA/A then to maximize the dynamic IPROPI voltage range an
RIPROPI of approximately 2.5 kΩ should be selected.
The accuracy tolerance of RIPROPI can be selected based on the application requirements. 10%, 5%, 1%, 0.1%
are all valid tolerance values. The typical recommendation is 1% for best tradeoff between performance and cost.
The output current regulation trip point (ITRIP) is configured with a combination of VREF and RIPROPI. Since RIPROPI
was previously calculated and AIPROPI is a constant, all the remains is to calculate VREF.
VREF = RIPROPI x (ITRIP x AIPROPI)
VREF = 2.5 V = 2.5 kΩ x (1 A x 1000 µA/A)
(6)
(7)
If RIPROPI = 2.5 kΩ, ITRIP = 1 A, and AIPROPI = 1000 µA/A then VREF should be set to 2.5 V.
VREF can be generated with a simple resistor divider (RREF1 and RREF2) from the controller supply voltage. The
resistor sizing can be achieved by selecting a value for RREF1 and calculating the required value for RREF2.
8.2.1.2.2 Power Dissipation and Output Current Capability
The output current and power dissipation capabilities of the device are heavily dependent on the PCB design and
external system conditions. This section provides some guidelines for calculating these values.
Total power dissipation for the device is composed of three main components. These are the quiescent supply
current dissipation, the power MOSFET switching losses. and the power MOSFET RDS(on) (conduction) losses.
While other factors may contribute additional power losses, these other items are typically insignificant compared
to the three main items.
PTOT = PVM + PSW + PRDS
(8)
PVM can be calculated from the nominal supply voltage (VM) and the IVM active mode current specification.
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Table 8. Design Parameters
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PVM = VM x IVM
PVM = 0.054 W = 13.5 V x 4 mA
(9)
(10)
PSW can be calculated from the nominal supply voltage (VM), average output current (IRMS), switching frequency
(fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications.
PSW = PSW_RISE + PSW_FALL
PSW_RISE = 0.5 x VM x IRMS x tRISE x fPWM
PSW_FALL =0.5 x VM x IRMS x tFALL x fPWM
PSW_RISE = 0.0675 W = 0.5 x 13.5 V x 0.5 A x 1 µs x 20 kHz
PSW_FALL = 0.0675 W= 0.5 x 13.5 V x 0.5 A x 1 µs x 20 kHz
PSW = 0.135 W = 0.0675 W + 0.0675 W
(11)
(12)
(13)
(14)
(15)
(16)
PRDS can be calculated from the device RDS(on) and average output current (IRMS)
PRDS = IRMS2 x (RDS(ON)_HS + RDS(ON)_LS)
(17)
It should be noted that RDS(ON) has a strong correlation with the device temperature. A curve showing the
normalized RDS(on) with temperature can be found in the Typical Characteristics curves. Assuming a device
temperature of 85 °C it can be expected that RDS(on) will see an increases of ~1.25 based on the normalized
temperature data.
ADVANCE INFORMATION
PRDS = 0.219 W = 0.5 A2 x (350 mΩ x 1.25 + 350 mΩ x 1.25)
(18)
By adding together the different power dissipation components it can be verified that the expected power
dissipation and device junction temperature is within design targets.
PTOT = PVM + PSW + PRDS
PTOT= 0.408 W = 0.054 W + 0.135 W + 0.219 W
(19)
(20)
The device junction temperature can be calculated with the PTOT, device ambient temperature (TA), and package
thermal resistance (RθJA). The value for RθJA is heavily dependent on the PCB design and copper heat sinking
around the device.
TJ = (PTOT x RθJA) + TA
TJ = 99°C = (0.408 W x 35 °C/W) + 85°C
(21)
(22)
It should be ensured that the device junction temperature is within the specified operating region. Other methods
exist for verifying the device junction temperature depending on the measurements available.
Additional information on motor driver current ratings and power dissipation can be found in Related
Documentation.
8.2.2 Alternative Application
In the alternative application example, the device is configured to drive a unidirectional current through two
external loads (such as two brushed DC motors) using a dual half-bridge configuration. The duty cycle of each
half-bridge is controlled with a PWM resource from the external controller to the EN/IN1 and PH/IN2 pins. The
device is configured for the independent half-bridge control mode by leaving the PMODE pin floating. Since the
current regulation scheme is disabled in the independent half-bridge control mode, the VREF pin is tied to VCC.
The combined load current is monitored with an ADC from the controller to detect the voltage across RIPROPI.
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VCC
1
PWM
EN/IN1
DRV887x
PMODE
2
PWM
VCC
15
PH/IN2
GND
nSLEEP
CPL
3
I/O
10 k
14
4
I/O
VCC
CPH
Thermal
Pad
5
VREF
12
0.1 …F
VM
VCP
6
RIPROPI
0.022 …F
13
nFAULT
ADC
16
X
11
IPROPI
VM
IMODE
OUT2
OUT1
PGND
7
10
8
0.1 …F
CBulk
9
VM
VM
BDC
ADVANCE INFORMATION
Controller
BDC
Figure 10. Typical Application Schematic
8.2.2.1 Design Requirements
Table 9. Design Parameters
REFERENCE
DESIGN PARAMETER
EXAMPLE VALUE
VM
Motor and driver supply voltage
13.5 V
VCC
Controller supply voltage
3.3 V
0.5 A
IRMS1
Output 1 RMS current
IPEAK1
Output 1 peak current
1A
IRMS2
Output 2 RMS current
0.25 A
IPEAK2
Output 2 peak current
0.5 A
fPWM
Switching frequency
20 kHz
AIPROPI
Current sense scaling factor
1000 µA/A
RIPROPI
IPROPI external resistor
2.5 kΩ
VADC
Controller ADC reference voltage
3.3 V
TA
PCB ambient temperature
–20 to 85 °C
TJ
Device max junction temperature
150 °C
RθJA
Device junction to ambient thermal resistance
35 °C/W
8.2.2.2 Detailed Design Procedure
You can refer to the Primary Application Detailed Design Procedure section for a detailed design procedure
example. The majority of the design concepts apply to the alternative application example. A few changes to the
procedure are outlined below.
8.2.2.2.1 Current Sense and Regulation
In the alternative application for two half-bridge loads, the IPROPI output will be the combination of the two
outputs currents. The current sense feedback resistor RIPROPI should be scaled appropriately to stay within the
dynamic voltage range of the controller ADC. An example of this is shown
RIPROPI <= VADC / ((IPEAK1 + IPEAK2) x AIPROPI)
RIPROPI = 2.2 kΩ <= 3.3 V / ((1 A + 0.5 A) x 1000 µA/A)
Copyright © 2018, Texas Instruments Incorporated
(23)
(24)
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If VADC = 3.3 V, IPEAK1 = 1 A, IPEAK2 = 0.5 A, and AIPROPI = 1000 µA/A then to maximize the dynamic IPROPI
voltage range an RIPROPI of approximately 2.2 kΩ should be selected.
The accuracy tolerance of RIPROPI can be selected based on the application requirements. 10%, 5%, 1%, 0.1%
are all valid tolerance values. The typical recommendation is 1% for best tradeoff between performance and cost.
In independent half-bridge mode, the internal current regulation of the device is disabled. VREF can be set directly
to the supply reference for the controller ADC.
ADVANCE INFORMATION
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9 Power Supply Recommendations
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk
capacitance is generally beneficial, while the disadvantages are increased cost and physical size.
The amount of local bulk capacitance needed depends on a variety of factors, including:
• The highest current required by the motor or load
• The capacitance of the power supply and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple of the system
• The motor braking method (if applicable)
The data sheet generally provides a recommended minimum value, but system level testing is required to
determine the appropriately sized bulk capacitor.
Parasitic Wire
Inductance
Power Supply
Motor Drive System
VBB
+
+
±
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 11. System Supply Parasitics Example
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ADVANCE INFORMATION
The inductance between the power supply and motor drive system limits how the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
DRV8876-Q1
SLVSDS6 – OCTOBER 2018
www.ti.com
10 Layout
10.1 Layout Guidelines
Since the DRV887x-Q1 family of devices are integrated power MOSFETs device capable of driving high current,
careful attention should be paid to the layout design and external component placement. Some design and layout
guidelines are provided below.
•
•
•
•
•
ADVANCE INFORMATION
•
•
•
Low ESR ceramic capacitors should be utilized for the VM to GND 0.1 µF bypass capacitor, the VCP to VM
0.1 µF charge pump storage capacitor, and the 0.022 µF charge pump flying capacitor. X5R and X7R types
are recommended.
The VM power supply and VCP, CPH, CPL charge pump capacitors should be placed as close to the device
as possible to minimize the loop inductance.
The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close
as possible to the device to minimize the loop inductance.
VM, OUT1, OUT2, and PGND carry the high current from the power supply to the outputs and back to
ground. Thick metal routing should be utilized for these traces as is feasible.
PGND and GND should connect together directly on the PCB ground plane. They are not intended to be
isolated from each other.
The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane
(when available) through thermal vias to maximize the PCB heat sinking.
A recommended land pattern for the thermal vias is provided in the package drawing section.
The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking.
10.2 Layout Example
10.2.1 HTSSOP Layout Example
EN/IN1
1
16
PMODE
PH/IN2
2
15
GND
nSLEEP
3
14
CPL
nFAULT
4
13
CPH
VREF
5
12
VCP
IPROPI
6
11
VM
0.022 …F
Thermal
Pad
0.1 …F
VIPROPI
RIPROPI
IMODE
7
10
OUT2
OUT1
8
9
PGND
MOT+
VM
0.1 …F
CBULK
MOT-
Figure 12. HTSSOP (PWP) Example Layout
22
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DRV8876-Q1
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SLVSDS6 – OCTOBER 2018
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Current Recirculation and Decay Modes application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
11.2 Receiving Notification of Documentation Updates
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2018, Texas Instruments Incorporated
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23
ADVANCE INFORMATION
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
DRV8876-Q1
SLVSDS6 – OCTOBER 2018
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
ADVANCE INFORMATION
24
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DRV8876-Q1
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SLVSDS6 – OCTOBER 2018
12.1 Package Option Addendum
(1)
(2)
(3)
(4)
(5)
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
PDRV8876QPWP
PREVIEW
HTSSOP
PWP
16
N/A
Green (RoHS
& no Sb/Br)
CU NIPDAU
PDRV8874QPWP
PREVIEW
HTSSOP
PWP
16
N/A
Green (RoHS
& no Sb/Br)
CU NIPDAU
Eco Plan
(2)
Lead/Ball
Finish (3)
Op Temp (°C)
Device Marking (5)
Level-2-260C-1
YEAR
-40 to 125
DRV8876Q
Level-2-260C-1
YEAR
-40 to 125
DRV8874Q
MSL Peak Temp
(4)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Copyright © 2018, Texas Instruments Incorporated
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25
ADVANCE INFORMATION
12.1.1 Packaging Information
DRV8876-Q1
SLVSDS6 – OCTOBER 2018
www.ti.com
PACKAGE OUTLINE
PWP0016C
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
6.6
TYP
6.2
A
C
PIN 1 INDEX
AREA
0.1 C
SEATING
PLANE
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
ADVANCE INFORMATION
8
9
4.5
4.3
B
16X
0.30
0.19
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
4X (0.3)
8
9
2X 0.23 MAX
NOTE 5
2.31
1.75
17
0.25
GAGE PLANE
16
1
0 -8
1.2 MAX
0.15
0.05
0.75
0.50
DETAIL A
A 20
THERMAL
PAD
2.46
1.75
TYPICAL
4224559/B 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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DRV8876-Q1
www.ti.com
SLVSDS6 – OCTOBER 2018
EXAMPLE BOARD LAYOUT
PWP0016C
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.46)
16X (1.5)
METAL COVERED
BY SOLDER MASK
SYMM
1
16X (0.45)
16
(1.2) TYP
SYMM
ADVANCE INFORMATION
(R0.05) TYP
(2.31)
17
(0.6)
(5)
NOTE 9
14X (0.65)
( 0.2) TYP
VIA
9
8
SOLDER MASK
DEFINED PAD
(1) TYP
SEE DETAILS
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4224559/B 01/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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DRV8876-Q1
SLVSDS6 – OCTOBER 2018
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016C
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.46)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
1
METAL COVERED
BY SOLDER MASK
16
16X (0.45)
(R0.05) TYP
ADVANCE INFORMATION
SYMM
(2.31)
BASED ON
0.125 THICK
STENCIL
17
14X (0.65)
9
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.75 X 2.58
2.46 X 2.31 (SHOWN)
2.25 X 2.11
2.08 X 1.95
4224559/B 01/2019
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
PDRV8876QPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
16
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRV8876-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2019
• Catalog: DRV8876
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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