Texas Instruments | DRV8811 Stepper Motor Controller IC (Rev. J) | Datasheet | Texas Instruments DRV8811 Stepper Motor Controller IC (Rev. J) Datasheet

Texas Instruments DRV8811 Stepper Motor Controller IC (Rev. J) Datasheet
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DRV8811
SLVS865J – SEPTEMBER 2008 – REVISED APRIL 2017
DRV8811 Stepper Motor Controller IC
1 Features
3 Description
•
The DRV8811 device provides an integrated stepper
motor driver solution for printers, scanners, and other
automated equipment applications. The device has
two H-bridge drivers, as well as microstepping
indexer logic to control a stepper motor.
1
•
•
•
•
•
•
Pulse Width Modulation (PWM) Microstepping
Motor Driver
– Up to 1/8-Step Microstepping Indexer
– Step and Direction Control
– Programmable Mixed Decay, Blanking, and
Off-Time
Up to 1.9-A Current Per Winding
Low 1.0-Ω (HS+LS) MOSFET RDS(on) (25°C)
8-V to 38-V Operating Supply Voltage Range
Pin-to-Pin Compatible With the DRV8818
Thermally Enhanced Surface Mount Package
Protection Features:
– VM Undervoltage Lockout (UVLO)
– Overcurrent Protection (OCP)
– Thermal Shutdown (TSD)
The output driver block consists of N-channel power
MOSFETs configured as full H-bridges to drive the
motor windings.
A simple STEP-and-DIR interface allows easy
interfacing to controller circuits. Step mode pins allow
for configuration of the motor in full-step, half-step,
quarter-step, or eighth-step modes. Decay mode and
PWM off-time are programmable.
Internal shutdown functions are provided for
overcurrent protection, short-circuit protection,
undervoltage lockout and overtemperature.
The DRV8811 device is packaged in a PowerPAD™
28-pin HTSSOP package with thermal pad.
2 Applications
•
•
•
•
•
•
Device Information(1)
Printers
Scanners
Office Automation Machines
Gaming Machines
Factory Automation
Robotics
PART NUMBER
DRV8811
PACKAGE
HTSSOP (28)
BODY SIZE (NOM)
9.70 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
8 V to 38 V
STEP
DRV8811
1.9 A
DIR
Controller
Step Size
1.9 A
HOMEn
M
Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8811
SLVS865J – SEPTEMBER 2008 – REVISED APRIL 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
5
5
5
5
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ....................................... 10
Feature Description................................................. 10
Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 17
9
Power Supply Recommendations...................... 20
9.1 Bulk Capacitance .................................................... 20
10 Layout................................................................... 21
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Information ..............................................
Power Dissipation .................................................
21
21
22
23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (January 2015) to Revision J
Page
•
Changed the pinout diagram ................................................................................................................................................. 3
•
Added a row for the thermal pad to the Pin Functions table .................................................................................................. 4
•
Changed multiple entries in the Absolute Maximum Ratings table ....................................................................................... 4
•
Added two rows to the Recommended Operating Conditions table ...................................................................................... 5
•
Deleted "active" or "inactive" from several timing requirements definitions ........................................................................... 7
•
Changed Equation 1............................................................................................................................................................. 12
•
Added units to Equation 2 .................................................................................................................................................... 12
•
Added units to Equation 3 .................................................................................................................................................... 12
•
Added units to Equation 4 ................................................................................................................................................... 13
•
Changed VVREF from 1.56 V to 1 V....................................................................................................................................... 18
Changes from Revision H (November 2013) to Revision I
Page
•
Changed Features list ............................................................................................................................................................ 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 5
Changes from Revision G (May 2010) to Revision H
Page
•
Changed Features bullet ........................................................................................................................................................ 1
•
Changed IO(peak) and deleted IO in Absolute Maximum Ratings table..................................................................................... 4
•
Changed maximum digital pin voltage.................................................................................................................................... 4
•
Added parameters to Logic-Level Inputs section of the ELECTRICAL CHARACTERISTICS............................................... 5
•
Changed Timing Requirements .............................................................................................................................................. 7
2
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5 Pin Configuration and Functions
PWP PowerPAD™ Package
28-Pin HTSSOP With Exposed Thermal Pad
Top View
ISENA
1
28
VMA
HOMEn
2
27
SLEEPn
DIR
3
26
ENABLEn
AOUT1
4
25
AOUT2
DECAY
5
24
CP2
RCA
6
23
CP1
GND
7
22
VCP
Thermal
pad
VREF
8
21
GND
RCB
9
20
VGD
VCC
10
19
STEP
BOUT1
11
18
BOUT2
USM1
12
17
RESETn
USM0
13
16
SRn
ISENB
14
15
VMB
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
AOUT1
4
O
Bridge A output 1. Connect to bipolar stepper motor winding A
AOUT2
25
O
Bridge A output 2. Positive current is AOUT1 → AOUT2
BOUT1
11
O
Bridge B output 1. Connect to bipolar stepper motor winding B
BOUT2
18
O
Bridge B output 2. Positive current is BOUT1 → BOUT2
CP1
23
PWR
Charge pump flying capacitor. Connect a 0.22-μF capacitor between CP1 and CP2
CP2
24
PWR
Charge pump flying capacitor. Connect a 0.22-μF capacitor between CP1 and CP2
DECAY
5
I
Decay mode select. Voltage applied sets decay mode - see motor driver description for details. Bypass to
GND with a 0.1-μF ceramic capacitor
DIR
3
I
Direction input. Level sets the direction of stepping
ENABLEn
26
I
Enable input. Logic high to disable device outputs, logic low to enable outputs
7, 21
—
Device ground
2
O
Home position. Logic low when at home state of step table, logic high at other states
ISENA
1
I
Bridge A ground / ISENSE. Connect to current sense resistor for bridge A
ISENB
14
I
Bridge B ground / ISENSE. Connect to current sense resistor for bridge B
RCA
6
I
Bridge A blanking and off time adjust. Connect a parallel resistor and capacitor to GND - see motor driver
description for details
RCB
9
I
Bridge B blanking and off time adjust. Connect a parallel resistor and capacitor to GND - see motor driver
description for details
GND
HOMEn
(1)
Directions: I = input, O = output, I/O = input/output, PWR = power
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
RESETn
17
I
Reset input. Active-low reset input initializes the indexer logic and disables the H-bridge outputs
SLEEPn
27
I
Sleep mode input. Logic high to enable device, logic low to enter low-power sleep mode
SRn
16
I
Synchronous rectification enable input. Active-low. When low, synchronous rectification is enabled. Weak
internal pulldown.
STEP
19
I
Step input. Rising edge causes the indexer to move one step
USM0
13
I
Microstep mode 0. USM0 and USM1 set the step mode - full step, half step, quarter step, or eight
microsteps/step
USM1
12
I
Microstep mode 1. USM0 and USM1 set the step mode - full step, half step, quarter step, or eight
microsteps/step
VCC
10
PWR
Logic supply voltage. Connect to 3-V to 5-V logic supply. Bypass to GND with a 0.1-μF ceramic capacitor
VCP
22
PWR
High-side gate drive voltage. Connect a 0.22-μF ceramic capacitor to VM
VGD
20
PWR
Low-side gate drive voltage. Bypass to GND with a 0.22-μF ceramic capacitor
VMA
28
PWR
Bridge A power supply. Connect to motor supply (8 V to 38 V). Both VMA and VMB must be connected to
same supply.
VMB
15
PWR
Bridge B power supply. Connect to motor supply (8 V to 38 V). Both VMA and VMB must be connected to
same supply.
VREF
8
I
Thermal
pad
—
—
Current set reference input. Reference voltage for winding current set
Thermal pad. Connect to system ground with large copper plane for improved thermal dissipation.
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
(2) (3)
MIN
MAX
UNIT
Power supply voltage range
VMA, VMB
–0.3
40
V
Power supply voltage range
VCC
–0.3
7
V
Digital pin voltage range
VI: DIR, DECAY, ENABLEn, HOME, RCA, RCB, RESETn, SLEEPn,
SRn, STEP, USM0, USM1
–0.5
7
V
Reference pin voltage range
VREF
Sense pin voltage range
ISENA, ISENB (4)
–0.3
7
V
–0.875
0.875
V
VVM +
0.7
V
Output pin voltage range
AOUT1, AOUT2, BOUT1, BOUT2
–0.7
Gate-drive pin-voltage range
VGD
–0.3
8
V
VCP, CP2
–0.3
VVM +
12
V
CP1
–0.3
VVM
Charge pump pin voltage range
Peak motor drive output current, IO(peak)
Internally limited
Operating virtual junction temperature range, TJ
–40
Operating ambient temperature range, TA
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
4
150
°C
–40
85
°C
–60
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed.
Transients of ±1 V for less than 25 ns are acceptable.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
(1)
NOM
MAX
UNIT
VVMx
Motor power supply voltage range
8
38
V
VCC
Logic power supply voltage range
3
5.5
V
VVREF
VREF input voltage
0
VCC
V
RX
RX resistance value
12
56
100
kΩ
CX
CX capacitance value
470
680
1500
pF
(1)
Both VMx pins must be connected to the same supply voltage.
6.4 Thermal Information
DRV8811
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
31.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.3
°C/W
RθJB
Junction-to-board thermal resistance
11.5
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
11.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.8
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Electrical Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
IVM
VM operating supply current
VM = 35 V, fPWM < 50 KHz
4.5
8
mA
IVCC
VCC operating supply current
fPWM < 50 KHz
0.4
4
mA
IVMQ
VM sleep mode supply current
VM = 35 V
12
20
μA
IVCCQ
VCC sleep mode supply current
5
20
μA
VM undervoltage lockout voltage
VM rising
6.7
8
VCC undervoltage lockout voltage
VCC rising
2.71
2.95
VUVLO
V
VREF INPUT, CURRENT CONTROL ACCURACY
IVREF
ΔICHOP
VREF input current
Chopping current accuracy
VVREF = 3.3 V
–3
3
VVREF = 2 V, 70% to 100% current
–5%
5%
VVREF = 2 V, 20% to 56% current
–10%
10%
μA
LOGIC-LEVEL INPUTS
VIL
Input low voltage
VIH
Input high voltage
0.3 × VCC
IIL
Input low current
VI = 0.3 × VCC
–20
20
IIH
Input high current
VIN = 0.3 × VCC
–20
20
RPU
Pullup resistance
ENABLEn, RESETn
1
MΩ
RPD
Pulldown resistance
DIR, STEP, SLEEPn, USM1, USM0, SRn
1
MΩ
0.7 × VCC
V
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μA
μA
5
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Electrical Characteristics (continued)
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HOMEn OUTPUT
VOL
Output low voltage
IO = 200 μA
VOH
Output high voltage
IO = –200 μA
0.3 × VCC
0.7 × VCC
V
V
DECAY INPUT
VIL
Input low threshold voltage
For fast decay mode
VIH
Input high threshold voltage
For slow decay mode
0.21 ×
VCC
V
0.6 × VCC
V
H-BRIDGE FETS
rDS(on)
HS FET on resistance
rDS(on)
LS FET on resistance
VM = 24 V, IO = 2.5 A, TJ = 25°C
0.50
VM = 24 V, IO = 2.5 A, TJ = 85°C
0.60
VM = 24 V, IO = 2.5 A, TJ = 25°C
0.50
VM = 24 V, IO = 2.5 A, TJ = 85°C
0.60
IOFF
–20
0.75
0.75
20
Ω
Ω
μA
MOTOR DRIVER
tOFF
Off-time
Rx = 56 kΩ, Cx = 680 pF
30
38
46
μs
tBLANK
Current-sense blanking time
Rx = 56 kΩ, Cx = 680 pF
700
950
1200
ns
tDT
Dead time (1)
SRn = 0
100
475
800
ns
2.5
4.5
6.5
A
Die temperature
150
160
180
°C
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tTSD
Thermal shutdown temperature (1)
(1)
6
Not tested in production - guaranteed by design.
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6.6 Timing Requirements
over operating ambient temperature range (unless otherwise noted) (see Figure 1)
MIN
TYP
MAX
UNIT
500
kHz
1
fSTEP
Step frequency
2
tWH(STEP)
Pulse duration, STEP high
1
3
tWL(STEP)
Pulse duration, STEP low
1
μs
4
tSU(STEP)
Setup time, command before STEP rising
200
ns
5
tH(STEP)
Hold time, command after STEP rising
200
6
tWAKE
Wakeup time, SLEEPn high to STEP input accepted
1
ms
7
tSLEEP
Sleep time, SLEEPn low to outputs disabled
5
μs
8
tENABLE
Enable time, ENABLEn high to outputs enabled
20
μs
9
tDISABLE
Disable time, ENABLEn low to outputs disabled
20
μs
μs
ns
10 tRESETR
Reset release time, RESETn high to outputs enabled
5
μs
11 tRESET
Reset time, RESETn low to outputs disabled
5
μs
6.7 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOTOR DRIVER
tOFF
Off-time
Rx = 56 kΩ, Cx = 680 pF
30
38
46
μs
tBLANK
Current-sense blanking time
Rx = 56 kΩ, Cx = 680 pF
700
950
1200
ns
tDT
Dead time (1)
SRn = 0
100
475
800
ns
(1)
Not tested in production - guaranteed by design.
1
2
3
STEP
DIR, USMx
4
5
6
SLEEPn, ENABLEn, RESETn
8
10
7
9
11
OUTPUT
Figure 1. Timing Diagram
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6.8 Typical Characteristics
4.6
6
4.4
5
4
4
IVMQ (mA)
IVM (mA)
4.2
8V
24 V
35 V
3.8
3.6
8V
24 V
35 V
3
2
3.4
1
3.2
3
-40
-20
0
20
40
VM (V)
60
80
0
-40
100
-20
0
80
100
D002
Figure 3. IVMQ vs VM
40 qC
0 qC
25 qC
85 qC
1500
LS (m:)
1400
1300
1200
1100
1000
900
800
8V
24 V
35 V
700
600
-20
0
20
40
VM (V)
60
80
100
6
9
D003
Figure 4. rDS(on) HS and LS vs VM
8
60
1600
RDS(on) HS
RDS(on) HS + LS (m:)
Figure 2. IVM vs VM
1400
1350
1300
1250
1200
1150
1100
1050
1000
950
900
850
800
750
-40
20
40
VM (V)
D001
12
15
18
21
24
VM (V)
27
30
33
36
D004
Figure 5. rDS(on) HS and LS vs Temperature
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7 Detailed Description
7.1 Overview
The DRV8811 device is a highly configurable, integrated motor driver solution for bipolar stepper motors. The
device integrates two H-bridges, current sense and regulation circuitry, and a microstepping indexer. The
DRV8811 device can be powered with a supply voltage between 8 V and 38 V and is capable of providing an
output current up to 1.9 A full-scale.
A simple STEP and DIR interface allows for easy interfacing to the controller. The internal indexer is able to
execute high-accuracy microstepping without requiring the controller to manage the current regulation loop.
The current regulation is highly configurable, with three decay modes of operation. They are fast, slow, and
mixed decay, which can be selected depending on the application requirements. The DRV8811 device also
provides configurable blanking, off time, and mixed decay, in order to adjust to a wide range of motors.
A low-power sleep mode is incorporated which allows for minimal power consumption when the system is idle.
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7.2 Functional Block Diagram
LS Gate
Drive
VCC
VM
+
VCC
CP1
LS Gate
Drive
VGD
Internal Logic
Regulator and
References
Charge
Pump
Low-Side Gate
Drive
CP2
HS Gate
Drive
VM
VCP
VCC
VM
VM
VREF
VMA
ENABLEn
RESETn
AOUT1
+
SLEEPn
Stepper
Motor
Motor Driver A
AOUT2
STEP
+
DIR
USM0
-
ISENA
Control
Logic/
Indexer
USM1
VM
VMB
SRn
VCC
HOMEn
BOUT1
DECAY
Motor Driver B
BOUT2
RCA
ISENB
RCB
Thermal
Shutdown
GND
PPAD
GND
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7.3 Feature Description
7.3.1 PWM H-Bridge Drivers
The DRV8811 device contains two H-bridge motor drivers with current-control PWM circuitry, and a
microstepping indexer. A block diagram of the motor control circuitry is shown in Figure 6.
10
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Feature Description (continued)
VM
OCP
VGD
VMA
VCP
AOUT1
+
RCA
Predrive
Step
Motor
AOUT2
–
PWM
+
–
OCP
ISENA
A=8
DAC
OCP
VGD
VCP
Control /
Indexer
Logic
VM
VMB
BOUT1
Predrive
BOUT2
PWM
OCP
ISENB
A=8
DAC
RCB
DECAY
VREF
Figure 6. Motor Control Circuitry
7.3.2 Current Regulation
The PWM chopping current is set by a comparator, which compares the voltage across a current-sense resistor,
multiplied by a factor of 8, with a reference voltage. The reference voltage is input from the VREF pin. The fullscale (100%) chopping current is calculated as follows:
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Feature Description (continued)
I CHOP (A) =
VVREF (V)
8 ´ R SENSE (W)
(1)
Example:
If a 0.22-Ω sense resistor is used and the VREF pin is 3.3 V, the full-scale (100%) chopping current is
3.3 V / (8 × 0.22 Ω) = 1.875 A.
The reference voltage is also scaled by an internal DAC that allows torque control for fractional stepping of a
bipolar stepper motor, as described in the Microstepping Indexer section.
When a winding is activated, the current through it rises until it reaches the chopping current threshold described
previously; then the current is switched off for a fixed off-time. The off-time is determined by the values of a
resistor and capacitor connected to the RCA (for bridge A) and RCB (for bridge B) pins. The off-time is
approximated by:
t OFF (ms) = R (W) ´ C (nF)
(2)
To avoid falsely tripping on transient currents when the winding is first activated, a blanking period is used
immediately after turning on the FETs, during which the state of the current-sense comparator is ignored. The
blanking time is determined by the value of the capacitor connected to the RCx pin and is approximated by:
t BLANK (ns) = 1400 (W) ´ C (nF)
(3)
7.3.3 Decay Mode
During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current
chopping threshold is reached. This is shown in Figure 7, Item 1. The current flow direction shown indicates
positive current flow in Table 2.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. If synchronous rectification is enabled (SRn pin logic low), the
opposite FETs are turned on; as the winding current approaches zero, the bridge is disabled to prevent any
reverse current flow. If SRn is high, current is recirculated through the body diodes, or through external Schottky
diodes. Fast-decay mode is shown in Figure 7, Item 2.
In slow-decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 7, Item 3.
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Feature Description (continued)
VM
1 Drive current
1
xOUT2
xOUT1
3
2
Fast decay (reverse)
3
Slow decay (brake)
2
Figure 7. Decay Mode
The DRV8811 device also supports a mixed decay mode. Mixed decay mode begins as fast decay, but after a
period of time switches to slow decay mode for the remainder of the fixed off-time.
Fast and mixed decay modes are only active if the current through the winding is decreasing; if the current is
increasing, then slow decay is always used.
Which decay mode is used is selected by the voltage on the DECAY pin. If the voltage is greater than 0.6 × VCC,
slow decay mode is always used. If DECAY is less than 0.21 × VCC, the device operates in fast decay mode
when the current through the winding is decreasing. If the voltage is between these levels, mixed decay mode is
enabled.
In mixed decay mode, the voltage on the DECAY pin sets the point in the cycle that the change to slow decay
mode occurs. This time can be approximated by:
æ 0.6 ´ VCC (V) ö
÷
t FD (ms) = R (W) ´ C (nF) ´ ln ç
ç VDECAY (V) ÷
è
ø
(4)
Operation of the blanking, fixed off time, and mixed decay mode is illustrated in Figure 8.
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Feature Description (continued)
PWM
ON
PWM
OFF
ON
ITRIP
ON
0.6 × VCC
(tOFF)
Q
S
Q
R
PWM_ON
ITRIP
VBLANK
BLANK
RCx
Winding
Current
PWM
R
0.6 ×
VBLANK
RCx
VCC
C
PWM_OFF
VCC
0.21 × VCC
VDECAY
Voltage
0.21 × VCC
FAST
BLANK
(tFD)
SLOW
FAST_DECAY
DECAY
DECAY
To other PWM
Figure 8. PWM
7.3.4 Microstepping Indexer
Built-in indexer logic in the DRV8811 device allows a number of different stepping configurations. The USM1 and
USM0 pins are used to configure the stepping format as shown in Table 1:
Table 1. Microstepping Selection Bits
USM1
USM0
0
0
Full step (2-phase excitation)
STEP MODE
0
1
1/2 step (1-2 phase excitation)
1
0
1/4 step (W1-2 phase excitation)
1
1
1/8 step (phase excitation)
Table 2 shows the relative current and step directions for different settings of USM1 and USM0. At each rising
edge of the STEP input, the indexer travels to the next state in the table. The direction is shown with the DIR pin
high; if the DIR pin is low the sequence is reversed. Positive current is defined as xOUT1 = positive with respect
to xOUT2.
Note that the home state is 45 degrees. This state is entered at power up or device reset. The HOMEn output pin
is driven low in this state. In all other states it is driven logic high.
Table 2. Microstepping Indexer
FULL STEP
USM = 00
1/4 STEP
USM = 10
1/8 STEP
USM = 11
1
1
1
100
0
0
2
98
20
11.325
3
92
38
22.5
4
83
56
33.75
5
71
71
45 (home state)
6
56
83
56.25
7
38
92
67.5
8
20
98
78.75
2
1
2
3
4
14
AOUTx
BOUTx
CURRENT
CURRENT
(% FULL-SCALE) (% FULL-SCALE)
1/2 STEP
USM = 01
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Table 2. Microstepping Indexer (continued)
FULL STEP
USM = 00
1/2 STEP
USM = 01
1/4 STEP
USM = 10
3
5
6
2
4
7
8
5
9
10
3
6
11
12
7
13
14
4
8
15
16
1/8 STEP
USM = 11
AOUTx
BOUTx
CURRENT
CURRENT
(% FULL-SCALE) (% FULL-SCALE)
STEP ANGLE
(DEGREES)
9
0
100
90
10
–20
98
101.25
11
–38
92
112.5
12
–56
83
123.75
13
–71
71
135
14
–83
56
146.25
15
–92
38
157.5
16
–98
20
168.75
17
–100
0
180
18
–98
–20
191.25
19
–92
–38
202.5
20
–83
–56
213.75
21
–71
–71
225
22
–56
–83
236.25
23
–38
–92
247.5
24
–20
–98
258.75
25
0
–100
270
26
20
–98
281.25
27
38
–92
292.5
28
56
–83
303.75
29
71
–71
315
30
83
–56
326.25
31
92
–38
337.5
32
98
–20
348.75
7.3.5 Protection Circuits
7.3.5.1 Overcurrent Protection (OCP)
If the current through any FET exceeds the preset overcurrent threshold, all FETs in the H-bridge are disabled
until the ENABLEn pin has been brought high and then back low, or power is removed and re-applied.
Overcurrent conditions are sensed in both directions; that is, any short to ground, supply, or across the motor
winding results in an overcurrent shutdown.
Note that overcurrent protection does not use the current-sense circuitry used for PWM current control and is
independent of the ISENSE resistor value or VVREF voltage. Additionally, in the case of an overcurrent event, the
microstepping indexer is reset to the home state.
7.3.5.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all drivers in the device are shut down and the indexer is reset to the
home state. Once the die temperature has fallen to a safe level, operation resumes.
7.3.5.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage-lockout threshold voltage, all circuitry in the
device is disabled and the indexer is reset to the home state. Operation resumes when VM rises above the
UVLO threshold.
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7.4 Device Functional Modes
7.4.1 RESETn, ENABLEn and SLEEPn Operation
The RESETn pin, when driven low, resets the indexer to the home position shown in Table 2. It also disables the
H-bridge drivers. The STEP input is ignored while RESETn is active.
The ENABLEn pin is used to control the output drivers. When ENABLEn is low, the output H-bridges are
enabled. When ENABLEn is high, the H-bridges are disabled and the outputs are in a high-impedance state.
Note that when ENABLEn is high, the input pins and control logic, including the indexer (STEP and DIR pins) are
still functional.
The SLEEPn pin is used to put the device into a low-power state. If SLEEPn is low, the H-bridges are disabled,
the gate drive charge pump is stopped, and all internal clocks are stopped. In this state, all inputs are ignored
until the SLEEPn pin returns high.
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8 Application and Implementation
NOTE
Information in the following application section is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8811 device is used for bipolar stepper-motor control. The microstepping motor driver provides precise
regulation of the coil current and ensures a smooth rotation from the stepper motor.
8.2 Typical Application
Figure 9 shows a common system application of the DRV8811 device.
VM
DRV8811
100 mΩ
1
2
3
VCC
AOUT1
10 kΩ
VMA
HOMEn
SLEEPn
DIR
ENABLEn
28
+
100 µF
27
0.1 µF
26
25
AOUT1
AOUT2
DECAY
CP2
RCA
CP1
GND
VCP 22
AOUT2
AOUT1
5
1000 pF
6
24
23
+
47 kΩ
VCC
Stepper Motor
0.22 µF
VM
7
AOUT2
+
47 kΩ
VCC
9
1000 pF
10
BOUT1
11
12
13
100 mΩ
14
21
VREF
GND
RCB
VGD 20
VCC
STEP 19
BOUT1
BOUT2
USM1
RESETn
USM0
ISENB
Thermal Pad
8
10 kΩ
SRn
BOUT1
0.22 µF
10 kΩ
18
–
–
BOUT2
10 kΩ
0.1 µF
4
ISENA
VM
0.22 µF
BOUT2
17
16
VM
VMB
15
0.1 µF
Figure 9. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
Table 3. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Supply voltage
VM
24 V
Motor winding resistance
RL
4Ω
Motor winding inductance
IL
3.7 mH
Motor full-step angle
θstep
1.8°
Target microstepping level
nm
8 µsteps per step
Target motor speed
V
120 rpm
Target full-scale current
IFS
1.25 A
8.2.2 Detailed Design Procedure
8.2.2.1 Stepper Motor Speed
The first step in configuring the DRV8811 device requires the desired motor speed and microstepping level. If the
target application requires a constant speed, then a square wave with frequency ƒstep must be applied to the
STEP pin.
If the target motor start-up speed is too high, the motor does not spin. Make sure that the motor can support the
target speed, or implement an acceleration profile to bring the motor up to speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
æ µsteps ö
°
æ rotations ö
æ
ö
vç
´ 360 ç
´ nm ç
÷
÷
÷
è minute ø
è rotation ø
è step ø
f step (µsteps / sec ond) =
æ ° ö
æ sec onds ö
60 ç
÷ ´qstep ç step ÷
è minute ø
è
ø
(5)
°
æ rotations ö
æ
ö æ µsteps ö
120 ç
÷ ´ 360 ç rotation ÷ ´ 8 ç step ÷
è minute ø
è
ø è
ø
f step (µsteps / sec ond) =
æ ° ö
æ sec onds ö
60 ç
÷ ´ 1.8 ç step ÷
è minute ø
è
ø
(6)
θstep can be found in the stepper motor data sheet or written on the motor itself.
For the DRV8811 device, the microstepping level is set by the USMx pins. Higher microstepping means a
smother motor motion and less audible noise, but increases switching losses and require a higher fstep to achieve
the same motor speed.
8.2.2.2 Current Regulation
In a stepper motor, the set full-scale current (IFS) is the maximum current driven through either winding. This
quantity depends on the VVREF analog voltage and the sense resistor value (RSENSE). During stepping, IFS defines
the current chopping threshold (ITRIP) for the maximum current step. The gain of DRV8811 device is set for
8 V/V.
VVREF (V )
VVREF (V )
I FS (A ) =
=
A v ´ R SENSE (W ) 8 ´R SENSE (W )
(7)
To achieve IFS = 1.25 A with RSENSE of 0.1 Ω, VVREF should be 1 V.
8.2.2.3 Decay Modes
The DRV8811 device supports three different decay modes: slow decay, fast decay, and mixed decay. The
current through the motor windings is regulated using a fixed off-time scheme.
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This means that the current increases until it reaches the current chopping threshold (ITRIP), after which it enters
the configured decay mode for a fixed period of time. The cycle then repeats after the decay period expires.
The blanking time tBLANK defines the minimum drive time for the current chopping. ITRIP is ignored during tBLANK,
so the winding current may overshoot the trip level.
8.2.3 Application Curves
Figure 10. Mixed Decay
Figure 11. Slow Decay on Increasing Steps
Figure 12. Mixed Decay on Decreasing Steps
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9 Power Supply Recommendations
9.1 Bulk Capacitance
Having an appropriate local bulk capacitance is an important factor in motor-drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The power supply capacitance and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed dc, brushless dc, stepper)
• The motor braking method
The inductance between the power supply and the motor drive system limits the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The device data sheet generally provides a recommended value, but system-level testing is required to
determine the appropriate sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
+
Motor
Driver
–
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 13. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
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10 Layout
10.1 Layout Guidelines
The VMA and VMB pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a
recommended value of 0.1 μF rated for VM. This capacitor should be placed as close to the VMA and VMB pins
as possible with a thick trace or ground plane connection to the device GND pin.
The VMA and VMB pins must be bypassed to ground using an appropriate bulk capacitor. This component may
be an electrolytic and should be located close to the DRV8811 device.
A low-ESR ceramic capacitor must be placed between the CP1 and CP2 pins. TI recommends a value of
0.22 μF rated for VM. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed between the VM and VCP pins. TI recommends a value of 0.22 μF
rated for 16 V. Place this component as close to the pins as possible.
Ensure proper connection of the DRV8811 thermal pad to the PCB. The thermal pad should be connected to a
copper plane that is connected to GND. The copper plane should have a large area to allow for thermal
dissipation from the DRV8811 device.
10.2 Layout Example
GND
100 PŸ
VMA
HOMEn
SLEEPn
DIR
ENABLE
AOUT1
AOUT2
DECAY
CP2
RCA
CP1
GND
VCP
VREF
GND
RCB
VGD
VCC
STEP
BOUT1
BOUT2
USM1
RESETn
USM0
SRn
ISENB
VMB
+
GND
0.1 µF
ISENA
VM
0.22 µF
0.22 µF
GND
0.22 µF
VCC
GND
VM
0.1 µF
100 PŸ
GND
Figure 14. Layout Example Schematic
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10.3 Thermal Information
The DRV8811 device has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die
temperature exceeds approximately 150°C, the device is disabled until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation,
insufficient heatsinking, or too high an ambient temperature.
10.3.1 Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, see TI Application Report SLMA002, PowerPAD™ Thermally
Enhanced Package and TI Application Brief SLMA004, PowerPAD™ Made Easy, available at www.ti.com.
PD - Max Power Dissipation - Watts
In general, the more copper area that can be provided, the more power can be dissipated. Figure 18 shows
thermal resistance vs copper plane area for a single-sided PCB with 2-oz. copper heatsink area. It can be seen
that the heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas.
A
A
2
TA - Ambien Temperature - °C
Figure 16. Power Dissipation
(4-Layer)
Figure 15. Power Dissipation
(2-Layer)
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Thermal Information (continued)
RDS(ON) - mΩ
θJA
Temperature - °C
Figure 17. Typical rDS(on)
vs
Temperature
Figure 18. Thermal Resistance
vs
Copper Area
10.4 Power Dissipation
Power dissipation in the DRV8811 device is dominated by the power dissipated in the output FET resistance, or
rDS(on). Average power dissipation when running a stepper motor can be roughly estimated by:
PTOT = 4 × rDS(on) × (IOUT(RMS))2
(8)
where PTOT is the total power dissipation, rDS(on) is the resistance of each FET, and IOUT(RMS) is the RMS output
current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7× the full-scale output current
setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are
conducting winding current for each winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the DRV8811 device is dependent on ambient
temperature and heatsinking. Figure 15 and Figure 16 show how the maximum allowable power dissipation
varies according to temperature and PCB construction. Figure 15 shows data for a JEDEC 2-layer low-K board
with 2-oz. copper, 76 mm × 114 mm × 1.6 mm thick, with either no backside copper or a 24 cm2 copper area on
the backside. Similarly, Figure 16 shows data for a JEDEC 4-layer high-K board with 1-oz. copper, 76 mm × 114
mm × 1.6 mm thick, and a solid internal ground plane. In this case, the thermal pad is tied to the ground plane
using thermal vias, and no additional outer layer copper.
Note that rDS(on) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink. See Figure 17.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
1.
2.
3.
4.
5.
PowerPAD™ Thermally Enhanced Package
PowerPAD™ Made Easy
Current Recirculation and Decay Modes
Calculating Motor Driver Power Dissipation
Understanding Motor Driver Current Ratings
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV8811PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8811
DRV8811PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8811
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8811PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8811PWPR
HTSSOP
PWP
28
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 28
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
4.4 x 9.7, 0.65 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/A
www.ti.com
PACKAGE OUTLINE
PWP0028C
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
26X 0.65
28
1
2X
9.8
9.6
NOTE 3
8.45
14
15
B
0.30
0.19
0.1
C A B
28X
4.5
4.3
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
14
15
2X 0.2 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
5.18
4.48
THERMAL
PAD
0 -8
0.15
0.05
0.75
0.50
DETAIL A
A 20
TYPICAL
28
1
3.1
2.4
4223582/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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EXAMPLE BOARD LAYOUT
PWP0028C
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.1)
METAL COVERED
BY SOLDER MASK
SYMM
28X (1.5)
1
28X (0.45)
28
SEE DETAILS
(R0.05) TYP
(5.18)
26X (0.65)
(0.6)
SYMM
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.2) TYP
( 0.2) TYP
VIA
15
14
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4223582/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0028C
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.1)
BASED ON
0.125 THICK
STENCIL
28X (1.5)
METAL COVERED
BY SOLDER MASK
1
28
28X (0.45)
(R0.05) TYP
26X (0.65)
(5.18)
BASED ON
0.125 THICK
STENCIL
SYMM
15
14
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
3.47 X 5.79
3.10 X 5.18 (SHOWN)
2.83 X 4.73
2.62 X 4.38
4223582/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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