Texas Instruments | DRV8801-Q1 DMOS Full-Bridge Motor Drivers (Rev. C) | Datasheet | Texas Instruments DRV8801-Q1 DMOS Full-Bridge Motor Drivers (Rev. C) Datasheet

Texas Instruments DRV8801-Q1 DMOS Full-Bridge Motor Drivers (Rev. C) Datasheet
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DRV8801-Q1
SLVSAS7C – FEBRUARY 2011 – REVISED JUNE 2016
DRV8801-Q1 DMOS Full-Bridge Motor Drivers
1 Features
3 Description
•
•
The DRV8801-Q1 provides a versatile power driver
solution with a full H-bridge driver. The device can
drive a brushed DC motor or one winding of a
stepper motor, as well as other devices like
solenoids. A simple PHASE/ENABLE interface allows
easy interfacing to controller circuits
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With The Following Results:
– Device Temperature Grade 1: TA = –40ºC to
125ºC
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4
Low RDS(on) Outputs (0.83-Ω HS + LS Typical)
Low-Power Sleep Mode
100% PWM Supported
8–38 V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
Configurable Overcurrent Limit
Protection Features
– VBB Undervoltage Lockout (UVLO)
– Overcurrent Protection (OCP)
– Short-to-supply Protection
– Short-to-ground Protection
– Overtemperature Warning (OTW)
– Overtemperature Shutdown (OTS)
– Overcurrent and Overtemperature Fault
Conditions Indicated on Pins (nFAULT)
The output stages use N-channel power MOSFETs
configured as ½-H-bridges. The DRV8801-Q1 is
capable of peak output currents up to ±2.8 A and
operating voltages up to 38 V. An internal charge
pump generates needed gate drive voltages.
A low-power sleep mode is provided which shuts
down internal circuitry to achieve very low quiescent
current draw. This sleep mode can be set using a
dedicated nSLEEP pin.
Internal
protection
functions
are
provided:
undervoltage lockout, overcurrent protection, short-tosupply
protection,
short-to-ground
protection,
overtemperature warning, and overtemperature
shutdown. Overcurrent (including short-to-ground and
short-to-supply) and overtemperature fault conditions
are indicated via an nFAULT pin.
The DRV8801-Q1 is packaged in a 16-pin QFN
package with exposed thermal pad, providing
enhanced thermal dissipation.
2 Applications
•
•
•
•
Device Information(1)
PART NUMBER
Automotive Body Systems
Door Locks
HVAC Actuators
Piezo Alarm
DRV8801-Q1
PACKAGE
QFN (16)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
8 V to 38 V
PH/EN
DRV8801-Q1
nSLEEP
Controller
nFAULT
Brushed DC
Motor Driver
BDC
VPROPI
Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
DRV8801-Q1
SLVSAS7C – FEBRUARY 2011 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9
Power Supply Recommendations...................... 18
9.1 Bulk Capacitance .................................................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2016) to Revision C
Page
•
Changed one of the MODE1 pins to MODE2 in the Functional Block Diagram section ..................................................... 10
•
Added the Receiving Notification of Documentation Updates section ................................................................................ 20
Changes from Revision A (January 2014) to Revision B
Page
•
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 5
•
Added tpd to the Overcurrent Control Timing image ............................................................................................................. 13
Changes from Original (February 2011) to Revision A
Page
•
Deleteted part nuimber DRV8800-Q! from page header........................................................................................................ 1
•
Added AEC-Q100 qualifications to Features list .................................................................................................................... 1
•
Added an Applications section to the front page .................................................................................................................... 1
•
Deleted Ordering Information table ........................................................................................................................................ 1
•
Deleted DRV8800-Q! pinout diagram..................................................................................................................................... 4
•
Deleted Terminal Name column for DRV8800-Q1 from Terminal Functions table ................................................................ 4
•
Deleted DRV8800-Q1 pin descriptions for pins 5 and 9 from Terminal Functions table........................................................ 4
•
Added a Thermal Information table ........................................................................................................................................ 5
•
Removed DRV8800-Q1 part number from column heading of Thermal Information table .................................................... 5
•
Changed parameter name and test condition for Electrical Characteristics, VTRP row ........................................................ 6
•
Added two notes to end of Electrical Characteristics table .................................................................................................... 6
•
Changed "Overcurrent protection period" parameter to "Overcurrent retry time" .................................................................. 7
•
Deleted DRV8800-Q1 from text of Device Operation section .............................................................................................. 10
•
Deleted DRV8800-Q1 Functional Block Diagram................................................................................................................. 10
2
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•
Updated the Overcurrent Control Timing image................................................................................................................... 13
•
Changed active low to low in Diagnostic Output section...................................................................................................... 14
•
Deleted VREG section; deleted "(DRV8801-Q1 Only)" from VPROPI section title.............................................................. 14
•
Changed a value in row 5 of the Control Logic Table .......................................................................................................... 14
•
Added a row to Control Logic Table ..................................................................................................................................... 14
•
Deleted DRV8800-Q1 from the text of the Low-Power Mode sedtion.................................................................................. 14
•
Deleted DRV8800-Q1 Typical Application Diagram ............................................................................................................. 15
•
Corrected part number in DRV8801-Q1 application diagram............................................................................................... 15
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5 Pin Configuration and Functions
MODE1
nFAULT
VPROPI
VCP
15
14
13
8
4
VBB
ENABLE
7
3
SENSE
nSLEEP
Exposed
Thermal Pad
6
2
OUT+
GND
5
1
MODE2
PHASE
16
RTY Package
16-Pin QFN With Exposed Thermal Pad
Top View
12
GND
11
CP2
10
CP1
9
OUT–
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CP1
10
PWR
Charge-pump capacitor 1
CP2
11
PWR
Charge-pump capacitor 2
ENABLE
4
I
GND
Enable logic input
2, 12
PWR
MODE 1
16
I
Mode logic input
MODE 2
5
I
Mode 2 logic input
nFAULT
15
O
Fault open-drain output
nSLEEP
3
I
Sleep logic input
OUT+
6
O
DMOS full-bridge output positive
OUT–
9
O
DMOS full-bridge output negative
PHASE
1
I
Phase logic input for direction control
SENSE
7
I
Sense power return
VBB
8
PWR
Load supply voltage
VCP
13
O
Reservoir capacitor
VPROPI
14
O
Winding current proportional voltage output
Thermal
Pad
PAD
PWR
4
Ground
Exposed pad for thermal dissipation; connect to GND pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
–0.3
40
UNIT
VBB
Load supply voltage (2)
IOUT
Output current
0
2.8
A
VSense
Sense voltage
–500
500
mV
VBB_OUT
VBB to OUTx
36
V
VOUT_SEN
OUTx to SENSE
36
V
VDD
Logic input voltage (2)
7
V
PD
Continuous total power dissipation
TA
Operating free-air temperature
–40
125
°C
TJ
Maximum junction temperature
–40
150
°C
Tstg
Storage temperature
–40
125
°C
(1)
(2)
–0.3
V
See Thermal Information
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2000
Corner pins (1, 4, 5, 8, 9, 12,
13, and 16)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
V
VBB
Power supply voltage
8
38
VDD
Logic voltage
0
5.5
V
fPWM
Applied PWM signal (PHASE and ENABLE)
0
100
kHz
TA
Ambient temperature
–40
125
°C
6.4 Thermal Information
DRV8801-Q1
THERMAL METRIC (1)
RTY (QFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
46.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43.0
°C/W
RθJB
Junction-to-board thermal resistance
22.5
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
22.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
POWER SUPPLIES (VBB)
VBB
VBB operating voltage
IVBB
VBB operating supply current
IVBBQ
VBB sleep-mode supply current
8
fPWM < 50 kHz
38
6
Charge pump on, outputs disabled
mA
3.2
nSLEEP = 0, TJ = 25°C
V
10
μA
CONTROL INPUTS (PHASE, ENABLE, MODE1, MODE2, nSLEEP)
VIL
Input logic low voltage
VIH
Input logic high voltage
VIHYS
Input hysteresis
IIL
Input logic low current
IIH
Input logic high current
IIL
Input logic low current
IIH
Input logic high current
VIL
Input logic low voltage
VIH
Input logic high voltage
IIL
Input logic low current
IIH
Input logic high current
0.8
PHASE, ENABLE,
MODE1, MODE2
2
PHASE, MODE1, MODE2
ENABLE
100
500
800
–20
< –2
20
VIN = 2.0 V
<1
20
VIN = 0.8 V
16
40
VIN = 2.0 V
40
100
VIN = 0.8 V
0.8
2.7
nSLEEP
V
mV
µA
μA
V
V
VIN = 0.8 V
<1
10
VIN = 2.7 V
27
50
0.4
V
12
13.8
V
μA
CONTROL OUTPUTS (nFAULT)
VOL
Output logic low voltage
IO = 1 mA
VBBNFR
VBB nFAULT release
8 V < VBB < 40 V
DMOS DRIVERS (OUT+, OUT-, SENSE, VPROPI)
RDS(on)
Output ON resistance
VTRIP
SENSE trip voltage
Vf
Body diode forward voltage
AVDA
Differential AMP gain
Source driver, IOUT = –2.8 A, TJ = 25°C
0.48
Source driver, IOUT = –2.8 A, TJ = 125°C
0.74
Sink driver, IOUT = 2.8 A, TJ = 25°C
0.35
Sink driver, IOUT = 2.8 A, TJ = 125°C
0.52
RSENSE between SENSE and GND
500
0.85
0.7
mV
Source diode, If = –2.8 A
1.4
Sink diode, If = 2.8 A
1.4
SENSE = 0.1 V to 0.4 V
Ω
5
V
V/V
PROTECTION CIRCUITRY
VUV
UVLO threshold
VBB increasing
IOCP
Overcurrent protection trip level
VBB = 8.0 approximately 38 V
TOTW
Thermal warning temperature
Die temperature Tj (1)
T OTW HYS
Thermal warning hysteresis
Die temperature Tj
TOTS
TOTS
(1)
(2)
6
HYS
Thermal shutdown temperature
Die temperature Tj
Thermal shutdown hysteresis
Die temperature Tj
6.5
(2)
3
7.5
V
A
160
°C
15
°C
175
°C
15
°C
Once the device reaches the thermal warning temperature of 160ºC, the device remains in thermal warning until the device cools to
145ºC. This is known as the thermal-warning hysteresis of the device.
Once the device reaches the thermal shutdown temperature of 175ºC, the device remains in thermal shutdown until the device cools to
160ºC. This is known as the thermal-shutdown hysteresis of the device.
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6.6 Timing Requirements
MIN
tpd
Propagation delay time
tCOD
Crossover delay
tDEG
Overcurrent deglitch time
tOCP
Overcurrent retry time
NOM
Input edge to source or sink ON
600
Input edge to source or sink OFF
100
MAX
UNIT
ns
500
ns
3
µs
1.2
ms
SLEEP
ENABLE
PHASE
MODE
VBB
VOUT+
0
VBB
VOUT-
0
IOUTX
0
A
1
2
3
4
5
6
7
VIN
1
8
9
VIN
5
6
7
OUT+
OUT-
3
2
OUT+
4
OUT8
9
A
Charge Pump and VREG power on delay (~200 us)
Figure 1. PWM Control Timing
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VOUTA
VOUTB High-Z
IPEAK
IOUTx
IOCP
Enable,
Source
or Sink
Charge Pump
Counter
tOCP
tDEG
NFAULT
Motor Lead
Short Condition
Normal DC
Motor Capacitance
Figure 2. Overcurrent Control Timing
8
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6.7 Typical Characteristics
Quiescent Current (µA)
9
8
1.02
±40ƒC
Source Driver
1.00
25°C
125°C
RDS(ON) (normalized)
10
7
6
5
4
3
2
Sink Driver
0.98
0.96
0.94
0.92
0.90
0.88
1
0
0.86
8V
32 V
8V
38 V
Supply Voltage
32V
Supply Voltage
C001
Figure 3. IVBBQvs VBB
C002
Figure 4. RDS(ON) vs VBB (Normalized to VBB = 8 V)
Charge Pump Voltage (V)
60
50
40
30
20
10
0
5V
15 V
25 V
35 V
Supply Voltage
45 V
C003
Figure 5. VCP vs VBB
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7 Detailed Description
7.1 Overview
The DRV8801-Q1 is an integrated motor driver solution for brushed-DC motors. The device integrates a DMOS
H-bridge and current sense and protection circuitry. The device can be powered with a supply voltage between 8
and 38 V, and is capable of providing an output current up to 2.8 A peak.
A simple PHASE-ENABLE interface allows control of the motor speed and direction.
A shunt amplifier output is provided for accurate current measurements by the system controller. The VPROPI
pin will output a voltage that is 5 times the voltage seen at the SENSE pin.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
7.2 Functional Block Diagram
VCP
Power
VBB
bulk
0.1 µF
0.1 µF
VCP
VBB
VBB
OUT1
PreDriver
VCP
CP1
0.1 µF
CP2
Charge
Pump
BDC
VCP
VBB
GND
OUT2
PreDriver
Regulators
GND
SENSE
Core
Logic
PPAD
RSENSE
PHASE
VMCU
ENABLE
Protection
MODE1
Overcurrent
Monitoring
MODE2
nSLEEP
Inputs
Outputs
nFAULT
Temperature
Sensor
x5
VPROPI
RVPROPI
Voltage
Monitoring
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7.3 Feature Description
7.3.1 Power Supervisor
The control input, nSLEEP, is used to minimize power consumption when the DRV8801-Q1 device is not in use.
The nSLEEP input disables much of the internal circuitry, including the internal voltage rails and charge pump.
nSLEEP is asserted logic low. A logic high on this input pin results in normal operation. When switching from low
to high, the user should allow a 1-ms delay before applying PWM signals. This time is needed for the charge
pump to stabilize.
10
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Feature Description (continued)
7.3.2 Bridge Control
Table 1 shows the logic for the DRV8801-Q1:
Table 1. Bridge Control Logic Table
nSLEEP
PHASE
ENABLE
MODE1
MODE2
OUTA
OUTB
OPERATION
0
X
X
X
X
1
0
1
X
X
Z
Z
Sleep mode
L
H
1
1
1
X
Reverse
X
H
L
Forward
1
0
0
1
1
0
0
X
H
L
Fast decay
0
X
L
H
Fast decay
1
X
0
1
0
L
L
Low-side Slow
decay
1
X
0
1
1
H
H
High-side Slow
decay
To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high impedance
state as the current approaches 0 A.
The path of current flow for each of the states in the above logic table is shown in Figure 6.
7.3.2.1 MODE 1
Input MODE 1 is used to toggle between fast-decay mode and slow-decay mode. A logic high puts the device in
slow-decay mode.
7.3.2.2 MODE 2
MODE 2 is used to select which set of drivers (high side versus low side) is used during the slow-decay
recirculation. MODE 2 is meaningful only when MODE 1 is asserted high. A logic high on MODE 2 has current
recirculation through the high-side drivers. A logic low has current recirculation through the low-side drivers.
7.3.3 Fast Decay with Synchronous Rectification
This decay mode is equivalent to a phase change where the FETs opposite of the driving FETs are switched on
(2 in Figure 6). When in fast decay, the motor current is not allowed to go negative because this would cause a
change in direction. Instead, as the current approaches zero, the drivers turn off. See the Power Dissipation
section for an equation to calculate power.
7.3.4 Slow Decay with Synchronous Rectification (Brake Mode)
In slow-decay mode, both low-side and high-side drivers turn on, allowing the current to circulate through the
low-side and high-side body diodes of the H-bridge and the load (3 and 4 in Figure 6). See the Power Dissipation
section for equations to calculate power for both high-side and low-side slow decay.
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VM
4
1 Drive
1
xOUTA
xOUTB
3
2
Fast decay with synchronous rectification
3 Low-side slow decay with synchronous rectification
2
4 High-side slow decay with synchronous rectification
xISEN
R(SENSE)
Figure 6. H-Bridge Operation Modes
7.3.5 Charge Pump
The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF
ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF
ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the highside DMOS devices.
7.3.6 SENSE
A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes. To
minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor should have an
independent ground return to the star ground point. This trace should be as short as possible. For low-value
sense resistors, the IR drops in the PCB can be significant, and should be taken into account.
To set a manual overcurrent trip threshold, place a resistor between the SENSE pin and GND. When the SENSE
pin rises above 500 mV, the H-bridge output is disabled (hi-Z). The device automatically retries with a period of
t(OCP).
The overcurrent trip threshold can be calculated using Equation 1.
I(trip) = 500 mV/R
(1)
The overcurrent trip level selected cannot be greater than I(OCP).
12
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V(OUTx)
Hi-Z
I(PEAK)
I(OUTx)
I(OCP)
Enable,
Source
or Sink
t(DEG)
tpd
t(OCP)
nFAULT
Motor Lead
Short Condition
Normal DC
No Fault Condition
Figure 7. Overcurrent Control Timing
7.3.7 VPROPI
The VPROPI output is equal to approximately five times the voltage present on the SENSE pin. VPROPI is
meaningful only if there is a resistor connected to the SENSE pin. If the SENSE pin is connected to ground,
VPROPI measures 0 V. Also note that during slow decay (brake), VPROPI measures 0 V. VPROPI can output a
maximum of 2.5 V, because at 500 mV on SENSE, the H-bridge is disabled.
7.3.8 Protection Circuits
The DRV8801-Q1 device is fully protected against VBB undervoltage, overcurrent, and overtemperature events.
Table 2. DRV8801-Q1 Fault Responses
FAULT
ERROR REPORT
H-BRIDGE
CHARGE PUMP
RECOVERY
VBB undervoltage (UVLO)
No error report – nFAULT
is hi-Z
Disabled
Shut Down
VBB > VUVLO RISING
Overcurrent (OCP)
nFAULT pulled low
Disabled
Operating
Retry time, t(OCP)
Overtemperature Warning
(OTW)
nFAULT pulled low
Enabled
Operating
TJ < T(OTW) – Thys(OTW)
Overtemperature
Shutdown (OTS)
nFAULT remains pulled
low (set during OTW)
Disabled
Shut Down
TJ < T(OTS) – Thys(OTS)
7.3.8.1 VBB Undervoltage Lockout (UVLO)
If at any time the voltage on the VBB pin falls below the undervoltage lockout threshold voltage, all FETs in the Hbridge are disabled and the charge pump is disabled. The nFAULT pin does not report the UVLO fault condition
and remains hi-Z. Operation resumes when VBB rises above the UVLO threshold.
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7.3.8.2 Overcurrent Protection (OCP)
The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not
shorted to supply or ground. If a short is detected, all FETs in the H-bridge are disabled, nFAULT is driven low,
and a t(OCP) fault timer is started. After this period, t(OCP), the device is then allowed to follow the input commands
and another turn-on is attempted (nFAULT releases during this attempt). If there is still a fault condition, the cycle
repeats. If the short condition is not present after t(OCP) expires, normal operation resumes and nFAULT is
released.
7.3.8.3 Overtemperature Warning (OTW)
If the die temperature increases past the thermal warning threshold the nFAULT pin is driven low. When the die
temperature has fallen below the hysteresis level, the nFAULT pin is released. If the die temperature continues to
increase, the device enters overtemperature shutdown as described in the Overtemperature Shutdown (OTS)
section.
7.3.8.4 Overtemperature Shutdown (OTS)
If the die temperature exceeds the thermal shutdown temperature, all FETs in the H-bridge are disabled and the
charge pump shuts down. The nFAULT pin remains pulled low during this fault condition. When the die
temperature falls below the hysteresis threshold, operation automatically resumes.
7.3.9 Thermal Shutdown (TSD)
Two die-temperature monitors are integrated on the chip. As die temperature increases toward the maximum, a
thermal warning signal is triggered at 160°C. This fault drives nFAULT low, but does not disable the operation of
the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs are disabled
until the internal temperature falls below a hysteresis of 15°C.
7.4 Device Functional Modes
The DRV8801-Q1 device is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is
disabled and the H-bridge FETs are disabled hi-Z. The DRV8801-Q1 device is brought out of sleep mode
automatically if nSLEEP is brought logic high.
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8801-Q1 device is used in medium voltage brushed DC motor control applications.
8.2 Typical Application
Controller
VMCU
ADC
DRV8801-Q1
10 NŸ
1
VMCU
2
GPIO
3
4
5
6
7
MODE 2
MODE 1
VPROPI
PHASE
VCP
GND
GND
nSLEEP
CP2
ENABLE
CP1
OUT+
PPAD
8
nFAULT
SENSE
VBB
100 NŸ
15
RC Filter
14
1000 pF
13
0.1 µF
12
0.1 µF
11
VBB
10
9
0
0.2 Ÿ
OUT-
16
0.1µF
100µF
BDC
Figure 8. Typical Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
DESIGN PARAMETER
REFERENCE
Motor Voltage
VBB
EXAMPLE VALUE
24 V
Motor RMS Current
IRMS
0.8 A
Motor Startup Current
ISTART
2A
Motor Current Trip Point
ITRIP
2.5 A
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8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The motor voltage to use will depend on the ratings of the motor selected and the desired RPM. A higher voltage
spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage
also increases the rate of current change through the inductive motor windings.
8.2.2.2 Power Dissipation
The power dissipation of the DRV8801-Q1 is a function of the RMS motor current and the each output’s FET
resistance (RDS(ON)).
Power ≈ IRMS2 x (High-Side RDS(ON) + Low-Side RDS(ON))
(2)
For this example, the ambient temperature is 35°C, and the junction temperature reaches 65°C. At 65°C, the
sum of RDS(ON) is about 1 Ω. With an example motor current of 0.8 A, the dissipated power in the form of heat
will be 0.8 A2x 1 Ω = 0.64 W.
The temperature that the DRV8801-Q1 reaches will depend on the thermal resistance to the air and PCB. It is
important to solder the device thermal pad to the PCB ground plane, with vias to the top and bottom board
layers, to dissipate heat into the PCB and reduce the device temperature. In the example used here, the
DRV8801-Q1 had an effective thermal resistance RθJA of 47°C/W, and:
TJ = TA + (PD x RθJA) = 35°C + (0.64 W x 47°C/W) = 65°C
(3)
8.2.2.3 Motor Current Trip Point
When the voltage on pin SENSE exceeds VTRIP (0.5 V), overcurrent is detected. The RSENSE resistor should be
sized to set the desired ITRIP level.
RSENSE = 0.5 V / ITRIP
(4)
To set ITRIP to 2.5 A, RSENSE = 0.5 V / 2.5 A = 0.2 Ω.
To prevent false trips, ITRIP must be higher than regular operating current. Motor current during startup is typically
much higher than steady-state spinning, because the initial load torque is higher, and the absence of back-EMF
causes a higher voltage and extra current across the motor windings.
It is beneficial to limit startup current by using series inductors on the DRV8801-Q1 output, as that allows ITRIP to
be lower, and it may decrease the system’s required bulk capacitance. Startup current can also be limited by
ramping the forward drive duty cycle.
8.2.2.4 Sense Resistor Selection
For optimal performance, it is important for the sense resistor to be:
• Surface-mount
• Low inductance
• Rated for high enough power
• Placed closely to the motor driver
8.2.2.5 Drive Current
This current path is through the high-side sourcing DMOS driver, motor winding, and low-side sinking DMOS
driver. Power dissipation I2R loses in one source and one sink DMOS driver, as shown in Equation 5.
PD = I 2 (rDS(on)Source + rDS(on)Sink )
16
(5)
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8.2.3 Application Curves
Figure 9. Forward Drive, Fast Decay
Figure 10. Reverse Drive, Fast Decay
Figure 11. Forward Drive, Slow Decay
Figure 12. Reverse Drive, Slow Decay
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9 Power Supply Recommendations
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system.
• The capacitance of the power supply and its ability to source current.
• The amount of parasitic inductance between the power supply and motor systems.
• The acceptable voltage ripple.
• The type of motor used (Brushed DC, Brushless DC, Stepper).
• The motor braking method.
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VBB
+
±
+
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 13. Example Setup of Motor Drive System With External Power Supply
18
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10 Layout
10.1 Layout Guidelines
•
•
•
•
The printed-circuit-board (PCB) should use a heavy ground plane. For optimal electrical and thermal
performance, the DRV8801-Q1 must be soldered directly onto the board. On the underside of the DRV8801Q1 is a thermal pad, which provides a path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of
the PCB.
The load supply pin VBB, should be decoupled with an electrolytic capacitor (typically 100 µF) in parallel with
a ceramic capacitor (0.1 µF) placed as close as possible to the device.
The ceramic capacitors (0.1 µF) between VCP and VBB and between CP1 and CP2 should be placed as
close as possible to the device.
The SENSE resistor should be close as possible to the SENSE pin and ground return to minimize parasitic
inductance.
10.2 Layout Example
GND
0.1 µF
VCP
VPROPI
nFAULT
MODE 1
GND
PHASE
GND
GND
GND
CP2
nSLEEP
CP1
ENABLE
OUT-
0.1 µF
0.1 µF
+
GND
VBB
0.2 Ÿ
SENSE
OUT+
MODE 2
GND
VBB
GND
BDC
GND
Figure 14. RTY Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
QFN/SON PCB Attachment
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
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26-May-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
DRV8801QRTYRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
QFN
RTY
16
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
DRV
8801Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2016
OTHER QUALIFIED VERSIONS OF DRV8801-Q1 :
• Catalog: DRV8801
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-May-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8801QRTYRQ1
Package Package Pins
Type Drawing
QFN
RTY
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
4.25
B0
(mm)
K0
(mm)
P1
(mm)
4.25
1.15
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-May-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8801QRTYRQ1
QFN
RTY
16
3000
367.0
367.0
35.0
Pack Materials-Page 2
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