Texas Instruments | DRV8307 Brushless DC Motor Controller (Rev. A) | Datasheet | Texas Instruments DRV8307 Brushless DC Motor Controller (Rev. A) Datasheet

Texas Instruments DRV8307 Brushless DC Motor Controller (Rev. A) Datasheet
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DRV8307
SLVSCK2A – APRIL 2014 – REVISED FEBRUARY 2016
DRV8307 Brushless DC Motor Controller
1 Features
3 Description
•
The DRV8307 is a three half-bridge pre-driver that
drives six N-type MOSFETs 30 mA with a single
power supply. Aimed at sensored three-phase
brushless DC motors, the DRV8307 is driven by a
single PWM input and supports integrated
commutation logic with three Hall sensor inputs. A
separate 5-V regulator is also included to be used to
power Hall-effect sensors and other external
components.
1
•
•
•
•
•
•
•
•
Three-Phase Brushless DC Motor Controller
– Single PWM Input Controls Speed
Operating Supply Voltage 8.5 to 32 V
30-mA Gate-Drive Current to 6 N-Channel
MOSFETs
Integrated Current Sense Amplifier
5-V Regulator for Hall Sensors
Low-Power Standby Mode
Locked Rotor Detection and Restart
Integrated Overcurrent and Overtemperature
Protection
6- × 6-mm VQFN Package, 0.5-mm Pitch
2 Applications
•
•
•
Industrial Pumps and Fans
White Goods
Robotic Appliances
The DRV8307 includes a current sense input for
current limiting and protection. The current limit can
be set by adjusting the value of the RISENSE sense
resistor.
Motor operation (start and stop) is controlled through
the ENABLEn terminal. If the ENABLEn terminal is
set high and motor rotation has stopped, the device
enters into a low-power standby state, thereby
conserving overall system power during periods of
inactivity.
Protection features are also included in the DRV8307
device such as locked rotor detection, as well as
overcurrent and overtemperature protection and
undervoltage lockout to bolster overall system
robustness and reliability.
Device Information
ORDER NUMBER
DRV8307RHA
PACKAGE
VQFN (40)
BODY SIZE
6 mm × 6 mm
Simplified Schematic
8.5V to 32 V
PWM
ENABLEn
DIR
Controller
(optional)
BRAKE
HALLOUT
FAULTn
DRV8307
BLDC
Controller
Predrive
Commutation
Logic
ISEN
Current
Regulation
FETs
M
Hall sensors
Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8307
SLVSCK2A – APRIL 2014 – REVISED FEBRUARY 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
6
7
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1 Trademarks ........................................................... 25
11.2 Electrostatic Discharge Caution ............................ 25
11.3 Glossary ................................................................ 25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Original (April 2014) to Revision A
Page
•
Changed Features From: PWM Input for Speed Control To: Single PWM Input Controls Speed......................................... 1
•
Changed the Simplified Schematic ........................................................................................................................................ 1
•
Changed the DESCRIPTION of pin LOCKn in the Pin Functions table ................................................................................ 4
•
Changed the "Power supply voltage MAX value From: 35 To: 42 in the Absolute Maximum Ratings ................................. 5
•
Moved the "Storage temperature range" to the Absolute Maximum Ratings ........................................................................ 5
•
Changed the Handling Rating table To: ESD Ratings .......................................................................................................... 5
•
Added the Timing Requirements ........................................................................................................................................... 8
•
Changed text in the Output Pre-Drivers section From: "The low-side gate drive ULSG is driven to VM ..." To: The
low-side gate drive ULSG is driven to VOUTL.." .................................................................................................................... 15
•
Added text to the Clock PWM Mode section following Figure 10: "When the DRV8307 is driving a motor,..." ................... 19
•
Added the NOTE to the Application and Implementation section ........................................................................................ 20
•
Deleted text from the ENABLEn Considerations section: "If ENABLEn is immediately returned to the active state,
the motor slows and stops for 1 s, then starts again." ........................................................................................................ 21
•
Added section: Faster Starting and Stopping ...................................................................................................................... 21
•
Changed Figure 13 .............................................................................................................................................................. 22
•
Changed the Layout Example image .................................................................................................................................. 24
2
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5 Pin Configurations and Functions
W
WHSG
VLSG
V
VHSG
ULSG
U
UHSG
39
38
37
36
35
34
33
32
31 ISEN
WLSG
40
RHA Package
40-Pin (VQFN)
Top View
HU+ 1
30 CP1
HU– 2
29 CP2
HV+ 3
28 VCP
HV– 4
27 VM
Thermal Pad
HW+ 5
26 GND
GND
HW– 6
25 VINT
PWM 19
BRAKE 20
LOCKn 18
FAULTn 17
21 DIR
RSVD 15
RSVD 10
HALLOUT 16
22 ENABLEn
RSVD 14
23 RSVD
RSVD 9
RSVD 13
RSVD 8
RSVD 12
24 VREG
RSVD 11
VSW 7
Pin Functions
PIN
NAME
NUMBER
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS
POWER AND GROUND
CP1
30
I/O
CP2
29
I/O
GND
26, PPAD
I
VCP
28
Charge pump flying capacitor
Connect a 0.1-μF 35-V capacitor between CP1 and CP2
Ground reference. Terminal 26 and the
Power Pad are internally connected.
Connect to board GND
I/O
Charge pump storage capacitor
Connect a 1-μF 35-V ceramic capacitor to VM
Internal 1.8-V core voltage regulator
bypass
Bypass to GND with a 1-μF 6.3-V ceramic capacitor
VINT
25
I/O
VM
27
I
Motor supply voltage
Connect to motor supply voltage.
Bypass to GND with a 0.1-μF ceramic capacitor, plus a
large electrolytic capacitor (47 μF or larger is
recommended), with a voltage rating of 1.5× to 2.5× VM.
VREG
24
O
5-V regulator output. Active when
ENABLEn is active.
Bypass to GND with a 0.1-μF 10-V ceramic capacitor.
Can provide 5-V power to Hall sensors.
VSW
7
O
Switched VM power output. When
ENABLEn is active, VM is applied to this
terminal.
Can be used for powering Hall elements, along with
added series resistance.
BRAKE
20
I
Causes motor to brake. Polarity is
programmable. Internal pulldown resistor.
PWM
19
I
The clock input, used in clock frequency
mode and clock PWM mode. Internal
pulldown resistor.
DIR
21
I
Sets motor rotation direction. Internal
pulldown resistor.
CONTROL
(1)
I = input, O = output, OD = open-drain output, I/O = input/output
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Pin Functions (continued)
PIN
NAME
NUMBER
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS
Enables and disables the motor – active
low. Internal pulldown resistor.
ENABLEn
22
I
FAULTn
17
OD
Fault indicator – active low when
overcurrent, overtemperature, or rotor stall
detected. Open-drain output.
HALLOUT
16
OD
Outputs a TACH signal generated from the
Hall U sensor. Open-drain output.
LOCKn
18
OD
This open-drain output drives low when a
spinning motor reaches a consistent speed,
based on the period of Hall U.
RSVD
11
RSVD
12
RSVD
13
RSVD
14
RSVD
15
RSVD
23
Reserved
Can be floating or connected to ground.
Low-side current sense resistor
Connect to low-side current sense resistor
Measures motor phase voltages for
VFETOCP
Connect to motor windings
High-side FET gate outputs
Connect to high-side ½ H-bridge N-channel FET gate
Low-side FET gate outputs
Connect to low-side ½ H-bridge N-channel FET gate
Reserved
Do not connect. Leave floating.
POWER STAGE INTERFACE
ISEN
31
I
U
33
I
V
36
I
W
39
I
UHSG
32
O
VHSG
35
O
WHSG
38
O
ULSG
34
O
VLSG
37
O
WLSG
40
O
RSVD
8
RSVD
9
RSVD
10
HU+
1
I
Hall sensor U positive input
HU–
2
I
Hall sensor U negative input
HV+
3
I
Hall sensor V positive input
HV–
4
I
Hall sensor V negative input
HW+
5
I
Hall sensor W positive input
HW–
6
I
Hall sensor W negative input
4
Connect to Hall sensors. Noise filter capacitors may be
desirable, connected between the + and – Hall inputs.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1) (2) (3)
MIN
MAX
Power supply voltage (VM)
–0.3
42
V
Charge pump and high-side gate drivers (VCP, UHSG, VHSG, WHSG)
–0.3
50
V
Output terminal, low side gate drivers, charge pump flying cap and switched VM power supply
voltage (U, V, W, ULSG, VLSG, WLSG, CP1, CP2 VSW)
–0.6
40
V
Internal core voltage regulator (VINT)
–0.3
2.0
V
Linear voltage regulator output (VREG)
–0.3
5.5
V
Sense current terminal (ISEN)
–0.3
2.0
V
Digital terminal voltage (FAULTn, LOCKn, PWM, BRAKE, DIR, ENABLEn, HALLOUT)
–0.5
5.75
V
0
VREG
V
Hall sensor input terminal voltage (HU+, HU–, HV+, HV–, HW+, HW–)
UNIT
See Thermal
Information
Continuous total power dissipation
Operating junction temperature range, TJ
–40
150
°C
Storage temperature range, Tstg
–60
150
°C
(1)
(2)
(3)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
(1)
VM
Motor power supply voltage range, ENABLEn = 0, motor operating
VMDIS
Motor power supply voltage range, ENABLEn = 1, motor not operating
IVREG
VREG output current (2)
(2)
IVSW
VSW output current
fHALL
Hall sensor input frequency (3)
fPWM
Frequency on PWM
(1)
(2)
(3)
(4)
NOM
MAX
8.5
32
4.5
35
0
30
0
30
0
16
50
UNIT
V
mA
30
kHz
(4)
kHz
Note that at VM < 12 V, gate drive output voltage tracks VM voltage
Power dissipation and thermal limits must be observed
fHALL of 50 Hz to 6.7 kHz is best
Operational with frequencies above 50 kHz, but resolution is degraded
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6.4 Thermal Information
DRV8307
THERMAL METRIC (1)
RHA (40 PINS)
UNIT
RθJA
Junction-to-ambient thermal resistance (2)
33.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (3)
23.0
°C/W
(4)
RθJB
Junction-to-board thermal resistance
8.8
°C/W
ψJT
Junction-to-top characterization parameter (5)
0.3
°C/W
ψJB
Junction-to-board characterization parameter (6)
8.8
°C/W
(7)
2.3
°C/W
RθJC(bot)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
Junction-to-case (bottom) thermal resistance
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
18
mA
120
µA
VM SUPPLY
IVM
VM active current
ENABLEn = 0, VREG and
VSW open
ISTBY
VM standby current
ENABLEn = 1
VRESET
VM logic reset voltage
VM falling
VM rising
4.6
5.0
V
VREG SUPPLY
VVREG
Output voltage
IVREG
Output current
IOUT = 1 to 30 mA
4.75
5
5.25
V
30
mA
20
Ω
30
mA
VSW SUPPLY
RDS(ON)
VSW switch on-resistance
IVSW
Output current
IOUT = 1 to 30 mA
9
INTERNAL CLOCK OSCILLATOR
fCLK50
Internal CLK50 clock frequency
50
MHz
LOGIC-LEVEL INPUTS AND OUTPUTS
VIL
Low-level input voltage
VIH
High-level input voltage
IIL
Low-level input current
IIH
VIN = 3.3 V, DIR, BRAKE,
PWM
High-level input current
VIN = 3.3 V, ENABLEn
VHYS
RPD
Input hysteresis voltage
DIR, BRAKE, PWM
Input pulldown resistance
ENABLEn
0.8
V
1.5
5.5
V
–50
50
µA
20
100
6
9
0.1
0.3
0.5
50
100
150
350
550
µA
V
kΩ
OPEN DRAIN OUTPUTS
VOL
Low-level output voltage
IOUT = 2.0 mA
IOH
Output leakage current
VOUT = 3.3 V
0.5
V
1
µA
25
mV
5
mV
HALL SENSOR INPUTS
VHYS
Hall amplifier hysteresis voltage
∆VHYS
Hall amplifier hysteresis difference
15
VID
Hall amplifier input differential
50
VCM
Hall amplifier input common mode voltage
range
1.5
3.5
V
IIN
Input leakage current
–10
10
μA
Between U, V, W
Hx+ = Hx–
20
–5
mV
MOSFET DRIVERS
VOUTH
High-side gate drive output voltage
IO = 100 μA, VM ≥ 12V
VOUTL
Low-side gate drive output voltage
IO = 100 μA
IOUT
Peak gate drive current
VM + 10
V
10
V
30
mA
CYCLE-BY-CYCLE CURRENT LIMITER
VLIMITER
Voltage limit across RISENSE for the current
limiter
0.225
0.25
0.275
V
V
PROTECTION CIRCUITS
VSENSEOCP
Voltage limit across RISENSE for overcurrent
protection
1.7
1.8
1.9
VFETOCP
Voltage limit across each external FET’s
drain
850
1000
1200
VUVLO
VM undervoltage lockout
VM rising
8
VM falling
7.8
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOVLO
VM overvoltage lockout
TTSD
Thermal shutdown die temperature
tLOCK
Locked rotor detect time
VCPFAIL
VCP failure threshold
MIN
VM rising
TYP
MAX
32
34
36
150
160
UNIT
V
°C
3
s
VM + 3.0
V
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
HALL SENSOR INPUTS
tHDEG
Hall deglitch time
20
μs
6
µs
CYCLE-BY-CYCLE CURRENT LIMITER
tBLANK
Time that VLIMITER is ignored, from the start of the PWM cycle
PROTECTION CIRCUITS
tRETRY
Fault retry time after RLOCK or OTS
5
s
tSENSEOCP
Deglitch time for VSENSEOCP to trigger
5
µs
tFETOCP
Deglitch time for VFETOCP to trigger
5
µs
6.7 Typical Characteristics
6
800
4
Turn-on Time (ns)
VREG Voltage (V)
5
3
2
1
600
400
200
0
0
±1
0
50
100
150
Current (mA)
0
50
100
150
200
Series Resistance (Ÿ)
C001
250
300
C001
With the CSD88537ND FETs, a series resistor was added to the
high-side gate drive, and the VGS rise time was measured.
Figure 1. VREG Load Capability
8
Figure 2. FET Turn-On Time vs Series Resistance
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7 Detailed Description
7.1 Overview
The DRV8307 device controls 3-phase brushless DC motors using a speed and direction input interface and Hall
signals from the motor. The device drives N-channel MOSFETs with 10-V VGS and a gate drive current of 30 mA.
The speed of the motor is controlled by varying the duty cycle of the input clock (pulse-width modulation). Motor
speed is indicated on the HALLOUT terminal, which follows the HALL U transitions.
When the DRV8307 device begins spinning a motor, it initially uses all three Hall sensor phases to commutate.
After a constant speed is reached, the LOCKn terminal is pulled low and only one Hall sensor becomes used;
this feature reduces jitter by eliminating the error caused by non-ideal Hall device placement and matching.
Numerous protection circuits prevent system components from being damaged during adverse conditions.
Monitored aspects include motor voltage and current, gate drive voltage and current, device temperature, and
rotor lockup. When a fault occurs, the DRV8307 device stops driving and pulls FAULTn low, in order to prevent
FET damage and motor overheating.
The DRV8307 device is packaged in a compact 6 × 6-mm, 40-terminal VQFN with a 0.5-mm terminal pitch, and
operates through an industrial ambient temperature range of –40°C to 85°C.
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7.2 Functional Block Diagram
VM
VM
VM
bulk
Power
UHSG
CP1
Charge
Pump
0.1 µF
CP2
VSW or VREG
VCP
Phase U
pre-driver
U
10 V
VM
ULSG
VCP
VCP
VM
1 µF
VINT
1.8-V Linear
Regulator
VREG
5-V Linear
Regulator
VCP
VHSG
1 µF
Phase V
pre-driver
V
10 V
VLSG
0.1 µF
VSW
VM
ENABLE#
GND
Hall
Power
VCP
WHSG
10 V
PPAD
10-V Linear
Regulator
Phase W
pre-driver
Hall
U
W
Hall
V
Hall
W
10 V
WLSG
-
PWM
DIR
BRAKE
VLIMITER
PWM
Limiter
ISEN
+
Control
Inputs
Core
Logic
ENABLEn
+
Hall
Differential
Comparators
Outputs
RISENSE
VSENSEOCP
SENSE
OCP
HU+
HU±
Optional
HALLOUT
Voltage
Monitoring
+
Thermal
Sensor
+
LOCKn
FAULTn
10
HV±
Optional
+
Oscillator
HV+
-
-
HW+
HW±
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7.3 Feature Description
7.3.1 Hall Comparators
Three comparators are provided to process the raw signals from Hall effect transducers to commutate the motor.
The Hall amplifiers sense zero crossings of the differential inputs and pass the information to digital logic.
The Hall amplifiers have hysteresis, and their detect threshold is centered at 0. Note, hysteresis is defined as
shown in Figure 3:
Hall
Differential
Voltage
VHYS
0V
Hall Amplifier
Output
(Internal)
Figure 3. Hall Amplifier Hysteresis
In addition to hysteresis, the Hall inputs are deglitched with a circuit that ignores any extra Hall transitions for a
period of 20 μs after sensing a valid transition. This prevents PWM noise from being coupled into the Hall inputs,
which can result in erroneous commutation.
If excessive noise is still coupled into the Hall comparator inputs, it may be necessary to add capacitors between
the + and – inputs of the Hall comparators, and (or) between the input or inputs and ground.
The ESD protection circuitry on the Hall inputs implements a diode to VREG. Because of this diode, the voltage
on the Hall inputs should not exceed the VREG voltage.
Since VREG is disabled in standby mode (ENABLEn inactive), the Hall inputs should not be driven by external
voltages in standby mode. The DRV8307 device specifies if the Hall sensors are powered from VREG or VSW;
however, if the Hall sensors are powered externally, they should be disabled when the DRV8307 is put into
standby mode. In addition, the Hall sensors should be powered-up before enabling the motor, or an invalid Hall
state may cause a delay in motor operation.
7.3.2 HALLOUT Output
The HALLOUT terminal indicates the speed of the motor. It follows the transitions observed from the HALL U hall
sensor. Figure 4 shows the HALLOUT signal.
HALL_U
HALL_V
HALL_W
HALLOUT
Figure 4. HALLOUT Relationship to Hall Transitions
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Feature Description (continued)
7.3.3 Enable, Reset, and Clock Generation
The ENABLEn terminal is used to start and stop motor operation. The ENABLEn terminal is active low.
When ENABLEn is active, operation of the motor is enabled. When ENABLEn is made inactive, the motor
coasts. After motor rotation has stopped (when no transitions occur on the HALLOUT terminal for a period of 1
s), the DRV8307 device enters a low-power standby state.
When in the standby state:
• The motor driver circuitry is disabled (all gate drive outputs are driven low, so the FET outputs are highimpedance).
• The gate drive regulator and charge pump are disabled.
• The VREG regulator and VSW power switch are disabled.
• All analog circuitry is placed into a low power state.
• The digital circuitry in the device still operates.
All internal logic is reset in two different ways:
• Upon device power-up
• When VM drops below VRESET
An internal clock generator provides all timing for the DRV8307 device. The master oscillator runs at 100 MHz.
This clock is divided to a nominal 50-MHz frequency that clocks the remainder of the digital logic.
7.3.4 Commutation
For 3-phase brushless DC motors, rotor position feedback is provided from Hall effect transducers mounted on
the motor. These transducers provide three overlapping signals, each 60° apart. The windings are energized in
accordance with the signals from the Hall sensors to cause the motor to move.
In addition to the Hall sensor inputs, commutation is affected by a direction control, which alters the direction of
motion by reversing the commutation sequence. Control of commutation direction is by the DIR input terminal.
If the commanded direction changes while the motor is moving, the device allows the motor to coast until the
motor stops. The stopped condition is determined by measuring the period of the HALL_U signal; when the
period exceeds 160 ms, typical operation resumes and the motor starts spinning in the commanded direction.
This prevents excessive current flow in the output stage if the motor is reversed while running at speed.
In standard 120° commutation, mis-positioning the Hall sensors can cause motor noise, vibration, and torque
ripple. 120° commutation using a single Hall sensor (single-Hall commutation) can improve motor torque ripple
and vibration because it relies on only one Hall edge for timing.
7.3.4.1 120° 3-Hall Commutation
In standard 120° commutation, the motor phases are energized using simple combination logic based on all
three Hall sensor inputs.
Standard 120° commutation is in accordance with Table 1, Figure 5, and Figure 6:
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Feature Description (continued)
Table 1. Standard 120° Commutation (1)
HALL INPUTS
STATE
DIR = 1
U_H
(1)
(2)
V_H
PRE-DRIVE OUTPUTS
DIR = 0
W_H U_H
V_H
Phase U
W_H
U_HSGATE
Phase V
U_LSGATE
Phase W
V_HSGATE V_LSGATE
L / !PWM
W_HSGATE
W_LSGATE
(2)
1
L
L
H
H
H
L
L
L
PWM
L
H
2
L
H
H
H
L
L
PWM
L / !PWM (2)
L
L
L
H
3
L
H
L
H
L
H
PWM
L / !PWM (2)
L
H
L
L
4
H
H
L
L
L
H
L
L
L
H
PWM
L / !PWM (2)
5
H
L
L
L
H
H
L
H
L
L
PWM
L / !PWM (2)
L / !PWM
(2)
6
H
L
H
L
H
L
L
H
PWM
L
L
1X
H
H
H
L
L
L
L
L
L
L
L
L
2X
L
L
L
H
H
H
L
L
L
L
L
L
Hall sensor is H if the positive input terminal voltage is higher than the negative input terminal voltage. States 1X and 2X are illegal input
combinations.
During states where the phase is driven with a PWM signal, using asynchronous rectification, the LS gate is held off (L); using
synchronous rectification, the LS gate is driven with the inverse of the HS gate.
State
1
2
3
4
5
6
1
2
3
4
5
6
1
Hall U
Hall V
Hall W
Phase U HS
Phase U LS
(1)
(1)
Phase V HS
Phase V LS
(1)
(1)
(1)
Phase W HS
Phase W LS
(1)
(1)
(1) !PWM for Sync Rectification
Figure 5. Standard 120° Commutation (DIR = 1)
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State
1
2
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3
4
5
6
1
2
3
4
5
6
1
Hall U
Hall V
Hall W
Phase U HS
Phase U LS
(1)
(1)
Phase V HS
Phase V LS
(1)
(1)
(1)
Phase W HS
Phase W LS
(1)
(1)
Figure 6. Standard 120° Commutation (DIR = 0)
7.3.4.2 120° Single-Hall Commutation
To generate commutation timing for single-Hall commutation, a digital timer is used to create a clock that runs at
960× the Hall sensor frequency. Only one Hall sensor input, HALL_U, is used for commutation; this eliminates
any torque ripple caused by mechanical or electrical offsets of individual Hall sensors.
Single-Hall commutation is only enabled when the motor is operating at a nearly constant speed or speed-locked
condition. To control this function, logic is used to determine when the speed is constant. This logic generates
the LOCK signal. The LOCK signal is also output on the LOCKn terminal.
Until LOCK goes active (for example, at start-up, stop, or application of a sudden load that causes motor speed
to drop very quickly), standard 120° commutation is used requiring all three Hall sensors.
Timing of 120° single-Hall commutation is essentially the same as standard 120° commutation shown previously.
However, there are small time differences in when the transitions occur.
7.3.5 Braking
Motor braking can be initiated by the BRAKE terminal.
Table 2. Brake Behavior
14
BRAKE Terminal
Resulting Function
0
Not brake
1
Brake
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When the motor is braking, all low-side drivers are held in an on state, causing all low-side FETs to turn on.
7.3.6 Output Pre-Drivers
The output drivers for each phase consist of N-channel and P-channel MOSFET devices arranged as a CMOS
buffer. They are designed to directly drive the gate of external N-channel power MOSFETs. The outputs provide
synchronous rectification operation. In synchronous rectification, the low-side FET is turned on when the high
side is turned off.
The high-side gate drive output UHSG is driven to VCP whenever the duty cycle output U_PD from the PWM
generator is high, the enable signal U_HS from the commutation logic is active, and the current limit (VLIMITER) is
not active. If the high-side FET is on and a current limit event occurs, the high-side FET is immediately turned off
until the next PWM cycle.
The low-side gate drive ULSG is driven to VOUTL whenever the internal signal U_LS is high, or whenever
synchronous rectification is active and UHSG is low.
Phases V and W operate in an identical fashion.
VCP
UHGS
Dead
Time
Generator
and
Drive
Logic
U_PD
ILIMIT
To Other
Phases
U
VM
11 V
U_LS
ULSG
BRAKE
Figure 7. Pre-Driver Block Diagram
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15 µs
High Z
High Z
High Z
Low Z
HS drive
Low
Z
xHS
15 µs
High Z
Low Z
High Z
High Z
LS drive
Low
Z
xLS
Figure 8. Gate Control Behavior
The peak drive current of the pre-drivers is fixed at 30 mA.
When changing the state of the output, the peak current is applied for a short period of time (15 μs) to charge the
gate capacitance. After this time, a weak current source is used to keep the gate at the desired state.
During high-side turn-on, the low-side gate is held low with a low impedance. This prevents the gate-source
capacitance of the low-side FET from inducing turn-on. Similarly, during low-side turn-on, the high-side gate is
held off with a low impedance.
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time.
7.3.7 Current Limit
The current limit circuit activates if the voltage detected across the low-side sense resistor exceeds VLIMITER.
Note that the current limit circuit is ignored immediately after the PWM signal goes active for a short blanking
time, to prevent false trips of the current limit circuit.
If current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle. If synchronous
rectification is enabled when the current limit activates, the low-side FET is activated while the high-side FET is
disabled.
7.3.8 Charge Pump
Since the output stages use N-channel FETs, a gate drive voltage higher than the VM power supply is needed to
fully enhance the high-side FETs. The DRV8307 device integrates a charge pump circuit that generates a
voltage approximately 10 V more than the VM supply for this purpose.
The charge pump requires two external capacitors for operation. For details on these capacitors (value,
connection, and so forth), refer to Figure 9.
The charge pump is shut down when in standby mode (ENABLEn inactive).
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VM
VM
0.1 µF
35 V
CP1
0.1 µF
35 V
CP2
Charge
Pump
VCP
1 µF
10 V
To Pre-Drivers
Figure 9. Charge Pump Block Diagram
7.3.9 5-V Linear Regulator
A 5-V linear regulator (VREG) is provided to power internal logic and external circuitry, such as the Hall effect
sensors.
A capacitor must be connected from the VREG output to ground, even if the output is not used for external
circuitry. The recommended capacitor value is a 0.1-μF, 10-V ceramic capacitor.
The VREG output is designed to provide up to 30-mA output current, but power dissipation and thermal
conditions must be considered. As an example, with 24 V in and 20 mA out, power dissipated in the linear
regulator is 19 V × 20 mA = 380 mW.
The VREG regulator is shutdown in standby mode (when ENABLEn is inactive).
7.3.10 Power Switch
A low-current switch is provided in the DRV8307 device that can be used to power the Hall sensors or other
external circuitry through the VSW terminal. When ENABLEn is active the switch is turned on, connecting the
VSW terminal to VM. When ENABLEn is inactive the switch is turned off (standby mode).
7.3.11 Protection Circuits
A number of protection circuits are included in the DRV8307 device. Faults are reported by asserting the
FAULTn terminal (an active-low, open-drain output signal).
7.3.11.1 VM Undervoltage Lockout (UVLO)
If the VM power supply drops, there may not be enough voltage to fully turn on the output FETs. Operation in this
condition causes excessive heating in the output FETs. To protect against this, the DRV8307 device contains an
UVLO circuit.
In the event that the VM supply voltage drops below the UVLO threshold (VUVLO), the FAULTn terminal is driven
active and the motor driver is disabled. After VM returns to a voltage above the UVLO threshold, the FAULTn
terminal is high impedance and operation of the motor driver automatically resumes.
7.3.11.2 VM Overvoltage (VMOV)
In some cases, energy from the mechanical system can be forced back into the VM power supply. This can
result in the VM power supply being boosted by the energy in the mechanical system, causing breakdown of the
output FETs, or damaging the DRV8307 device. To protect against this, the DRV8307 device has overvoltage
protection.
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An overvoltage event is recognized if the VM voltage exceeds the overvoltage threshold (VMOVLO). Note that for
the output FETs to be protected, they must be rated for a voltage greater than the selected overvoltage
threshold.
In the event of an overvoltage, the FAULTn terminal is pulled low. The output stage is forced into asynchronous
rectification. After VM returns to a voltage below the overvoltage threshold, the FAULTn terminal is high
impedance. After a fixed 60-μs delay, synchronous rectification is re-enabled.
7.3.11.3 Motor Overcurrent Protection (OCP)
OCP is provided on each FET in addition to the current limit circuit. The OCP circuit is designed to protect the
output FETs from atypical conditions such as a short circuit between the motor outputs and each other, power, or
ground.
The OCP circuit is independent from the current limit circuitry. OCP works by monitoring the voltage drop across
the external FETs when they are enabled. If the voltage across a driven FET exceeds VFETOCP for more than
tFETOCP an OCP event is recognized.
In addition to monitoring the voltage across the FETs, an OCP event is triggered if the voltage applied to the
ISEN terminal exceeds the VSENSEOCP threshold voltage.
In the event of an OCP event, FAULTn is pulled low and the motor driver is disabled.
After a fixed delay of 5 ms, the FAULTn terminal is driven inactive and the motor driver is re-enabled.
7.3.11.4 Charge Pump Failure (CPFAIL)
If the voltage generated by the high-side charge pump is too low, the high-side output FETs are not fully turned
on and excessive heating results. To protect against this, the DRV8307 device has a circuit that monitors the
charge pump voltage.
If the charge pump voltage drops below VCPFAIL, the FAULTn terminal is pulled low and the motor driver is
disabled. After the charge pump voltage returns to a voltage above the VCPFAIL threshold, the FAULTn terminal is
high impedance and operation of the motor driver automatically resumes.
7.3.11.5 Charge Pump Short (CPSC)
To protect against excessive power dissipation inside the DRV8307 device, a circuit monitors the charge pump
and disables it in the event of a short circuit on the PCB.
If a short circuit is detected on the charge pump, the FAULTn terminal is pulled low and the motor driver is
disabled. After a fixed period of 5 s, the FAULTn terminal is high impedance and operation of the motor driver
automatically resumes. If the short circuit condition is still present, the cycle repeats.
7.3.11.6 Rotor Lockup (RLOCK)
Circuitry in the DRV8307 device detects a locked or stalled rotor. This RLOCK can occur in the event of a
mechanical jam or excessive torque load that causes the motor to stop rotating while enabled. The rotor lock
condition is set if there are no transitions detected on the HALLOUT signal for 3 s. RLOCK can also occur if the
three Hall signals are an invalid state (all High or all Low), which can be caused by a bad wire connection. If the
BRAKE terminal goes high for longer than 3 s while the PWM clock is on DRV8307 will detect RLOCK.
If a locked rotor condition is recognized, the FAULTn terminal is pulled low and the motor driver is disabled. The
part re-enables itself after a fixed delay of 5 s.
7.3.11.7 Overtemperature (OTS)
To protect against any number of faults that could result in excessive power dissipation inside the device, the
DRV8307 device includes overtemperature protection.
Overtemperature protection activates if the temperature of the die exceeds the OTS threshold temperature
(TTSD). If this occurs, the FAULTn terminal is pulled low and the device is disabled. The part re-enables itself
after a fixed delay of 5 s.
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7.4 Device Functional Modes
7.4.1 Clock PWM Mode
In PWM input mode, the PWM input signal is timed using a 50-MHz clock to generate a 12-bit number that
corresponds to the duty cycle of the incoming PWM signal. The input PWM frequency should be between 16 and
50 kHz; higher PWM frequencies work, but resolution is degraded. Note that the gate driver’s output PWM
frequency is independent of the speed control PWM input frequency; the output PWM frequency is 25 kHz.
The outputs of the PWM generators are the signals U_PD, V_PD, and W_PD. These contain the duty cycle
information for each phase.
Figure 10 shows modulation and PWM generation.
PWM Generators
100 MHz
PWM
PWM Input
Timer
12-bit
PWM
U_PD
12-bit
PWM
V_PD
12-bit
PWM
W_PD
Figure 10. Modulation and PWM Generation
When the DRV8307 is driving a motor, the motor should not be stopped by setting the PWM input to 0% duty
cycle. Instead, ENABLEn should be brought high.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Hall Sensor Configurations and Connections
The Hall sensor inputs on the DRV8307 device are capable of interfacing with a variety of Hall sensors.
Typically, a Hall element is used, which outputs a differential signal on the order of 100 mV. To use this type of
sensor, the VREG regulator can be used to power the Hall sensor. Figure 11 shows the connections.
VREG
INP
OUTN
Hall
Sensor
OUTP
Hx+
+
+
Hall
Amp
Optional
INN
Hx±
±
Figure 11. Differential Hall Sensor Connections
Since the amplitude of the Hall sensor output signal is very low, often capacitors are placed across the Hall
inputs to help reject noise coupled from the motor PWM. Typically capacitors from 1 to 10 nF are used.
Some motors use digital Hall sensors with open-drain outputs. These sensors can also be used with the
DRV8307 device, with the addition of a few resistors (see Figure 12).
All Resistors 1 to 4.7 k
VREG
VCC
Hall
Sensor
Hx+
OUT
Hx±
GND
+
+
Hall
Amp
-±
To Other
Hx± Inputs
Figure 12. Single-Ended Hall Sensor Connections
The negative (Hx–) inputs are biased to 2.5 V by a pair of resistors between VREG and ground. For opencollector Hall sensors, an additional pullup resistor to VREG is needed on the positive (Hx+) input.
20
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Application Information (continued)
8.1.2 ENABLEn Considerations
Because the ENABLEn function doubles as a sleep (low-power shutdown) function, there are some important
considerations when asserting and deasserting ENABLEn.
While the motor driver is enabled, the deassertion of ENABLEn initiates a stop-and-power-down sequence. This
sequence starts by disabling the motor (coasting) and waiting for rotation to stop. After rotation is stopped for 1 s
(as determined by the absence of transitions on HALLOUT), the internal circuitry is powered-down, the V5
regulator and power switch are disabled, and internal clocks are stopped.
After this stop-and-power-down sequence has been initiated (by deasserting the ENABLEn terminal for at least
1.2 μs), the sequence continues to completion, regardless of the state of ENABLEn.
8.1.3 Faster Starting and Stopping
When the DRV8307 is spinning a motor and ENABLEn is brought high while BRAKE is left low, the external
MOSFETs is disabled and the motor coasts to a stop. The motor cannot be re-driven until it first completely
stops.
For more dynamic performance, the ENABLEn and BRAKE inputs can be tied together. Then when the motor is
disabled (by bringing ENABLEn high), BRAKE is also high, causing the low-side of each half-H bridge to be on.
This causes the motor to stop faster, and allows it to be re-driven sooner.
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8.2 Typical Application
VM
VM
BLDC
VM
H1
ISEN
UHSG
U
ULSG
VHSG
V
VLSG
WHSG
180Ÿ
W
WLSG
0.03Ÿ
UH+
CP1
UH-
CP2
VH+
VCP
0.1µF
0.1µF
H2
VM
1µF
0.1µF
VH-
VM
+
470µF
0.1µF
WH+
WH-
VREG
RSVD
RSVD
RSVD
ENABLEn
24V
0.1µF
BRAKE
PWM
DIR
LOCKn
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
±
1µF
VINT
VSW
FAULTn
1.3NŸ
GND
DRV8307
0.1µF
HALLOUT
H3
+
PPAD
Controller
PU
PU
PU
Figure 13. Schematic
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Typical Application (continued)
8.2.1 Design Requirements
Design Parameter
Value
Supply voltage
8.5 to 32 V
PWM frequency
16 to 50 kHz
PWM duty cycle
0% to 100%
Current limiter
VLIMITER / RISENSE
External FETs
N-channel MOSFETs
Bulk supply capacitance
2 to 4 µF per watt
8.2.2 Detailed Design Procedure
When designing a system with the DRV8307, determine an operating motor voltage between 8.5 to 32 V. Higher
voltages directly scale motor speed, with the same PWM input.
The frequency of the input clock (PWM) must be between 16 and 50 kHz. Note that this frequency does not
affect the pre-driver output frequency, which is fixed at 25 kHz (typical).
The PWM duty cycle controls motor speed and can be set either to a fixed value or varied while the motor is
spinning. If it is changed while spinning, use gradual steps (for example, 1% increments), because a large
change in the commanded duty cycle can cause a large step in commutation, which can lock up the motor. This
behavior is typical with other industry devices.
The DRV8307 device constantly monitors motor current and reduces FET drive when necessary, to keep current
within VLIMITER / RISENSE. This feature reduces the requirements of power supply current capacity and bulk
capacitance to maintain a stable voltage, especially during motor startup. The designer should target a peak
current limit and size RISENSE appropriately. VLIMITER is fixed at 0.25 V (typical).
RISENSE = 0.25 V / IPEAK
(1)
For example, if 4-A peak is desired, then a 0.06-Ω resistor should be chosen as in Equation 2.
0.06 Ω = 0.25 V / 4 A
(2)
When selecting the power FETs, use six N-channel MOSFETs. They must support VGS > 10 V (since the
DRV8307 device drives 10 V VGS). They must also support VDS > VM, and TI recommends to have 1.5× to 2×
margin, to prevent FET damage during transient voltage spikes that can occur when motors change speeds.
It is important to use large bulk capacitance on VM, and the required size depends on the power of the motor. Of
course, power = voltage × current. A general recommendation is to use 2 to 4 µF per watt. If a motor system
uses 24 V and 3 A, a reasonable choice is 144 to 288 µF.
8.2.3 Application Performance Plot
LOCKn
ENABLE
RPM
Figure 14. Typical Spinup Profile
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9 Power Supply Recommendations
The DRV8307 device is designed to operate from an input voltage supply range between 8.5 and 32 V. This
supply should be well regulated. TI recommends using a minimum bulk capacitance of 47 μF to minimize
transients on the supply.
10 Layout
10.1 Layout Guidelines
For VM, place 0.1-μF bypass capacitor close to the device. Take care to minimize the loop formed by the bypass
capacitor connection from VM to GND.
+
10.2 Layout Example
ISEN
UH SG
U
ULSG
V
VHSG
VLSG
W
UH+
CP1
UH-
CP2
VH+
VCP
VH-
VM
WH+
GND
WH-
VINT
VSW
VREG
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BR AKE
PWM
LOC Kn
FAULTn
RSVD
DIR
HA LLOUT
RSVD
RSVD
ENA BLEn
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
24
WHSG
WLSG
Power FETs
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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2-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV8307RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8307
DRV8307RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8307
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Feb-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DRV8307RHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
DRV8307RHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8307RHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
DRV8307RHAT
VQFN
RHA
40
250
210.0
185.0
35.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Copyright © 2019, Texas Instruments Incorporated
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