Texas Instruments | DRV8832-Q1 Low-Voltage Motor Driver IC (Rev. C) | Datasheet | Texas Instruments DRV8832-Q1 Low-Voltage Motor Driver IC (Rev. C) Datasheet

Texas Instruments DRV8832-Q1 Low-Voltage Motor Driver IC (Rev. C) Datasheet
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DRV8832-Q1
SLVSBW9C – APRIL 2013 – REVISED DECEMBER 2015
DRV8832-Q1 Low-Voltage Motor Driver IC
1 Features
3 Description
•
•
The DRV8832-Q1 device provides an integrated
motor driver solution for battery-powered toys,
printers, and other low-voltage or battery-powered
motion control applications. The device has one Hbridge driver, and can drive one DC motor or one
winding of a stepper motor, as well as other loads like
solenoids. The output driver block consists of Nchannel and P-channel power MOSFETs configured
as an H-bridge to drive the motor winding.
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
H-Bridge Voltage-Controlled Motor Driver
– Drives DC Motor, One Winding of a Stepper
Motor, or Other Actuators/Loads
– Efficient PWM Voltage Control for Constant
Motor Speed With Varying Supply Voltages
– Low MOSFET ON-Resistance:
HS + LS 450 mΩ
1-A Maximum DC/RMS or Peak Drive Current
2.75-V to 6.8-V Operating Supply Voltage Range
300-nA (Typical) Sleep Mode Current
Reference Voltage Output
Current Limit Circuit
Fault Output
Thermally Enhanced Surface Mount Packages
2 Applications
•
•
Battery-Powered:
– Printers
– Toys
– Robotics
– Cameras
– Phones
Small Actuators, Pumps, and so forth
Provided with sufficient PCB heatsinking, the
DRV8832-Q1 can supply up to 1-A of DC/RMS or
peak output current. It operates on power supply
voltages from 2.75 V to 6.8 V.
To maintain constant motor speed over varying
battery voltages while maintaining long battery life, a
PWM voltage regulation method is provided. An input
pin allows programming of the regulated voltage. A
built-in voltage reference output is also provided.
Internal protection functions are provided for over
current
protection,
short-circuit
protection,
undervoltage
lockout,
and
overtemperature
protection.
The DRV8832-Q1 also provides a current limit
function to regulate the motor current during
conditions like motor startup or stall, as well as a fault
output pin to signal a host processor of a fault
condition.
The DRV8832-Q1 is available in tiny 3-mm x 3-mm
10-pin MSOP package with PowerPAD™ (Ecofriendly: RoHS & no Sb/Br).
Device Information(1)
PART NUMBER
DRV8832-Q1
PACKAGE
BODY SIZE (NOM)
MSOP-PowerPAD (10) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2.75V to 6.8V
DRV8832-Q1
IN1
IN2
Controller
Controller
Brushed DC
Motor Driver
1.3A peak
BDC
Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8832-Q1
SLVSBW9C – APRIL 2013 – REVISED DECEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1
7.2
7.3
7.4
Overview ................................................................... 7
Functional Block Diagram ......................................... 7
Feature Description................................................... 8
Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9
Power Supply Recommendations...................... 16
9.1 Power Supervisor.................................................... 16
9.2 Bulk Capacitance .................................................... 16
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
10.3 Thermal Considerations ........................................ 17
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2014) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 4
Changes from Revision A (August 2013) to Revision B
Page
•
Changed Bridge Control section............................................................................................................................................. 8
•
Changed Current Limit section ............................................................................................................................................. 10
•
Changed Thermal Shutdown (TSD) section......................................................................................................................... 10
•
Added Power Supervisor section ......................................................................................................................................... 16
2
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5 Pin Configuration and Functions
DGQ Package
10-Pin MSOP
Top View
OUT2
ISENSE
OUT1
VCC
GND
1
10
2
9
GND
(PPAD)
3
4
5
8
7
6
IN2
IN1
VREF
VSET
FAULTn
Pin Functions
PIN
NAME
NO.
I/O (1)
EXTERNAL COMPONENTS
OR CONNECTIONS
DESCRIPTION
GND
5
—
Device ground
FAULTn
6
OD
Fault output
Open-drain output driven low if fault condition
present
IN1
9
I
Bridge A input 1
Logic high sets OUT1 high
IN2
10
I
Bridge A input 2
Logic high sets OUT2 high
ISENSE
2
IO
Current sense resistor
Connect current sense resistor to GND.
Resistor value sets current limit level.
OUT1
3
O
Bridge output 1
Connect to motor winding
OUT2
1
O
Bridge output 2
Connect to motor winding
VCC
4
—
Device and motor supply
Bypass to GND with a 0.1-μF (minimum)
ceramic capacitor.
VREF
8
O
Reference voltage output
Reference voltage output
VSET
7
I
Voltage set input
Input voltage sets output regulation voltage
(1)
Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
(1) (2)
MIN
MAX
UNIT
Power supply voltage
–0.3
7
V
Input pin voltage
–0.5
7
V
Internally limited
A
Peak motor drive output current (3)
Continuous motor drive output current (3)
–1
Continuous total power dissipation
1
A
See Themral Information
TJ
Operating virtual junction temperature
–40
150
°C
Tstg
Storage temperature
–60
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Motor power supply voltage
IOUT
(1)
Continuous or peak H-bridge output current
(1)
NOM
MAX
UNIT
2.75
6.8
V
0
1
A
Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV8832-Q1
THERMAL METRIC (1)
DGQ (MSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
69.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
63.5
°C/W
RθJB
Junction-to-board thermal resistance
51.6
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
23.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
9.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
VCC = 2.75 V to 6.8 V, TA = -40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
IVCC
VCC operating supply current
VCC = 5 V
1.4
2
mA
IVCCQ
VCC sleep mode supply current
VCC = 5 V, TA = 25°C
0.3
1
μA
VCC undervoltage lockout
voltage
VCC rising
2.575
2.75
VCC falling
2.47
VUVLO
V
LOGIC-LEVEL INPUTS
VIL
Input low voltage
0.25 x VCC
VIH
Input high voltage
VHYS
Input hysteresis
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
0.5 x VCC
V
V
0.08 × VCC
-10
10
μA
50
μA
LOGIC-LEVEL OUTPUTS (FAULTn)
VOL
Output low voltage
VCC = 5 V, IOL = 4 mA (1)
0.5
VCC = 5 V, IO = 0.8 A, TJ = 125°C
340
VCC = 5 V, IO = 0.8 A, TJ = 25°C
250
VCC = 5 V, IO = 0.8 A, TJ = 125°C
270
VCC = 5 V, IO = 0.8 A, TJ = 25°C
200
V
H-BRIDGE FETS
RDS(ON)
HS FET on resistance
RDS(ON)
LS FET on resistance
IOFF
Off-state leakage current
450
360
mΩ
mΩ
–20
20
μA
ns
MOTOR DRIVER
tR
Rise time
VCC = 3 V, load = 4 Ω
50
300
tF
Fall time
VCC = 3 V, load = 4 Ω
50
300
fSW
Internal PWM frequency
44.5
ns
kHz
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tOCP
OCP deglitch time
TTSD
Thermal shutdown temperature
1.3
3
2
Die temperature (1)
A
μs
150
160
180
°C
1.235
1.285
1.335
V
VOLTAGE CONTROL
VREF
Reference output voltage
ΔVLINE
Line regulation
VCC = 3.3 V to 6 V, VOUT = 3 V (1)
IOUT = 500 mA
ΔVLOAD
Load regulation
VCC = 5 V, VOUT = 3 V
IOUT = 200 mA to 800 mA (1)
±1%
±1%
CURRENT LIMIT
VILIM
Current limit sense voltage
tILIM
Current limit fault deglitch time
RISEN
Current limit set resistance
(external resistor value)
(1)
160
200
240
275
0
mV
ms
1
Ω
Not production tested.
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100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
0.2
100%
90%
80%
70%
EFFICENCY
EFFICIENCY
6.6 Typical Characteristics
60%
50%
40%
30%
0.4
0.6
0.8
LOAD - A
Linear Regulator
20%
DRV8832-Q1
10%
0%
0.5
1.5
2.5
3.5
4.5
5.5
VOUT - V
Figure 2. Efficiency vs Output Voltage (VIN = 5 V,
IOUT = 500 mA)
Figure 1. Efficiency vs Load Current (VIN = 5 V, VOUT = 3 V)
2000
5500
5000
–40°C
25°C
125°C
1800
–40°C
25°C
125°C
4500
4000
IVCCQ (nA)
I VCC (µA)
1600
1400
3500
3000
2500
2000
1200
1500
1000
1000
500
800
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
2.5
6.5
VVCC (V)
3.0
3.5
Figure 3. IVCC vs VVCC
1000
–40°C
25°C
125°C
900
5.0
5.5
6.0
6.5
C002
2.9 V
5V
6V
900
RDS(ON) HS + LS) (mΩ)
C003
RDS(ON) (HS + LS) (mΩ)
4.5
Figure 4. IVCCQ vs VVCC
1000
800
700
600
500
800
700
600
500
400
400
300
3.0
3.5
4.0
4.5
5.0
5.5
VVCC (V)
6.0
300
–40
25
Temperature (°C)
C003
Figure 5. RDS(on) HS + LS vs VVCC
6
4.0
VVCC (V)
C001
125
C004
Figure 6. RDS(on) HS + LS vs Temperature
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7 Detailed Description
7.1 Overview
The DRV8832-Q1 is an integrated motor driver solution used for brushed motor control. The device integrates
one H-bridge, current regulation circuitry, and a PWM voltage regulation method.
Using the PWM voltage regulation allows the motor to maintain the desired speed as VCC changes. Battery
operation is an example of using this feature. When the battery is new or fully charged VCC will be higher than
when the battery is old or partially discharged. The speed of the motor will vary based on the voltage of the
battery. By setting the desired voltage across the motor at a lower voltage, a fully charged battery will use less
power and spin the motor at the same speed as a battery that has been partially discharged.
7.2 Functional Block Diagram
Battery
VCC
VCC
VCC
OCP
Integ.
Comp
VREF
Ref
Gate
Drive
+
OUT1
VSET
DCM
VCC
Logic
IN1
OCP
IN2
Gate
Drive
OverTemp
FAULTn
OUT2
Osc
Current
Sense
ISENSE
GND
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7.3 Feature Description
7.3.1 PWM Motor Driver
The DRV8832-Q1 contains an H-bridge motor driver with PWM voltage-control circuitry with current limit circuitry.
See Figure 7 for a block diagram of the motor control circuitry.
VCC
VCC
OCP
IN1
OUT 1
IN2
Predrive
PWM
DCM
OUT2
VSET
+
COMP
-
OCP
/4
Integrator
DIFF
+
-
ITRIP
ISENSE
COMP
REF
Figure 7. Motor Control Circuitry
7.3.2 Bridge Control
The IN1 and IN2 control pins enable the H-bridge outputs. The following table shows the logic:
Table 1. H-Bridge Logic
IN1
IN2
OUT1
OUT2
Function
0
0
Z
Z
Sleep/coast
0
1
L
H
Reverse
1
0
H
L
Forward
1
1
H
H
Brake
When both bits are zero, the output drivers are disabled and the device is placed into a low-power sleep state.
The current limit fault condition (if present) is also cleared. Note that when transitioning from either brake or sleep
mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle slowly ramps up to
the commanded voltage. This can take up to 12 ms to go from sleep to 100% duty cycle. Because of this, highspeed PWM signals cannot be applied to the IN1 and IN2 pins. To control motor speed, use the VSET pin as
described in the following paragraph.
Because of the sleep mode functionality described previously, when applying an external PWM to the DRV8832Q1, hold one input logic high while applying a PWM signal to the other. If the logic input is held low instead, then
the device will cycle in and out of sleep mode, causing the FAULTn pin to pulse low on every sleep mode exit.
8
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7.3.3 Voltage Regulation
The DRV8832-Q1 provides the ability to regulate the voltage applied to the motor winding. This feature allows
constant motor speed to be maintained even when operating from a varying supply voltage such as a
discharging battery.
The DRV8832-Q1 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current
consumption and maximize battery life.
The circuit monitors the voltage difference between the output pins and integrates it, to get an average DC
voltage value. This voltage is divided by 4 and compared to the VSET pin voltage. If the averaged output voltage
(divided by 4) is lower than VSET, the duty cycle of the PWM output is increased; if the averaged output voltage
(divided by 4) is higher than VSET, the duty cycle is decreased.
During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on
time. This is shown in Figure 8 as case 1. The current flow direction shown indicates the state when IN1 is high
and IN2 is low.
Note that if the programmed output voltage is greater than the supply voltage, the device will operate at 100%
duty cycle and the voltage regulation feature will be disabled. In this mode the device behaves as a conventional
H-bridge driver.
During the PWM off time, winding current is re-circulated by enabling both of the high-side FETs in the bridge.
This is shown as case 2 in Figure 8.
VCC
2
1
OUT1
Shown with
OUT2
IN1=1, IN2=0
1 PWM on
2 PWM off
Figure 8. Voltage Regulation
7.3.4 Reference Output
The DRV8832-Q1 includes a reference voltage output that can be used to set the motor voltage. Typically for a
constant-speed application, VSET is driven from VREF through a resistor divider to provide a voltage equal to
1/4 the desired motor drive voltage.
For example, if VREF is connected directly to VSET, the voltage will be regulated at 5.14 V. If the desired motor
voltage is 3 V, VREF should be 0.75 V. This can be obtained with a voltage divider using 53 kΩ from VREF to
VSET, and 75 kΩ from VSET to GND.
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7.3.5 Current Limit
A current limit circuit is provided to protect the system in the event of an overcurrent condition, such as what
would be encountered if driving a DC motor at start-up or with an abnormal mechanical load (stall condition).
The motor current is sensed by monitoring the voltage across an external sense resistor. When the voltage
exceeds a reference voltage of 200 mV for more than approximately 3 µs, the PWM duty cycle is reduced to limit
the current through the motor to this value. This current limit allows for starting the motor while controlling the
current.
If the current limit condition persists for some time, it is likely that a fault condition has been encountered, such
as the motor being run into a stop or a stalled condition. An overcurrent event must persist for approximately
275 ms before the fault is registered. After approximately 275 ms, a fault signaled to the host by driving the
FAULTn signal low. Operation of the motor driver will continue.
The current limit fault condition is self-clearing and will be released when the abnormal load (stall condition) is
removed.
The resistor used to set the current limit must be less than 1 Ω. Its value may be calculated as follows:
200 mV
RISENSE = ¾
ILIMIT
where
•
•
RISENSE is the current sense resistor value
ILIMIT is the desired current limit (in mA)
(1)
If the current limit feature is not needed, the ISENSE pin may be directly connected to ground.
7.3.6 Protection Circuits
The DRV8832-Q1 is fully protected against undervoltage, overcurrent and overtemperature events.
7.3.6.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled, and the
FAULTn signal will be driven low. The device will remain disabled until VCC is removed and re-applied.
Overcurrent conditions are sensed independently on both high and low side devices. A short to ground, supply,
or across the motor winding will all result in an overcurrent shutdown. Note that OCP is independent of the
current limit function, which is typically set to engage at a lower current level; the OCP function is intended to
prevent damage to the device under abnormal (for example, short circuit) conditions.
7.3.6.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the FAULTn signal will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
7.3.6.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all circuitry in
the device will be disabled, the FAULTn signal will be driven low, and internal logic will be reset. Operation will
resume when VCC rises above the UVLO threshold.
Table 2. Device Protection
FAULT
CONDITION
ERROR REPORT
H-BRIDGE
INTERNAL CIRCUITS
RECOVERY
VCC undervoltage
(UVLO)
VCC < VUVLO
FAULTn
Disabled
Disabled
VCC > VUVLO
Overcurrent (OCP)
IOUT > IOCP
FAULT n
Disabled
Operating
Power cycle VCC
Thermal shutdown
(TSD)
TJ > TTSD
FAULTn
Disabled
Operating
TJ > TTSD – THYS
10
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7.4 Device Functional Modes
The DRV8832-Q1 is active when either IN1 or IN2 are set to a logic high. Sleep mode is entered when both IN1
and IN2 are set to a logic low. When in sleep mode, the H-bridge FETs are disabled (Hi-Z).
Table 3. Modes of Operation
FAULT
CONDITION
H-BRIDGE
INTERNAL CIRCUITS
Operating
IN1 or IN2 high
Operating
Operating
Sleep mode
IN1 or IN2 low
Disabled
Diabled
Fault encountered
Any fault condition met
Disabled
See Table 2
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8832-Q1 is used in brushed DC applications to provide a constant motor speed over varying voltages.
The following design procedure can be used to configure the DRV8832 for a system with a VCC variance of 4V
to 6V.
8.2 Typical Application
Figure 9 is a common application of the DRV8832-Q1.
VCC
VCC
OUT1
10 µF
BDC
IN1
IN2
Controller
OUT2
VREF
2.87k
ISENSE
VSET
0.4
10k
FAULTn
GND
PPAD
Figure 9. Motor Control Circuitry
12
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Typical Application (continued)
8.2.1 Design Requirements
Table 4 lists the design parameters of the DRV8832-Q1.
Table 4. Design Parameters
DESIGN
PARAMETER
REFERENCE
EXAMPLE VALUE
Motor voltage
VCC
5V
Motor RMS current
IRMS
0.3 A
Motor start-up
ISTART
1.3 A
Motor current trip
point
ILIMIT
0.9 A
8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The motor voltage to use will depend on the ratings of the motor selected and the desired RPM. A higher voltage
spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage
also increases the rate of current change through the inductive motor windings.
For the DRV8832-Q1, TI recommends to set a motor voltage at the lowest system VCC. This will maintain a
constant RPM across varying VCC conditions.
For example if the VCC voltage can vary from 4.5V to 5.5V, setting the VSET voltage to 1.125 V will compensate
for power supply variation. The DRV8832-Q1 will set the motor voltage at 4.5 V, even if VCC is 5.5 V.
8.2.2.2 Motor Current Trip Point
When the voltage on pin ISENSE exceeds VILIM (0.2 V), overcurrent is detected. The RSENSE resistor should
be sized to set the desired ILIMIT level.
RISENSE = 0.2 V / ILIMIT
(2)
To set IILIMIT to 0.5 A, RISENSE = 0.2 V / 0.9 A = 0.22 Ω.
To prevent false trips, ILIMIT must be higher than regular operating current. Motor current during start-up is
typically much higher than steady-state spinning, because the initial load torque is higher, and the absence of
back-EMF causes a higher voltage and extra current across the motor windings.
It can be beneficial to limit start-up current by using series inductors on the DRV8832-Q1 output, as that allows
ILIMIT to be lower, and it may decrease the system’s required bulk capacitance. Start-up current can also be
limited by ramping the forward drive duty cycle.
8.2.2.3 Sense Resistor Selection
For optimal performance, it is important for the sense resistor to be:
• Surface-mount
• Low inductance
• Rated for high enough power
• Placed closely to the motor driver
The power dissipated by the sense resistor equals IRMS² x R. For example, if peak motor current is 1 A, RMS
motor current is 0.7 A, and a 0.4-Ω sense resistor is used, the resistor will dissipate 0.7 A² x 0.4 Ω = 0.2 W. The
power quickly increases with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a de-rated power
curve for high ambient temperatures. When a PCB is shared with other components generating heat, margin
should be added. It is always best to measure the actual sense resistor temperature in a final system, along with
the power MOSFETs, as those are often the hottest components.
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Because power resistors are larger and more expensive than standard resistors, it is common practice to use
multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat
dissipation.
8.2.2.4 Low Power Operation
Under normal operation, using sleep mode to minimize supply current should be sufficient.
If desired, power can be removed to the DRV8832-Q1 to further decrease supply current. TI recommends to
remove power to the FAULTn pullup resistor when removing power to the DRV8832-Q1. Removing power from
the FAULTn pullup resistor will eliminate a current path from the FAULTn pin through an ESD protection diode to
VCC. TI recommends to set both IN1 and IN2 as a logic low when power is removed.
8.2.3 Application Curves
The following scope captures show how the output duty cycle changes to as VCC increases. This allows the
motor to spin at a constant speed as VCC changes. At VCC = 3.9 V, the output duty cycle is 100% on. As the
VCC voltage increases to greater than 4 V, the output duty cycle begins to decrease. The output duty cycle is
shown at VCC = 4.5 V, VCC = 5 V and VCC = 5.5 V.
• Channel 1 – OUT1: IN1 – Logic Low
• Channel 2 – OUT2: IN2 – Logic High
• Channel 4 – Motor current: VSET – 1 V
• Motor used: NMB Technologies Corporation, PPN7PA12C1
14
Figure 10. Output Pulse Width Modulating at VCC = 3.9 V
Figure 11. Output Pulse Width Modulating at VCC = 4 V
Figure 12. Output Pulse Width Modulating at VCC = 4.5 V
Figure 13. Output Pulse Width Modulating at VCC = 5 V
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Figure 14. Output Pulse Width Modulating at VCC = 5.5 V
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9 Power Supply Recommendations
9.1 Power Supervisor
The DRV8832-Q1 is capable of entering a low-power sleep mode by bringing both of the INx control inputs logic
low. The outputs will be disabled Hi-Z.
To exit the sleep mode, bring either or both of the INx inputs logic high. This will enable the H-bridges. When
exiting the sleep mode, the FAULTn pin will pulse low.
9.2 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system.
• The power supply’s capacitance and ability to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (Brushed DC, Brushless DC, Stepper).
• The motor braking method.
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VCC
++
±±
+
Motor Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 15. Example Setup of Motor Drive System with External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
16
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10 Layout
10.1 Layout Guidelines
The VCC pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value
of 0.1-μF rated for VCC. This capacitor should be placed as close to the VCC pin as possible with a thick trace or
ground plane connection to the device GND pin.
The VCC pin must be bypassed to ground using an appropriate bulk capacitor. This component may be an
electrolytic and should be placed close to the DRV8832-Q1.
10.2 Layout Example
10 µF
OUT2
IN2
ISENSE
IN1
OUT1
VREF
VCC
VSET
GND
FAULTn
Figure 16. Layout Recommendations
10.3 Thermal Considerations
The DRV8832-Q1 has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die temperature
exceeds approximately 160°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
10.3.1 Power Dissipation
Power dissipation in the DRV8832-Q1 is dominated by the power dissipated in the output FET resistance, or
RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 3.
PTOT = 2 · RDS(ON) · (IOUT(RMS))
2
(3)
where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output
current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current
setting. The factor of 2 comes from the fact that at any instant two FETs are conducting winding current for each
winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
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Thermal Considerations (continued)
10.3.2 Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, see TI application report, PowerPAD™ Thermally Enhanced Package
(SLMA002), and TI application brief, PowerPAD™ Made Easy (SLMA004), available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
18
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package Application Report, SLMA002
• PowerPAD™ Made Easy, SLMA004
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV8832QDGQQ1
ACTIVE
HVSSOP
DGQ
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
8832Q
DRV8832QDGQRQ1
ACTIVE
HVSSOP
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
8832Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
OTHER QUALIFIED VERSIONS OF DRV8832-Q1 :
• Catalog: DRV8832
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8832QDGQRQ1
Package Package Pins
Type Drawing
SPQ
HVSSOP
2500
DGQ
10
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8832QDGQRQ1
HVSSOP
DGQ
10
2500
367.0
367.0
35.0
Pack Materials-Page 2
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