Texas Instruments | DRV8804 Quad Serial Interface Low-Side Driver IC (Rev. F) | Datasheet | Texas Instruments DRV8804 Quad Serial Interface Low-Side Driver IC (Rev. F) Datasheet

Texas Instruments DRV8804 Quad Serial Interface Low-Side Driver IC (Rev. F) Datasheet
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DRV8804
SLVSAW4F – JULY 2011 – REVISED DECEMBER 2015
DRV8804 Quad Serial Interface Low-Side Driver IC
1 Features
3 Description
•
The DRV8804 provides a 4-channel low-side driver
with overcurrent protection. It has built-in diodes to
clamp turnoff transients generated by inductive loads
and can be used to drive unipolar stepper motors, DC
motors, relays, solenoids, or other loads.
1
•
•
•
•
4-Channel Protected Low-Side Driver
– Four N-Channel MOSFETs With Overcurrent
Protection
– Integrated Inductive Clamp Diodes
– Serial Interface
DW Package: 1.5-A (Single Channel On) /
800-mA (Four Channels On) Maximum Drive
Current per Channel (at 25°C)
PWP Package: 2-A (Single Channel On) /
1-A (Four Channels On) Maximum Drive Current
per Channel (at 25°C, With Proper PCB
Heatsinking)
8.2-V to 60-V Operating Supply Voltage Range
Thermally-Enhanced Surface Mount Package
2 Applications
•
•
•
•
Relay Drivers
Unipolar Stepper Motor Drivers
Solenoid Drivers
General Low-Side Switch Applications
In the SOIC (DW) package, the DRV8804 can supply
up to 1.5-A (one channel on) or 800-mA (all channels
on) continuous output current per channel, at 25°C. In
the HTSSOP (PWP) package, it can supply up to 2-A
(one channel on) or 1-A (four channels on)
continuous output current per channel, at 25°C with
proper PCB heatsinking.
A serial interface is provided including a serial data
output, which can be daisy-chained to control multiple
devices with one serial interface.
Internal shutdown functions are provided for
overcurrent protection, short-circuit protection,
undervoltage lockout, and overtemperature, and
faults are indicated by a fault output pin.
The DRV8804 is available in a 20-pin, thermallyenhanced SOIC package and a 16-pin HTSSOP
package (Eco-friendly: RoHS & no Sb/Br).
Device Information(1)
PART NUMBER
DRV8804
PACKAGE
BODY SIZE (NOM)
SOIC (20)
12.80 mm × 7.50 mm
HTSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
8.2 V to 60 V
4
DRV8804
RESET
Quad Low-side
Driver
1A
+
Serial
Interface
1A
nFAULT
1A
±
Controller
M
+
±
Fault Protection
Clamp
Diodes
1A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8804
SLVSAW4F – JULY 2011 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
9
Power Supply Recommendations...................... 13
9.1 Bulk Capacitance .................................................... 13
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
10.3 Thermal Considerations ........................................ 14
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2014) to Revision F
Page
•
Changed Catch Diodes to Clamp Diodes in Features .......................................................................................................... 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
2
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5 Pin Configuration and Functions
DW (Wide SOIC) Package
20-Pin Package
Top View
VM
VCLAMP
OUT1
OUT2
GND
GND
GND
OUT3
OUT4
nENBL
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
PWP (HTSSOP)
16-Pin Package
Top View
nFAULT
SDATOUT
SDATIN
SCLK
GND
GND
GND
LATCH
NC
RESET
VM
VCLAMP
OUT1
OUT2
GND
OUT3
OUT4
nENBL
1
16
2
15
3
14
13
4
5
GND
6
7
12
11
10
9
8
nFAULT
SDATOUT
SDATIN
SCLK
GND
LATCH
NC
RESET
Pin Functions
PIN
NAME
SOIC
HTSSOP
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS
OR CONNECTIONS
POWER AND GROUND
5, 6, 7,
14, 15, 16
5, 12,
PPAD
—
Device ground
All pins must be connected to GND.
1
1
—
Device power supply
Connect to motor supply (8.2 V - 60 V).
LATCH
13
11
I
Latch input
Rising edge latches shift register to output
stage – internal pulldown
nENBL
10
8
I
Enable input
Active low enables outputs – internal pulldown
RESET
11
9
I
Reset input
Active-high reset input initializes internal
logic – internal pulldown
SCLK
17
13
I
Serial clock
Serial clock input – internal pulldown
SDATIN
18
14
I
Serial data input
Serial data input – internal pulldown
SDATOUT
19
15
O
Serial data output
Serial data output; push-pull structure; see
serial interface section for details
20
16
OD
Fault
Logic low when in fault condition
(overtemperature, overcurrent)
OUT1
3
3
O
Output 1
Connect to load 1
OUT2
4
4
O
Output 2
Connect to load 2
OUT3
8
6
O
Output 3
Connect to load 3
OUT4
9
7
O
Output 4
Connect to load 4
VCLAMP
2
2
—
Output clamp voltage
Connect to VM supply, or zener diode to VM
supply
GND
VM
CONTROL
STATUS
nFAULT
OUTPUT
(1)
Directions: I = input, O = output, OD = open-drain output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VM
Power supply voltage
–0.3
65
V
VOUTx
Output voltage
–0.3
65
V
VCLAMP
Clamp voltage
–0.3
65
V
SDATOUT,
nFAULT
Output current
20
mA
Peak clamp diode current
2
A
DC or RMS clamp diode current
1
A
SDATOUT,
nFAULT
Digital input pin voltage
–0.5
7
V
Digital output pin voltage
–0.5
7
V
Peak motor drive output current, t < 1 μs
Internally limited
Continuous total power dissipation
A
See Thermal Information
TJ
Operating virtual junction temperature
–40
150
°C
Tstg
Storage temperature
–60
150
°C
(1)
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VM
Power supply voltage
VCLAMP
Output clamp voltage (1)
Continuous output current, single channel on, TA = 25°C, SOIC package
MAX
UNIT
60
V
0
60
V
(2)
1.5
Continuous output current, four channels on, TA = 25°C, SOIC package (2)
IOUT
(1)
(2)
NOM
8.2
0.8
Continuous output current, single channel on, TA = 25°C, HTSSOP package (2)
2
Continuous output current, four channels on, TA = 25°C, HTSSOP package (2)
1
A
VCLAMP is used only to supply the clamp diodes. It is not a power supply input.
Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV8804
THERMAL METRIC (1)
DW (SOIC)
PWP (HTSSOP)
UNIT
20 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
67.7
39.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.9
24.6
°C/W
RθJB
Junction-to-board thermal resistance
35.4
20.3
°C/W
ψJT
Junction-to-top characterization parameter
8.2
0.7
°C/W
ψJB
Junction-to-board characterization parameter
34.9
20.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Thermal Information (continued)
DRV8804
THERMAL METRIC (1)
RθJC(bot)
DW (SOIC)
PWP (HTSSOP)
20 PINS
16 PINS
N/A
2.3
Junction-to-case (bottom) thermal resistance
UNIT
°C/W
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.6
2.1
mA
8.2
V
0.7
V
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V
VUVLO
VM undervoltage lockout voltage
VM rising
LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS)
VIL
Input low voltage
VIH
Input high voltage
0.6
VHYS
Input hysteresis
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Pulldown resistance
2
V
0.45
–20
V
20
μA
100
μA
100
kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
0.5
V
1
μA
IO = 5 mA
0.5
V
IO = 100 µA, VM = 11 V - 60 V, peak
6.5
SDATOUT OUTPUT (PUSH-PULL OUTPUT)
VOL
Output low voltage
VOH
Output high voltage
IO = 100 µA, VM = 11 V - 60 V, steady state
3.3
IO = 100 µA, VM = 8.2 V - 11 V, steady state
2.5
4.5
5.6
V
ISRC
Output source current
VM = 24 V
1
mA
ISNK
Output sink current
VM = 24 V
5
mA
LOW-SIDE FETS
RDS(ON)
FET on resistance
IOFF
Off-state leakage current
VM = 24 V, IO = 700 mA, TJ = 25°C
0.5
VM = 24 V, IO = 700 mA, TJ = 85°C
0.75
0.8
Ω
50
μA
–50
50
μA
–50
HIGH-SIDE DIODES
VF
Diode forward voltage
VM = 24 V, IO = 700 mA, TJ = 25°C
IOFF
Off-state leakage current
VM = 24 V, TJ = 25°C
1.2
V
tR
Rise time
VM = 24 V, IO = 700 mA, Resistive load
50
300
ns
tF
Fall time
VM = 24 V, IO = 700 mA, Resistive load
50
300
ns
OUTPUTS
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tOCP
Overcurrent protection deglitch time
tRETRY
Overcurrent protection retry time
tTSD
(1)
Thermal shutdown temperature
2.3
Die temperature
(1)
150
3.8
A
3.5
µs
1.2
ms
160
180
°C
Not production tested.
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6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted) (1)
MIN
NOM MAX
UNIT
1
tCYC
Clock cycle time
62
ns
2
tCLKH
Clock high time
25
ns
3
tCLKL
Clock low time
25
ns
4
tSU(SDATIN)
Setup time, SDATIN to SCLK
5
ns
5
tH(SDATIN)
Hold time, SDATIN to SCLK
1
ns
6
tD(SDATOUT)
Delay time, SCLK to SDATOUT, no external pullup resistor,
COUT = 100 pF
7
tW(LATCH)
Pulse width, LATCH
8
tOE(ENABLE)
Enable time, nENBL to output low
9
tD(LATCH)
Delay time, LATCH to output change
—
tRESET
RESET pulse width
20
µs
10
tD(RESET)
Reset delay before clock
20
µs
11
tSTARTUP
Start-up delay VM applied before clock
55
µs
(1)
50
100
200
ns
ns
60
ns
200
ns
Not production tested.
10
RESET
nENBL
VM
7
11
1
LATCH
SCLK
2
3
Data in
valid
SDATIN
OUTx
8
4
SDATOUT
9
5
Data out valid
6
More than 400 ns of delay should exist between the final SCLK rising edge and the LATCH rising edge. This ensures
that the last data bit is shifted into the device properly.
Figure 1. DRV8804 Timing Requirements
6
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1.80
1.80
1.75
1.75
1.70
1.70
Supply Current (mA)
Supply Current (mA)
6.7 Typical Characteristics
1.65
1.60
1.55
1.50
1.45
1.40
-40° C
1.35
1.60
1.55
1.50
1.45
1.40
25° C
75° C
1.30
1.65
1.35
125° C
8V
24 V
30 V
60 V
1.30
8V
24 V
30 V
60 V
Supply Voltage (V)
-40° C
Figure 2. Supply Current over VM
1000
900
25° C
75° C
125° C
Temperature (ƒC)
C002
C001
Figure 3. Supply Current Over Temperature
-40° C
25° C
75° C
125° C
900
800
Rdson (mŸ)
Rdson (mŸ)
800
700
600
500
700
600
500
400
400
300
8V
60 V
300
200
8V
60 V
Supply Voltage (V)
-40° C
C006
Figure 4. RDS(on) Over VM
25° C
75° C
125° C
Temperature (ƒC)
C005
Figure 5. RDS(on) Over Temperature
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7 Detailed Description
7.1 Overview
The DRV8804 is an integrated 4-channel low side driver solution for a low side switch application. A serial
interface controls the low-side driver outputs and allows for multiple drivers to be chained together and save
space on communication lines. The four low-side driver outputs consist of four N-channel MOSFETs that have a
typical RDS(on) of 500 mΩ. A single motor supply input VM serves as device power and is internally regulated to
power the low side gate drive. The device outputs can be disabled by bringing nENBL pin logic high. This device
has several safety features including integrated overcurrent protection that limits the motor current to a fixed
maximum above which the device will shut down. Thermal shutdown protection enables the device to
automatically shut down if the die temperature exceeds a TTSD limit and will restart once the die reaches a safe
temperature. UVLO protection will disable all circuitry in the device if VM drops below the undervoltage lockout
threshold.
7.2 Functional Block Diagram
8.2V – 60V
Internal
Reference
Regs
UVLO
VM
nENBL
LS Gate
Drive
OCP
&
Gate
Drive
LATCH
8.2V – 60V
Optional
Zener
Int. VCC
VCLAMP
OUT1
Inductive
Load
SDATIN
SDATOUT
Control
Logic
SCLK
RESET
nFAULT
Thermal
Shut down
OCP
&
Gate
Drive
OUT2
Inductive
Load
OCP
&
Gate
Drive
OUT3
OCP
&
Gate
Drive
OUT4
Inductive
Load
Inductive
Load
GND
(multiple pins)
8
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7.3 Feature Description
7.3.1 Output Drivers
The DRV8804 contains four protected low-side drivers. Each output has an integrated clamp diode connected to
a common pin, VCLAMP.
VCLAMP can be connected to the main power supply voltage, VM. It can also be connected to a Zener or TVS
diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be beneficial
when driving loads that require very fast current decay, such as unipolar stepper motors.
In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification.
7.3.2 Serial Interface Operation
The DRV8804 is controlled with a simple serial interface. Logically, the interface is shown in Figure 6.
nENBL
LATCH
RESET
SCLK
SDATIN
D
D
Q
OUT1
Q
CLR
CLR
D
D
Q
OUT2
Q
CLR
CLR
D
Q
D
OUT3
Q
CLR
CLR
D
Q
D
OUT4
Q
CLR
CLR
D
Q
CLR
SDATOUT
Figure 6. Serial Interface Operation
Data is shifted into a temporary holding shift register in the part using the SDATIN pin, one bit at each rising
edge of the SCLK pin. Data is simultaneously shifted out of the SDATOUT pin, allowing multiple devices to be
daisy-chained onto one serial port. Note that the SDATOUT pin has a push-pull driver, which can support driving
another DRV8804 SDATIN pin at clock frequencies of up to 1 MHz without an external pullup. A pullup resistor
can be used between SDATOUT and an external 5-V logic supply to support higher clock frequencies. TI
recommends a resistor value greater than 1 kΩ. The SDATOUT pin is capable of approximately 1-mA source
and 5-mA sink. To supply logic signals to a lower-voltage microcontroller, use a resistor divider from SDATOUT
to GND.
A rising edge on the LATCH pin latches the data from the temporary shift register into the output stage.
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Feature Description (continued)
7.3.3 nENBL and RESET Operation
The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does
not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown.
The RESET pin, when driven active high, resets internal logic, including the OCP fault. All serial interface
registers are cleared. Note that RESET has an internal pulldown. An internal power-up reset is also provided, so
driving RESET at power up is not required.
7.3.4 Protection Circuits
The DRV8804 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.4.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the tOCP deglitch time (approximately 3.5 µs), the driver will be
disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time
(approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either
RESET pin is activated or VM is removed and re-applied.
7.3.4.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.
Once the die temperature has fallen to a safe level, operation will automatically resume.
7.3.4.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout (UVLO) threshold voltage, all
circuitry in the device will be disabled, and internal logic will be reset. Operation will resume when VM rises above
the UVLO threshold.
7.4 Device Functional Modes
When the nENBL pin of the DRV8804 is pulled logic low, the open-drain FET outputs are enabled. Having the
device be enabled at logic low allows for the use of long data lines in a high noise environment that do not
unintentionally enable the device with coupled noise. The device will still shift data through the SDATIN /
SDATOUT lines and SCLK line regardless of the state of the nENBL pin.
Once data has been moved into each of the four shift register lines the LATCH pin can be pulled high to output
the state of the four shift registers. Once LATCH is pulled high the state of the four shift registers is placed in a
logical AND with the inverse state of the nENBL pin. If the nENBL pin is logic low input and the LATCH pin is
logic high the open-drain output of that driver channel will be turned on.
If the device detects that VM has dropped below the UVLO threshold, it will immediately enter a state where all
the internal logic is disabled. The device stays in a disabled state until VM rises above the UVLO threshold and
all internal logic is then reset. During an Overcurrent Protection (OCP) event the device removes gate drive for
one tRETRY interval and the nFAULT pin is driven low. The fault is cleared immediately if RESET is activated or
VM is removed and re-applied.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8804 can be used to drive one unipolar stepper motor.
8.2 Typical Application
VM
+
0.1 µF
100 µF
1
2
±
4
+
M
3
5
+
±
6
7
8
9
10
nFAULT
VM
SDATOUT
VCLAMP
OUT1
SDATIN
OUT2
SCLK
GND
GND
DRV8804
GND
GND
GND
GND
OUT3
LATCH
OUT4
NC
nENBL
RESET
20
19
18
17
16
15
14
13
12
11
Figure 7. Typical Application Schematic
8.2.1 Design Requirements
Table 1 lists the design parameters for this design example.
Table 1. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Supply Voltage
VM
24 V
Motor Winding Resistance
RL
7.4 Ω/phase
Motor Full Step Angle
θstep
1.8°/step
Motor Rated Current
IRATED
0.75 A
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8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The motor voltage to use will depend on the ratings of the motor selected and the desired torque. A higher
voltage shortens the current rise time in the coils of the stepper motor allowing the motor to produce a greater
average torque. Using a higher voltage also allows the motor to operate at a faster speed than a lower voltage.
8.2.2.2 Drive Current
The current path starts from the supply VM, moves through the inductive winding load and low-side sinking
NMOS power FET. Power dissipation losses in one sink NMOS power FET are shown in Equation 1.
P = I2 × RDS (on)
(1)
The DRV8804 has been measured to be capable of 1.5-A Single Channel or 800-mA Four Channels with the
DW package and 2-A Single Channel or 1-A Four Channels with the PWP package at 25°C on standard FR-4
PCBs. The maximum RMS current will vary based on PCB design and the ambient temperature..
8.2.3 Application Curves
12
Figure 8. Current Ramp With a 16-Ω, 1-mH, RL Load and
VM = 8.2 V
Figure 9. Current Ramp With a 16-Ω, 1-mH RL Load and VM
= 30 V
Figure 10. OCP With VM = 8.2 V and OUT1 Shorted to VM
Figure 11. OCP Separated by tRETRY With VM = 8.2 V and
OUT1 Shorted to VM
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Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: DRV8804
DRV8804
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SLVSAW4F – JULY 2011 – REVISED DECEMBER 2015
9 Power Supply Recommendations
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system.
• The power supply’s capacitance and ability to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (Brushed DC, Brushless DC, Stepper).
• The type of motor used (Brushed DC, Brushless DC, Stepper).
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Power Supply
Motor Drive System
VM
+
+
Motor
Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 12. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
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13
DRV8804
SLVSAW4F – JULY 2011 – REVISED DECEMBER 2015
www.ti.com
10 Layout
10.1 Layout Guidelines
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
• Small-value capacitors should be ceramic, and placed closely to device pins.
• The high-current device outputs should use wide metal traces.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
I2 × RDS(on) heat that is generated in the device.
10.2 Layout Example
+
VM
nFAULT
VCLAMP
SDATOUT
OUT1
SDATIN
OUT2
SCLK
GND
GND
OUT3
LATCH
OUT4
NC
nENBL
RESET
Figure 13. Layout Recommendation
10.3 Thermal Considerations
The DRV8804 has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die temperature
exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
10.3.1 Power Dissipation
Power dissipation in the DRV8804 is dominated by the power dissipated in the output FET resistance, or RDS(ON).
Average power dissipation of each FET when running a static load can be roughly estimated by Equation 2.
P = RDS(ON) · (IOUT)2
where
•
•
•
14
P is the power dissipation of one FET
RDS(ON) is the resistance of each FET
IOUT is equal to the average current drawn by the load
Submit Documentation Feedback
(2)
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: DRV8804
DRV8804
www.ti.com
SLVSAW4F – JULY 2011 – REVISED DECEMBER 2015
Thermal Considerations (continued)
Note that at start-up and fault conditions this current is much higher than normal running current; these peak
currents and their duration also must be taken into consideration. When driving more than one load
simultaneously, the power in all active output stages must be summed.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
10.3.2 Heatsinking
The DRV8804DW package uses a standard SOIC outline, but has the center pins internally fused to the die pad
to more efficiently remove heat from the device. The two center leads on each side of the package should be
connected together to as large a copper area on the PCB as is possible to remove heat from the device. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
In general, the more copper area that can be provided, the more power can be dissipated.
The DRV8804PWP package uses an HTSSOP package with an exposed PowerPAD™. The PowerPAD package
uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally
connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be
accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without
internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on
the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom
layers.
For details about how to design the PCB, see TI Application Report, PowerPAD Thermally Enhanced Package
(SLMA002), and TI Application Brief, PowerPAD Made Easy (SLMA004), available at www.ti.com.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: DRV8804
15
DRV8804
SLVSAW4F – JULY 2011 – REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally Enhanced Package, SLMA002
• PowerPAD Made Easy, SLMA004
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: DRV8804
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV8804DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8804DW
DRV8804DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8804DW
DRV8804PWP
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8804
DRV8804PWPR
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8804
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DRV8804DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
DRV8804PWPR
HTSSOP
PWP
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8804DWR
SOIC
DW
20
2000
367.0
367.0
45.0
DRV8804PWPR
HTSSOP
PWP
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016J
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
A
SEATING
PLANE
0.1 C
PIN 1 INDEX
AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
4.5
4.3
16X
(0.15) TYP
SEE DETAIL A
9
8
0.25
GAGE PLANE
3.55
2.68
0 -8
16
1
2.46
1.75
1.2 MAX
0.15
0.05
0.75
0.50
DETAIL A
A 20
TYPICAL
THERMAL
PAD
4223595/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016J
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 8
METAL COVERED
BY SOLDER MASK
(2.46)
16X (1.5)
16X (0.45)
SEE DETAILS
SYMM
1
16
(1.3) TYP
(R0.05) TYP
(0.65)
SYMM
(3.55)
(5)
NOTE 8
14X (0.65)
( 0.2) TYP
VIA
8
9
(1.35) TYP
SOLDER MASK
DEFINED PAD
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4223595/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016J
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.46)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
16X (0.45)
METAL COVERED
BY SOLDER MASK
1
16
(R0.05) TYP
(3.55)
BASED ON
0.125 THICK
STENCIL
SYMM
14X (0.65)
9
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.75 X 3.97
2.46 X 3.55 (SHOWN)
2.25 X 3.24
2.08 X 3.00
4223595/A 03/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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