Texas Instruments | TPIC2030 Serial I/F Controlled 7-Channel Motor-Driver With 1-Channel Step Down Regulator | Datasheet | Texas Instruments TPIC2030 Serial I/F Controlled 7-Channel Motor-Driver With 1-Channel Step Down Regulator Datasheet

Texas Instruments TPIC2030 Serial I/F Controlled 7-Channel Motor-Driver With 1-Channel Step Down Regulator Datasheet
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TPIC2030
SLIS171 – DECEMBER 2015
TPIC2030 Serial I/F Controlled 7-Channel Motor-Driver With 1-Channel Step Down
Regulator
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Serial Peripheral Interface
– Maximum Read/Write 35 MHz
– 3.3-V Digital I/O
Actuator and Motor Driver
– PWM Control With H-Bridge Output
– Focus / Tracking / Tilt Actuator Driver With 12Bit DAC Control
– Sled Motor Drivers With Current Mode, 10-Bit
DAC Control
– Load Driver With 12-Bit DAC Control
– End Position Sensing for Sled Without Position
Sensor
Spindle Motor Driver
– Integrated Spindle Current Sense Resistor
– Sensor-Less: Rotor Position Sense by Motor
BEMF
– 12-Bit Spindle DAC
– Quick Stop by Automatic Controlled Brake
(Auto Short Brake)
– LS Mode: Restricted to 25% of Normal Speed
On-Chip Thermometer (15°C to 165°C/1.2°C)
Software Controlled Switch for LED Driver With
0.1-A OCP
Switch
– CSW: Low RDS(ON) Current Switch With
Selectable OCP Limit (Supposing Use <0.2 A)
– LED: Software Control Current Output Port
With 0.1-A OCP
DC-DC Converter
– Pin Selectable Conversion Voltage 1.0 V/ 1.2
V/ 1.5 V/ 3.3 V (or Disable)
– Improved Efficiency at Low Current With
Discontinuous Regulation Mode
Protection
– Individual Thermal Protect Circuit on
LED/CSW, Switch, DCDC Converter, SPM,
and Actuator
– Overcurrent Protection
– Undervoltage Lockout (UVLO) and
Overvoltage Protection (OVP)
DVD Player
CD Player
Optical Disk Drive
3 Description
TPIC2030 is very-low noise type motor driver IC
suitable for slim or ultra-slim DVD reader/writer. The
integrated current sense resistance for the spindle
motor reduces cost and board area in designs. The
TPIC2030 is an integrated solution for driving the
spindle motor, sled motor, load motor, and Focus /
Tracking / Tilt actuators in an optical disk drive. It also
integrates a synchronous DC-DC converter to supply
1.0 or 3.3 V. The discontinuous mode regulation
feature on the DC-DC converter improves efficiency
at low power consumption.
Device Information(1)
PART NUMBER
TPIC2030DBT
PACKAGE
BODY SIZE (NOM)
TSSOP (44)
11.10 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
MCOM
TPIC2030
5V
5V
SPM
Driver
3.3 V
U
V
W
SLED1+
Controller
1
5V
SLED1
SPI
SLED1SLED2+
5V
SLED2
1PX V
output
5V
TLT
5V
FCS
1.x/3.3 V
output
SLED2TLT+
TLTFCS+
FCSTRK+
REGOUT
REGFB
10 mF
DCDC
V3P3
5V
TRK
TRKLOAD+
5V
LOAD
LOAD-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC2030
SLIS171 – DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.17 Serial Port I/F Write Timing Requirements ........... 11
7.18 Serial I/F Read Timing Requirements................... 11
7.19 Typical Characteristics .......................................... 12
1
1
1
2
3
3
5
8
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
8.5
8.6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics – Common Part ................ 7
Electrical Characteristics – Charge Pump Part......... 7
Electrical Characteristics – DC-DC Converter .......... 8
Electrical Characteristics – Spindle Motor Driver
Part............................................................................. 8
7.9 Electrical Characteristics – Sled Motor Driver Part... 9
7.10 Electrical Characteristics – Focus/
Tilt/Tracking/Driver Part ............................................. 9
7.11 Electrical Characteristics – Load Driver Part .......... 9
7.12 Electrical Characteristics – Current Switch Part ..... 9
7.13 Electrical Characteristics – LED Switch Part ........ 10
7.14 Electrical Characteristics – Thermometer Part ..... 10
7.15 Electrical Characteristics – Actuator Protection .... 10
7.16 Electrical Characteristics – Serial Port Voltage
Levels....................................................................... 10
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
13
14
15
21
24
26
Application and Implementation ........................ 43
9.1 Application Information............................................ 43
9.2 Typical Application ................................................. 52
10 Power Supply Recommendations ..................... 54
11 Layout................................................................... 54
11.1 Layout Guidelines ................................................. 54
11.2 Layout Example .................................................... 54
12 Device and Documentation Support ................. 55
12.1
12.2
12.3
12.4
12.5
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
55
13 Mechanical, Packaging, and Orderable
Information ........................................................... 55
4 Revision History
2
DATE
REVISION
NOTES
December 2015
*
Initial release.
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SLIS171 – DECEMBER 2015
5 Description (continued)
Sensorless control using BEMF allows for self-starting and low-noise operation of the spindle motor without
requiring external sensors. In addition, the TPIC2030 has many built-in protection features including: spindle
driver output current limiting, thermal shutdown, sled-end detection, and power-reset circuit. It also integrates a
thermometer to measure IC temperature.
6 Pin Configuration and Functions
DBT Package
44-Pin TSSOP
Top View
1
PGND_1
LOAD–
44
2
PGND_SW
LOAD+
43
3
REGOUT
SLED2–
42
4
P5V_SW
SLED2+
41
5
REGFB
SLED1–
40
6
SIOV
SLED1+
39
7
SWR_VSEL1
LEDO
38
8
SWR_VSEL2
CSWO
37
9
SSZ
MCOM
36
10
SCLK
P5V_1
35
11
SIMO
P5V_SPM
34
12
SOMI
W
33
13
XMUTE
U
32
14
XFG
V
31
15
XRESET
PGND_SPM
30
16
GPOUT
TRK-–
29
17
CP1
TRK+
28
18
CP2
FCS–
27
19
CP3
FCS+
26
20
AGND
TLT–
25
21
CV3P3A
TLT+
24
22
P5V_2
PGND_2
23
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Pin Functions
PIN
NO.
(1)
4
NAME
I/O
(1)
DESCRIPTION
1
PGND_1
PS
GND terminal
2
PGND_SW
PS
GND terminal for DC-DC converters
3
REGOUT
O
DC-DC converter switching output. Possible GPOUT pin in disable DC-DC
4
P5V_SW
PS
Power supply terminal for DC-DC converters
5
REGFB
I
Feedback input terminal for DC-DC converter
6
SIOV
7
SWR_VSEL1
I
Setting DC-DC converter output voltage
8
SWR_VSEL2
I
Setting DC-DC converter output voltage setting
9
SSZ
I
SIO slave select low active input terminal
10
SCLK
I
SIO serial clock input terminal
11
SIMO
I
SIO slave input master output terminal
12
SOMI
O
SIO slave output master input terminal
13
XMUTE
I
XMUTE input terminal to disable driver output
14
XFG
O
Motor speed signal output
15
XRESET
O
Power on reset output. Internally pulled up to SIOV
16
GPOUT
O
General-purpose output (test monitor)
17
CP1
MISC
Capacitance connection for charge pump
18
CP2
MISC
Capacitance connection for charge pump
19
CP3
MISC
Capacitance connection for charge pump
20
AGND
21
CV3P3A
22
P5V_2
PS
Power supply terminal
23
PGND_2
PS
GND terminal
24
TLT+
O
Tilt positive output terminal
25
TLT–
O
Tilt negative output terminal
26
FCS+
O
Focus positive output terminal
27
FCS–
O
Focus negative output terminal
28
TRK+
O
Tracking positive output terminal
29
TRK–
O
Tracking negative output terminal
30
PGND_SPM
PS
GND terminal for spindle driver
31
V
O
V phase output terminal for spindle motor
32
U
O
U phase output terminal for spindle motor
33
W
O
W phase output terminal for spindle motor
34
P5V_SPM
PS
Power supply terminal for Spindle driver
35
P5V_1
PS
Power supply terminal
36
MCOM
I
Motor center tap connection
37
CSWO
O
Power switch output for 5V OEIC in OPU
38
LEDO
O
LED output terminal
39
SLED1+
O
Sled1 positive output terminal
40
SLED1–
O
Sled1 negative output terminal
41
SLED2+
O
Sled2 positive output terminal
42
SLED2–
O
Sled2 negative output terminal
43
LOAD+
O
Load positive output terminal
44
LOAD–
O
Load negative output terminal
PS
PS
MISC
Power supply terminal for serial port typical 3.3 V
Ground terminal for internal logic
Capacitance terminal for internal 3.3-V regulator
I: Input; O: Output; PS: Power; MISC: Miscellaneous
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SLIS171 – DECEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
+ 5 V supply voltage P5V, P5V_SW, P5V_SPM
Voltage
V
7
V
1.0
A
Spindle output peak current (PW ≦ 2 ms, Duty ≦ 30%)
2.5
A
Current
0.8
A
Focus/tilt/tracking driver output peak current
1.5
A
Current
0.8
A
–0.3
Power dissipation
(1)
UNIT
6
Spindle output current
Input/output voltage
Tstg
MAX
VCC + 0.3 V
V
1438
mW
Operating temperature
–20
75
°C
Storage temperature
–50
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
P5V
Operating supply voltage(Apply for P5V)
4.5
5.0
5.5
V
VSIOV
SIOV voltage
3.0
3.3
3.6
V
VSIFH
XMUTE, SIMO, SSZ, SCLK pin H level input voltage range
2.2
SIOV + 0.2
V
VSIFL
XMUTE, SIMO, SSZ, SCLK pin L level input voltage range
–0.2
0.8
V
VIHB
SWR_VSEL1, SWR_VSEL2 pin H level input voltage
2.2
P5V + 0.1
V
VILB
SWR_VSEL1, SWR_VSEL2 pin L level input voltage range
–0.1
0.8
V
V disRFB
REGFB input level for DC-DC converter disable
ISPMOA
Spindle output average current (U, V, W total)
700
mA
ISPMO
Spindle output current
700
mA
ISLDOA
Sled output average current
400
mA
ILd1Px
DC-DC converter load current 1.x V
700
mA
ILd3P3
DC-DC converter load current 3.3 V
500
mA
IACTOA
Focus / tracking / tilt / loading output average current
400
mA
ILEDOA
LED output average current
50
mA
ICSWOA
CSWO output average current
Fck
SCLK frequency
TO
Operating
P5V – 0.1
P5V
P5V + 0.1
UNIT
V
200
mA
30
33.8688
35
MHz
–20
25
75
℃
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SLIS171 – DECEMBER 2015
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7.4 Thermal Information
TPIC2030
THERMAL METRIC (1)
DBT (TSSOP)
UNIT
TBD PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
(2)
71.9
°C/W
Junction-to-case (top) thermal resistance
19.1
°C/W
Junction-to-board thermal resistance
34.3
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
33.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
(2)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The JEDEC specification low K (1 s) board design used to derive this data
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7.5 Electrical Characteristics – Common Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.97
3.3
3.63
V
ISTBY
Standby supply current
REGFB = P5V, XSLEEP = L
VCV3
CV3P3 output voltage
Iload = 25 mA, REGFB < 3.7 V
0.2
RXM
XMUTE pulldown resistor
80
200
320
kΩ
RSW1
SWR_VSEL1 pulldown resistor
80
200
320
kΩ
RSW2
SWR_VSEL2 pulldown resistor
80
200
320
kΩ
RXRST
XRESET pullup resistor
13.2
33
52.8
kΩ
VXRSTL
XRESET low level output voltage
0.3
V
TPOR
Power on reset delay
RXFG
XFG output resistor
SIOV = 3.3 V, IOL = –100 µA
VXFGH
XFG high level output voltage
SIOV = 3.3 V, XSLEEP = 1,
IOH = 100 µA
VXFGL
XFG low level output voltage
SIOV = 3.3 V, XSLEEP = 1,
IOL = –100 µA
RGPO
GPOUT output resistor
mA
15
20
25
ms
100
200
300
Ω
SIOV –
0.3
100
VGPOH
GPOUT high level output voltage
SIOV = 3.3 V, XSLEEP = 1,
GPOUT_ENA = 1, GPOUT_HL = 1,
IOH = 100 µA
VGPOL
GPOUT low level output voltage
SIOV = 3.3 V, XSLEEP = 1,
GPOUT_ENA = 1,GPOUT_HL = 0,
IOH = 100 µA
tTSD
Thermal protect on temperature
Design specified value
hytTSD
Thermal protect hys temperature
5
Vonvcc
P5V Reset on voltage
3.4
Voffvcc
P5V Reset off voltage
3.6
VonCV3
CV3P3 reset on voltage
VoffCV3
CV3P3 reset off voltage
VonSIO
VoffSIO
V
200
0.3
V
300
Ω
SIOV –
0.3
V
0.3
V
165
ºC
15
25
ºC
3.65
3.9
V
3.85
4.1
V
2.4
2.6
2.8
V
2.5
2.7
2.9
V
SIOV reset on voltage
2.3
2.5
2.7
V
SIOV reset off voltage
2.4
2.6
2.8
V
6.0
6.2
6.5
V
5.8
6.0
6.3
V
110
230
350
mV
VovpspmOn
OVP detection voltage (spindle)
VovpspmOff
OVP release voltage (spindle)
(1)
(1)
VovpSpmHys OVP voltage hysteresis (spindle)
(1)
135
150
VovpOn
OVP detection voltage (except
spindle) (1)
6.3
6.5
6.8
V
VovpOff
OVP release voltage (except
spindle) (1)
6.1
6.3
6.6
V
VovpHys
OVP voltage hysteresis (except
Spindle) (1)
120
240
360
mV
(1)
Those are value as protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause
permanent damage to the device.
7.6 Electrical Characteristics – Charge Pump Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
TEST CONDITIONS
FCHGP
Frequency
XSLEEP = 1
VCHGP
Output Voltage
Ccp1 = Ccp3 = 0.1 µF
IO = –1 mA
MIN
TYP
MAX
UNIT
132.6
156
179.4
kHz
7.76
9.7
11.64
V
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7.7 Electrical Characteristics – DC-DC Converter
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.42
0.62
Ω
0.2
0.4
Ω
Rds1pxH
High Side FET RDSON
REGFB = 0 V REGOUT + 100 mA,
+300 mA
Rds1pxL
Low Side FET RDSON
REGFB = 1.2 V REGOUT – 100
mA, –300 mA
VO1p0
Output Voltage(1p0V)
[SWR_VSEL2, SWR_VSEL1] = 10
0.95
1.0
1.05
V
VO1p2
Output Voltage(1p2V)
[SWR_VSEL2, SWR_VSEL1] = 01
1.14
1.2
1.26
V
VO1p5
Output Voltage(1p5V)
[SWR_VSEL2, SWR_VSEL1] = 11
1.425
1.5
1.575
V
VO3p3
Output Voltage(3p3V)
[SWR_VSEL2, SWR_VSEL1] = 00
3.13
3.3
3.47
V
Tdly1p2
Soft start time
[SWR_VSEL2, SWR_VSEL1] = 01
From P5V reset off to target 90%
0.66
0.82
0.98
ms
RdsO1p2
Output Pull down transistor Rdson
REGFB = 1 V (at DC-DC enable)
Fsw1px
Switching frequency
Vrston1px
616
880
1144
Ω
2.125
2.5
2.875
MHz
Reset on voltage threshold level
75%
80%
85%
Vrstoff1px
Reset off voltage threshold level
85%
90%
95%
VrstHys
Reset off voltage threshold Hys
5%
10%
15%
P5V_SW = 5 V + 200 mVpp,
IO = 200 mA,
F ≈ 100 kHz
26
–
–
dB
[SWR_VSEL2, SWR_VSEL1] ≠ 00
SWR_BSTAUTON = 0
1.3
1.85
2.4
A
[SWR_VSEL2, SWR_VSEL1] = 00
SWR_BSTAUTON = 0
0.65
1.15
1.65
A
0.7
1.0
1.3
ms
PSRRDCDC
IovcDCDC
TMskovctpic
(1)
(2)
PSRR ratio
Overcurrent protective level
(1) (2)
mask time of over current protection
(1)
Those are value as protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause
permanent damage to the device.
These value may fall in low temperature at selecting auto discontinuous mode (SWR_BSTAUTON = 1)
7.8 Electrical Characteristics – Spindle Motor Driver Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
RttlSPM
Total output resistance
High side + low side (IncldRcs)
ResSPM
Resolution
GnSPM
Gain
WidDZSPM
Spindle dead band
WidDZSPMLS
Spindle dead band (LS mode)
SPMClim
8
Current limit
TEST CONDITIONS
MIN
IOUT = 0.5 A
TYP
MAX
0.37
0.7
Ω
times
12
UNIT
bit
Magnification to 1.0 input
5.2
6.0
6.8
Forward
12h
52h
92h
Reverse
–92h
–52h
–12h
–40h
0h
40h
SPM_RCOM_SEL = 00
801
890
979
mA
SPM_RCOM_SEL = 01
882
980
1078
mA
SPM_RCOM_SEL = 10
652
725
798
mA
SPM_RCOM_SEL = 11
705
784
863
mA
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7.9 Electrical Characteristics – Sled Motor Driver Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
RttlSLD
Total output resistance
High side + low side
ResSLD
Resolution
WidDZSLD
input Dead band
GnSLD
Sled current gain
VthEdetSLD
END_DET BEMF threshold voltage
TEST CONDITIONS
MIN
IO = 0.5 A
TYP
MAX
0.8
1.2
UNIT
Ω
10
bit
Forward
2h
1Fh
60h
Reverse
–60h
–1Fh
–2h
380
440
500
mA
SLEDENDTH<1:0> = 00
26
46
66
mV
SLEDENDTH<1:0> = 01
42
82
122
mV
SLEDENDTH<1:0> = 11
9
22
35
mV
P5V = 5 V
RL = 10 Ω, 2.2 mH
VSLED = 7FFh
7.10 Electrical Characteristics – Focus/ Tilt/Tracking/Driver Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
IO = 0.5 A
TYP
MAX
0.7
1.1
UNIT
RttlAct
Total output resistance
High side + low side
ResACT
Resolution
VOfstACT
Each channel output offset voltage
DAC_code = 000h
–30
0
30
mV
VOfstDACT
Output offset voltage focus and tilt
DIFF_TLT = 1
–50
0
50
mV
GnDAct
Difference gain focus and tilt
DIFF_TLT = 1
–1
0
1
GnAct
Gain
magnification to 1.0 input
5.2
6
6.8
Ω
12
bit
db
times
7.11 Electrical Characteristics – Load Driver Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
RttlLOD
Total output resistance
High side + low side
ResLOD
Resolution
GnLOD
Gain
WidDZLOD
Dead band
TocpLOD
Output 100% limit time
IocpLOD
DlyocpLOD
Overcurrent protective Level
Overcurrent protection delay time
TEST CONDITIONS
MIN
IO = 0.5 A
TYP
MAX
UNIT
0.7
1.1
Ω
6.8
times
12
Magnification to 1.0 input
5.2
Forward
6
bit
20h
Reverse
–21h
LOAD_05CH = 0
0.64
0.8
0.96
s
LOAD_05CH = 1 at
Load_OCP_IUP = 0
120
240
360
mA
LOAD_05CH = 1 at
Load_OCP_IUP = 1
215
430
645
mA
LOAD_05CH = 1
0.64
0.8
0.96
s
7.12 Electrical Characteristics – Current Switch Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
RdsCSW
Rds(on)
IlmtCSW
Current limit threshold level
ThlCSW
Protection hold time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
500
mΩ
0.25
0.5
0.75
A
1.47
1.6
2.0
ms
IO = 0.2 A
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7.13 Electrical Characteristics – LED Switch Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
TEST CONDITIONS
RdsLED
Rds(on)
IO = 10 mA
IlmtLED
Current limit threshold level
P5V = 5 V
ThlLED
Protection hold time
MIN
TYP
MAX
UNIT
4.4
10
0.055
0.1
0.145
A
0.35
0.4
0.66
ms
Ω
7.14 Electrical Characteristics – Thermometer Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
ResTEMP
TEST CONDITIONS
MIN
TYP
Resolution
TEMPrng
Temperature range
FTEMP
Update cycle
MAX
7
CHIPTEMP[6:0] = 00
CHIPTEMP[6:0] = 7Fh
UNIT
bit
8
15
22
155
165
175
8
10
12
°C
KHz
7.15 Electrical Characteristics – Actuator Protection
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
TintACTTEMP
TEST CONDITIONS
Update cycle
MIN
TYP
MAX
21
26
31
UNIT
ms
7.16 Electrical Characteristics – Serial Port Voltage Levels
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
High-level output voltage, VOH
IOH = 1 mA
SOMI
Low-level output voltage, VOL
IOL = 1 mA
SIMO
High-level input voltage, VIH
SIMO
Low level input voltage, VIL
SIMO
Input rise/fall time
SOMI
Output rise/fall time (1)
SCLK
Internal pulldown resistance
80
SSZ
Internal pullup resistance
80
10
MAX
80 %
SIOV
SOMI
(1)
TYP
UNIT
V
20%
SIOV
70%
SIOV
V
V
20%
SIOV
V
10% → 90% SIOV
3.5
ns
Cload = 30 pF,10% 90% SIOV
10
ns
200
320
kΩ
200
320
kΩ
Specified by design
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7.17 Serial Port I/F Write Timing Requirements
MIN
NOM
SIOV = 3.3 V
MAX
UNIT
35
MHz
Fck
SCLK clock frequency
tckl
SCLK low time
11
ns
tckh
SCLK high time
11
ns
tsens
SSZ setup time
7
ns
tsenh
SSZ hold time
7
ns
tsl
SSZ disable high time
11
ns
tds
SIMO setup time (Write)
7
ns
tdh
SIMO hold time (Write)
7
ns
7.18 Serial I/F Read Timing Requirements
MIN
NOM
UNIT
35
MHz
SCLK clock frequency
tckl
SCLK low time
11
ns
tckh
SCLK high time
11
ns
tsens
SSZ setup time
7
ns
tsenh
SSZ hold time
7
ns
tsl
SSZ disable high time
11
ns
tds
SIMO setup time (Write)
7
ns
tdh
SIMO hold time (Write)
7
ns
trdly
SOMI delay time (Read)
CLOAD = 10 pF, SIOV = 3.3 V
2
9
ns
tsendl
SOMI hold time (Read)
CLOAD = 10 pF, SIOV = 3.3 V
2
9
ns
SOMI release time (Read)
CLOAD = 10 pF, SIOV = 3.3 V
From SSZ rise to SOMI HIZ
0
9
ns
trls
SIOV = 3.3 V
MAX
Fck
Tsl
SSZ
Tsens
Fck
Tsenh
SCLK
Tckh
Tckl
SIMO
Tds
Tdh
SOMI
Hi-Z
Figure 1. Serial Port Write Timing
Tsl
SSZ
Tsenh
Fck
Tsens
Trls
SCLK
Tckh
Tckl
Tds
Tdh
R
SIMO
SOMI
Hi -Z
Trdly
Tsendl
Figure 2. Serial Port Read Timings
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120
120
100
100
80
80
D u ty C y c le ( % )
D u ty C y c le ( % )
7.19 Typical Characteristics
60
FCS
40
FCS+
TLT
40
TLT+
20
20
0
0
-3000
-2000
-1000
0
DAC Code
1000
2000
3000
-3000
-2000
-1000
0
DAC Code
D001
Figure 3. DAC Code vs Duty Cycle for FCS Outputs
12
60
1000
2000
3000
D002
Figure 4. DAC Code vs Duty Cycle for TLT Outputs
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8 Detailed Description
8.1 Overview
TPIC2030 is low noise type motor driver IC suitable for 5V optical disk drives. The 7-channel driver IC controlled
by serial I/F is optimum for driving a spindle motor, a sled motor (stepping motor applicable), a load motor, and
Focus / Tracking / Tilt actuators. The integrated current sense resistance for spindle motor current measurement
reduces drive system cost. The spindle motor driver part uses integrated sensorless logic to attain very low-noise
operation during startup and runtime. By using BEMF feedback, external sensors, such as a Hall device, are not
needed to carry out self-starting by the starting circuit or perform position detection. By using the efficient PWM
drivers, low-power operation can be achieved by controlling the PWM outputs. Dead zone less control is possible
for a Focus / Tracking / Tilt actuator driver. In addition, the spindle part output current limiting circuit, the thermal
shut down circuit, and the sled end-detection circuit offer protection for all actuators and motors.
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CP3
10 µ 0.1 µ
P5V_ 2
0.1 µ
10 µ
P5V_ 1
5V
5V
0.1 µ
CP2
CP1
5V
5V
0.1 µ
10 µ
P5V_ SPM
8.2 Functional Block Diagram
PGND_SPM
Analog
XSLEEP
10 V(P5Vx2)
Charge
Pump
3.3 V
SPM_RCOM
SPM
Current Limit
SPM_ENA
SPM Logic
DAC PWM
XFG
XFG
M COM
BEM F
Detector
U
Pre-driver
SIOV
W
SPI I/F
SSZ
SSZ
SCLK
SCLK
200 k
SLD_ ENA
ENDDET_ ENA
Dig ital Core
3.3 V
GPOU T
GPOUT
200 k
DAC PWM
TLT_ENA
int 3.3 V
Reg ulator
SLED2–
Pre-driver
TLT+
p w r FET
DAC PWM
P5V
SIOV
FCS_ ENA
Pow er
Monitor
ACTTEMPTH>0
SWR_ VSEL1
200 k
TRK_ EN A
Pre-driver
FCS+
p w r FET
FCS–
Pre-driver
TRK+
p w r FET
200 k
TRK–
F/B
DAC PWM
SWR_ VSEL2
TLT–
F/B
ACTTEMP
33 k
SIOV
LOAD+
Pre-driver
p w r FET
LOAD–
F/B
LOAD_ ENA
P5V
CSW
CSWO
CSWO
P5V_ SW
5V
CSW _ O N
DC-DC
Control
REGOUT
On Chip
Thermometer
2.2 µH
REGFB
1.x/ 3.3V
p w r FET
F/B
0.1 µ
5V
SLED2+
I-F/B
CV3P3V
XRESET
SLED END
Detection
SLD_ ENA
P5V
XRESET
SLED1–
Pre-driver
DAC PWM
XM U TE
InterLock
p w r FET
I-F/B
SOM I
SOMI
SLED1+
Pre-driver
DAC PWM
200 k
SIM O
SIMO
V
p w r FET
200 k
3.3 V
10 µ
LED
LED O
LED O
LED_ ON
10 µ
10 µ
0.1 µ
TPIC2030
14
PGND_1-2
AGND
PGND_ SW
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8.3 Feature Description
8.3.1 Protection Functions
TPIC2030 has five protection features, under voltage lock out (UVLO), over voltage protection (OVP), short
circuit protection (SCP), thermal protection (TSD), and actuator temperature protection (ACTTIMER) in order to
protect target equipment. A protect behavior differ by generated events.
8.3.1.1 Undervoltage Lockout (UVLO)
Power faults are reported in the UVLOMon register. Each UVLOMon bit will be initialized to zero upon a cold
power up.
After a fault is detected the appropriate fault bit will be latched high. Writing to the RST_ERRFLG (REG77) will
clear all UVLOMon bits. The power device faults and actions are summarized in Table 1.
Table 1. Power Fault Monitor
LATCHED
REGISTER
XRESET
CRITERIA
SPM
ACTUATOR
DC-DC
UVLO_P5V
Yes
<3.7 V
Hi-Z
Hi-Z
REGOUT = Hi-Z
REGFB = GND
(enable DC-DC)
Internal 3.3 V under voltage
UVLO_INT3P3
Yes
<2.6 V
Hi-Z
Hi-Z
Hi-Z
DC-DC output under voltage
UVLO_SWR
Yes
<80%
Hi-Z
Hi-Z
SIOV under voltage
UVLO_SIOV
Yes
<2.5 V
Hi-Z
Hi-Z
>6.2 V
Brake
–
–
>6.5 V
Hi-Z
Hi-Z
Hi-Z
FAULT TYPE
P5V under voltage
P5V over voltage
OVP_P5V
8.3.1.2 Overvoltage Protection (OVP)
Over voltage protect function is aimed to protect the unit from the supplying hi-voltage.
When the supply voltage exceeds 6.5 V, all driver and DC-DC converter output goes Hi-Z. When the supply
voltage falls below typical 6.2 V, (6.0 V for SPM) all output start to operate again. The OVP and POR (XRESET)
function is not interlocking. However, DC-DC converter output falls by Hi-Z operations, output voltage falls to
80% then XRESET signal goes low.
Moreover, when power supply exceeds 6.2 V, especially SPM enter short brake mode. This operation is offered
supposing a voltage rising by motor BEMF of the high velocity revolution.
This function is for insurance, so it can not assure that the device is safety in the condition. Because the absolute
maximum ratings range of the supply voltage is 6 V. When this function works, the feed back terminals are not
shorted to GND.
Figure 5 shows the behavior of over voltage protection.
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5 -V sup p ly
6.5 V
6.3 V
6.2 V
6.0 V
SPM
Short B rake
Hi-Z
Actuator
DCDC
LED/CSW
Hi-Z
Figure 5. Overvoltage Protection
8.3.1.3 Overcurrent Protection (OCP)
The over current protect function serve to protect the device from break down by large current. The OCP is
provided for four circuit blocks, and each threshold are on Table 2.
Table 2. OCP Threshold
BLOCK
DC-DC converter
Load driver 1 channel
DETECTION CURRENT
MONITOR TIME
PROTECTION TIME
LATCHED FLAG
1850 mA (1.x V)
1200 mA (3.3 V)
1 ms
Forever
(P5V power recycle)
OCP_SWR
Continue 100% duty
800 ms
forever
OCP_LOAD
Load driver 0.5 channel
240 mA
800 ms
forever
OCP_LOAD
LED driver
100 mA
20 µs
0.4 ms
OCP_LED
CSW driver
500 mA
20 µs
1.6 ms
OCP_CSW
When the large current is detected on each block, device put the output FET to Hi-Z.
The amounts of currents and time have specified the detection threshold for every circuit block.
When OCP occurs, it returns automatically after expiring set Hi-Z period. However, it restricts, the POR is
performed at OCP for DC-DC converter. It keeps XRESET = L and does not return forever. It’s necessary power
ON/OFF actuation in order to make it release.
OCPERR (REG7F) and OCP flag (REG7B) are set at OCP detection.
16
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8.3.1.3.1 OCP for DC-DC Converter
1.8 A(1xV) / 1.2 A(3.3 V)
DCDC conv Load-I
1 ms
0 mA
Hi-Z
REGOUT
DCDC output
XRESET
No release
(until P5V supply recycle)
Figure 6. Overcurrent Protection DC-DC Converter
8.3.1.3.2 OCP for Load Driver
LOAD current
0 mA
Hi-Z
LOAD+
LOAD–
100% duty
800 ms
XRESET
Figure 7. Overcurrent Protection Load 1-Channel
800 ms
240 mA
LOAD current
0 mA
Hi-Z
LOAD+
LOAD–
XRESET
Figure 8. Overcurrent Protection Load 0.5-Channel
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8.3.1.3.3 OCP for LED Driver
LED_ ON
100 mA
20 µs
LED current
0 mA
0.4 ms
LED voltag e
Hi-Z
Hi-Z
Hi-Z
XRESET
Figure 9. Overcurrent Protection LED Driver
8.3.1.3.4 OCP for CSW
CSW _ ON
20 µs
500 m A
CSW current
Hi-Z
0 mA
1.6 ms
CSW voltag e
XRESET
Figure 10. Overcurrent Protection Current Switch
8.3.1.3.4.1 Short Circuit Protection (SCP)
SCP function always monitors the output voltage of high-side and low-side FET of output driver, and when the
setting voltage is not outputted, it recognizes as SCP and changed output Hi-Z. It returns to the original state
automatically 1.6 ms after.
Table 3. SCP Condition
BLOCK
FUNCTION
DETECTION CONDITION
DETECT TIME
HI-Z HOLD TIME
SPM driver
SCP
Monitor driver output voltage
High-side FET output V = GND
Low-side FET output V = Supply V
0.8 to 1.6 µs
1.6 ms
Sled driver
Load driver
Actuator driver
VDAC set
Driver current
Hi-Z
Hi-Z
detect 1.6 µs
Driver voltage
Short to GND
1.6 ms
XRESET
Figure 11. Example of SCP (Driver Short to GND)
18
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8.3.1.4 Thermal Protection (TSD)
The thermal protection (TSD) is a protect function which intercepts an output and suspends an operation when
the IC temperature exceed a maximum permissible on a safety. TSD makes an output Hi-Z when the
temperature rises up and a threshold value is exceeded. There are two levels for threshold Alert and Trip. Alarm
is given by status register TSD_FAULT_ on Alert level with 135°C. It continues rising up temperature, the register
TSD_ is set at 150°C and the driver output changes HI-Z. If temperature falls and is reached 135 degrees, it will
output again.
TPIC2030 has total 11 temperature sensors in each circuit block. Particular sensor is assigned to appropriate
status flag in Table 4.
Table 4. Thermal Sensor Assignment
CIRCUIT
ALERT (°C)
TRIP (°C)
RELEASE (°C)
ALERT FLAG
TRIP FLAG
U
135
150
135
TSD_FAULT_SPM
TSD_SPM
V
135
150
135
TSD_FAULT_SPM
TSD_SPM
W
135
150
135
TSD_FAULT_SPM
TSD_SPM
TLT
135
150
135
TSD_FAULT_ACT
TSD_ACT
FCS
135
150
135
TSD_FAULT_ACT
TSD_ACT
TRK
135
150
135
TSD_FAULT_ACT
TSD_ACT
SLED1
135
150
135
TSD_FAULT_ACT
TSD_ACT
SLED2
135
150
135
TSD_FAULT_ACT
TSD_ACT
LOAD
135
150
135
TSD_FAULT_ACT
TSD_ACT
LED/CSW
135
150
135
TSD_FAULT_LEDCSW
TSD_ LEDCSW
DCDC
135
150
135
TSD_FAULT_SWR
TSD_SWR
8.3.1.5 Actuator Temperature Protection (ACTTIMER)
TPIC2030 has an actuator protect function named ACTTIMER. This function protects the IC by setting actuator
channel output to HIZ when actuator coil current exceeds the specific value. This circuitry calculates heat
accumulation to protect the actuators. When this function operates, sled1, 2 and load channel output will be Hi-Z,
too. And spindle channel will be forced Auto short brake and disc motor will stop.
It’s able to know the protection has occurred by checking Fault register ACTTIMER_FAULT (REG7F) and
ACT_TIMER_PROT (REG78). ACTTIMER_FAULT has a character of advance notice, is set before detecting
ACT_TIMER_PROT. Once an ACT_TIMER_PROT is set, even if temperature falls, it will not release protection
automatically. It is necessary to clear the flag by setting RST_ERR_FLAG (REG77) or setting 0 to ACTTEMPTH
(REG72). ACTTIMER function is able to disable by setting H to ACTPROT_OFF (REG72) or setting 0 to
ACTTEMPTH (REG72).
In order to acquire the optimal value for ACTTEMPTH, you should set device into the condition of the detection
level, and reading the value of ACTTEMP. Because of the present value can be read from ACTTEMP (REG78).
(1)
(1)
The ACTTEMP data is updated on Register in ACTPROT_OFF = 0 and ACTTEMPTH > 0.
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RST_ERR_FLAG
ACTTIMER_FAULT
ACT_TIMER_PROT
ACTTEMPTH
ACTTEMPTH-1
ACTTEMP count
Hi-Z
FCS+, TRK+, TLT+
FCS–, TRK–, TLT–
Hi-Z
Sled1+, Sled2+
Sled1–, Sled2–
Load+
Hi-Z
Load–
Hi-Z
Motor rpm
0
Auto Short Brake
XFG
Disable 300 ms
Figure 12. Actuator Temperature Protections
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8.4 Device Functional Modes
8.4.1 Power-On Reset (POR)
8.4.1.1 Power-Up Sequences
In TPIC2030, the normal sequence is to wait for 5-V supply to come up to 2.2 V. After 5 V establish, the internal
3.3 V will start and wait until stabilize. Now the voltage monitors start to work and begin to look for the DC-DC
converter output. DC-DC converters stabilize the power up sequence finishes and the part starts to function.
Once the part finishes all of its power up tasks, it takes XRESET high to indicate that the part is no longer in
reset and ready to communicate to the outside world. All the DC-DC converter have soft-start features to avoid
rush current and voltage over shoot. Each soft-start sequence takes about 0.8 ms.
Less than 10 ms
P5V Supply
5.0 V
3.9 V
CV3P3
2.8 V
2.2 V
REGOUT
90% (REGOUT)
XRESET
time
0V
1.6 ms 0.8 ms
20 ms
P5V>3.9V && CV3P3>2.8V
Figure 13. POR (Enable DCDC)
P5V Supply
5.0 V
3.9 V
CV3P3
2.8 V
2.2 V
XRESET
time
0V
20 ms
P5V>3.9 V && CV3P3>2.8 V
Figure 14. POR (Disable DCDC)
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Device Functional Modes (continued)
8.4.1.2 XRESET
TPIC2030 is preparing XRESET pin in order to notify an own status to DSP. TPIC2030 set XRESET to L when
the event which has a serious effect on DSP occurs such like the power failure, the over temperature and the
drop of DCDC converter output. If all the exception is removed, it will tell that XRESET pin would be set to H and
it would be in the ready state. The POR (power-on reset) condition is shown in Figure 15. All the behavior of
XRESET is shown in Figure 16.
P5V
SIOV
P5V_SW
< 6.5 V
> 2.6 V
> 3.9 V
INT 3.3-V
Regulator
DC-DC
REGOUT
> 2.8 V
XRESET
> 90%
Delay
Timer
Thermal
Protection
REGFB
Figure 15. POR Block Diagram
XRESET: High
(Write Data)
Register Reset
Register Valid Data
RST_REGS = 1
SIF_TIMEOUTERR_MON = 1
20 ms
P5V < 3.65 V
or CV3P3 < 2.6 V
or SIOV < 2.5 V
or DC-DC conv output < 80% (DC-DC enable)
or P5V > 6.5 V (*2)
or TSD > 150 degree (only TSD_SWR = 1)
or OCP_SWR = 1
P5V > 3.85 V
and CV3P3 > 2.7 V
and SIOV > 2.6 V
and DC-DC conv output > 90%
and P5V < 6.3 V (*2 )
P5V > 3.85 V
and CV3P3 > 2.7 V
and SIOV > 2.6 V
and DC-DC conv Disable (*1)
eset
XRESET: Low
TSD < 135 degree
Power on Reset
OCP_SWR = 1
Hold XRESET
(*1) DC-DC converter disable is REGFB>3.7 V
(*2) When exceed 6.5 V, DC-DC converter output
changed Hi-Z and output falling <80%.
Consequently force RESET event. (Released > 90%)
Figure 16. XRESET Behavior
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Device Functional Modes (continued)
8.4.2 XMUTE
If XMUTE signal is inputted during operation, all the outputs will be suspended and the danger will be avoided.
TPIC2030 will turn off all enable bits, actuator (TLT_ENA/FCS_ENA/TRK_ENA), SPM_ENA, SLD_ENA,
LOAD_ENA and CSW_ON when XMUTE input change to L. LOAD_ENA bit will be disabled only when
LOAD_05CH =1. Also log this event to error latch flag XMUTE_DETECT (REG79) and PWRERR (REG7F).
If XMUTE_NORST (REG7F) = 1, change of XMUTE will not influence to enable bits.
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8.5 Programming
8.5.1 Serial Port Functional Description
The serial communication of TPIC2030 is based on a SPI communications protocol. TPIC2030 is put on the
slave side.
All 16-bit transmission data is effective in SSZ=L period.
The bit stream sent through SIMO from a master (DSP) is latched to an internal shift register by the rising edge
of SCLK. All the data is transmitted in a total of 16-bit format of a command and data. A format has two types of
data, 8 bits and 12 bits length. In order to access specific registers, an address and R/W flag are specified as a
command part. In addition, 12 bit data do not have R/W flag in the packet because DAC register ( =12bit data
form) are Write only. A transfer packet, command and data, is transmitted sequentially from MSB to LSB. A
packet is distinguished in MSB 2 bits of command. In the case of 11, it handles a packet for control register
access, and the other processed as a packet for a DAC data setting.
There are the following four kinds of serial-data communication packets.
1. Write 12 bits DAC data (MSB two bit ≠ 11)
2. Write 8 bits control register (MSB two bit = 11)
3. Read 8 bits control register (MSB two bit = 11)
4. Write 12 bits Focus DAC data+Read 8 bits status register at the same time (MSB two bit ≠ 11)
8.5.2 Write Operation
For write operation, DSP transmits 16 bit (command + address + data) data a bit every in an order from MSB.
Only the 16-bit data which means 16 SCLK sent from the master during SSZ=L becomes effective. If more than
17 or less than 15 SCLK pulses are received during the time that SSZ is low, the whole packet will be ignored.
For all valid write operations, the data of the shift register is latched into its designated internal register at rising
edge of 16th SCLK. All internal register bits, except indicated otherwise, are reset to their default states upon
power-on-reset.
SSZ
SCLK
SIMO
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D4
D3
D2
D1
D0
SOMI
Hi -Z
Figure 17. Write 12-Bits DAC Data
SSZ
SCLK
SIMO
A6
A5
A4
A3
A2
A1
A0
W
D7
D6
D5
SOMI
Hi-Z
Figure 18. Write 8-Bits Control Register
24
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Programming (continued)
8.5.3 Read Operation
DSP sends 8-bit header through SIMO, in order to perform Read operation. TPIC2030 will start to drive the
SOMI line upon the eighth falling edge of SCLK and shift out eight data bits. The master DSP inputs 8-bits data
from SOMI after the ninth rising edge of SCLK. There is optional read mode that SOMI data is advanced a half
clock cycle of SCLK. This mode becomes effective by setting ADVANCE_RD (REG74) = H.
SSZ
SCLK
A6
SIMO
SOMI
A5
A4
A3
A2
A1
A0
R
D7
Hi-Z
D6
D5
D4
D3
D2
D1
D0
Figure 19. Read 8-Bits Control Register
8.5.4 Write and Read Operation
Optionally, the master DSP can read Status register during writing 12 bits DAC (Focus DAC) packet. It’s enabled
by setting bit RDSTAT_ON_VFCS (REG74) = H.
SSZ
SCLK
SIMO
C3
C2
C1
C0
SOMI
Hi-Z
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 20. Write 12-Bits Focus DAC Data + Read 8-Bits Status Data
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8.6 Register Maps
All registers are in WRITE-protect mode after XRESET release. WRITE_ENA bit (REG76) = H is required before
writing data in register.
8.6.1 Register State Transition
Version D ata
(REG7E)
Device Pow er On
In itial Value Set
P5V
P5V<<3.65
3.7VV
or CV3P3
CV3P3<<2.7V
2.6 V
or
or SIOV < 2.5 V
or
SIOV
<
2.5V
or DCDC converter < 80%
or
converter
< 80%
or DCDC
P5V > 6.5
V
or P5V>
RST_REGS
or
6.5V = 1
or RST_
SIF_TIMEOUT_ERR
=1
or
REGS= 1
or SIF_ TIM EOUT_ ERR= 1
XRESET = H
(TPIC2030 outp ut)
Con trol Reg d ata
(REG70 .. 7 F, 6D .. 6F)
P5V< 2.0 V
or CV3P3 < 2.0 V
or RST_ ERR_ FLAG = 1
W RITE_ ENABLE = 0
or XSLEEP = 0
Driver En ab le
(REG70 xxx_ ENA, REG71 CSW _ ON)
disab le (0)
W rite (1)
XM UTE= L
(@ XM UTE_ NORST= 0) *
enab le (1)
P5V < 3.65 V
or CV3P3 < 2.6 V
or SIOV < 2.5 V
or DCDC converter < 80%
or P5V > 6.5 V
or XMUTE = L
or SIF_TIMEOUT_ERR = 1
or RST_REGS = 1
*disable LOAD_ENA only Load05_CH = 1
** SWR_xxx isnot influenced by XMUTE = L
Error latch ed Reg d ata
(REG78,79,7A,7B,7F[5:1])
VDAC Reg d ata
W rite(Vxxx)
(REG01-09)
SetValue
Initial (000)
(error occur, xmute = L)
RST_ INDAC = 1
or XXX_ ENA = 0
Reg ister Enab le
Figure 21. Register State Transition Chart
26
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8.6.2 DAC Register (12-Bit Write Only)
Two difference forms are prepared in 12-bit DAC register, and the forms can be selected by setting VDAC_MAPSW (REG74h).
Table 5. DAC Register (VDAC_MAPSW = 0)
REG
NAME
F
00h
N/A
W
01h
VTLT
W
VTLT[11]
VTLT[10]
VTLT[9]
VTLT[8]
VTLT[7]
VTLT[6]
VTLT[5]
VTLT[4]
VTLT[3]
VTLT[2]
VTLT[1]
VTLT[0]
02h
VFCS
W
VFCS[11]
VFCS[10]
VFCS[9]
VFCS[8]
VFCS[7]
VFCS[6]
VFCS[5]
VFCS[4]
VFCS[3]
VFCS[2]
VFCS[1]
VFCS[0]
03h
VTRK
W
VTRK[11]
VTRK[10]
VTRK[9]
VTRK[8]
VTRK[7]
VTRK[6]
VTRK[5]
VTRK[4]
VTRK[3]
VTRK[2]
VTRK[1]
VTRK[0]
04h
VSLD1
W
VSLD1[11]
VSLD1[10]
VSLD1[9]
VSLD1[8]
VSLD1[7]
VSLD1[6]
VSLD1[5]
VSLD1[4]
VSLD1[3]
VSLD1[2]
VSLD1[1] (1
VSLD1[0]
05h
VSLD2
W
VSLD2[11]
VSLD2[10]
VSLD2[9]
VSLD2[8]
VSLD2[7]
VSLD2[6]
VSLD2[5]
VSLD2[4]
VSLD2[3]
VSLD2[2]
VSLD2[1]
VSLD2[0]
06h
N/A
W
N/A
N/A
07h
N/A
W
N/A
N/A
08h
VSPM
W
VSPM[11]
VSPM[10]
VSPM[9]
VSPM[8]
VSPM[7]
VSPM[6]
VSPM[5]
VSPM[4]
VSPM[3]
VSPM[2]
VSPM[1]
VSPM[0]
09h
VLOAD
W
VLOAD[11] VLOAD[10]
VLOAD[9]
VLOAD[8]
VLOAD[7]
VLOAD[6]
VLOAD[5]
VLOAD[4]
VLOAD[3]
VLOAD[2]
VLOAD[1]
VLOAD[0]
0Ah
N/A
W
N/A
N/A
N/A
0Bh
N/A
W
N/A
N/A
N/A
(1)
11
10
9
8
7
6
N/A
5
4
3
2
N/A
1
0
N/A
)
(1)
(1)
(1)
N/A
N/A
TPIC2030 process as 0 even if set 1.
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Table 6. DAC Register (VDAC_MAPSW = 1)
REG
NAME
F
11
10
9
8
7
6
00h
N/A
W
01h
VTLT
02h
5
4
3
2
W
VTRK[11]
VTRK[10]
VTRK[9]
VTRK[8]
VTRK[7]
VTRK[6]
VTRK[5]
VTRK[4]
VTRK[3]
VFCS
W
VFCS[11]
VFCS[10]
VFCS[9]
VFCS[8]
VFCS[7]
VFCS[6]
VFCS[5]
VFCS[4]
03h
VTRK
W
VTLT[11]
VTLT[10]
VTLT[9]
VTLT[8]
VTLT[7]
VTLT[6]
VTLT[5]
04h
VSLD1
W
VSLD1[11]
VSLD1[10]
VSLD1[9]
VSLD1[8]
VSLD1[7]
VSLD1[6]
05h
VSLD2
W
VSLD2[11]
VSLD2[10]
VSLD2[9]
VSLD2[8]
VSLD2[7]
VSLD2[6]
06h
VSPM
W
VSPM[11]
07h
N/A
W
VSPM[10]
N/A
VSPM[9]
VSPM[8]
VSPM[7]
VSPM[6]
N/A
N/A
08h
N/A
W
N/A
N/A
N/A
N/A
1
0
VTRK[2]
VTRK[1]
VTRK[0]
VFCS[3]
VFCS[2]
VFCS[1]
VFCS[0]
VTLT[4]
VTLT[3]
VTLT[2]
VTLT[1]
VTLT[0]
VSLD1[5]
VSLD1[4]
VSLD1[3]
VSLD1[2]
VSLD1[1]
VSLD1[0]
VSLD2[5]
VSLD2[4]
VSLD2[3]
VSLD2[2]
VSLD2[1]
VSLD2[0]
VSPM[5]
VSPM[4]
VSPM[3]
VSPM[2]
VSPM[1]
VSPM[0]
VLOAD[5]
VLOAD[4]
N/A
VLOAD
W
N/A
N/A
W
N/A
N/A
N/A
0Bh
N/A
W
N/A
N/A
N/A
28
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VLOAD[8]
VLOAD[7]
(1)
09h
TPIC2030 process as 0 even if set 1.
VLOAD[9]
(1)
0Ah
(1)
VLOAD[11] VLOAD[10]
N/A
VLOAD[6]
(1)
(1)
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8.6.3 Control Register
Table 7. Control Register (8bit Read/Write)
(1)
(1)
REG
NAME
F
7
6
5
4
3
2
1
0
70h
DriverEna
R/W
TLT_ENA
FCS_ENA
TRK_ENA
SPM_ENA
SLD_ENA
SWR_MD_BURST
LOAD_ENA
XSLEEP
71h
FuncEna
R/W
SPM_LSMODE
ENDDET_ENA
SWR_BSTAUTON
LED_ON
CSW_ON
TEMPMON_ENA
72h
ACTCfg
R/W
LOAD_O5CH_HIGH
LOADPROT_OFF
ACTPROT_OFF
73h
Parm0
R/W
74h
OptSet
R/W
75h
Protect
R/W
76h
WriteEna
R/W
WRITE_ENABLE
77h
ClrReg
W
RST_INDAC
78h
ActTemp
R
TI reserved
ACT_TIMER_PROT
79h
UVLOMon
R
TI reserved
XMUTE_DETECT
UVLO_P5V
UVLO_INT3P3
UVLO_SIOV
UVLO_SWR
OVP_P5V
7Ah
TsdMon
R
TSD_SWR
TSD_SPM
TSD_ACT
TSD_ LEDCSW
7Bh
ProtMon
SCP_SPM
SCP_SLED
SCP_LOAD
SCP_ACT
7Ch
TempMon
7Dh
Protect
R
7Eh
Version
R
7Fh
Status
R
OCPSCPERR
TSDFAULT
FG
60h
Protect
R/W
TI reserved
61h
Protect
R/W
TI reserved
62h
Protect
R/W
TI reserved
63h
Protect
R/W
TI reserved
64h
Protect
R/W
65h
Protect
R/W
FBSVR_SBRK_OFF
TI reserved
66h
Protect
R/W
TI reserved
TI reserved
SIF_TIMEOUT_TH
DIFF_TLT
LOAD05_CH
TI reserved
ACTTEMPTH
SLEDEND_HZTIME
SLDENDTH
STATUS_ON_VFCS
VSLD2_POL
SPM_RCOM_SEL
LOAD_OCP_IUP
TI reserved
XMUTE_NORST
SOMI_HIZ
VDAC_MAPSW
TI reserved
TI reserved
RST_REGS
RST_ERR_FLAG
TI reserved
ACTTEMP
TSD_FAULT_SWR
TSD_FAULT_SPM
TSD_FAULT_ACT
TSD_FAULT_LEDCSW
R
OCP_SWR
OCP_LOAD
OCP_LED
OCP_CSW
R
CHIPTEMP_STATUS
CHIPTEMP
TI reserved
Version
ACTTIMER_FAULT
ENDDET
SIF_TIMEOUTERR
PWRERR
TSDERR
TI reserved
TI reserved
6Ah
Protect
R/W
6Ch
Protect
R/W
6Dh
DCCfg
R/W
6Eh
UtilCfg
R/W
GPOUT_HL
GPOUT_ENA
TI reserved
SWR_GPIO_CNTL
6Fh
MonitorSet
R/W
ACTTIMER_FLT_MON
ENDDET_MON
SIF_TIMEOUTERR_M
ON
PWRERR_MON
TI reserved
TI reserved
SWR_BST_HEFF
TI reserved
SWR_VOUTUP
TI reserved
TSDERR_MON
OCPSCPERR_MON
TSDFAULT_MON
TI reserved
VTRK and VLOAD is exclusive, using same DAC block
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8.6.4 Detailed Description of Registers
8.6.4.1 REG01 12-bit DAC for Tilt (VDAC_MAPSW = 0)
Figure 22. Tilt (REG01)
15
14
13
12
11
10
9
8
VTLT
7
6
5
4
w-0
w-0
w-0
w-0
3
2
1
0
w-0
w-0
w-0
w-0
VTLT
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Tilt (REG01) Field Descriptions
Bit
Field
Type
Default
Description
11-0
VTLT
w
0
Digital input code for Tilt.
2’s compliment format 0x800(-2048) to 0x7ff(+2047)
Output is changed by differential Tilt mode (REG74[7])
TLT_OUT = VTLT* (6.0/2048) (DIFF_TLT=0)
TLT_OUT = (VFCS-VTLT)* (6.0/2048) (DIFF_TLT=1)TLT_OUT should
be changed after writing VFCS.
In DIFF_TLT mode (DIFF_TLT=1), TLT_OUT should be changed after
writing VFCS.
8.6.4.2 REG02 12-bit DAC for Focus (VDAC_MAPSW = 0)
Figure 23. Focus (REG02)
15
14
13
12
11
10
9
8
VFCS
7
6
5
4
w-0
w-0
w-0
w-0
3
2
1
0
w-0
w-0
w-0
w-0
VFCS
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Focus (REG02) Field Descriptions
30
Bit
Field
Type
Default
Description
11-0
VFCS
w
0
Digital input code for Focus.
2’s compliment format 0x800(-2048) to 0x7ff(+2047)
Output is changed by differential Tilt mode (REG74[7])
FCS_OUT = VFCS × (6.0/2048) (DIFF_TLT=0)
FCS_OUT = (VFCS+VTLT)* (6.0/2048) (DIFF_TLT=1)
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8.6.4.3 REG03 12-bit DAC for Track (VDAC_MAPSW = 0)
Figure 24. Track (REG03)
15
14
13
12
11
10
9
8
VTRK
7
6
5
4
w-0
w-0
w-0
w-0
3
2
1
0
w-0
w-0
w-0
w-0
VTRK
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. Track (REG03) Field Descriptions
Bit
Field
Type
Default
Description
11-0
VTRK
w
0
Digital input code for Tracking.
2’s compliment format 0x800(-2048) to 0x7ff(+2047)
TRK_OUT = VTRK* (6.0/2048)
8.6.4.4
REG04 10bit DAC for Sled1 (VDAC_MAPSW = 0)
Figure 25. Sled1 (REG04)
15
14
13
12
11
10
9
8
VSLD1
7
6
5
4
w-0
w-0
w-0
w-0
3
2
1
0
w-0
w-0
w-0
w-0
VSLD1
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. Sled1 (REG04) Field Descriptions
Field
Type
Default
Description
11-2
Bit
VSLD1
w
0
Digital input code for Sled1.
2’s compliment format 0x800(-2048) to 0x7ff(+2047)
Two bits on LSB, VSLD1[1:0], will be handled with zero.
SLD1_OUT = VSLD1* (440mA/2048)
1-0
TI reserved
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REG05 10bit DAC for Sled2 (VDAC_MAPSW = 0)
Figure 26. Sled2 (REG05)
15
14
13
12
11
10
9
8
VSLD2
7
6
5
4
w-0
w-0
w-0
w-0
3
2
1
0
w-0
w-0
w-0
w-0
VSLD2
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. Sled2 (REG05) Field Descriptions
Bit
Field
Type
Default
Description
11-2
VSLD2
w
0
Digital input code for Sled2.
2’s compliment format 0x800(-2048) to 0x7ff(+2047)
Two bits on LSB, VSLD2[1:0], will be handled with zero.
SLD2_OUT = VSLD2* (440mA/2048)
1-0
TI reserved
8.6.4.6 REG08 12-bit DAC for Spindle (VDAC_MAPSW = 0)
Figure 27. Spindle (REG08)
15
14
13
12
11
10
9
8
VSPM
7
6
5
4
w-0
w-0
w-0
w-0
3
2
1
0
w-0
w-0
w-0
w-0
VSPM
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Spindle (REG08) Field Descriptions
Bit
Field
Type
Default
Description
11-0
VSPM
w
0
Digital input code for Spindle.
2’s compliment format 0x800(-2048) to 0x7ff(+2047)
SPM_OUT = VSPM* (6.0/2048)
8.6.4.7 REG09 12-bit DAC for Load (VDAC_MAPSW = 0)
Figure 28. Load (REG09)
15
14
13
12
11
10
9
8
VLOAD
7
6
5
4
w-0
w-0
w-0
w-0
3
2
1
0
w-0
w-0
w-0
w-0
VLOAD
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. Load (REG09) Field Descriptions
Bit
11-0
32
Field
Type
Default
Description
VLOAD
w
0
Digital input code for Load.
2’s compliment format 0x800(-2048) to 0x7ff(+2047)
LOAD_OUT = VLOAD* (6.0/2048)
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8.6.4.8 REG65 8bit Control Register for FBSVR
Figure 29. FBSVR (REG65)
7
6
5
4
3
2
rw-0
rw-0
rw-0
1
FBSVR_SBRK
_OFF
rw-0
TI reserved
rw-0
rw-0
rw-0
0
TI reserved
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. FBSVR (REG65) Field Descriptions (1)
(1)
Bit
Field
Type
Default
7-2
TI reserved
rw
0
rw
0
rw
0
1
FBSVR_SBRK_OFF
0
TI reserved
Description
SPM FB saver mode
0: Reset only when F/R transition (Default)
1: Reset all time when SBRK (Recommend)
To improve FG behavior, we strongly recommend FBSVR_SBRK_OFF = 1
8.6.4.9 REG6D 8bit Control Register for DCCfg
Figure 30. DCCfg (REG6D)
7
6
TI reserved
rw-0
rw-0
5
SWR_BST_HE
FF
rw-0
4
rw-0
3
TI reserved
2
rw-0
rw-0
1
0
SWR_VOUTUP
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. DCCfg (REG6D) Field Descriptions
Bit
Field
Type
Default
7-6
TI reserved
rw
0
SWR_BST_HEFF
rw
0
4-2
TI reserved
rw
0
1-0
SWR_VOUTUP
rw
0
5
Description
Select high efficiency mode in discontinuous mode (for 1.xV only)
0: normal regulation
1: high efficiency mode
DCDC converter output voltage up. (for 1.xV only)
00: 0%, 01: 2% 10: 3.8% 11: 5.4% (for 1.2V, 1.5V)
00: 0%, 01: 1.3% 10: 2.4% 11: 3.3% (for 1.0V)
Prohibit setting in 3.3V output mode.
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8.6.4.10 REG6E 8bit Control Register for UtilCfg
Figure 31. UtilCfg (REG6E)
7
GPOUT_HL
6
GPOUT_ENA
5
TI reserved
rw-0
rw-0
rw-0
4
SWR_GPIO_C
NTL
rw-0
3
2
1
0
rw-0
rw-0
TI reserved
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. UtilCfg (REG6E) Field Descriptions
Bit
Field
Type
Default
Description
7
GPOUT_HL
rw
0
GPOUT (General Purpose Output) pin output selection
0: low output
1: high output
valid only REG6F=00h
6
GPOUT_ENA
rw
0
Enable monitor signal output to GPOUT pin
0: No signal output, Hi-Z
1: output signal selected in REG6F with CMOS output
Output is Logical OR when selected two more signals
4
SWR_GPIO_CNTL
rw
0
Set GPOUT output value (disable DCDC converter)
0: output L in REGOUT pin (open drain)
1: output H in REGOUT pin (open drain)
TI reserved
rw
0
3-0
8.6.4.11 REG6F 8bit Control Register for MonitorSet (REG6F)
Figure 32. MonitorSet (REG6F)
7
6
ACTTIMER_FL ENDDET_MON
T_MON
rw-0
rw-0
5
SIF_TIMEOUT
ERR_MON
rw-0
4
PWRERR_MO
N
rw-0
3
TSDERR_MON
rw-0
2
OCPERR_MO
N
rw-0
1
TSDFAULT_M
ON
rw-0
0
TI reserved
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. MonitorSet (REG6F) Field Descriptions
Bit
34
Field
Type
Default
Description
0
Assign signal to GPIO pin
1: ACTTIMER fault output to GPOUT pin
0
Assign signal to GPIO pin
1: ENDDET monitor output to GPOUT pin
0
Assign signal to GPIO pin
1: SIF timeout monitor output to GPOUT pin
0
Assign signal to GPIO pin
1: PWRERR monitor output to GPOUT pin
7
ACTTIMER_FLT_MON
6
ENDDET_MON
5
SIF_TIMEOUTERR_MON
4
PWRERR_MON
3
TSDERR_MON
rw
0
Assign signal to GPIO pin
1: TSDERR fault output to GPOUT pin
2
OCPERR_MON
rw
0
Assign signal to GPIO pin
1: OCPERR fault output to GPOUT pin
1
TSDFAULT_MON
rw
0
Assign signal to GPIO pin
1: TSDFAULT fault output to GPOUT pin
0
TI reserved
rw
0
rw
rw
rw
rw
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8.6.4.12 REG70 8bit Control Register for DriverEna
Figure 33. DriverEna (REG70)
7
TLT_ENA
6
FCS_ENA
5
TRK_ENA
4
SPM_ENA
3
SLD_ENA
rw-0
rw-0
rw-0
rw-0
rw-0
2
SWR_MD_BUR
ST
rw-0
1
LOAD_ENA
0
XSLEEP
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. DriverEna (REG70) Field Descriptions
Bit
Field
Type
Default
Description
7
TLT_ENA
rw
0
1 : Tilt enable (with XSLEEP=1)
It’s reset when XMUTE changes to L.
6
FCS_ENA
rw
0
1: Focus enable (with XSLEEP=1)
It’s reset when XMUTE changes to L.
5
TRK_ENA
rw
0
1: Track enable (with XSLEEP=1)
It’s reset when XMUTE changes to L.
4
SPM_ENA
rw
0
1: Spindle enable (with XSLEEP=1)
It’s reset when XMUTE changes to L.
3
SLD_ENA
rw
0
1: Sled enable (with XSLEEP=1)
It’s reset when XMUTE changes to L.
2
SWR_MD_BURST
rw
0
1 : Enable DCDC converter discontinuous regulation mode.
Regardless of the amount of current consumption, it will always be in
discontinuous mode. Holds a former value after XMUTE = L event.
1
LOAD_ENA
rw
0
1 : LOAD enable (with XSLEEP=1)
Track (bit5:TRK_ENA) will be disabled at LOAD_ENA=1 because of
sharing the DAC PWM module. Load priority is higher than TRK_ENA.
It’s reset when XMUTE changes to L. (with LOAD_05CH=1)
0
XSLEEP
rw
0
1: Operation mode 0 : Power save mode
Charge pump enable bit.
All driver enable bit (Bit[7:1]) change disabled and output change to Hi-Z
(regardless of setting xxx_ENA bit is 1) when setting XSLEEP to 0.
Therefore set 1 to XSLEEP before setting each enable bits.
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8.6.4.13 REG71 8bit Control Register for FuncEna
Figure 34. FuncEna (REG71)
7
SPM_LSMODE
6
ENDDET_ENA
rw-0
rw-0
5
SWR_BSTAUT
ON
rw-0
4
LED_ON
3
CSW_ON
rw-0
rw-0
2
TEMPMON_EN
A
rw-0
1
0
TI reserved
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. FuncEna (REG71) Field Descriptions
Bit
Field
Type
Default
Description
7
SPM_LSMODE
rw
0
0 : Spindle rotation mode
1 : Light Scribe mode (slow rotation mode)
6
ENDDET_ENA
rw
0
1 : use Sled end detection enable ( with SLD_ENA=1)
5
SWR_BSTAUTON
rw
0
1 : Enable auto DCDC converter discontinuous regulation mode.
At low current consumption, it changes to discontinuous mode
automatically. Holds a former value after XMUTE = L event.
SWR_BSTAUTON mode is chosen when both bit SWR_BSTAUTON
and SWR_MD_BURST are set.
4
LED_ON
rw
0
1 : LEDO enable ( with XSLEEP=1)
3
CSW_ON
rw
0
1 : CSWO enable ( with XSLEEP=1)
It’s reset when XMUTE changes to L
2
TEMPMON_ENA
rw
0
1: enable chip temperature monitoring ( with XSLEEP=1)
TI reserved
rw
0
1-0
8.6.4.14 REG72 8bit Control Register for ACTCfg
Figure 35. ACTCfg (REG72)
7
LOAD_O5CH_
HIGH
rw-0
6
LOADPROT_O
FF
rw-0
5
ACTPROT_OF
F
rw-0
4
3
2
ACTTEMPTH
1
0
rw-0
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. ACTCfg (REG72) Field Descriptions
Bit
Field
Type
Default
Description
7
LOAD_05CH_HIGH
rw
0
LOAD output polarity at 0.5CH ( REG74h[6]=1 )
0: LOADP=Low
1: LOADP=High
6
LOADPROT_OFF
rw
0
1: Load Overcurrent Protection OFF
5
ACTPROT_OFF
rw
0
0 : Actuator protection ON 1 : Actuator Fault monitor disable (No
protection for ACT channel)
ACTTEMPTH
rw
0
Actuator thermal protection (=ACT Timer) threshold level
ACT Timer Protection enable except ACTTEMPTH[4:0]=0x00
ACTTEMPTH = 0x00 equal to ACTPROT_OFF = 1
By writing value 0x00, ACTTIMER_PROT flag is cleared.
4-0
36
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8.6.4.15 REG73 8bit Control Register for Parm0
Figure 36. Parm0 (REG73)
7
6
SIF_TIMEOUT_TH
rw-0
rw-0
5
SLEDEND_HZ
TIME
rw-0
4
3
SLDENDTH
rw-0
rw-0
2
1
SPM_RCOM_SEL
rw-0
rw-0
0
XMUTE_NORS
T
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. Parm0 (REG73) Field Descriptions
Bit
Field
Type
Default
Description
7-6
SIF_TIMEOUT_TH
rw
0
Watch dog timer for Serial communication
0: disable 1: 1 ms 2: 100 µs 3: 10 µs
Set SIF_TIMEOUTERR (REG7F) if communication is suspended for this
time period. XRESET processing will be performed if a
SIF_TIMEOUTERR occurs.
5
SLEDEND_HZTIME
rw
0
Time window for sled end detection.
0: 400 µs 1: 200 µs
Caution) Need to recycle ENDDET_ENA=0→1 after writing this bit.
4-3
SLDENDTH
rw
0
Sled end detection sensibility setting. Detection threshold for motor
BEMF
00: 46 mV; 01: 86 mV; 10: 0 mV; 11: 22 mV
2-1
SPM_RCOM_SEL
rw
0
Select resistor value of spindle current sense resistor. Current limit is set
as following current.
00: 890 mA; 01: 980 mA; 10: 725 mA; 11: 784 mA
XMUTE_NORST
rw
0
Reset driver enable bit (XXX_ENA and CSW_ON) register at XMUTE =
L.
0: Reset enable bit at XMUTE = L
1: XMUTE status does not influence enable bit.
0
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8.6.4.16 REG74 8bit Control Register for OptSet
Figure 37. OptSet (REG74)
7
DIFF_TLT
6
LOAD_05CH
rw-0
rw-0
5
RDSTAT_ON_
VFCS
rw-0
4
VSLD2_POL
rw-0
3
LOAD_OCP_
IUP
rw-0
2
TI reserved
1
SOMI_HIZ
0
VDAC_MAPSW
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. OptSet (REG74) Field Descriptions
Bit
Field
Type
Default
Description
7
DIFF_TLT
rw
0
1 : Differential Tilt mode enable (with TLT_ENA=FCS_ENA=1)
Differential Tilt mode (DIFF_TLT=1), DAC value setting as follows
FCS_OUT = (VFCS + VTLT) × 6 / 2048
TLT_OUT = (VFCS – VTLT) × 6 / 2048
In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after
writing VFCS.
6
LOAD_05CH
rw
0
The setting of Load motor driving type. Load output changes as follow
0: step down mode (LOAD output is controlled by DAC code, VLOAD)
Use for Slot-in model or step down tray model.
1: 0.5Ch mode (LOAD is only controlled by LOAD_05CH_HIGH)
Use for Tray model
5
RDSTAT_ON_VFCS
rw
0
Set Read status data (REG7F) at VFCS write command (REG02)
1: enable Write and Read mode
(Write 12-bits Focus DAC data + Read 8bits status data)
4
VSLD2_POL
rw
0
change direction of SLED rotation
3
LOAD_OCP_IUP
rw
0
Select over current protection (OCP) threshold for Load channel current
0: 250mA
1: 425mA
2
TI reserved
rw
0
1
SOMI_HIZ
rw
0
0: SOMI line High-Z at bus idling time.
1: SOMI line Pull Down at bus idling time.
0
VDAC_MAPSW
rw
0
Selection of DAC register channel assignments (REG01~09)
8.6.4.17 REG76 8bit Control Register for WriteEna
Figure 38. WriteEna (REG76)
7
WRITE_ENABLE
rw-0
6
5
4
rw-0
rw-0
rw-0
3
TI reserved
rw-0
2
1
0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. WriteEna (REG76) Field Descriptions
Bit
7
Type
WRITE_ENABLE
6-0
38
Field
Default
Description
0
0: Register Write disable except REG76
1: Write enable for registers REG01~0B, REG70~7F, REG6C~6F
TI reserved
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8.6.4.18 REG77 8bit Control Register for ClrReg
Figure 39. ClrReg (REG77)
7
RST_INDAC
w-0
6
RST_REGS
w-0
5
RST_ERR_FLAG
w-0
4
RST_REGS_WO3
w-0
3
2
1
0
w-0
w-0
TI reserved
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. ClrReg (REG77) Field Descriptions
Bit
Field
Type
Default
Description
7
RST_INDAC
w
0
1 : Reset all 12-bit input DAC register (REG01~0B)
*Self clear bit
6
RST_REGS
w
0
1 : Reset all 8bit R/W Registers (REG70h~77h, 60h-6Fh)
*Self clear bit
5
RST_ERR_FLAG
w
0
1 : Reset Fault Flag Latch (REG7F[5:1], REG79~REG7B)
*Self clear bit
TI reserved
w
0
4-0
8.6.4.19 REG78 8bit Control Register for ActTemp
Figure 40. ActTemp (REG78)
7
6
TI reserved
r-0
r-0
5
ACT_TIMER_
PROT
r-0
4
3
2
ACTTEMP
1
0
r-0
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. ActTemp (REG78) Field Descriptions
Bit
Field
Type
Default
7-6
TI reserved
r
0
ACT_TIMER_PROT
r
0
ACT timer protection flag
1: ACT Timer Protection has detected and latched.
(ACTTEMP > ACTTEMPTH)
This bit holds data after temperature change to low since this is a latch
bit. Also driver output keep Hi-Z until setting RST_ERR_FLAG or
ACTTEMPTH=0.
ACTTEMP
r
0
An integrated value of ACT_TIMER counters at present.
5
4-0
Description
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8.6.4.20 REG79 8bit Control Register for UVLOMon
Figure 41. UVLOMon (REG79)
7
6
TI reserved
r-0
r-0
5
XMUTE_
DETECT
r-0
4
UVLO_P5V
3
UVLO_INT3P3
2
UVLO_SIOV
1
UVLO_SWR
0
OVP_P5V
r-0
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. UVLOMon (REG79) Field Descriptions
(1)
Bit
Field
Type
Default
7-6
TI reserved
r
0
Description
5
XMUTE_DETECT
r
0
XMUTE flag for detection Lo input. (>20 µs) (1)
4
UVLO_P5V
r
0
UVLO (Under Voltage Lock Out) flag for detection Low P5V supply (1)
3
UVLO_INT3P3
r
0
UVLO flag for detection Low internal 3.3-V regulator (1)
2
UVLO_SIOV
r
0
UVLO flag for detection Low SIOV (1)
1
UVLO_SWR
r
0
UVLO flag for detection Low DCDC (1)
0
OVP_P5V
r
0
Over voltage protection flag for P5Vsply (1)
Latched first event only. Cleared by RST_ERR_FLG (REG77)
8.6.4.21 REG7A 8bit Control Register for TsdMon
Figure 42. TsdMon (REG7A)
7
6
5
4
TSD_FAULT_S TSD_FAULT_S TSD_FAULT_A TSD_FAULT_L
WR
PM
CT
EDCSW
r-0
r-0
r-0
r-0
3
TSD_SWR
2
TSD_SPM
1
TSD_ACT
r-0
r-0
r-0
0
TSD_
LEDCSW
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. TsdMon (REG7A) Field Descriptions
Bit
(1)
40
Field
Type
Default
Description
7
TSD_FAULT_SWR
r
0
Pre alert of thermal protection for DCDC converter block (1)
6
TSD_FAULT_SPM
r
0
Pre alert of thermal protection of Spindle block (1)
5
TSD_FAULT_ACT
r
0
Pre alert of thermal protection of Focus /Track /Tilt Sled1 /Sled2 /
/Load (1)
4
TSD_FAULT_LEDCS
W
r
0
Pre alert of thermal protection of CSW/LED (1)
3
TSD_SWR
r
0
Thermal protection flag for DCDC converter block (1)
DCDC converter output Hi-Z until temperature falls on release level
1: detect (latch)
2
TSD_SPM
r
0
Thermal protection flag for Spindle (1)
SPM output Hi-Z until temperature falls on release level
1: detect (latch)
1
TSD_ACT
r
0
Thermal protection flag for Focus /Track /Tilt Sled1 /Sled2 /Load (1)
Actuator output Hi-Z until temperature falls on release level
1: detect (latch)
0
TSD_ LEDCSW
r
0
Thermal protection flag for CSW/LED (1)
LED/CSW output Hi-Z until temperature falls on release level
1: detect (latch)
Cleared by RST_ERR_FLAG bit (REG77)
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8.6.4.22 REG7B 8bit Control Register for ProtMon
Figure 43. ProtMon (REG7B)
7
OCP_SWR
r-0
6
OCP_LOAD
r-0
5
OCP_LED
r-0
4
OCP_CSW
r-0
3
SCP_SPM
r-0
2
SCP_SLED
r-0
1
SCP_LOAD
r-0
0
SCP_ACT
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29. ProtMon (REG7B) Field Descriptions
Bit
(1)
Field
Type
Default
Description
7
OCP_SWR
r
0
Overcurrent protection flag bit for DCDC converter (1)
6
OCP_LOAD
r
0
Overcurrent protection flag bit for Load channel (1)
5
OCP_LED
r
0
Overcurrent protection flag bit for LED channel (1)
4
OCP_CSW
r
0
Overcurrent protection flag bit for CSW channel (1)
3
SCP_SPM
r
0
Short circuit protection flag bit for spindle channe (1)
2
SCP_SLED
r
0
Short circuit protection flag bit for sled channe (1)
1
SCP_LOAD
r
0
Short circuit protection flag bit for load channe (1)
0
SCP_ACT
r
0
Short circuit protection flag bit for Fcs/Trk/Tilt channel (1)
Cleared by RST_ERR_FLAG bit (REG77)
8.6.4.23 REG7C 8bit Control Register for TempMon
Figure 44. TempMon (REG7C)
7
CHIPTEMP_ST
ATUS
r-0
6
5
4
3
CHIPTEMP
2
1
0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. TempMon (REG7C) Field Descriptions
Bit
7
6-0
Field
Type
Default
Description
CHIPTEMP_STATUS
r
0
1: New data CHIPTEMP[6:0] is updated
It will be cleared after reading.
CHIPTEMP
r
0
Chip temperature monitor (1.2deg/LSB)
15(0) to 165(127) degrees.
For monitoring, TEMPMON_ENA=1 and XSLEEP=1 is required
8.6.4.24 REG7E 8bit Control Register for Version
Figure 45. Version (REG7E)
7
6
5
4
3
2
1
0
r-0
r-0
r-0
r-0
Version
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. Version (REG7E) Field Descriptions
Bit
Field
Type
Default
Description
7-0
Version
r
X
Version[7:4] = revision number of TPIC2030
Version[3:0] = option
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8.6.4.25 REG7F 8bit Control Register for Status
Figure 46. Status (REG7F)
7
ACTTIMER_FA
ULT
r-0
6
ENDDET
r-0
5
SIF_TIMEOUT
ERR
r-0
4
PWRERR
3
TSDERR
2
OCPERR
1
TSDFAULT
0
FG
r-0
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. Status (REG7F) Field Descriptions
Bit
42
Field
Type
Default
Description
7
ACTTIMER_FAULT
r
0
Status flag of ACTTIMER protection
1: Pre alert of ACTTIMER protection. It is close to the threshold level.
You can get current ACTTIMER value in REG78.
Both of this bit and ACT_TIMER_PROT (REG78) will be set when over
the threshold.
6
ENDDET
r
0
status flag of END detection
1: end position detected (not latch bit)
5
SIF_TIMEOUTERR
r
0
error flag of serial I/F watch dog timer
1: SIF communication was interrupted, expired watch dog timer
4
PWRERR
r
0
error flag of Power
1 : Voltage problem occurred, details in REG79
3
TSDERR
r
0
error flag of any over thermal protections
1: Dispatched thermal protection, details in REG7A
2
OCPERR
r
0
error flag of any over current protection
1: Dispatched OCP, details in REG7Bh
1
TSDFAULT
r
0
warning of TSD of any thermal protection
1 : Detect pre thermal protection details in REG7A
0
FG
r
0
FG signal. Spindle rotation pulse for speed monitor
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
•
•
•
NOTE
Operate every driver channel after 5-V power supplied and stable.
Appropriate capacity of de-coupling capacitor is required enough value of over 10μF
due to reduce influence of PWM switching noise. And the P5V pin needs to connect a
filter of 1μF. It is effective to put bypass capacitor(about 0.1uF) near Power
pin(P5V_1,P5V_2, P5V_SW,P5V_SPM)for PWM switching noise reduction on
power and GND line.
Much current flow to driver circuits, to consider as below matters.
–
Pattern-lay-out and line-impedance. And noise influence from supply line.
9.1 Application Information
9.1.1 DAC Type
TPIC2030 has nine channels of Actuator. Each channel is assigned to the most suitable DAC engine with a
different type respectively. ACT(F/T/Ti) has 12-bit DAC. Upper 8 (MSB sign bit) are converted at a time in 5 MHz
and LSB 4 bits are output in sequence with 1.25-MHz PWM. SPIN, SLED, and Load DAC has same DAC types
and sampling rate with 312 kHz. All channels except SLED have x6 gain. Table 33 shows configuration of each
actuator.
Table 33. DAC Type
Resolution
Type
Sampling
PWM frequency
Out range
Feedback
FCS/TRK/TLT
SLED
SPIN
LOAD
12 bit
10 bit
12 bit
12 bit
8-bit oversampling
10-bit voltage
8-bit oversampling
8-bit oversampling
312K
312K
312 kHz
1.25M / 10bit
312K / 12bit
312 kHz
About 156 kHz(variable)
156 kHz
±6 V
±440 mA
±6 V
±6 V
Power supply
compensation
Voltage feedback
Shared with TRK
Voltage feedback
Current feedback
9.1.2 Example Sampling Rate of 12-Bit DAC for FCS/TRK/TLT
The input data is separated in the upper 8 bits and the lower 4 bits. Upper 8 bits (MSB sign 1 bit) will be put into
8bit current DAC in every 5 MHz. The lower 4bits will be put into one bit current DAC in sequence from upper to
lower bit. This one-bit DAC output with PWM in 1.25 MHz. At any PWM duty, 100%, 75%, 50%, 25%, or 0%, will
be summed in 8-bit current DAC in every 1.25 MHz. Thus, it takes 3.2 µs for all lower 4bits summing to PWM
output. As a result, 12 bit data is sampled in every PWM cycle. Example of sampling rate for FCS/TRK/TLT is
Figure 47.
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White DAC
5 MHz
8
8
8
8
8
8
8
10 bit
1.25 MHz
625 kHz
8
8
8
10 bit
8
8
8
8
8
10 bit
8
8
8
10 bit
11 bit
11 bit
312 kHz
12 bit
LSB 4-bit width
PWM duty
12-bit DAC (8-bit DAC + 4-bit PWM DAC) output
one PWM cycle (312 kHz = 3.2 µs)
Figure 47. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)
9.1.3 Digital Input Coding
The output voltage (current) is commanded via programming to the DAC. All of the DAC input format is 12bit in
2’s complement though some DAC has a low resolution. When 12 bits data is input 8 bits DAC, TPIC2030
recognizes four subordinate position bits (LSB) as 0. To arrange for 12-bit DAC format, DSP should shift 8bit or
10 bit data to an appropriate bit position. The full scale is ±1.0 V and driver gain is set 6. The output voltage
(Vout) is given by the following equation:
Vout
D A C code u
Vdac
9GDF
Vout
1 .0 u
±
6 .0
(1)
2048
b it[1 0 ] u 0 .5
u E LW>
1
@ u
b it[9 ] u 0 .5
1
E LW> @ u
2
b it[8 ] u 0 .5
2
E LW> @ u
3
...
3
b i t[0 ] u 0 .5
.
11
b it[0 ] u 0 .5
11
0 .5
12
V d a c u 6 .0 ( V )
S L E D Io u t
V d a c u 0 .4 4 ( A )
where
•
bit[11:0] is the digital input value, range 000000000000b to 111111111111b.
(2)
Table 34. DAC Format
MSB
44
DIGITAL INPUT (BIN)
LSB
HEX
DEC
VDAC
ANALOG OUTPUT
1000_0000_0000
0x800
–2048
–0.9995
–5.997
1000_0000_0001
0x801
–2047
–0.9995
–5.997
1111_1111_1111
0xFFF
–1
–0.0005
–0.003
0000_0000_0000
0x000
0
0
0.000
0000_0000_0001
0x001
+1
+0.0005
+0.003
0111_1111_1110
0x7FE
+2046
+0.9990
+5.994
0111_1111_1111
0x7FF
+2047
+0.9995
+5.997
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Analog output (V)
VDAC
+ 1.000
+ 6.0
*
+ 5.0
800h
000
DAC code
7FFh
–5.0
*
–6.0
–1.000
* following P5V input voltage
Figure 48. Output Voltage vs DAC Code
9.1.4 Example Timing of Target Control System
TPIC2030 is designed for that meets the requirements updating control data in 400 kHz. The example of control
system parameter is listed in . It takes 0.51 µs for transmit a 16-bit data packet to TPIC2030 with 35 MHz SCLK.
Therefore, DSP can be sent four packets a 400-kHz interval. If SCLK is lower than 28.8 MHz, it is required
reducing packet quantity under three. For example, Focus/Track command is updating in every 2.5 µs (400 kHz),
and it is able to send another two kind of packet in this same slot. shows the example of the control timing when
TPIC2030 is used.
Table 35. Example Timing of Target Control System
SIGNAL
BIT
UPDATE CYCLE (kHz)
Focus
12
400
Track
12
400
Tilt
12
200
Sled1
10
100
Sled2
10
100
Spindle
12
100
Load
12
—
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312 kHz /3.2 µs (PWM one cycle)
Track
R
Focus
R
R
R
R
Tilt
Sled 1
Sled 2
SPM
Load
Control
reg ister
400 kHz /2.5 µs
100 kHz /10 µs (one control cycle)
PWM cycle
DAC command
R
DAC command with status read
0.51 µs (SCLK:35 MHz) for data transmit
Control register command
Figure 49. Example DAC Control
9.1.5 Spindle Motor Driver Part
When VSPM is set to a positive DAC code then the part will be in acceleration mode. IS mode operates then the
start-up circuit offers the special start-up pattern sequence to the driver in start-up, and then switches to spin-up
mode by detecting the rotor position by BEMF signal from the spindle motor coil.
The spin-down and brake function also be controlled by VSPM DAC value. When it is set the brake command to
VSPM, driver goes into active-brake mode, then switch to short-brake mode in slow revolution speed, and then
stop automatically. The FG signal is composed from EXOR of three-phase signal, and is output from XFG pin
shown in Figure 50.
XRESET
WRITE_ENABLE
XSLEEP
SPM_ENA
VSPM
VSPM[11.0] > 0
VSPM[11.0] < 0
0
XFG
brake
> 15 ms
Release
speed
300 ms
130 rpm
time
Figure 50. Spindle Operating Sequence
•
•
•
•
46
It is recommended to use down-edge of FG signal for monitoring FG frequency. The FG terminal needs to be
pull up to the appropriate supply voltage by external resistor.
Short Brake mode is asserted after 300 ms of FG signal stays L-level in deceleration.
The FG output is set to H-level in sleep mode in order to reduce sleep mode current.
This value is the nominal number of using motor with 16-poles.
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First of all, power supply voltage of P5V must be supplied before any signals input.
9.1.5.1 Spindle PWM Control
The output PWM duty of Spindle is controlled by DAC code (VSPM). The gain in acceleration setting is always
six times. However, the maximum output is restricted to P5V_SPM voltage. A dead band which output = 0 exists
in the width of plus or minus 0x52 focusing on zero.
PWM Output Duty
Output (V)
6.0 V
SPM_LSMODE = 0
5.0 V
100%
Dead Band
Duty = 0%
25%
Slow Down
Speed Up
0%
VSPM[11:0]
800h
FAEh
000
7FFh
52h
Figure 51. Spindle PWM Control
9.1.5.2 Auto Short Brake Function
TPIC2030 provides auto short brake function which is selecting brake mode automatically by motor speed.
Auto Short Brake is the intelligent brake function that includes 2 modes, Short Brake and Active Brake.
When VSPM value is controlled more than equivalent 75% duty brake, deceleration is done by short brake under
the rotation speed is over 3000 rpm. After deceleration, driver goes into Active-brake mode automatically by
internal logic circuit under rotation speed is lower 2000 rpm. This function enables low power consumption and
silent during braking.
Table 36. Brake Mode
ROTATION SPEED(
(RPM)
VSPM[11:0]
ABOUT 0 TO 2000
ABOUT 3000
0x000 - 0xFAE
2-phase short Brake
2-phase short Brake
0xFAE - 0xA00
Active Brake
Active Brake
0xA00 - 0x800
Active Brake
3-phase short Brake
rpm
Slow down
4000
2-phase short
3-phase
short
3000
Active
2000
Active
1000
VSPM[11:0]
0
800h
A00h
FAEh
000
Figure 52. Brake Mode Selections
This value is the nominal number of using motor with 16-poles motor.
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9.1.5.3 Spindle Low Speed Mode
LS mode is the low rotation mode which made the maximum 25% duty. When using SPM_LSMODE = 1, brake
mode is always SHORT BRAKE. shows the output duty of LS mode.
PWM Output Duty
Output (V)
SPM_LSMODE = 1
6.0 V
100%
5.0 V
25%
Sp eed up
Duty = 0%
VSPM[11:0]
0%
800h
000
7FFh
Figure 53. Spindle PWM Control (Low Speed Mode)
9.1.5.4 Spindle Driver Current Limit Circuit
This IC builds in the SPM current sense resistor which can select resistor value. .
The spindle current limit circuit monitors motor current which flows through this resistance, and limits the output
current by reducing PWM duty when detecting over current conditions. shows resistor value.
A limit current value can be calculated from following formulas.
Limit current = 196mV / resistor value
Table 37. SPM Current Sense Resistor
SPM_RCOM_SEL[1:0]
RESISTOR VALUE (Ω)
LIMIT CURRENT (mA)
00
0.22
890
01
0.20
980
10
0.27
725
11
0.25
784
9.1.6 Sled Driver Part
9.1.6.1 Sled Channel Input vs Output PWM Duty
The Sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feed back. The maximum output
is restricted to 440mA at 0x7FF and 0x800. A dead band which output = 0 exists in the width of plus or minus
focusing on zero.
48
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Output Current
Reverse
Forward
440 mA
Dead Band
ISLEDxP = ISLEDxN
ISLEDxP< ISLEDxN
ISLEDxP> ISLEDxN
0
FE0h
800h
VSLDx[11:0]
1Fh
7FFh
000
Figure 54. Sled Output Current
•
Both outputs of SLED1/2 are L when input code is in dead band.
9.1.6.2 Sled End Detect Function
This device has the function of end position detection for Sled. By this function aim to eliminate the position
switch at PUH inner. When this function is enabled, internal logic will detect the sled out zero-cross point and at
that time, internal BEMF detect circuit measures the BEMF level of stepping motor. There’re four threshold
levels. If BEMF is lower than selected threshold, device recognizes motor at stop and ENDDET bit to 1. ENDDET
bit will be cleared at the BEMF voltage exceed threshold again.
I-SLED1
I-SLED2
BEM F1
BEM F2
Motor Stop
1
ENDDET
Figure 55. Timing of Sled End Detection
•
•
In order to perform high-precision detection, the sled motor needs to generate higher BEMF voltage. BEMF
level depends on the stepping motor characteristic and its speed.
BEMF detection level is selectable 22, 46, 86 mV.
9.1.7 Load Driver Part
9.1.7.1 Load Channel Input vs Output PWM Duty
Load driver outputs the voltage with voltage feed back corresponding to the input DAC value. This channel has
power voltage compensation thus it is suit for Slot-in type load control. This channel becomes active exclusively
to other actuator channels. Load driver is shared with the TRK driver.
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PWM Output Duty
Output (V)
6.0 V
5.0 V
100%
Dead Band
Duty = 0%
Load+ < Load–
Load+ > Load–
0%
VLOAD[11:0]
800h
FE0h
000
1Fh
7FFh
Figure 56. Load Output Duty
•
•
Output voltage is controlled by PWM
Both LOAD+ and LOAD- are connected to PGND through the internal clamp diode respectively.
9.1.8 Focus/Track/Tilt Driver Part
PW M outp ut duty
100%
P5V
reverse
forw ard
ACT+ < ACT-
ACT+ > ACT-
0%
800h
000
7FFh
ACT(FCS/TRK/TLT)[11:0]
Figure 57. FCS/TRK/TLT Output Duty
9.1.8.1 Differential Tilt Mode
TPIC2030 support differential Tilt mode which output the value calculated from Focus and Tilt. Focus and Tilt can
be set in differential mode by DIFF_TLT (REG74) = 1. Because Focus and Tilt are updated at the same time, the
update interval of Tilt can be thinned out. Output data changes at after writing VFCS data. Therefore it is
necessary to write VFCS data when set VTLT. In differential mode, the output value is calculated as follows.
9.1.9 Step-Down Synchronous DC-DC Converter
TPIC2030 has a synchronous step-down DC-DC converter which can output various voltages. Switching
frequency is 2.5MHz. Because the ripple current in the coil can reduce, the smaller inductor value can be
selected. And the inductor with lowest DC resistance can be selected for highest efficiency. And the regulators
have fast transient response.
50
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Step-down DC-DC converter produces an output 1.0, 1.2, 1.5, and 3.3 V. It only requires an external inductor
and bypass capacitor(s). The gate drivers and compensations are all internal to the chip. The required input
supply is 5 V for P5V_SW. It has a soft start approximately about 0.8 ms to limit the in-rush current when the
regulator comes alive. The soft-start circuit uses the internal clock to profile its ramp.
It’s able to up 2%, 3.8% and 5.4% of the output voltage by setting SWR_VOUTUP (REG6D) for 1.2 V and 1.5 V,
up 1.3%, 2.4%, and 3.3% for 1.0V.
Table 38. Output Voltage Setting
(1)
SWR_VSEL2
SWR_VSEL1
INPUT REGFB
DCDC CONVERTER OUTPUT
0
0
<3.7 V
3.3 V
0
1
<3.7 V
1.2 V
1
0
<3.7 V
1.0 V
1
1
<3.7 V
X
X
over 3.7V
1.5 V
Disable
(1)
It is necessary to maintain REGFB > 3.7 V for 100 µs in DC-DC working.
9.1.9.1 Discontinuous Regulation Mode
Provide a regulation mode named discontinuous regulation mode, which improves the conversion efficiency at a
low current loading by changing regulation timing. Discontinuous mode is able to set 1 to SWR_MD_BURST
(REG6D) bit. Furthermore by setting SWR_BSTAUTON (REG6D), the discontinuous mode is automatically
chosen at the time of low power consumption. shows the discontinuous regulation action. The current
consumption has been reduced by shortening the energizing time of driving FET. On the other hand, DC voltage
ripple grows.
• •
CLK2.5 MHz
SWR_MD_BURST
• •
Discontinuous Mode
REGFB
• •
• •
REGOUT
• •
• •
REGOUT
Output Hi-Z term
• •
• •
REGOUT
Output Hi-Z
Figure 58. Discontinuous Regulation Mode
9.1.9.2 High Efficiency Mode (in Discontinuous Regulation Mode)
The high efficiency mode which raises efficiency further at the time of low consumption can be chosen for 1.0 V,
1.2 V, and 1.5 V. This mode is selected by SWR_BST_HEFF = 1 (REG6D) in discontinuous mode.
9.1.10 Monitor Signal on GPOUT
The device can output a specific signal to the GPOUT pin. To output a signal, choose a signal from REG6F by
enabling first, then enable GPOUT_ENA. When two or more signals are set for GPOUT, the output is a logical
sum.
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9.2 Typical Application
P5V
10 µF
1.x/3.3V
output
10 µF
0.1 µF
TPIC2030
1
PGND_1
LOAD-
44
2
PGND_SW
LOAD+
43
3
REGOUT
SLED2-
42
4
P5V_SW
SLED2+
41
5
REGFB
SLED1-
40
6
SIOV
SLED1+
39
7
SWR_VSEL1
LEDO
38
8
SWR_VSEL2
CSWO
37
SSZ
9
SSZ
MCOM
36
SCLK
10
SCLK
P5V_1
35
2.2 µH
3.3V
LEDO
CSWO
10 µF
0.1 µF
MCOM
W
SIMO
11
SIMO
P5V_SPM
34
SOMI
12
SOMI
W
33
XMUTE
13
XMUTE
U
32
14
XFG
V
31
15
XRESET
GND_SPM
30
16
GPOUT
TRK-
29
17
CP1
TRK+
28
18
CP2
FCS-
27
19
CP3
FCS+
26
20
AGND
TLT-
25
21
CV3P3
TLT+
24
22
P5V_2
PGND_2
23
10 µF
XFG
V
U
XRESET
GPOUT
0.1 µF
0.1 µF
10 µF
0.1 µF
0.1 µF
Figure 59. Example of Application Circuit
Table 39. Pin Connection When Specific Function is
not Applied
FUNCTION
DC-DC
converter
PIN
NUMBER
CONNECTION
SWR_VSEL1
7
GND
SWR_VSEL2
8
GND
P5V_SW
4
P5V
PGND_SW
2
GND
REGOUT
3
Open
REGFB
5
P5V
9.2.1 Design Requirements
To begin the design process, determine the following:
1. Motor configuration: The user can use all motor channels or some of them.
2. Power up devices with a 5-V supply.
9.2.2 Detailed Design Procedure
After power up on 5-V supply, the following values may be written to the following registers to enable motors.
1. Set WRITE_ENABLE = 1 on REG76 via SPI.
2. Set XSLEEP = 1 at REG70
3. Enable motor channel by ENA_XXX bits on REG70
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4. Change the DAC settings for each motor in REG01-0B. Then, output channels will start driving load.
Table 40. Recommended External Components
PIN
TO
VALUE (rate)
UNIT
P5V_1
PGND
Noise decoupling
FUNCTION
10.0 (10%16 V)
µF
P5V_2
PGND
Noise decoupling
10.0 (10%16 V)
µF
P5V_SW
PGND_SW
Noise decoupling
10.0 (10%16 V)
µF
P5V_SPM
PGND
Noise decoupling
10.0 (10%16 V)
µF
SIOV
PGND
Noise decoupling
1.0 (10%10 V)
µF
REGOUT
REGFB
Inductor (ESR = 0.1 Ω) for DC-DC converter
2.2 (20% 1.2 A)
µH
REGFB
PGND_SW
10.0 (10%10 V)
µF
LOAD_P
PGND
Capacitor (ESR = 0.025 Ω)
Prevent surge current
10000 (10% 16 V)
pF
LOAD_N
PGND
Prevent surge current
10000(10% 16 V)
pF
CP1
CP2
Charge pump capacitor
0.1 (10% 16 V)
µF
CP3
P5V
Charge pump capacitor (P5V only, prohibit
other power supply)
0.1 (10% 16 V)
µF
Table 41. Specific for DCDC Converter Components
COMPONENTS
RECOMMENDED VALUE
RECOMMENDED SUPPLIER
PART NUMBER
Inductor
2.2 (µH)
TAIYO YUDEN
BRL2518T2R2M
Capacitor
10 (µF)
MURATA
GRM21BB31A106KE18L
120
120
100
100
80
80
D u ty C y c le ( % )
D u ty C y c le ( % )
9.2.3 Application Curves
60
LOAD
40
LOAD+
20
TRK
40
TRK+
20
0
-3000
60
0
-2000
-1000
0
DAC Code
1000
2000
3000
-3000
Figure 60. DAC Code vs Duty Cycle for LOAD Outputs
-2000
-1000
0
1000
2000
DAC Code
D003
3000
D004
Figure 61. DAC Code vs Duty Cycle for TRK Outputs
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10 Power Supply Recommendations
All driver channels should be operated after the required power is supplied and stable.
The appropriate capacity of the decoupling capacitor requires a value over 10 μF to reduce the influence of PWM
switching noise. The P5V1, P5V2, P5V_SW, and P5V_SPM pins must connect to 10-μF decoupling capacitors.
Current flow to the driver circuits takes both pattern-layout, line-impedance, and noise influence from the supply
line into consideration.
11 Layout
11.1 Layout Guidelines
1. CV3P3V requires an external capacitor. Because these are reference voltage for device, locate the capacitor
as close to device as possible. Keep away from noise sources.
2. TI recommends SCLK ground shielding.
3. Place the inductor for the DC-DC converter as close to the chip as possible, and keep the feedback line to
the REGFB pin as short as possible.
11.2 Layout Example
To 3.3-V supply
10
To MPU
To MPU
GPOUT
To MPU
XFG
XMUTE
GND Shield
To MPU
SSZ
SCLK
GND Shield
SIMO
SOMI
To MPU
SIOV
To MPU
REGOUT
REGFB
To 3.3-V supply
1.x/3.3-V output
Figure 62. Layout Recommendation
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
TPIC2030DBTRG4
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
DBT
44
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-20 to 75
TPIC2030
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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16-Dec-2016
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPIC2030DBTRG4
Package Package Pins
Type Drawing
TSSOP
DBT
44
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
6.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
11.7
1.6
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPIC2030DBTRG4
TSSOP
DBT
44
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBT0044A
TSSOP - 1.2 mm max height
SCALE 1.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6
TYP
6.2
A
C
0.1 C
PIN 1 INDEX
AREA
42X 0.5
44
1
2X
10.5
11.1
10.9
NOTE 3
22
23
44X
B
4.5
4.3
NOTE 4
0.27
0.17
0.08
1.2 MAX
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220223/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
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EXAMPLE BOARD LAYOUT
DBT0044A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
44X (1.5)
(R0.05) TYP
1
44
44X (0.3)
42X (0.5)
SYMM
23
22
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220223/A 02/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBT0044A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
44X (1.5)
SYMM
(R0.05) TYP
1
44
44X (0.3)
42X (0.5)
SYMM
23
22
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
4220223/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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