Texas Instruments | DRV8805 Unipolar Stepper Motor Driver IC (Rev. D) | Datasheet | Texas Instruments DRV8805 Unipolar Stepper Motor Driver IC (Rev. D) Datasheet

Texas Instruments DRV8805 Unipolar Stepper Motor Driver IC (Rev. D) Datasheet
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DRV8805
SLVSAW3D – JULY 2011 – REVISED JANUARY 2016
DRV8805 Unipolar Stepper Motor Driver IC
1 Features
3 Description
•
The DRV8805 provides an integrated solution for
driving unipolar stepper motors. It includes four lowside drivers with overcurrent protection and provides
built-in diodes to clamp turnoff transients generated
by the motor windings.
1
•
•
•
•
•
4-Channel Protected Low-Side Driver
– Four NMOS FETs With Overcurrent Protection
– Integrated Inductive Clamp Diodes
Indexer/Translator for Unipolar Stepper Motors
– Simple Step/Direction Interface
– Three Step Modes (2-Phase Full-Step, 1-2Phase Half-Step, 1-Phase Wave Drive)
DW Package: 1.5-A (Single Channel On) /
800-mA (Four Channels On) Maximum Drive
Current per Channel (at 25°C)
PWP Package: 2-A (Single Channel On) /
1-A (Four Channels On) Maximum Drive Current
per Channel (at 25°C, With Proper PCB
Heatsinking)
8.2-V to 60-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
2 Applications
•
•
Gaming Machines
General Unipolar Stepper Motor Drivers
Indexer logic to control a unipolar stepper motor
using a simple step/direction interface is also
integrated. Three stepping modes are supported: 2
phase (full-step), 1-2 phase (half-step), and 1-phase
(wave drive).
In the SOIC (DW) package, the DRV8805 can supply
up to 1.5-A (one channel on) or 800-mA (all channels
on) continuous output current per channel, at 25°C. In
the HTSSOP (PWP) package, it can supply up to 2-A
(one channel on) or 1-A (four channels on)
continuous output current per channel, at 25°C with
proper PCB heatsinking.
Internal shutdown functions are provided for
overcurrent protection, short-circuit protection, under
voltage lockout, and overtemperature, and faults are
indicated by a fault output pin.
The DRV8805 is available in a 20-pin thermallyenhanced SOIC package and a 16-pin HTSSOP
package (Eco-friendly: RoHS & no Sb/Br).
Device Information(1)
PART NUMBER
DRV8805
PACKAGE
BODY SIZE (NOM)
SOIC (20)
12.80 mm × 7.50 mm
HTSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
8.2V to 60V
5
nFAULT
Fault
Protection
Clamp
Diodes
1A
M
1A
1A
±
RESET
DRV8805
Quad
Low-Side
Driver
+
Controller
STEP/DIR
+
±
1A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8805
SLVSAW3D – JULY 2011 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
9
Power Supply Recommendations...................... 14
9.1 Bulk Capacitance .................................................... 14
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Considerations ........................................ 15
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2012) to Revision D
Page
•
Changed Catch Diodes to Clamp Diodes in Features .......................................................................................................... 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Updated the text in the EXTERNAL COMPONENTS OR CONNECTIONS column for nHOME row .................................. 3
•
Updated PARAMETERS, TEST CONDTIONS, MIN, TYP, and MAX values in the nHOME OUTPUT section in the
Electrical Characteristics table ............................................................................................................................................... 5
2
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5 Pin Configuration and Functions
DW Package
20-Pin Wide SOIC
Top View
VM
VCLAMP
OUT1
OUT2
GND
GND
GND
OUT3
OUT4
nENBL
PWP Package
16-Pin HTSSOP
Top View
1
20
2
19
3
18
4
17
5
6
16
15
7
14
8
13
9
12
10
11
nFAULT
nHOME
STEP
DIR
GND
GND
GND
SM0
SM1
RESET
VM
VCLAMP
OUT1
OUT2
GND
OUT3
OUT4
nENBL
1
16
2
15
3
14
13
4
5
GND
12
6
11
7
10
8
9
nFAULT
nHOME
STEP
DIR
GND
SM0
SM1
RESET
Pin Functions
PIN
NAME
SOIC
HTSSOP
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS
OR CONNECTIONS
POWER AND GROUND
5, 6, 7,
14, 15, 16
5, 12,
PPAD
—
Device ground
All pins must be connected to GND.
1
1
—
Device power supply
Connect to motor supply (8.2 V to 60 V).
DIR
17
13
I
Direction input
Level controls direction of rotation – internal
pulldown
nENBL
10
8
I
Enable input
Active low enables outputs – internal pulldown
RESET
11
9
I
Reset input
Active-high reset input initializes internal
logic – internal pulldown
SM0
13
11
SM1
12
10
I
Step mode
Sets step mode – see step modes section for
details – internal pulldowns
STEP
18
14
I
Step input
Rising edge advances motor to next step –
internal pulldown
nFAULT
20
16
OD
Fault
Logic low when in fault condition (overtemp,
overcurrent)
nHOME
19
15
OD
Home
Logic low when indexer is at home position –
push-pull structure
OUT1
3
3
O
Output 1
Connect to load 1
OUT2
4
4
O
Output 2
Connect to load 2
OUT3
8
6
O
Output 3
Connect to load 3
OUT4
9
7
O
Output 4
Connect to load 4
VCLAMP
2
2
—
Output clamp voltage
Connect to VM supply, or Zener diode to VM
supply
GND
VM
CONTROL
STATUS
OUTPUT
(1)
Directions: I = input, O = output, OD = open-drain output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VM
Power supply voltage
–0.3
65
V
VOUTx
Output voltage
–0.3
65
V
VCLAMP
Clamp voltage
–0.3
65
V
Digital input pin voltage
–0.5
7
V
nHOME,
nFAULT
Digital output pin voltage
–0.5
–0.5 to 7
V
nHOME,
nFAULT
Output current
20
mA
Peak clamp diode current
2
A
DC or RMS clamp diode current
1
A
Peak motor drive output current, t < 1 μS
Internally limited
A
Continuous total power dissipation
See Thermal Information
TJ
Operating virtual junction temperature
–40
150
°C
Tstg
Storage temperature
–60
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VM
Power supply voltage
VCLAMP
Output clamp voltage
IOUT
(1)
(2)
4
(1)
NOM
MAX
UNIT
8.2
60
V
0
60
V
Continuous output current, single channel on, TA = 25°C, SOIC package (2)
1.5
Continuous output current, four channels on, TA = 25°C, SOIC package (2)
0.8
Continuous output current, single channel on, TA = 25°C, HTSSOP package (2)
2
Continuous output current, four channels on, TA = 25°C, HTSSOP package (2)
1
A
VCLAMP is used only to supply the clamp diodes. It is not a power supply input.
Power dissipation and thermal limits must be observed.
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6.4 Thermal Information
DRV8805
THERMAL METRIC (1)
DW (SOIC)
PWP (HTSSOP)
20 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
67.7
39.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.9
24.6
°C/W
RθJB
Junction-to-board thermal resistance
35.4
20.3
°C/W
ψJT
Junction-to-top characterization parameter
8.2
0.7
°C/W
ψJB
Junction-to-board characterization parameter
34.9
20.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.6
2.1
mA
8.2
V
0.7
V
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V
VUVLO
VM undervoltage lockout voltage
VM rising
LOGIC-LEVEL INPUTS(SCHMITT TRIGGER INPUTS WITH HYSTERESIS)
VIL
Input low voltage
VIH
Input high voltage
0.6
VHYS
Input hysteresis
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Pulldown resistance
2
V
0.45
–20
V
20
μA
100
μA
100
kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
0.5
V
1
μA
IO = 5 mA
0.5
V
IO = 100 µA, VM = 11 V – 60 V, peak
6.5
nHOME OUTPUT (OPEN-DRAIN OUTPUT WITH WEAK INTERNAL PULLUP)
VOL
VOH
Output low voltage
Output high voltage
IO = 100 μA, VM = 11 V – 60 V, steady state
3.3
IO = 100 μA, VM = 8.2 V – 11 V, steady state
2.5
4.5
5.6
V
ISRC
Output source current
VM = 24 V
1
mA
ISNK
Output sink current
VM = 24 V
5
mA
LOW-SIDE FETS
RDS(ON)
FET on resistance
IOFF
Off-state leakage current
VM = 24 V, IO = 700 mA, TJ = 25°C
0.5
VM = 24 V, IO = 700 mA, TJ = 85°C
0.75
0.8
Ω
50
μA
–50
50
μA
–50
HIGH-SIDE DIODES
VF
Diode forward voltage
VM = 24 V, IO = 700 mA, TJ = 25°C
IOFF
Off-state leakage current
VM = 24 V, TJ = 25°C
1.2
V
OUTPUTS
tR
Rise time
VM = 24 V, IO = 700 mA, Resistive load
50
300
ns
tF
Fall time
VM = 24 V, IO = 700 mA, Resistive load
50
300
ns
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Electrical Characteristics (continued)
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tOCP
Overcurrent protection deglitch time
tRETRY
Overcurrent protection retry time
tTSD
Thermal shutdown temperature
(1)
2.3
3.8
3.5
1.2
Die temperature (1)
A
µs
ms
150
160
180
°C
MIN
NOM
MAX
UNIT
250
kHz
Not production tested.
6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted) (1)
1
fSTEP
Step frequency
2
tWH(STEP)
Pulse duration, STEP high
1.9
µs
3
tWL(STEP)
Pulse duration, STEP low
1.9
µs
4
tSU(STEP)
Setup time, DIR, SMx to STEP rising
1
µs
5
tH(STEP)
Hold time, DIR, SMx to STEP rising
1
6
tOE(ENABLE)
Enable time, nENBL to output low
7
tPD(L-H)
8
tPD(H-L)
—
tRESET
RESET pulse width
(1)
µs
50
ns
Propagation delay time, STEP to OUTx, low to high
500
ns
Propagation delay time, STEP to OUTx, high to low
500
20
ns
µs
Not production tested.
nENBL
1
2
3
STEP
STEP
DIR, SMx
OUTx
4
5
7
6
8
Figure 1. DRV8805 Timing Requirements
6
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1.80
1.80
1.75
1.75
1.70
1.70
Supply Current (mA)
Supply Current (mA)
6.7 Typical Characteristics
1.65
1.60
1.55
1.50
1.45
1.40
-40° C
1.35
1.60
1.55
1.50
1.45
1.40
25° C
75° C
1.30
1.65
1.35
125° C
8V
24 V
30 V
60 V
1.30
8V
24 V
30 V
60 V
Supply Voltage (V)
-40° C
Figure 2. Supply Current Over VM
1000
900
25° C
75° C
125° C
Temperature (ƒC)
C002
C001
Figure 3. Supply Current Over Temperature
-40° C
25° C
75° C
125° C
900
800
Rdson (mŸ)
Rdson (mŸ)
800
700
600
500
700
600
500
400
400
300
8V
60 V
300
200
8V
60 V
Supply Voltage (V)
-40° C
C006
Figure 4. RDS(ON) Over VM
25° C
75° C
125° C
Temperature (ƒC)
C005
Figure 5. RDS(ON) Over Temperature
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7 Detailed Description
7.1 Overview
The DRV8805 is an integrated 4-channel unipolar stepper motor driver with a step / direction interface that
controls the low-side driver outputs and allows for simple control schemes. The four low-side driver outputs
consist of four N-channel MOSFETs that have a typical RDS(on) of 500 mΩ. A single motor supply input VM
serves as device power and is internally regulated to power the low-side gate drive. The device outputs can be
disabled by bringing the nENBL pin logic high. This device has several safety features including integrated
overcurrent protection that limits the motor current to a fixed maximum above which the device will shut down.
Thermal shutdown protection enables the device to automatically shut down if the die temperature exceeds a
TTSD limit and will restart once the die reaches a safe temperature. UVLO protection will disable all circuitry in
the device if VM drops below the undervoltage lockout threshold.
7.2 Functional Block Diagram
8.2 V-60 V
8.2 V-60 V
Internal
Reference
Regs
UVLO
VM
Optional
Zener
Int. VCC
LS Gate
Drive
VCLAMP
OCP
and
Gate
Driver
OUT1
OCP
and
Gate
Driver
OUT2
OCP
and
Gate
Driver
OUT3
OCP
and
Gate
Driver
OUT4
nENBL
STEP
Winding 1
DIR
SM0
SM1
Winding 2
Control
Logic
RESET
nFAULT
Winding 3
nHOME
Thermal
Shutdown
Winding 4
Unipolar
Stepper
GND
(Multiple Pins)
8
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7.3 Feature Description
7.3.1 Output Drivers
The DRV8805 contains four protected low-side drivers. Each output has an integrated clamp diode connected to
a common pin, VCLAMP.
VCLAMP can be connected to the main power supply voltage, VM. It can also be connected to a Zener or TVS
diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be beneficial
when driving loads that require very fast current decay, such as unipolar stepper motors.
In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification.
7.3.2 Indexer Operation
The DRV8805 integrates an indexer to allow motor control with a simple step-and-direction interface. Logically,
the indexer is shown in Figure 6.
nENBL
RESET
OUT1
RESET
CLK
STEP
OUT2
DIR
DIR
Counter
Lookup
Table
(Translator)
OUT3
nHOME
SM0
OUT4
SM1
Figure 6. Indexer Operation
7.3.3 nENBL and RESET Operation
The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does
not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown.
The RESET pin, when driven active high, resets the internal logic. The indexer is reset to the home state. All
inputs are ignored while RESET is active. Note that RESET has an internal pulldown. An internal power-up reset
is also provided, so it is not required to drive RESET at power up.
7.3.4 Protection Circuits
The DRV8805 is fully protected against undervoltage, overcurrent and overtemperature events.
7.3.4.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the tOCP deglitch time (approximately 3.5 µs), the driver will be
disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time
(approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either
RESET pin is activated or VM is removed and re-applied.
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Feature Description (continued)
7.3.4.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.
The STEP input will be ignored. Once the die temperature has fallen to a safe level, operation will automatically
resume.
7.3.4.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
7.4 Device Functional Modes
7.4.1 Step Modes
The SM0 and SM1 pins select the stepping mode of the translator as shown in Table 1.
Table 1. Step Modes
SM1
SM0
MODE
0
0
2-phase drive (full step)
0
1
1-2 phase drive (half step)
1
0
1-phase excitation (wave drive)
1
1
Reserved
In all modes, during a fault condition, the STEP input will be ignored. See Protection Circuits for more
information.
The sequence of the outputs is shown in Table 2, Table 3, and Table 4.
Table 2. 2-Phase Excitation (Full-Step)
10
Function
Step
RESET
DIR
STEP
nHOME
OUT1
OUT2
OUT3
Reset
1
1
X
X
0
ON
OFF
OFF
OUT4
ON
CW
2
0
1
↑
1
ON
ON
OFF
OFF
CW
3
0
1
↑
1
OFF
ON
ON
OFF
CW
4
0
1
↑
1
OFF
OFF
ON
ON
CW to home
1
0
1
↑
0
ON
OFF
OFF
ON
CCW
4
0
0
↑
1
OFF
OFF
ON
ON
CCW
3
0
0
↑
1
OFF
ON
ON
OFF
OFF
CCW
2
0
0
↑
1
ON
ON
OFF
CCW to home
1
0
0
↑
0
ON
OFF
OFF
ON
Hold
X
0
X
↑
no chg
no chg
no chg
no chg
no chg
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Table 3. 1-2-Phase Excitation (Half-Step)
Function
Step
RESET
DIR
STEP
nHOME
OUT1
OUT2
OUT3
OUT4
Reset
1
1
X
X
0
ON
OFF
OFF
OFF
CW
2
0
1
↑
1
ON
ON
OFF
OFF
CW
3
0
1
↑
1
OFF
ON
OFF
OFF
CW
4
0
1
↑
1
OFF
ON
ON
OFF
CW
5
0
1
↑
1
OFF
OFF
ON
OFF
CW
6
0
1
↑
1
OFF
OFF
ON
ON
CW
7
0
1
↑
1
OFF
OFF
OFF
ON
CW
8
0
1
↑
1
ON
OFF
OFF
ON
CW to home
1
0
1
↑
0
ON
OFF
OFF
OFF
CCW
8
0
0
↑
1
ON
OFF
OFF
ON
CCW
7
0
0
↑
1
OFF
OFF
OFF
ON
CCW
6
0
0
↑
1
OFF
OFF
ON
ON
CCW
5
0
0
↑
1
OFF
OFF
ON
OFF
CCW
4
0
0
↑
1
OFF
ON
ON
OFF
CCW
3
0
0
↑
1
OFF
ON
OFF
OFF
CCW
2
0
0
↑
1
ON
ON
OFF
OFF
CCW to home
1
0
0
↑
0
ON
OFF
OFF
OFF
Hold
X
0
X
↑
no chg
no chg
no chg
no chg
no chg
Table 4. 1-Phase Excitation (Wave Drive)
Function
Step
RESET
DIR
STEP
nHOME
OUT1
OUT2
OUT3
OUT4
Reset
1
1
X
X
0
ON
OFF
OFF
OFF
CW
2
0
1
↑
1
OFF
ON
OFF
OFF
CW
3
0
1
↑
1
OFF
OFF
ON
OFF
CW
4
0
1
↑
1
OFF
OFF
OFF
ON
CW to home
1
0
1
↑
0
ON
OFF
OFF
OFF
CCW
4
0
0
↑
1
OFF
OFF
OFF
ON
CCW
3
0
0
↑
1
OFF
OFF
ON
OFF
CCW
2
0
0
↑
1
OFF
ON
OFF
OFF
CCW to home
1
0
0
↑
0
ON
OFF
OFF
OFF
Hold
X
0
X
↑
no chg
no chg
no chg
no chg
no chg
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8805 can be used to drive one unipolar stepper motor.
8.2 Typical Application
+
0.1µF
100µF
1
±
2
+
M
3
4
5
+
±
6
7
8
9
10
VM
nFAULT
VCLAMP
nHOME
OUT1
STEP
OUT2
DIR
GND
GND
GND
DRV8805
GND
GND
GND
OUT3
SM0
OUT4
SM1
nENBL
RESET
20
19
18
17
16
15
14
13
12
11
Figure 7. Typical Application Schematic
8.2.1 Design Requirements
Table 5 lists the design parameters for this design example.
Table 5. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Supply Voltage
VM
24 V
Motor Winding Resistance
RL
7.4 Ω/phase
Motor Full Step Angle
θstep
1.8°/step
Motor Rated Current
IRATED
0.75 A
PWM frequency
fPWM
31.25 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The motor voltage to use will depend on the ratings of the motor selected and the desired torque. A higher
voltage shortens the current rise time in the coils of the stepper motor allowing the motor to produce a greater
average torque. Using a higher voltage also allows the motor to operate at a faster speed than a lower voltage.
12
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8.2.2.2 Drive Current
The current path is starts from the supply VM, moves through the inductive winding load, and low-side sinking
NMOS power FET. Power dissipation losses in one sink NMOS power FET are shown in the following equation.
P = I2 × RDS(on)
(1)
The DRV8805 has been measured to be capable of 1.5-A Single Channel or 800-mA Four Channels with the
DW package and 2-A Single Channel or 1-A Four Channels with the PWP package at 25°C on standard FR-4
PCBs. The maximum RMS current will vary based on PCB design and the ambient temperature.
8.2.3 Application Curves
Figure 8. Current Ramp With a 16-Ω, 1-mH,
RL Load and VM = 8.2 V
Figure 9. Current Ramp With a 16-Ω,
1-mH RL Load and VM = 30 V
Figure 10. OCP With 8.2 V and
OUT1 Shorted to VM
Figure 11. OCP Separated by tRETRY With VM = 8.2 V and
OUT1 Shorted to VM
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9 Power Supply Recommendations
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The power supply’s capacitance and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (Brushed DC, Brushless DC, Stepper)
• The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Power Supply
Motor Drive System
VM
+
+
Motor
Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 12. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
14
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10 Layout
10.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
• Small-value capacitors should be ceramic, and placed closely to device pins.
• The high-current device outputs should use wide metal traces.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
I2 × RDS(on) heat that is generated in the device.
10.2 Layout Example
+
VM
nFAULT
VCLAMP
nHOME
OUT1
STEP
OUT2
DIR
GND
GND
OUT3
SM0
OUT4
SM1
nENBL
RESET
Figure 13. Example Layout Drawing
10.3 Thermal Considerations
The DRV8805 has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die temperature
exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
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Thermal Considerations (continued)
10.3.1 Power Dissipation
Power dissipation in the DRV8805 is dominated by the power dissipated in the output FET resistance, or RDS(ON).
Average power dissipation of each FET when running a static load can be roughly estimated by Equation 2.
P = RDS(ON) · (IOUT)2
where
•
•
•
P is the power dissipation of one FET
RDS(ON) is the resistance of each FET
IOUT is equal to the average current drawn by the load
(2)
Note that at start-up and fault conditions this current is much higher than normal running current; these peak
currents and their duration also must be taken into consideration. When driving more than one load
simultaneously, the power in all active output stages must be summed.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
10.3.2 Heatsinking
The DRV8805DW package uses a standard SOIC outline, but has the center pins internally fused to the die pad
to more efficiently remove heat from the device. The two center leads on each side of the package should be
connected together to as large a copper area on the PCB as is possible to remove heat from the device. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
In general, the more copper area that can be provided, the more power can be dissipated.
The DRV8805PWP package uses an HTSSOP package with an exposed PowerPAD™. The PowerPAD™
package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally
connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be
accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without
internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on
the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom
layers.
For details about how to design the PCB, see TI Application Report, PowerPAD™ Thermally Enhanced Package
(SLMA002), and TI Application Brief, PowerPAD Made Easy (SLMA004), available at www.ti.com.
16
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SLVSAW3D – JULY 2011 – REVISED JANUARY 2016
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package, SLMA002.
• PowerPAD Made Easy, SLMA004.
11.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV8805DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8805DW
DRV8805DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8805DW
DRV8805PWP
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8805
DRV8805PWPR
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8805
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DRV8805DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
DRV8805PWPR
HTSSOP
PWP
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8805DWR
SOIC
DW
20
2000
367.0
367.0
45.0
DRV8805PWPR
HTSSOP
PWP
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016J
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
A
SEATING
PLANE
0.1 C
PIN 1 INDEX
AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
4.5
4.3
16X
(0.15) TYP
SEE DETAIL A
9
8
0.25
GAGE PLANE
3.55
2.68
0 -8
16
1
2.46
1.75
1.2 MAX
0.15
0.05
0.75
0.50
DETAIL A
A 20
TYPICAL
THERMAL
PAD
4223595/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016J
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 8
METAL COVERED
BY SOLDER MASK
(2.46)
16X (1.5)
16X (0.45)
SEE DETAILS
SYMM
1
16
(1.3) TYP
(R0.05) TYP
(0.65)
SYMM
(3.55)
(5)
NOTE 8
14X (0.65)
( 0.2) TYP
VIA
8
9
(1.35) TYP
SOLDER MASK
DEFINED PAD
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4223595/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016J
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.46)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
16X (0.45)
METAL COVERED
BY SOLDER MASK
1
16
(R0.05) TYP
(3.55)
BASED ON
0.125 THICK
STENCIL
SYMM
14X (0.65)
9
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.75 X 3.97
2.46 X 3.55 (SHOWN)
2.25 X 3.24
2.08 X 3.00
4223595/A 03/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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