Texas Instruments | DRV8802-Q1 Automotive DC Motor-Driver IC (Rev. A) | Datasheet | Texas Instruments DRV8802-Q1 Automotive DC Motor-Driver IC (Rev. A) Datasheet

Texas Instruments DRV8802-Q1 Automotive DC Motor-Driver IC (Rev. A) Datasheet
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DRV8802-Q1
SLVSCI2A – JUNE 2014 – REVISED JUNE 2014
DRV8802-Q1 Automotive DC Motor-Driver IC
1 Features
3 Description
•
•
The DRV8802-Q1 device provides an integrated
motor driver solution for automotive applications. The
device has two H-bridge drivers, and is intended to
drive DC motors. The output driver block for each
consists of N-channel power MOSFET’s configured
as H-bridges to drive the motor windings. The
DRV8802-Q1 device can supply up to 1.6-A peak or
1.1-A RMS output current (with proper heatsinking at
24 V and 25°C) per H-bridge.
1
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Dual H-Bridge Current-Control Motor Driver
– Drives Two DC Motors
– Brake Mode
– Two-Bit Winding Current Control Allows Up to
4 Current Levels
– Low MOSFET On-Resistance
1.6-A Maximum Drive Current at 24 V, 25°C
Built-In 3.3-V Reference Output
Industry Standard Parallel Digital Control
Interface
8-V to 45-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
A simple parallel digital control interface is compatible
with industry-standard devices. Decay mode is
programmable to allow braking or coasting of the
motor when disabled.
Internal shutdown functions are provided for over
current protection, short circuit protection, under
voltage lockout and overtemperature.
The DRV8802-Q1 device is available in a 28-pin
HTSSOP package with PowerPAD™ (Eco-friendly:
RoHS & no Sb/Br).
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2 Applications
DRV8802-Q1
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Automotive HVAC
Automotive Valves
Automotive Infotainment
HTSSOP (28)
9.70 mm × 4.40 mm
Simplified Application Diagram
8 to 45 V
Controller
Decay mode
Dual
H-Bridge
Motor Driver
1.6 A
t +
nSLEEP
DRV8802-Q1
+
xPHASE
xENBL
1.6 A
xVREF
nFAULT
t
nRESET
ISENA
ISENB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8802-Q1
SLVSCI2A – JUNE 2014 – REVISED JUNE 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9
Power Supply Recommendations...................... 15
9.1 Bulk Capacitance .................................................... 15
9.2 Power Supply and Logic Sequencing ..................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 16
10.3 Thermal Information .............................................. 16
11 Device and Documentation Support ................. 18
11.1 Trademarks ........................................................... 18
11.2 Electrostatic Discharge Caution ............................ 18
11.3 Glossary ................................................................ 18
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
2
DATE
REVISION
NOTES
June 2014
A
Initial release.
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5 Pin Configuration and Functions
28-Pin HTSSOP With PowerPAD
PWP Package
Top View
CP1
CP2
VCP
VMA
AOUT1
ISENA
AOUT2
BOUT2
ISENB
BOUT1
VMB
AVREF
BVREF
GND
1
2
28
27
3
26
4
25
5
6
24
23
7
PowerPAD
8
22
21
9
20
10
19
11
18
12
17
13
14
16
15
GND
BI1
BI0
AI1
AI0
BPHASE
BENBL
AENBL
APHASE
DECAY
nFAULT
nSLEEP
nRESET
V3P3OUT
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
EXTERNAL COMPONENTS
OR CONNECTIONS
POWER AND GROUND
CP1
1
IO
Charge pump flying capacitor
CP2
2
IO
Charge pump flying capacitor
—
Device ground
15
O
3.3-V regulator output
VMA
4
—
Bridge A power supply
VMB
11
—
Bridge B power supply
VCP
3
IO
High-side gate drive voltage
Connect a 0.1-μF 16-V ceramic capacitor and
a 1-MΩ resistor to VMx.
AI0
24
I
AI1
25
I
Bridge A current set
Sets bridge A current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
AENBL
21
I
Bridge A enable
Logic high to enable bridge A
APHASE
20
I
Bridge A phase (direction)
Logic high sets AOUT1 high, AOUT2 low
AVREF
12
I
Bridge A current set reference input
BVREF
13
I
Bridge B current set reference input
Reference voltage for winding current set.
Can be driven individually with an external
DAC for microstepping, or tied to a reference
(for example, V3P3OUT).
BI0
26
I
BI1
27
I
BENBL
22
BPHASE
23
DECAY
GND
V3P3OUT
14
28
Connect a 0.01-μF 50-V capacitor between
CP1 and CP2.
Bypass to GND with a 0.47-μF 6.3-V ceramic
capacitor. Can be used to supply VREF.
Connect to motor supply (8 to 45 V). Both
pins must be connected to same supply.
CONTROL
Bridge B current set
Sets bridge B current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
I
Bridge B enable
Logic high to enable bridge B
I
Bridge B phase (direction)
Logic high sets BOUT1 high, BOUT2 low
19
I
Decay (brake) mode
Low = brake (slow decay),
high = coast (fast decay)
nRESET
16
I
Reset input
Active-low reset input initializes internal logic
and disables the H-bridge outputs
nSLEEP
17
I
Sleep mode input
Logic high to enable device, logic low to enter
low-power sleep mode
(1)
I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
EXTERNAL COMPONENTS
OR CONNECTIONS
STATUS
nFAULT
Logic low when in fault condition
(overtemperature, overcurrent)
18
OD
Fault
AOUT1
5
O
Bridge A output 1
AOUT2
7
O
Bridge A output 2
BOUT1
10
O
Bridge B output 1
BOUT2
8
O
Bridge B output 2
ISENA
6
IO
Bridge A ground and current sense
Connect to current sense resistor for bridge A
ISENB
9
IO
Bridge B ground and current sense
Connect to current sense resistor for bridge B
OUTPUT
4
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Connect to motor winding A
Connect to motor winding B
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Power supply voltage
V(VMx)
–0.3
47
V
Charge pump voltage
VCP, CP1, CP2
–0.3
V(VMx)+7
V
Digital pin voltage
xPHASE, xENBL, nSLEEP, nFAULT, nRESET, xI0, xI1,
DECAY
–0.5
7
V
Reference input voltage
V(xVREF)
–0.3
4
V
Sense pin voltage
V(ISENx)
–0.3
0.8
V
H-bridge output Current
xOUT1, xOUT2,
ISENx
Peak motor drive, t < 1 μS
Continuous motor drive
Internally limited
(3)
A
1.6
Continuous total power dissipation
A
See the Power Dissipation section
Operating virtual junction temperature, TJ
–40
150
°C
Operating ambient temperature, TA
–40
125
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed.
6.2 Handling Ratings
Tstg
MIN
MAX
UNIT
–60
150
°C
–2000
2000
Corner pins (1, 14, 15,
and 28)
–750
750
Other pins
–500
500
Storage temperature range
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
(1)
V(VMx)
Power supply voltage
V(xVREF)
VREF input voltage (2)
I(OUT1x,
H-Bridge Output Current
MAX
UNIT
8.2
45
V
1
3.5
V
1.6
A
OUT2x)
IL(V3P3OUT)
(1)
(2)
V3P3OUT load current
1
mA
All VMx pins must be connected to the same supply voltage.
Operational at V(xVREF) between 0 V and 1 V, but accuracy is degraded.
6.4 Thermal Information
THERMAL METRIC (1)
PWP
28 PINS
RθJA
Junction-to-ambient thermal resistance
38.9
RθJC(top)
Junction-to-case (top) thermal resistance
23.3
RθJB
Junction-to-board thermal resistance
21.2
ψJT
Junction-to-top characterization parameter
0.8
ψJB
Junction-to-board characterization parameter
20.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.6
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temp range of -40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
I(VMx)
VMx operating supply current
V(VMx) = 24 V, ƒ(PWM) < 50 kHz
5
8
mA
I(VMx_Q)
VMx sleep mode supply current
V(VMx) = 24 V
10
20
μA
V(UVLO)
VMx undervoltage lockout
voltage
V(VMx) rising
7.8
8.2
V
3.3
3.5
V
0.7
V
V3P3OUT REGULATOR
V(V3P3OUT)
V3P3OUT voltage
IO = 0 to 1 mA
3.1
LOGIC-LEVEL INPUTS
VIL
Input low voltage
VIH
Input high voltage
Vhys
Input hysteresis
IIL
Input low current
VI = 0
20
μA
IIH
Input high current
VI = 3.3 V
100
μA
0.5
V
1
μA
0.8
V
±40
µA
Ω
2.1
V
0.45
–20
V
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
DECAY INPUT
VIL
Input low threshold voltage
For slow decay mode
0
VIH
Input high threshold voltage
For fast decay mode
2
II
Input current
V
H-BRIDGE FETS
rDS(on)
HS FET on resistance
rDS(on)
LS FET on resistance
Ilkg(OFF)
VM = 24 V, I O = 1 A, TJ = 25°C
0.63
VM = 24 V, IO = 1 A, TJ = 85°C
0.76
0.9
VM = 24 V, IO = 1 A, TJ = 125°C
0.85
1
VM = 24 V, IO = 1 A, TJ = 25°C
0.65
VM = 24 V, IO = 1 A, TJ = 85°C
0.78
0.9
VM = 24 V, IO = 1 A, TJ = 125°C
0.85
1
Off-state leakage current
–20
20
Ω
μA
MOTOR DRIVER
ƒ(PWM)
Internal PWM frequency
t(blank)
Current-sense blanking time
50
kHz
tr
Rise time
VM = 24 V
100
360
ns
tf
Fall time
VM = 24 V
80
250
ns
t(dead)
Dead time
μs
3.75
400
ns
PROTECTION CIRCUITS
I(OCP)
Overcurrent protection trip level
T(SD)
Thermal shutdown temperature
1.8
Die temperature
150
5
A
160
180
°C
3
μA
CURRENT CONTROL
I(xVREF)
xVREF input current
V(TRIP)
xISENSE trip voltage
G(ISENx)
Current sense amplifier gain
6
V(xVREF) = 3.3 V
–3
V(xVREF) = 3.3 V, 100% current setting
635
660
685
V(xVREF) = 3.3 V, 71% current setting
445
469
492
V(xVREF) = 3.3 V, 38% current setting
225
251
276
Reference only
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5
mV
V/V
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6.6 Typical Characteristics
14
Sleep-Mode Supply Current (A)
7.0
Supply Current (mA)
6.5
6.0
5.5
5.0
25ƒC
4.5
85ƒC
125ƒC
4.0
10
15
20
25
30
35
40
Supply Current (V)
13
12
11
10
9
-40ƒC
8
25ƒC
85ƒC
7
125ƒC
6
10
45
15
-40ƒC
85ƒC
30
35
40
45
C002
Figure 2. I(VMx_Q) vs V(VMx)
2000
25ƒC
125ƒC
10 V
24 V
1800
RDS(ON) HS + LS (mŸ)
1800
RDS(ON) HS + LS (mŸ)
25
Supply Votage (V)
Figure 1. I(VMx) vs V(VMx)
2000
20
C001
1600
1400
1200
1000
45 V
1600
1400
1200
1000
800
800
10
15
20
25
30
35
Supply Voltage (V)
40
45
±50
C003
Figure 3. rDS(on) vs V(VMx)
±25
0
25
50
75
100
Ambient Temperature (ƒC)
125
C004
Figure 4. rDS(on) vs Temperature
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7 Detailed Description
7.1 Overview
The DRV8802-Q1 device provides an integrated motor driver solution for automotive applications. The device
has two H-bridge drivers, and is intended to drive DC motors. The output driver block for each consists of Nchannel power MOSFET’s configured as H-bridges to drive the motor windings. The DRV8802-Q1 device can
supply up to 1.6-A peak or 1.1-A RMS output current (with proper heatsinking at 24 V and 25°C) per H-bridge. A
simple parallel digital control interface is compatible with industry-standard devices. Decay mode is
programmable to allow braking or coasting of the motor when disabled. Internal shutdown functions are provided
for over current protection, short circuit protection, under voltage lockout and overtemperature.
7.2 Functional Block Diagram
VM
VM
Internal
Reference &
Regs
3.3 V
CP1
Int. VCC
LS Gate
Drive
V3P3OUT
0.01 mF
CP2
VM
Charge
Pump
VCP
3.3 V
0.1 mF
Thermal
Shut down
HS Gate
Drive
1 MW
VM
AVREF
VMA
BVREF
AOUT1
Motor
Driver A
APHASE
AENBL
DCM
AOUT2
AI0
ISENA
AI1
BPHASE
BENBL
BI0
Control
Logic
VM
VMB
BI1
BOUT1
DECAY
Motor
Driver B
nRESET
DCM
BOUT2
nSLEEP
ISENB
nFAULT
GND
8
GND
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7.3 Feature Description
7.3.1 PWM Motor Drivers
The DRV8802-Q1 device contains two H-bridge motor drivers with current-control PWM circuitry. Figure 5 shows
a block diagram of the motor control circuitry.
VM
OCP
VM
VCP, VGD
AOUT1
Predrive
AENBL
DCM
APHASE
AOUT 2
DECAY
PWM
OCP
AISEN
+
AI0, AI1
A=5
DAC
2
AVREF
VM
OCP
VM
VCP, VGD
BOUT 1
Predrive
BENBL
DCM
BPHASE
BOUT 2
PWM
OCP
BISEN
+
BI0, BI1
A =5
DAC
2
BVREF
Figure 5. Motor Control Circuitry
Note that there are multiple VM pins (VMx). All VMx pins must be connected together to the motor supply
voltage.
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Feature Description (continued)
7.3.2 Bridge Control
The xPHASE input pins control the direction of current flow through each H-bridge, and therefore control the
direction of rotation of a DC motor. The xENBL input pins enable the H-bridge outputs when active high, and can
also be used for PWM speed control of the motor. Table 1 lists the H-bridge logic.
Table 1. H-Bridge Logic
(1)
xENBL
xPHASE
0
X
xOUT1
see
1
1
H
L
1
0
L
H
(1)
xOUT2
see
(1)
Depends on state of the DECAY pin. See the Decay Mode and
Braking section.
7.3.3 Current Regulation
The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current
chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage
and inductance of the winding. When the current hits the current chopping threshold, the bridge disables the
current until the beginning of the next PWM cycle.
For stepping motors, current regulation is normally used at all times, and can change the current that is used to
microstep the motor. For DC motors, current regulation is used to limit the start-up and stall current of the motor.
The PWM chopping current is set by a comparator that compares the voltage across a current sense resistor
connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the xVREF pins, and is scaled by a 2-bit DAC that allows current settings of 38%, 71%, and 100% of fullscale, plus zero.
Use Equation 1 to calculate the full-scale (100%) chopping current.
V(xVREF)
I(CHOP) =
5 ´ R(ISENx)
(1)
For example:
If a 0.5-Ω sense resistor is used and the voltage on the xVREF pin is 3.3 V, the full-scale (100%) chopping
current is 3.3 V / (5 × 0.5 Ω) = 1.32 A.
Two input pins per H-bridge (xI1 and xI0) are used to scale the current in each bridge as a percentage of the fullscale current set by the xVREF input pin and sense resistance. Table 2 lists the function of the pins.
Table 2. H-Bridge Pin Functions
xI1
xI0
RELATIVE CURRENT
(% FULL-SCALE CHOPPING CURRENT)
1
1
0% (Bridge disabled)
1
0
38%
0
1
71%
0
0
100%
Note that when both xI bits are 1, the H-bridge is disabled and no current flows.
For example:
If a 0.5-Ω sense resistor is used and the voltage on the xVREF pin is 3.3 V, the chopping current is 1.32 A at
the 100% setting (xI1, xI0 = 00). At the 71% setting (xI1, xI0 = 01) the current is 1.32 A × 0.71 = 0.937 A. At
the 38% setting (xI1, xI0 = 10) the current is 1.32 A × 0.38 = 0.502 A. If (xI1, xI0 = 11) the bridge is disabled
and no current will flow.
10
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7.3.4 Decay Mode and Braking
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. See case 1 in Figure 6. The current-flow direction shown indicates the
state when the xENBL pin is high.
When the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, when the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. See case 2 in Figure 6 for fast decay mode.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. See
case 3 in Figure 6.
VM
1 Drive
1
xOUTA
xOUTB
3
2
Fast decay with synchronous rectification
3 Low-side slow decay with synchronous rectification
2
xISEN
R(SENx)
Figure 6. Decay Mode
The DRV8802-Q1 device supports fast decay and slow decay mode. Slow or fast decay mode is selected by the
state of the DECAY pin. A logic low selects slow decay, and logic high sets fast decay mode. Note that the
DECAY pin sets the decay mode for both H-bridges.
The DECAY mode also affects the operation of the bridge when it is disabled (by taking the ENBL pin inactive).
This effect applies if the ENABLE input is being used for PWM speed control of the motor, or if it is simply being
used to start and stop motor rotation.
If the DECAY pin is high (fast decay), when the bridge is disabled, all FETs are turned off and decay current
flows through the body diodes, allowing the motor to coast to a stop.
If the DECAY pin is low (slow decay), both low-side FETs are turned on when the xENBL pin is made inactive.
When the xENBL pin is made inactive, the inactivation essentially shorts out the back EMF of the motor, causing
the motor to brake, and stop quickly. The low-side FETs stays in the ON state even after the current reaches
zero.
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7.3.5 Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.
7.3.6 nRESET and nSLEEP Operation
The nRESET pin, when driven active low, resets the internal logic. This pin also disables the H-bridge drivers. All
inputs are ignored while nRESET is active.
Driving nSLEEP low puts the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) must pass before the motor driver becomes fully operational.
7.3.7 Protection Circuits
The DRV8802-Q1 device is fully protected against undervoltage, overcurrent, and overtemperature events.
FAULT
ERROR REPORT
H-BRIDGE
CHARGE PUMP
RECOVERY
V(VMx) undervoltage
(UVLO)
No error report – nFAULT
is hi-Z
Disabled
Shut Down
V(VMx) > VUVLO RISING
Overcurrent (OCP)
nFAULT pulled low
Disabled
Operating
Retry time, t(OCP)
Overtemperature
Shutdown (OTS)
nFAULT remains pulled
low (set during OTW)
Disabled
Shut Down
TJ < T(OTS) – Thys(OTS)
7.3.7.1 Overcurrent Protection (OCP)
An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current-limit persists for longer than the OCP time, all FETs in the H-bridge are disabled and the nFAULT
pin is driven low. The device remains disabled until either nRESET pin is applied, or V(VMx) is removed and reapplied.
Overcurrent conditions on both high-side and low-side devices (such as a short to ground, supply, or across the
motor winding) result in an overcurrent shutdown. Note that overcurrent protection does not use the current
sense circuitry used for PWM current control and is independent of the R(ISENx) resistor value or xVREF voltage.
7.3.7.2 Thermal Shutdown (TSD)
If the die temperature exceeds the thermal shutdown temperature limit, all FETs in the H-bridge are disabled and
the nFAULT pin is driven low. When the die temperature has fallen below the temperature hsyteresis level,
operation resumes automatically.
7.3.7.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VMx pins falls below the undervoltage lockout threshold voltage, all circuitry in
the device is disabled and internal logic resets. Operation resumes when VM rises above the UVLO threshold.
7.4 Device Functional Modes
The DRV8802-Q1 device is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is
disabled, the V3P3OUT regulator is disabled, and the H-bridge FETs are disabled hi-Z. The DRV8802-Q1 is
brought out of sleep mode when nSLEEP is brought logic high.
12
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8 Application and Implementation
8.1 Application Information
The DRV8802-Q1 device is used in medium voltage brushed-DC motor control applications.
8.2 Typical Application
CP1
0.01 µF
1M
0.1 µF
+
0.01 µF
DRV8802-Q1
GND
CP2
BI1
VCP
BI0
VMA
AI1
AOUT1
AI0
400 m
ISENA
±
VM
BPHASE
AOUT2
BENBL
BOUT2
AENBL
±
+
100 µF
400 m
V3P3OUT
ISENB
+
APHASE
BOUT1
DECAY
VMB
nFAULT
AVREF
nSLEEP
BVREF
nRESET
V3P3OUT
0.1 µF
10 k
30 k
GND
PPAD
10 k
V3P3OUT
V3P3OUT
0.47 µF
Figure 7. Typical Application Diagram
8.2.1 Design Requirements
The example supply for this design is V(VMx) = 18 V.
8.2.2 Detailed Design Procedure
8.2.2.1 Drive Current
The current path is through the high-side sourcing DMOS driver, motor winding, and low-side sinking DMOS
power driver. Power dissipation I2R losses in one source and sink DMOS driver are shown in Equation 2.
PD = I 2 (rDS(on)Source + rDS(on)Sink )
(2)
8.2.2.2 Slow-Decay SR (Brake Mode)
In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the low side
of the H-bridge (two sink drivers) and the load. Power dissipation I2R loses in the two sink DMOS drivers as
shown in Equation 3.
PD = I 2 (2 ´ rDS(on)Sink )
(3)
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Typical Application (continued)
8.2.3 Application Curves
OUTA
OUTA
OUTB
OUTB
IO
IO
Figure 8. 75% Drive, 25% Slow Decay; ƒ(PWM) = 5 kHz
14
Figure 9. 75% Drive, 25% Fast Decay; ƒ(PWM) = 5 kHz
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9 Power Supply Recommendations
The DRV8802-Q1 is designed to operate from an input voltage supply V(VMx) range between 8.2 and 45 V. Two
0.1-µF ceramic capacitors rated for V(VMx) must be placed as close as possible to the VMA and VMB pins
respectively (one on each pin). In addition to the local decoupling caps, additional bulk capacitance is required
and must be sized accordingly to the application requirements.
9.1 Bulk Capacitance
Bulk capacitance sizing is an important factor in motor drive system design. It is dependent on a variety of factors
including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (Brushed DC, Brushless DC, Stepper)
• Motor startup current
• Motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. You should size the bulk capacitance to meet acceptable
voltage ripple levels. The datasheet generally provides a recommended value but system level testing is required
to determine the appropriate sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
±
+
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10. Example Setup of Motor Drive System WIth External Power Supply
9.2 Power Supply and Logic Sequencing
No specific sequence exists for powering-up the DRV8802-Q1 device. Digital input signals can be present before
V(VMx) is applied. After V(VMx) is applied to the DRV8802-Q1 device, it begins operation based on the status of the
control pins.
10 Layout
10.1 Layout Guidelines
The VMA and VMB pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a
recommended value of 0.1-μF rated for VM. This capacitor should be placed as close to the VMA and VMB pins
as possible with a thick trace or ground plane connection to the device GND pin. The VMA and VMB pins must
be bypassed to ground using an appropriate bulk capacitor. This component may be an electrolytic and should
be located close to the DRV8802-Q1. A low-ESR ceramic capacitor must be placed in between the CPL and
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Layout Guidelines (continued)
CPH pins. TI recommends a value of 0.01-μF rated for VM. Place this component as close to the pins as
possible. A low-ESR ceramic capacitor must be placed in between the VMA and VCP pins. TI recommends a
value of 0.1-μF rated for 16 V. Place this component as close to the pins as possible. Also, place a 1-MΩ resistor
between VCP and VMA. Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypass
capacitor as close to the pin as possible.
10.2 Layout Example
0.1 µF
CP1
GND
CP2
BI1
VCP
BI0
VMA
AI1
AOUT1
AI0
ISENA
BPHASE
AOUT2
BENBL
BOUT2
AENBL
ISENB
APHASE
BOUT1
DECAY
VMB
nFAULT
AVREF
nSLEEP
BVREF
nRESET
GND
V3P3OUT
0.01 µF
1 MŸ
0.1 µF
R(ISENA)
R(ISENB)
+
0.1 µF
0.47 µF
Figure 11. DRV8802-Q1 Layout Example
10.3 Thermal Information
10.3.1 Thermal Protection
The DRV8802-Q1 device has thermal shutdown (TSD) as described in the Thermal Shutdown (TSD) section. If
the die temperature exceeds approximately 150°C, the device is disabled until the temperature drops below the
hysteresis level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
16
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Thermal Information (continued)
10.3.2 Power Dissipation
Power dissipation in the DRV8802-Q1 device is dominated by the power dissipated in the output FET resistance,
or rDS(on). Use Equation 4 to calculate the estimated average power dissipation of each H-bridge when running a
DC motor.
PD = 2 ´ rDS(on) ´ IO2
where
•
•
•
PD is the power dissipation of one H-bridge
rDS(on) is the resistance of each FET
IO is the RMS output current being applied to each winding
(4)
IO is equal to the average current drawn by the DC motor. Note that at startup and fault conditions this current is
much higher than normal running current; these peak currents and the current duration must also be considered.
The factor of 2 exists because at any instant two FETs are conducting winding current (one high-side and one
low-side).
The total device dissipation is the power dissipated in each of the two H-bridges added together.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
NOTE
rDS(on) increases with temperature, so as the device heats, the power dissipation
increases. This fact must be taken into consideration when sizing the heatsink.
10.3.3 Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this connection can be accomplished by adding a number of vias to connect the thermal pad to the ground plane.
On PCBs without internal planes, a copper area can be added on either side of the PCB to dissipate heat. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
For details about how to design the PCB, refer to the TI application report, PowerPAD™ Thermally Enhanced
Package (SLMA002), "" and the TI application brief, PowerPAD Made Easy™ (SLMA004), available at
www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
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11 Device and Documentation Support
11.1 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Jul-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
DRV8802QPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
28
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
DRV8802Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2014
OTHER QUALIFIED VERSIONS OF DRV8802-Q1 :
• Catalog: DRV8802
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8802QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8802QPWPRQ1
HTSSOP
PWP
28
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 28
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
4.4 x 9.7, 0.65 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/A
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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