Texas Instruments | Three Phase PWM Motor Driver, DRV8332-HT (Rev. B) | Datasheet | Texas Instruments Three Phase PWM Motor Driver, DRV8332-HT (Rev. B) Datasheet

Texas Instruments Three Phase PWM Motor Driver, DRV8332-HT (Rev. B) Datasheet
DRV8332-HT
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SLES274B – AUGUST 2013 – REVISED JANUARY 2014
THREE PHASE PWM MOTOR DRIVER
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FEATURES
1
•
•
•
•
•
•
•
•
•
•
High-Efficiency Power Stage (up to 97%) with
Low RDS(on) MOSFETs (80 mΩ at TJ = 25°C)
Operating Supply Voltage up to 50 V
(70 V Absolute Maximum)
Up to 5 A Continuous Phase Current
(7 A Peak)
Independent Control of Three Phases
PWM Operating Frequency up to 500 kHz
Integrated Self-Protection Circuits Including
Undervoltage, Overtemperature, Overload, and
Short Circuit
Programmable Cycle-by-Cycle Current Limit
Protection
Independent Supply and Ground Pins for Each
Half Bridge
Intelligent Gate Drive and Cross Conduction
Prevention
No External Snubber or Schottky Diode is
Required
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
•
•
•
•
•
•
•
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Extreme (–55°C to 175°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures. All devices are characterized
and qualified for 1000 hours continuous
operating life at maximum rated temperature.
Simplified Application Diagram
PVDD
GVDD
APPLICATIONS
•
•
•
•
•
GVDD_B
BLDC Motors
Three Phase Permanent Magnet Synchronous
Motors
Inverters
Half Bridge Drivers
Robotic Control Systems
OTW
FAULT
GVDD_A
BST_A
PVDD_A
PWM_A
OUT_A
RESET_A
GND_A
PWM_B
GND_B
OC_ADJ
OUT_B
M
Controller
GND
AGND
NC
M3
NC
M2
GND
PWM_C
GND
GND_C
RESET_C
OUT_C
RESET_B
PVDD_C
VDD
GVDD_C
(1)
BST_B
VREG
M1
GVDD
PVDD_B
BST_C
GVDD_C
Custom temperature ranges available
DESCRIPTION
The DRV8332 is a high performance, integrated three phase motor driver with an advanced protection system.
Because of the low RDS(on) of the power MOSFETs and intelligent gate drive design, the efficiency of this motor
driver can be up to 97%, which enables the use of smaller power supplies and heatsinks, and is a good
candidate for energy efficient applications.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013–2014, Texas Instruments Incorporated
DRV8332-HT
SLES274B – AUGUST 2013 – REVISED JANUARY 2014
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DESCRIPTION (CONTINUED)
The DRV8332 requires two power supplies, one at 12 V for GVDD and VDD, and another up to 50 V for PVDD.
The DRV8332 can operate at up to 500-kHz switching frequency while still maintain precise control and high
efficiency. It also has an innovative protection system safeguarding the device against a wide range of fault
conditions that could damage the system. These safeguards are short-circuit protection, overcurrent protection
and undervoltage protection. The DRV8332 has a current-limiting circuit that prevents device shutdown during
load transients such as motor start-up. A programmable overcurrent detector allows adjustable current limit and
protection level to meet different motor requirements.
The DRV8332 has unique independent supply and ground pins for each half bridge, which makes it possible to
provide current measurement through external shunt resistor and support half bridge drivers with different power
supply voltage requirements.
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–55°C to 175°C
DDV
DRV8332HDDV
DRV8332H
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted
(1)
VALUE
VDD to GND
–0.3 V to 13.2 V
GVDD_X to GND
–0.3 V to 13.2 V
PVDD_X to GND_X
(2)
–0.3 V to 70 V
OUT_X to GND_X
(2)
–0.3 V to 70 V
BST_X to GND_X
(2)
–0.3 V to 80 V
Maximum bootstrap in rush current, IBST_In
0.4 A
Transient peak output current (per pin), pulse width limited by internal over-current protection circuit.
16 A
Transient peak output current for latch shut down (per pin)
20 A
VREG to AGND
–0.3 V to 4.2 V
GND_X to GND
–0.3 V to 0.3 V
GND to AGND
–0.3 V to 0.3 V
PWM_X, RESET_X to GND
–0.3 V to 4.2 V
OC_ADJ, M1, M2, M3 to AGND
–0.3 V to 4.2 V
FAULT, OTW to GND
–0.3 V to 7 V
Maximum continuous sink current (FAULT, OTW)
9 mA
Maximum operating junction temperature range, TJ
-55°C to 185°C
Storage temperature, TSTG
–55°C to 175°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
PVDD_X
Half bridge X (A, B, or C) DC supply voltage
0
50
52.5
V
GVDD_X
Supply for logic regulators and gate-drive circuitry
10.8
12
13.2
V
VDD
Digital regulator supply voltage
10.8
12
13.2
V
IO_PULSE
Pulsed peak current per output pin (could be limited by thermal)
7
A
IO
Continuous current per output pin (DRV8332)
FSW
PWM switching frequency
ROCP_CBC
OC programming resistor range in cycle-by-cycle current limit modes
30
CBST
Bootstrap capacitor range
33
TON_MIN
Minimum PWM pulse duration, low side
TJ
Operating junction temperature
5
kHz
200
kΩ
220
nF
175
°C
50
-55
ns
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THERMAL INFORMATION
DRV8332-HT
THERMAL METRIC (1)
DDV
UNITS
44 PINS
Junction-to-ambient thermal resistance (2)
θJA
42.6
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
17.4
ψJT
Junction-to-top characterization parameter (5)
0.5
ψJB
Junction-to-board characterization parameter (6)
17.4
θJCbot
Junction-to-case (bottom) thermal resistance (7)
N/A
(1)
(2)
(3)
(4)
(5)
(6)
(7)
0.2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
MODE SELECTION PINS
MODE PINS
4
M3
M2
M1
OUTPUT
CONFIGURATION
1
0
0
1 3PH or 3 HB
Three-phase or three half bridges with cycle-by-cycle current limit
1
0
1
1 3PH or 3 HB
Three-phase or three half bridges with OC latching shutdown (no cycle-bycycle current limit)
0
x
x
Reserved
1
1
x
Reserved
DESCRIPTION
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DEVICE INFORMATION
Pin Assignment
DDV PACKAGE
(TOP VIEW)
GVDD_B
1
44
OTW
NC
NC
FAULT
PWM_A
RESET_A
2
43
3
42
4
41
PWM_B
OC_ADJ
GND
AGND
VREG
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
M3
M2
M1
RESET_B
RESET_C
13
32
14
31
15
30
16
29
17
28
PWM_C
NC
NC
18
27
VDD
GVDD_C
19
26
20
25
21
24
22
23
GVDD_A
BST_A
NC
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
NC
NC
GND
GND
GND_C
OUT_C
PVDD_C
PVDD_C
NC
BST_C
GVDD_C
Pin Functions
(1)
FUNCTION
(1)
NAME
PIN
AGND
11
P
Analog ground
DESCRIPTION
BST_A
43
P
High side bootstrap supply (BST), external capacitor to OUT_A required
BST_B
34
P
High side bootstrap supply (BST), external capacitor to OUT_B required
BST_C
24
P
High side bootstrap supply (BST), external capacitor to OUT_C required
GND
10, 30, 31
P
Ground
GND_A
38
P
Power ground for half-bridge A
GND_B
37
P
Power ground for half-bridge B
GND_C
29
P
Power ground for half-bridge C
GVDD_A
44
P
Gate-drive voltage supply
GVDD_B
2
P
Gate-drive voltage supply
GVDD_C
22, 23
P
Gate-drive voltage supply
M1
15
I
Mode selection pin
M2
14
I
Reserved mode selection pin, AGND connection is recommended
M3
13
I
Reserved mode selection pin, VREG connection is recommended
NC
3,4,19,20,25,32, 33, 42
-
No connection pin. Ground connection is recommended
OC_ADJ
9
O
Analog overcurrent programming pin, requires resistor to AGND
OTW
2
O
Overtemperature warning signal, open-drain, active-low. An internal pull-up resistor to
VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be obtained by
adding external pull-up resistor to 5 V
OUT_A
39
O
Output, half-bridge A
OUT_B
36
O
Output, half-bridge B
OUT_C
28
O
Output, half-bridge C
PVDD_A
40, 41
P
Power supply input for half-bridge A requires close decoupling capacitor to ground.
PVDD_B
35
P
Power supply input for half-bridge B requires close decoupling capacitor to gound.
PVDD_C
26, 27
P
Power supply input for half-bridge C requires close decoupling capacitor to ground.
PWM_A
6
I
Input signal for half-bridge A
I = input, O = output, P = power, T = thermal
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FUNCTION
(1)
NAME
PIN
PWM_B
8
I
Input signal for half-bridge B
DESCRIPTION
PWM_C
18
I
Input signal for half-bridge C
RESET_A
7
I
Reset signal for half-bridge A, active-low
RESET_B
16
I
Reset signal for half-bridge B, active-low
RESET_C
17
I
Reset signal for half-bridge C, active-low
FAULT
5
O
Fault signal, open-drain, active-low. An internal pull-up resistor to VREG (3.3 V) is
provided on output. Level compliance for 5-V logic can be obtained by adding external
pull-up resistor to 5 V
VDD
21
P
Power supply for digital voltage regulator requires capacitor to ground for decoupling.
VREG
12
P
Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
SYSTEM BLOCK DIAGRAM
VDD
4
Undervoltage
Protection
OTW
Internal Pullup
Resistors to VREG
FAULT
M1
Protection
and
I/O Logic
M2
M3
4
VREG
VREG
Power
On
Reset
AGND
Temp.
Sense
GND
RESET_A
Overload
Protection
RESET_B
Isense
OC_ADJ
RESET_C
GVDD_C
BST_C
PVDD_C
PWM_C
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_C
GND_C
GVDD_B
BST_B
PVDD_B
PWM_B
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_B
GND_B
GVDD_A
BST_A
PVDD_A
PWM_A
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_A
GND_A
6
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ELECTRICAL CHARACTERISTICS
TJ = -55°C to 175°C, PVDD = 50 V, GVDD = VDD = 12 V, fSw = 380 kHz, unless otherwise noted. All performance is in
accordance with recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.85
3.3
3.75
9
15
mA
2.5
mA
1
mA
Internal Voltage Regulator and Current Consumption
VREG
Voltage regulator, only used as a reference node
IVDD
VDD = 12 V
Idle, reset mode
VDD supply current
Operating, 50% duty cycle
V
10.5
Reset mode
1.7
IGVDD_X
Gate supply current per half-bridge
IPVDD_X
Half-bridge X (A, B, or C) idle current
Reset mode
0.7
MOSFET drain-to-source resistance, low side (LS)
TJ = 25°C, GVDD = 12 V
260
mΩ
MOSFET drain-to-source resistance, high side (HS)
TJ = 25°C, GVDD = 12 V
260
mΩ
VF
Diode forward voltage drop
TJ = 25°C - 125°C, IO = 5 A
tR
Output rise time
tF
tPD_ON
Operating, 50% duty cycle
8
Output Stage
RDS(on)
1
V
Resistive load, IO = 5 A
14
ns
Output fall time
Resistive load, IO = 5 A
14
ns
Propagation delay when FET is on
Resistive load, IO = 5 A
38
ns
tPD_OFF
Propagation delay when FET is off
Resistive load, IO = 5 A
38
ns
tDT
Dead time between HS and LS FETs
Resistive load, IO = 5 A
5.5
ns
8.5
V
I/O Protection
Gate supply voltage GVDD_X undervoltage
protection threshold
Vuvp,G
Vuvp,hyst
(1)
IOC
IOCT
Hysteresis for gate supply undervoltage event
0.3
V
Overcurrent limit protection
Resistor—programmable, nominal, ROCP = 36 kΩ
7.4
A
Overcurrent response time
Time from application of short condition to Hi-Z of
affected FET(s)
250
ns
Static Digital Specifications
VIH
High-level input voltage
PWM_A, PWM_B, PWM_C, M1, M2, M3
2
3.6
V
VIH
High-level input voltage
RESET_A, RESET_B, RESET_C
2
3.6
V
VIL
Low-level input voltage
PWM_A, PWM_B, PWM_C, M1, M2, M3,
RESET_A, RESET_B, RESET_C
0.8
V
llkg
Input leakage current
100
μA
kΩ
-100
OTW / FAULT
RINT_PU
Internal pullup resistance, OTW to VREG, FAULT to
VREG
VOH
High-level output voltage
Internal pullup resistor only
VOL
Low-level output voltage
IO = 4 mA
(1)
20
26
35
1.95
3.3
3.65
V
0.2
0.4
V
Specified by design
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Estimated Life (Hours)
100000.00
10000.00
1000.00
120
130
140
150
160
170
180
190
Operating Junction Temperature (°C)
(1)
See datasheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
Figure 1. Electromigration Fail Mode Derating Chart
8
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TYPICAL CHARACTERISTICS
EFFICIENCY
vs
SWITCHING FREQUENCY (DRV8332)
NORMALIZED RDS(on)
vs
GATE DRIVE
1.10
100
TJ = 25°C
Normalized RDS(on) / (RDS(on) at 12 V)
90
80
Efficiency – %
70
60
50
40
30
Full Bridge
20
Load = 5 A
PVDD = 50 V
TC = 75°C
10
0
0
50
1.08
1.06
1.04
1.02
1.00
0.98
0.96
8.0
100 150 200 250 300 350 400 450 500
8.5
9.0
f – Switching Frequency – kHz
Figure 2.
NORMALIZED RDS(on)
vs
JUNCTION TEMPERATURE
10.0
10.5
11.0
11.5
12
DRAIN TO SOURCE DIODE FORWARD
ON CHARACTERISTICS
6
1.020
GVDD = 12 V
TJ = 25°C
1.015
5
1.010
4
I – Current – A
Normalized RDS(on) / RDS(on) at 25ƒC)
9.5
GVDD – Gate Drive – V
Figure 3.
1.005
1.000
3
2
0.995
1
0.990
0
0.985
±55 ±30
–1
±5 20 45 70 95 120 145 170
TJ ± Junction Temperature ± ƒC
0
0.2
0.4
0.6
0.8
1
1.2
V – Voltage – V
C001
Figure 4.
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT DUTY CYCLE
vs
INPUT DUTY CYCLE
100
fS = 500 kHz
TC = 25°C
90
Output Duty Cycle – %
80
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
100
Input Duty Cycle – %
Figure 6.
10
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the DRV8332 needs only
a 12-V supply in addition to H-Bridge power supply
(PVDD). An internal voltage regulator provides
suitable voltage levels for the digital and low-voltage
analog circuitry. Additionally, the high-side gate drive
requiring a floating voltage supply, which is
accommodated by built-in bootstrap circuitry requiring
external bootstrap capacitor.
To provide symmetrical electrical characteristics, the
PWM signal path, including gate drive and output
stage, is designed as identical, independent halfbridges. For this reason, each half-bridge has a
separate gate drive supply (GVDD_X), a bootstrap
pin (BST_X), and a power-stage supply pin
(PVDD_X). Furthermore, an additional pin (VDD) is
provided as supply for all common circuits. Special
attention should be paid to place all decoupling
capacitors as close to their associated pins as
possible. In general, inductance between the power
supply pins and decoupling capacitors must be
avoided. Furthermore, decoupling capacitors need a
short ground path back to the device.
For a properly functioning bootstrap circuit, a small
ceramic capacitor (an X5R or better) must be
connected from each bootstrap pin (BST_X) to the
power-stage output pin (OUT_X). When the powerstage output is low, the bootstrap capacitor is
charged through an internal diode connected
between the gate-drive power-supply pin (GVDD_X)
and the bootstrap pin. When the power-stage output
is high, the bootstrap capacitor potential is shifted
above the output potential and thus provides a
suitable voltage supply for the high-side gate driver.
In an application with PWM switching frequencies in
the range from 10 kHz to 500 kHz, the use of 100-nF
ceramic capacitors (X5R or better), size 0603 or
0805, is recommended for the bootstrap supply.
These 100-nF capacitors ensure sufficient energy
storage, even during minimal PWM duty cycles, to
keep the high-side power stage FET fully turned on
during the remaining part of the PWM cycle. In an
application running at a switching frequency lower
than 10 kHz, the bootstrap capacitor might need to be
increased in value.
Special attention should be paid to the power-stage
power supply; this includes component selection, and
routing. As indicated, each half-bridge has
independent power-stage supply pin (PVDD_X). For
optimal electrical performance, EMI compliance, and
system reliability, it is important that each PVDD_X
pin is decoupled with a ceramic capacitor (X5R or
better) placed as close as possible to each supply
pin.
The 12-V supply should be from a low-noise, lowoutput-impedance voltage regulator. Likewise, the 50V power-stage supply is assumed to have low output
impedance and low noise. The power-supply
sequence is not critical as facilitated by the internal
power-on-reset circuit. Moreover, the DRV8332 are
fully protected against erroneous power-stage turn-on
due to parasitic gate charging. Thus, voltage-supply
ramp rates (dv/dt) are non-critical within the specified
voltage range (see the Recommended Operating
Conditions section of this data sheet).
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
The DRV8332 does not require a power-up
sequence. The outputs of the H-bridges remain in a
high impedance state until the gate-drive supply
voltage GVDD_X and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, holding
RESET_A, RESET_B, and RESET_C in a low state
while powering up the device is recommended. This
allows an internal circuit to charge the external
bootstrap capacitors by enabling a weak pulldown of
the half-bridge output.
Powering Down
The DRV8332 does not require a power-down
sequence. The device remains fully operational as
long as the gate-drive supply (GVDD_X) voltage and
VDD voltage are above the UVP voltage threshold
(see the Electrical Characteristics section of this data
sheet). Although not specifically required, it is a good
practice to hold RESET_A, RESET_B and RESET_C
low during power down to prevent any unknown state
during this transition.
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ERROR REPORTING
Bootstrap Capacitor Under Voltage Protection
The FAULT and OTW pins are both active-low, opendrain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control
device.
When the device runs at a low switching frequency
(e.g. less than 10 kHz with a 100-nF bootstrap
capacitor), the bootstrap capacitor voltage might not
be able to maintain a proper voltage level for the
high-side gate driver. A bootstrap capacitor
undervoltage protection circuit (BST_UVP) will
prevent potential failure of the high-side MOSFET.
When the voltage on the bootstrap capacitors is less
than the required value for safe operation, the
DRV8332 will initiate bootstrap capacitor recharge
sequences (turn off high side FET for a short period)
until the bootstrap capacitors are properly charged for
safe operation. This function may also be activated
when PWM duty cycle is too high (e.g. less than 20
ns off time at 10 kHz). Note that bootstrap capacitor
might not be able to be charged if no load or
extremely light load is presented at output during
BST_UVP operation, so it is recommended to turn on
the low side FET for at least 50 ns for each PWM
cycle to avoid BST_UVP operation if possible.
Any fault resulting in device shutdown, such as
overtemperatue shut down, overcurrent shut-down, or
undervoltage protection, is signaled by the FAULT pin
going low. Likewise, OTW goes low when the device
junction temperature exceeds 125°C (see Table 1).
Table 1. Protection Mode Signal Descriptions
FAULT
OTW
DESCRIPTION
0
0
Overtemperature warning and
(overtemperature shut down or overcurrent
shut down or undervoltage protection) occurred
0
1
Overcurrent shut-down or GVDD undervoltage
protection occurred
1
0
Overtemperature warning
1
1
Device under normal operation
TI recommends monitoring the OTW signal using the
system microcontroller and responding to an OTW
signal by reducing the load current to prevent further
heating of the device resulting in device
overtemperature shutdown (OTSD).
To reduce external component count, an internal
pullup resistor to internal VREG (3.3 V) is provided on
both FAULT and OTW outputs. Level compliance for
5-V logic can be obtained by adding external pull-up
resistors to 5 V (see the Electrical Characteristics
section of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The DRV8332 contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from
permanent failure due to a wide range of fault
conditions such as short circuits, overcurrent,
overtemperature, and undervoltage. The DRV8332
responds to a fault by immediately setting the half
bridge outputs in a high-impedance (Hi-Z) state and
asserting the FAULT pin low. In situations other than
overcurrent
or
overtemperature,
the
device
automatically recovers when the fault condition has
been removed or the gate supply voltage has
increased. For highest possible reliability, reset the
device externally no sooner than 1 second after the
shutdown when recovering from an overcurrent shut
down (OCSD) or OTSD fault.
12
For all applications, it is recommended to add 26-Ω
resistor between the GVDD power supply and
GVDD_X pins to limit the inrush current on the
internal bootstrap diodes.
Overcurrent (OC) Protection
The DRV8332 has independent, fast-reacting current
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. There are two settings for OC protection
through mode selection pins: cycle-by-cycle (CBC)
current limiting mode and OC latching (OCL) shut
down mode.
In CBC current limiting mode, the detector outputs
are monitored by two protection systems. The first
protection system controls the power stage in order to
prevent the output current from further increasing,
i.e., it performs a CBC current-limiting function rather
than prematurely shutting down the device. This
feature could effectively limit the inrush current during
motor start-up or transient without damaging the
device. During short to power and short to ground
conditions, the current limit circuitry might not be able
to control the current to a proper level, a second
protection system triggers a latching shutdown,
resulting in the related half bridge being set in the
high-impedance (Hi-Z) state. Current limiting and
overcurrent protection are independent for halfbridges A, B, and C, respectively.
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Figure 7 illustrates cycle-by-cycle operation with high
side OC event and Figure 8 shows cycle-by-cycle
operation with low side OC. Dashed lines are the
operation waveforms when no CBC event is triggered
and solide lines show the waveforms when CBC
event is triggered. In CBC current limiting mode,
when low side FET OC is detected, the device will
turn off the affected low side FET and keep the high
side FET at the same half bridge off until next PWM
cycle; when high side FET OC is detected, the device
will turn off the affected high side FET and turn on the
low side FET at the half bridge until next PWM cycle.
It is important to note that if the input to a half bridge
is held to a constant value when an over current
event occurs in CBC, then the associated half bridge
will be in a HI-Z state upon the over current event
ending. Cycling IN_X will allow OUT_X to resume
normal operation.
In OC latching shut down mode, the CBC current limit
and error recovery circuits are disabled and an
overcurrent condition will cause the device to
shutdown immediately. After shutdown, RESET_A,
RESET_B, and RESET_C must be asserted to
restore normal operation after the overcurrent
condition is removed.
For added flexibility, the OC threshold is
programmable using a single external resistor
connected between the OC_ADJ pin and AGND pin.
See Table 2 for information on the correlation
between programming-resistor value and the OC
threshold.
The values in Table 2 show typical OC thresholds for
a given resistor. Assuming a fixed resistance on the
OC_ADJ pin across multiple devices, a 20% deviceto-device variation in OC threshold measurements is
possible. Therefore, this system is designed for
system protection and not for precise current control.
Table 2. Programming-Resistor Values and OC
Threshold
OC-ADJUST RESISTOR
VALUES (kΩ)
MAXIMUM CURRENT BEFORE
OC OCCURS (A)
30
8.8
36
7.4
39
6.9
43
6.3
47
5.8
56
4.9
68
4.1
Table 2. Programming-Resistor Values and OC
Threshold (continued)
OC-ADJUST RESISTOR
VALUES (kΩ)
MAXIMUM CURRENT BEFORE
OC OCCURS (A)
82
3.4
100
2.8
120
2.4
150
1.9
200
1.4
It should be noted that a properly functioning
overcurrent detector assumes the presence of a
proper inductor or power ferrite bead at the powerstage output. Short-circuit protection is not
guaranteed with direct short at the output pins of the
power stage.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the DRV8332 fully
protect the device in any power-up / down and
brownout situation. While powering up, the POR
circuit resets the overcurrent circuit and ensures that
all circuits are fully operational when the GVDD_X
and VDD supply voltages reach 9.8 V (typical).
Although GVDD_X and VDD are independently
monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all
half-bridge outputs immediately being set in the highimpedance (Hi-Z) state and FAULT being asserted
low. The device automatically resumes operation
when all supply voltage on the bootstrap capacitors
have increased above the UVP threshold.
DEVICE RESET
Three reset pins are provided for independent control
of half-bridges A, B, and C. When RESET_X is
asserted low, two power-stage FETs in half-bridges X
are forced into a high-impedance (Hi-Z) state.
A rising-edge transition on reset input allows the
device to resume operation after a shut-down fault.
That is, when half-bridge X has OC shutdown in CBC
mode, a low to high transition of RESET_X pin will
clear the fault and FAULT pin. When an OTSD
occurs or OC shutdown in Latching mode occurs, all
three RESET_A, RESET_B, and RESET_C need to
have a low to high transition to clear the fault and
reset FAULT signal.
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DIFFERENT OPERATIONAL MODES
The DRV8332 supports two different modes of
operation:
1. Three-phase (3PH) or three half bridges (HB)
with CBC current limit
2. Three-phase or three half bridges with OC
latching shutdown (no CBC current limit)
Because each half bridge has independent supply
and ground pins, a shunt sensing resistor can be
inserted between PVDD to PVDD_X or GND_X to
GND (ground plane). A high side shunt resistor
between PVDD and PVDD_X is recommended for
differential current sensing because a high bias
voltage on the low side sensing could affect device
operation. If low side sensing has to be used, a shunt
resistor value of 10 mΩ or less or sense voltage 100
mV or less is recommended.
and Figure 9 show the three-phase application
examples, and Figure 10 shows how to connect to
DRV8332 with some simple logic to accommodate
conventional 6 PWM inputs control.
We recommend using complementary control
scheme for switching phases to prevent circulated
energy flowing inside the phases and to make current
limiting feature active all the time. Complementary
control scheme also forces the current flowing
through sense resistors all the time to have a better
current sensing and control of the system.
Figure 11 shows six steps trapezoidal scheme with
hall sensor control and Figure 12 shows six steps
trapezoidal scheme with sensorless control. The hall
sensor sequence in real application might be different
than the one we showed in Figure 11 depending on
the motor used. Please check motor manufacture
datasheet for the right sequence in applications. In
six step trapezoidal complementary control scheme, a
half bridge with larger than 50% duty cycle will have a
positive current and a half bridge with less than 50%
duty cycle will have a negative current. For normal
operation, changing PWM duty cycle from 50% to
100% will adjust the current from 0 to maximum value
with six steps control. It is recommanded to apply a
minimum 50 ns to 100 ns PWM pulse at each
switching cycle at lower side to properly charge the
bootstrap cap. The impact of minimum pulse at low
side FET is pretty small, e.g., the maximum duty
cycle is 99.9% with 100ns minimum pulse on low
side. RESET_Xpin can be used to get channel X into
high impedance mode. If you prefer PWM switching
one channel but hold low side FET of the other
channel on (and third channel in Hi-Z) for 2-quadrant
mode, OT latching shutdown mode is recommended
to prevent the channel with low side FET on stuck in
Hi-Z during OC event in CBC mode.
The DRV8332 can also be used for sinusoidal
waveform control and field oriented control. Please
check TI website MCU motor control library for
control algorithms.
CBC with High Side OC
During T_OC Period
PVDD
Current Limit
Load
Current
PWM_HS
Load
PWM_LS
PWM_HS
PWM_LS
GND_X
T_HS T_OC T_LS
Figure 7. Cycle-by-Cycle Operation with High Side OC
(dashed line: normal operation; solid line: CBC event)
14
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During T_OC Period
CBC with Low Side OC
PVDD
Current Limit
Load
Current
PWM_HS
PWM_HS
Load
PWM_LS
PWM_LS
T_LS T_OC T_HS
GND_X
Figure 8. Cycle-by-Cycle Operation with Low Side OC
(dashed line: normal operation; solid line: CBC event)
1mF
DRV8332
GVDD
GVDD_B
330 mF
GVDD_A
PVDD
100 nF
1mF
OTW
BST_A
3.3
NC
10 nF
1000 mF
NC
Controller
(MSP430
C2000 or
Stellaris MCU)
NC
PVDD_A
FAULT
PVDD_A
PWM_A
OUT_A
RESET_A
GND_A
PWM_B
GND_B
Loc
Rsense_A
100nF
M
Rsense_B
Loc
Roc_adj
OC_ADJ
OUT_B
1
GND
PVDD_B
AGND
BST_B
VREG
NC
M3
NC
M2
GND
100 nF
100nF
100 nF
M1
Rsense_x £ 10 mW
or
Vsense < 100 mV
GND
Rsense_C
GVDD
47 mF
1mF
RESET_B
GND_C
RESET_C
OUT_C
PWM_C
PVDD_C
NC
PVDD_C
NC
NC
VDD
GVDD_C
Loc
100nF
PVDD
BST_C
GVDD_C
100 nF
1mF
Figure 9. DRV8332 Application Diagram for Three-Phase Operation
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PVDD
Controller
PWM_AH
PWM_BH
PWM_CH
PWM_A
PWM_B
PWM_C
MOTOR
OUT_A
OUT_B
RESET_A
OUT_C
PWM_AL
RESET_B
PWM_BL
RESET_C
PWM_CL
GND_A
GND_B
GND_C
Figure 10. Control Signal Logic with Conventional 6 PWM Input Scheme
16
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S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
Hall Sensor H1
Hall Sensor H2
Hall Sensor H3
Phase Current A
Phase Current B
Phase Current C
PWM_A
PWM_B
PWM_C
RESET_A
RESET_B
RESET_C
360
o
PWM= 100%
360
o
PWM=75%
Figure 11. Hall Sensor Control with 6 Steps Trapezoidal Scheme
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S1
Back EMF (Vab)
Back EMF (Vbc)
Back EMF (Vca)
S2
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S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
0V
0V
0V
Phase A
Current and Voltage
Va
Ia
0A
0V
Phase B
Current and Voltage
Vb
Ib
0A
0V
Vc
Phase C
Current and Voltage
Ic
0A
0V
PWM_A
PWM_B
PWM_C
RESET_A
RESET_B
RESET_C
360
o
PWM= 100%
360
o
PWM= 75%
Figure 12. Sensorless Control with 6 Steps Trapezoidal Scheme
18
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APPLICATION INFORMATION
SYSTEM DESIGN RECOMMENDATIONS
Voltage of Decoupling Capacitor
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. The high frequency decoupling capacitor
should use ceramic capacitor with X5R or better rating. For a 50-V application, a minimum voltage rating of 63 V
is recommended.
Current Requirement of 12V Power Supply
The DRV8332 requires a 12V power supply for GVDD and VDD pins. The total supply current is pretty low at
room temp (less than 50mA), but the current could increase significantly when the device temperature goes too
high (e.g. above 125°C), especially at heave load conditions due to substrate current collection by 12V guard
rings. So it is recommended to design the 12V power supply with current capability at least 5-10% of your load
current and no less than 100mA to assure the device performance across all temperature range.
VREG Pin
The VREG pin is used for internal logic and should not be used as a voltage source for external circuitries. The
capacitor on VREG pin should be connected to AGND.
VDD Pin
The transient current in VDD pin could be significantly higher than average current through VDD pin. A low
resistive path to GVDD should be used. A 22-µF to 47-µF capacitor should be placed on VDD pin beside the
100-nF to 1-µF decoupling capacitor to provide a constant voltage during transient.
OTW Pin
OTW reporting indicates the device approaching high junction temperature. This signal can be used with MCU to
decrease system power when OTW is low in order to prevent OT shut down at a higher temperature.
No external pull up resistor or 3.3V power supply is needed for 3.3V logic. The OTW pin has an internal pullup
resistor connecting to an internal 3.3V to reduce external component count. For 5V logic, an external pull up
resistor to 5V is needed.
FAULT Pin
The FAULT pin reports any fault condition resulting in device shut down. No external pull up resistor or 3.3V
power supply is needed for 3.3V logic. The FAULT pin has an internal pullup resistor connecting to an internal
3.3V to reduce external component count. For 5V logic, an external pull upresistor to 5V is needed.
OC_ADJ Pin
For accurate control of the oevercurrent protection, the OC_ADJ pin has to be connected to AGND through an
OC adjust resistor.
PWM_X and RESET_X Pins
It is recommanded to connect these pins to either AGND or GND when they are not used, and these pins only
support 3.3V logic.
Mode Select Pins
Mode select pins (M1, M2, and M3) should be connected to either VREG (for logic high) or AGND for logic low. It
is not recommended to connect mode pins to board ground if 1-Ω resistor is used between AGND and GND.
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Output Inductor Selection
For normal operation, inductance in motor (assume larger than 10 µH) is sufficient to provide low di/dt output
(e.g. for EMI) and proper protection during overload condition (CBC current limiting feature). So no additional
output inductors are needed during normal operation.
However during a short condition, the motor (or other load) could be shorted, so the load inductance might not
present in the system anymore; the current in short condition can reach such a high level that may exceed the
abs max current rating due to extremely low impendence in the short circuit path and high di/dt before oc
detection circuit kicks in. So a ferrite bead or inductor is recommended to utilize the short circuit protection
feature in DRV8332. With an external inductor or ferrite bead, the current will rise at a much slower rate and
reach a lower current level before oc protection starts. The device will then either operate CBC current limit or
OC shut down automatically (when current is well above the current limit threshold) to protect the system.
For a system that has limited space, a power ferrite bead can be used instead of an inductor. The current rating
of ferrite bead has to be higher than the RMS current of the system at normal operation. A ferrite bead designed
for very high frequency is NOT recommended. A minimum impedance of 10 Ω or higher is recommended at 10
MHz or lower frequency to effectively limit the current rising rate during short circuit condition.
The TDK MPZ2012S300A and MPZ2012S101A (with size of 0805 inch type) have been tested in our system to
meet short circuit conditions in the DRV8332. But other ferrite beads that have similar frequency characteristics
can be used as well.
For higher power applications, such as in the DRV8332, there might be limited options to select suitable ferrite
bead with high current rating. If an adequate ferrite bead cannot be found, an inductor can be used.
The inductance can be calculated as:
PVDD × Toc _ delay
Loc _ min =
Ipeak - Iave
(1)
Where Toc_delay = 250 nS, Ipeak = 15 A (below abs max rating).
Because an inductor usually saturates pretty quickly after reaching its current rating, it is recommended to use an
inductor with a doubled value or an inductor with a current rating well above the operating condition.
THERMAL INFORMATION
The thermally enhanced package provided with the DRV8332 is designed to interface directly to heat sink using
a thermal interface compound in between, (e.g., Ceramique from Arctic Silver, TIMTronics 413, etc.). The heat
sink then absorbs heat from the ICs and couples it to the local air.
RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the
following components:
• RθJC (the thermal resistance from junction to case, or in this example the power pad or heat slug)
• Thermal grease thermal resistance
• Heat sink thermal resistance
The thermal grease thermal resistance can be calculated from the exposed power pad or heat slug area and the
thermal grease manufacturer's area thermal resistance (expressed in °C-in 2/W or °C-mm2/W). The approximate
exposed heat slug size is as follows:
• DRV8332, 44-pin DDV …… 0.055 in2 (35.6 mm 2)
The thermal resistance of a thermal pad is considered higher than a thin thermal grease layer and is not
recommended. Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink
thermal resistance is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model,
or measured.
Thus the system RθJA = RθJC + thermal grease resistance + heat sink resistance.
See the TI application report, IC Package Thermal Metrics (SPRA953A), for more thermal information.
20
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REVISION HISTORY
Changes from Revision A (September 2013) to Revision B
Page
•
Changed Overcurrent (OC) Protection section ................................................................................................................... 12
•
Deleted Overtemperature Protection section ...................................................................................................................... 13
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PACKAGE OPTION ADDENDUM
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31-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
DRV8332HDDV
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
DDV
44
35
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-55 to 175
DRV8332H
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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31-Jan-2014
OTHER QUALIFIED VERSIONS OF DRV8332-HT :
• Catalog: DRV8332
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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