Texas Instruments | Layout for the DRV832x Family of Three-Phase Smart Gate Drivers | Application notes | Texas Instruments Layout for the DRV832x Family of Three-Phase Smart Gate Drivers Application notes

Texas Instruments Layout for the DRV832x Family of Three-Phase Smart Gate Drivers Application notes
Application Report
SLVA951 – March 2018
Layout Guide for the DRV832x Family of Three-Phase
Smart Gate Drivers
ABSTRACT
Effective printed circuit board (PCB) layout is required to achieve the best performance for high-power,
high-speed, or low-noise systems. Issues with PCB layout can cause EMI or EMC radiation, additional
heat, noise coupling, device faults, and a host of other possible problems on the board. The DRV832x
family of Smart Gate Drivers is no exception to this rule, and, although the device is designed to operate
in the harshest conditions, knowledge on the best way to layout the PCB can lead to maximizing the
effectiveness of the driver. This document describes two-layer PCB layout with the DRV832x devices,
however these principles also apply to boards with more than two layers. This application report can also
be applied to the DRV8304 device, which has the same pin out as DRV8323. However, some external
component values may be different.
For additional layout examples, refer to the following resources:
• BOOSTXL-DRV8320S EVM or BOOSTXL-DRV8320H EVM
• BOOSTXL-DRV8323RS EVM or BOOSTXL-DRV8323RH EVM
• TIDA-00774
• TIDA-01485
• TIDA-01516
1
2
3
4
5
6
7
8
9
Contents
DRV832x Family Introduction .............................................................................................. 2
Proper Device Grounding ................................................................................................... 3
Heat Sinking .................................................................................................................. 5
Traces and Vias .............................................................................................................. 5
DRV832x Base External Components .................................................................................... 5
Gate Driver Layout........................................................................................................... 7
6.1
VDRAIN Pin ......................................................................................................... 7
6.2
GHx Pins ............................................................................................................. 7
6.3
SHx Pins ............................................................................................................ 8
6.4
GLx Pins ............................................................................................................ 8
6.5
SLx or SPx Pins .................................................................................................... 8
Half-H Bridge Layout ........................................................................................................ 8
7.1
High-Side MOSFET (QHS) .......................................................................................... 8
7.2
Low-Side MOSFET (QLS) .......................................................................................... 8
7.3
Decoupling Capacitor (CBYPASS) .................................................................................... 8
7.4
Sense Resistor (RSENSE) ............................................................................................ 8
Sense Amplifier Layout .................................................................................................... 10
DC-DC Buck Regulator Layout ........................................................................................... 11
9.1
Small Current Loops .............................................................................................. 12
9.2
Continuous Ground Plane ........................................................................................ 12
9.3
Feedback Path..................................................................................................... 13
9.4
Split Ground Plane ................................................................................................ 13
List of Figures
1
DRV832x Device Legend
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Layout Guide for the DRV832x Family of Three-Phase Smart Gate Drivers
Copyright © 2018, Texas Instruments Incorporated
2
1
DRV832x Family Introduction
www.ti.com
2
DRV8320 Common Ground Plane ........................................................................................ 3
3
DRV8320 Split Ground Plane .............................................................................................. 3
4
DRV8320R Common Ground Plane ...................................................................................... 3
5
DRV8320R Split Ground Plane ............................................................................................ 3
6
DRV8323 Common Ground Plane ........................................................................................ 3
7
DRV8323 Split Ground Plane .............................................................................................. 3
8
DRV8323R Common Ground Plane ...................................................................................... 4
9
DRV8323R Split Ground Plane ............................................................................................ 4
10
DRV8320 Base External Component Layout
11
12
13
14
15
16
17
18
19
20
21
........................................................................... 6
DRV8320R Base External Component Layout ......................................................................... 6
DRV8323 Base External Component Layout ........................................................................... 6
DRV8323R Base External Component Layout ......................................................................... 6
Half-H Bridge Layout ........................................................................................................ 9
Half-H Bridge Current Loop ................................................................................................ 9
DRV8323 Sense Amplifier Layout ....................................................................................... 10
DRV8323R Sense Amplifier Layout ..................................................................................... 10
Shielding on a Split-Supply System ..................................................................................... 11
DRV8320R Buck Regulator Layout ...................................................................................... 11
DRV8323R Buck Regulator Layout ...................................................................................... 11
Small Current Loop Layout ............................................................................................... 12
Trademarks
SIMPLE SWITCHER is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
1
DRV832x Family Introduction
The DRV832x family of Smart Gate Drivers includes several device variants that integrate optional sense
amplifiers, a DC/DC buck regulator, or both. The packages for this family are QFN-type, ranging from 5 ×
5 mm and 32 pins, to 7 × 7 mm and 48 pins. For more information on the DRV832x family of devices,
refer to the DRV832x 6 to 60-V Three-Phase Smart Gate Driver data sheet.
DRV83
(2)
(3)
(R)
(S)
(RGZ) (R)
Prefix
DRV83 ± Three Phase Brushless DC
Tape and Reel
R ± Tape and Reel
T ± Small Tape and Reel
Series
2 ± 60 V device
Package
RTV ± 5 × 5 × 0.75 mm QFN
RHA ± 6 x 6 × 0.9 mm QFN
RTA ± 6 x 6 × 0.75 mm QFN
RGZ ± 7 × 7 × 0.9 mm QFN
Sense amplifiers
0 ± No sense amplifiers
3 ± 3x sense amplifiers
Interface
S ± SPI interface
H ± Hardware interface
Buck Regulator
[blank] ± No buck regulator
R ± Buck regulator
Figure 1. DRV832x Device Legend
2
Layout Guide for the DRV832x Family of Three-Phase Smart Gate Drivers
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Proper Device Grounding
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2
Proper Device Grounding
Typical systems using the DRV832x device have one ground plane encompassing the system. In common
ground plane systems, all ground pins should be connected directly to the thermal pad and to the ground
plane. Typically, a mostly solid ground plane is included on the bottom layer (or some inner layer for multilayer boards) underneath the DRV832x device, and the thermal pad is connected to the solid ground
plane using vias. Thermal reliefs should never be used to attach thermal pads to the PCB.
In some systems, splitting the power and logic ground planes is required to isolate noise from power
switching from the logic and microcontroller (MCU). In this case more care must be used when connecting
the pins of the DRV832x device to the correct ground plane (either power or logic). The two ground planes
must be connected at a place close enough to the DRV832x device. The thermal pad on the DRV832x
device is connected to the power ground plane in this case, and TI recommends having a power ground
that fills the area directly beneath the component on a different layer to let the vias from the thermal pad
connect.
Ground (common)
17 nFAULT
19 SDI/IDRIVE
18 SDO/MODE
21 nSCS/NC
20 SCLK/VDS
22 ENABLE
24 DVDD
23 AGND
Recommended Ground
Connection Point
17 nFAULT
19 SDI/IDRIVE
18 SDO/MODE
21 nSCS/NC
20 SCLK/VDS
22 ENABLE
24 DVDD
23 AGND
Logic Ground
(MCU Side)
INHA 25
16 SLC
INHA 25
16 SLC
INLA 26
15 GLC
INLA 26
15 GLC
INLB 28
Alternative
Ground
Connection
Point
14 SHC
Thermal Pad &
Vias
INHB 27
13 GHC
14 SHC
Thermal Pad &
Vias
INHB 27
INLB 28
13 GHC
INHC 29
12 GHB
INHC 29
12 GHB
INLC 30
11 SHB
INLC 30
11 SHB
PGND 31
10 GLB
PGND 31
10 GLB
9
SLB
SLA 8
GLA 7
SHA 6
GHA 5
VM 3
CPH 1
VDRAIN 4
CPL 32
SLA 8
GLA 7
SHA 6
GHA 5
VM 3
VDRAIN 4
VCP 2
CPH 1
SLB
VCP 2
9
CPL 32
Power Ground
(FET Side)
Top Layer
Top Layer
Bottom Layer
Bottom Layer
Figure 2. DRV8320 Common Ground Plane
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Figure 3. DRV8320 Split Ground Plane
Layout Guide for the DRV832x Family of Three-Phase Smart Gate Drivers
Copyright © 2018, Texas Instruments Incorporated
3
Proper Device Grounding
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Logic Ground
(MCU Side)
21 SDO/MODE
23 SCLK/VDS
22 SDI/IDRIVE
25 ENABLE
24 nSCS/NC
27 DVDD
26 AGND
INLB 31
20 nFAULT
INHC 32
19 GND
INLC 33
18 SLC
BGND 34
17 GLC
CB 35
16 SHC
Thermal Pad & Vias
SW 36
15 GHC
Reommended
NC 37
Ground
VIN 38
Connection
Point
nSHDN 39
13 SHB
FB 40
11 SLB
14 GHB
SLA 10
GLA 9
SHA 8
GHA 7
VDRAIN 6
VM 5
PGND
CPL
CPH
VCP
VM
VDRAIN
GHA
SHA
GLA
SLA
PGND 1
12 GLB
CPH 3
Thermal Pad & Vias
nFAULT
GND
SLC
GLC
SHC
GHC
GHB
SHB
GLB
SLB
CPL 2
20
19
18
17
16
15
14
13
12
11
28 INHA
30 INHB
30
29
28
27
26
25
24
23
22
21
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
INLB
INHC
INLC
BGND
CB
SW
NC
VIN
nSHDN
FB
29 INLA
INHB
INLA
INHA
DVDD
AGND
ENABLE
nSCS/NC
SCLK/VDS
SDI/IDRIVE
SDO/MODE
Alternative Ground Connection Point
VCP 4
Ground (common)
Power Ground
(FET Side)
Top Layer
Top Layer
Bottom Layer
Bottom Layer
Figure 5. DRV8320R Split Ground Plane
Figure 4. DRV8320R Common Ground Plane
ENABLE
nSCS/GAIN
SCLK/VDS
SDI/IDRIVE
SDO/MODE
nFAULT
VREF
SOA
SOB
SOC
30
29
28
27
26
25
24
23
22
21
30
29
28
27
26
25
24
23
22
21
Recommended
Ground Connection
Point
20
19
18
17
16
15
14
13
12
11
31
32
33
34
35
36
37
38
39
40
Thermal Pad & Vias
1
2
3
4
5
6
7
8
9
10
CAL
AGND
DVDD
INHA
INLA
Alternative
INHB
Ground
Connection INLB
Point
INHC
INLC
PGND
CPL
CPH
VCP
VM
VDRAIN
GHA
SHA
GLA
SPA
SNA
Thermal Pad & Vias
SNC
SPC
GLC
SHC
GHC
GHB
SHB
GLB
SNB
SPB
1
2
3
4
5
6
7
8
9
10
31
32
33
34
35
36
37
38
39
40
CPL
CPH
VCP
VM
VDRAIN
GHA
SHA
GLA
SPA
SNA
CAL
AGND
DVDD
INHA
INLA
INHB
INLB
INHC
INLC
PGND
ENABLE
nSCS/GAIN
SCLK/VDS
SDI/IDRIVE
SDO/MODE
nFAULT
VREF
SOA
SOB
SOC
Logic Ground
(MCU Side)
Ground (common)
20
19
18
17
16
15
14
13
12
11
SNC
SPC
GLC
SHC
GHC
GHB
SHB
GLB
SNB
SPB
Power Ground
(FET Side)
Top Layer
Top Layer
Bottom Layer
Bottom Layer
Figure 6. DRV8323 Common Ground Plane
4
Figure 7. DRV8323 Split Ground Plane
Layout Guide for the DRV832x Family of Three-Phase Smart Gate Drivers
Copyright © 2018, Texas Instruments Incorporated
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Heat Sinking
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Ground (common)
36
35
34
33
32
31
30
29
28
27
26
25
36
35
34
33
32
31
30
29
28
27
26
25
DVDD
AGND
CAL
ENABLE
nSCS/GAIN
SCLK/VDS
SDI/IDRIVE
SDO/MODE
nFAULT
DGND
VREF
SOA
DVDD
AGND
CAL
ENABLE
nSCS/GAIN
SCLK/VDS
SDI/IDRIVE
SDO/MODE
nFAULT
DGND
VREF
SOA
Logic Ground
(MCU Side)
24
23
22
21
20
19
18
17
16
15
14
13
INHA
INLA
INHB
INLB
INHC
INLC
BGND
CB
SW
NC
VIN
nSHDN
Alternative Ground
Connection Point
37
38
39
40
41
42
43
44
45
46
47
48
Thermal Pad & Vias
FB
PGND
CPL
CPH
VCP
VM
VDRAIN
GHA
SHA
GLA
SPA
SNA
Recommended
Ground Connection
Point
Top Layer
SOB
SOC
SNC
SPC
GLC
SHC
GHC
GHB
SHB
GLB
SPB
SNB
Power Ground
(FET Side)
Top Layer
Bottom Layer
Bottom Layer
Figure 8. DRV8323R Common Ground Plane
3
24
23
22
21
20
19
18
17
16
15
14
13
FB
PGND
CPL
CPH
VCP
VM
VDRAIN
GHA
SHA
GLA
SPA
SNA
1
2
3
4
5
6
7
8
9
10
11
12
Thermal Pad & Vias
SOB
SOC
SNC
SPC
GLC
SHC
GHC
GHB
SHB
GLB
SPB
SNB
1
2
3
4
5
6
7
8
9
10
11
12
INHA 37
INLA 38
INHB 39
INLB 40
INHC 41
INLC 42
BGND 43
CB 44
SW 45
NC 46
VIN 47
nSHDN 48
Figure 9. DRV8323R Split Ground Plane
Heat Sinking
The DRV832x device is a gate driver and therefore it is not the primary power generator in the system.
However, the gate driver and additional DC/DC buck regulator dissipate power while in operation. This
power is removed from the device through the thermal pad into the copper of the ground plane on the
PCB. Adequate PCB area for the ground plane should be a priority in layout because a constricted or
isolated ground plane will cause the DRV832x device to operate with a temperature that is hotter than
required. As mentioned previously, thermal reliefs should never be used on thermal pads.
4
Traces and Vias
In general, all traces should be as short and thick as possible. Typically, rules such as 15 mils (0.381mm)
per Ampere of current are used to minimize the parasitic inductance and resistance of board components.
Long, skinny traces result in a large inductor effect and can even act as an antenna to radiate EMI. Vias
are usually an inductive element and follow a general rule that each via is capable of at most 200 mA. A
good practice is to avoid vias wherever possible, especially in high-speed switching or power elements.
This practice usually leads to more traces on the top layer of the board, which in turn allows for a more
solid ground plane on the bottom layer. Another good practice is to make sure the diameter of the via is at
least the width of the incoming trace.
5
DRV832x Base External Components
The DRV832x basic features include a charge pump to power the high-side N-channel MOSFETs as well
as DVDD, a 3.3-V low-dropout (LDO) regulator that powers internal digital circuits but can also be used to
power other circuits externally (up to 30 mA). The external components for these features are defined as
follows:
CVM — The CVM capacitor is the supply bypass capacitor which should be a supply-rated X5R or X7R type,
0.1-µF ceramic capacitor connected from the VM pin to the PGND pin.
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DRV832x Base External Components
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CVCP — The CVCP capacitor is the charge pump bucket capacitor which should be a supply-rated X5R or
X7R type, 47-nF ceramic capacitor connected from the CPH pin to the CPL pin.
CSW — The CSW capacitor is the charge pump storage capacitor which should be a 16-V, X5R or X7R
type, 1-µF ceramic capacitor connected from the VCP pin to the VM pin.
CDVDD — The CDVDD capacitor is the LDO bypass capacitor which should be a 6.3-V, X5R or X7R type, 1µF ceramic capacitor connected from the DVDD pin to the AGND pin.
These components should be placed as close as possible to the pins without any long traces or ground
loops.
INLA 26
Thermal Pad &
Vias
INHB 27
21 SDO/MODE
23 SCLK/VDS
22 SDI/IDRIVE
25 ENABLE
24 nSCS/NC
27 DVDD
26 AGND
28 INHA
30 INHB
16 SLC
INHA 25
29 INLA
17 nFAULT
19 SDI/IDRIVE
18 SDO/MODE
21 nSCS/NC
22 ENABLE
24 DVDD
23 AGND
CDVDD
20 SCLK/VDS
CDVDD
INLB 31
20 nFAULT
INHC 32
19 GND
15 GLC
INLC 33
18 SLC
14 SHC
BGND 34
17 GLC
13 GHC
CB 35
INHC 29
12 GHB
SW 36
INLC 30
11 SHB
NC 37
14 GHB
PGND 31
10 GLB
VIN 38
13 SHB
15 GHC
CSW
CVCP
SLA 10
GLA 9
SHA 8
GHA 7
VDRAIN 6
CSW
VM 5
11 SLB
VCP 4
12 GLB
FB 40
CPH 3
nSHDN 39
SLA 8
GLA 7
SHA 6
GHA 5
VM 3
VDRAIN 4
2
CPH 1
SLB
CPL 2
9
CPL 32
16 SHC
Thermal Pad & Vias
PGND 1
INLB 28
CVCP
CVM
CVM
Top Layer
Top Layer
Bottom Layer
Bottom Layer
Figure 10. DRV8320 Base External Component Layout
6
Figure 11. DRV8320R Base External Component Layout
Layout Guide for the DRV832x Family of Three-Phase Smart Gate Drivers
Copyright © 2018, Texas Instruments Incorporated
SLVA951 – March 2018
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26 VREF
28 nFAULT
27 DGND
30 SDI/IDRIVE
29 SDO/MODE
32 nSCS/GAIN
31 SCLK/VDS
34 CAL
33 ENABLE
36 DVDD
35 AGND
21 SOC
23 SOA
22 SOB
25 nFAULT
24 VREF
27 SDI/IDRIVE
26 SDO/MODE
28 SCLK/VDS
30 ENABLE
29 nSCS/GAIN
CDVDD
CDVDD
25 SOA
Gate Driver Layout
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INHA 37
24 SOB
CAL 31
20 SNC
INLA 38
23 SOC
AGND 32
DVDD 33
19 SPC
INHB 39
22 SNC
18 GLC
INLB 40
21 SPC
INHA 34
17 SHC
INHC 41
20 GLC
INLA 35
16 GHC
INLC 42
19 SHC
15 GHB
BGND 43
INLB 37
14 SHB
CB 44
INHC 38
13 GLB
SW 45
16 SHB
INLC 39
12 SNB
NC 46
15 GLB
PGND 40
11 SPB
Thermal Pad & Vias
18 GHC
17 GHB
CSW
SPA 11
SNA 12
GLA 10
SHA 9
GHA 8
VM 6
VCP 5
VDRAIN 7
CVCP
CPL 3
14 SPB
13 SNB
CPH 4
VIN 47
nSHDN 48
FB 1
PGND 2
SNA 10
SPA 9
GLA 8
SHA 7
GHA 6
VDRAIN 5
VM 4
CPL 1
CPH 2
VCP 3
Thermal Pad & Vias
INHB 36
CVCP
CVM
CSW
CVM
Top Layer
Top Layer
Bottom Layer
Bottom Layer
Figure 12. DRV8323 Base External Component Layout
6
Figure 13. DRV8323R Base External Component Layout
Gate Driver Layout
The gate driver pins on the DRV832x family of devices are the VDRAIN, GHx, SHx, GLx, and SLx or SPx
pins. The following sections describe these pins.
6.1
VDRAIN Pin
The VDRAIN pin is used to sense the high-side MOSFET drain voltage, which is the supply to the external
MOSFETs, for overcurrent VDS sensing. The DRV832x device monitors the drain-to-source voltage
across the external MOSFETs to determine if an overcurrent event occurs. Typically, the VDRAIN pin is
on the same net as the VM pin on the DRV832x device. In some boards, some distance between the
DRV832x and the FETs can exist, and traces may add inductance or voltage drops to affect the accuracy
of this overcurrent protection. The device has a dedicated pin so that a Kelvin connection can be made to
the high-side FETs. This connection allows the VDRAIN pin to be routed as close to the external MOSFET
drains as possible without interference from other sources. Net Ties are components that can be used in
schematics to make sure that the Kelvin connection is maintained.
6.2
GHx Pins
The GHx pins are the high-side gate and should be connected directly to the gate pin of the high-side
MOSFETs. These traces will conduct the source or sink current into and out of the external MOSFET
gate. TI recommends that a gate signal stays in the same layer when possible to avoid vias and maintain
at least a 20 mil wide trace.
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Gate Driver Layout
6.3
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SHx Pins
The SHx pins are the high-side source, also called the output or the phase node. These pins route to the
connection between the high-side MOSFET source and low-side MOSFET drain, which is the same node
that is connected to the brushless-DC motor. This pin is used internally for overcurrent VDS sensing of the
high-side (VDRAIN to SHx) and low-side (SHx to SLx or SPx) MOSFETS. The SHx pin should be routed
as close to the low-side MOSFET drain and high-side MOSFET source as possible.
6.4
GLx Pins
The GLx pins are the low-side gate, and should be connected directly to the gate pin of the low-side
MOSFETs. These traces will conduct the source or sink current into and out of the external MOSFET
gate. TI recommends that a gate signal stays in the same layer when possible to avoid vias and maintain
at least a 20 mil wide trace.
6.5
SLx or SPx Pins
On the DRV8320 and DRV8320R devices, which have no integrated sense amplifiers, the SLx pin is the
low-side MOSFET VDS monitor. The low-side MOSFET overcurrent monitor measures the voltage across
the SHx to SLx pins. On the DRV8323 and DRV8323R devices, the SLx pin is replaced by the SPx pin.
The SPx pin is actually a sense amplifier input pin, however the functionality of the low-side VDS monitor
is included on the SPx pin as well. On the DRV832x devices with sense amplifiers the low-side MOSFET
overcurrent monitor measures the voltage across SHx to SPx. These signals should be routed as a
differential for a more accurate measurement.
7
Half-H Bridge Layout
The DRV832x device interfaces with the external MOSFETs in a half-H configuration. The half-H bridge
has two N-channel MOSFETs (high-side and low-side) as well as any decoupling capacitor and (usually) a
sense resistor.
7.1
High-Side MOSFET (QHS)
The QHS component is connected to the supply voltage (on the drain), the motor (on the source), and the
DRV832x device (on the gate). Do not use thermal relief on any pads of this component. The GHx pin of
the DRV832x device should be routed to the gate of QHS with as short of a trace as possible.
7.2
Low-Side MOSFET (QLS)
The QLS component is connected to the motor (on the drain), ground or the sense resistor (on the source),
and the DRV832x device (on the gate). Do not use thermal relief on any pads of this component. The GLx
pin of the DRV832x device should be routed to the gate of QLS with as short of a trace as possible.
7.3
Decoupling Capacitor (CBYPASS)
The CBYPASS component is connected between the drain of the high-side MOSFET and the source of the
low-side MOSFET. This component supplies current to the half-H bridge during fast switching. Do not use
thermal relief on any pads of this component.
7.4
Sense Resistor (RSENSE)
The RSENSE component (if present) is connected between the low-side MOSFET source and power ground.
The SPx and SNx pins are connected to the terminals of the sense resistor to amplify and measure the
voltage across the resistor when current is flowing. The SPx and SNx pins must be routed as independent
traces directly to the terminals of the sense resistor. Do not use thermal relief on the sense resistor
terminals because it can cause large voltage spikes because of increased parasitic inductance.
8
Layout Guide for the DRV832x Family of Three-Phase Smart Gate Drivers
Copyright © 2018, Texas Instruments Incorporated
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Half-H Bridge Layout
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S
D
S
D
S
D
G
D
RSENSE
QLS
(to SNx)
(to SPx)
(to GLx)
(to SHx)
(to GHx)
OUTx
D
G
D
S
D
S
D
S
QHS
CBYPASS
(to VDRAIN)
Figure 14. Half-H Bridge Layout
NOTE: The VDRAIN pin should be a unique connection to the supply close to the external high-side
MOSFET drain which ensures best operation of the VDS overcurrent monitors. Similarly, the
SHx pin should be routed to the connection between the high-side MOSFET source and lowside MOSFET drain as an independent trace.
The following path should have a minimal length: GND-CBYPASS-VM-QHS-OUTx-QLS-RSENSE-GND. This path
is the high-current path in the system and all traces in this loop should have traces sized to carry the
motor current (with additional margin).
S
D
S
D
S
D
G
D
RSENSE
QLS
(to SNx)
(to SPx)
(to GLx)
(to SHx)
(to GHx)
OUTx
D
G
D
S
D
S
D
S
QHS
CBYPASS
(to VDRAIN)
Figure 15. Half-H Bridge Current Loop
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9
Sense Amplifier Layout
8
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Sense Amplifier Layout
The DRV8323 and DRV8323R devices contain three current sense amplifiers which are used with the
external current sense resistors to measure the current in each winding of the motor. The SPx and SNx
pins are the sense amplifier inputs and are routed directly across the sense resistor. The SOx pin is the
sense amplifier output. The VREF pin is a voltage input which sets the range of the sense amplifier output
and sets the bias of the amplifier output at VREF/2. The VREF pin requires one ceramic bypass capacitor,
a VREF-rated X5R to X7R type, 0.1-µF ceramic capacitor from the VREF pin to either the AGND (on
DRV8323) or DGND (on DRV8323R) pin.
Thermal Pad & Vias
BGND 43
(Phase C)
26 VREF
25 SOA
28 nFAULT
27 DGND
30 SDI/IDRIVE
29 SDO/MODE
32 nSCS/GAIN
31 SCLK/VDS
34 CAL
33 ENABLE
36 DVDD
35 AGND
19 SHC
18 GHC
17 GHB
CB 44
SW 45
16 SHB
NC 46
15 GLB
Current Sense
Amplifier Inputs
(Phase A)
SPA 11
SNA 12
14 SPB
13 SNB
GLA 10
VIN 47
nSHDN 48
SHA 9
SNA 10
SPA 9
GLA 8
SHA 7
GHA 6
11 SPB
VDRAIN 5
PGND 40
VM 4
12 SNB
VCP 3
13 GLB
INLC 39
CPL 1
INHC 38
CPH 2
14 SHB
20 GLC
INLC 42
(Phase B)
15 GHB
INLB 37
(Phase B)
INHB 36
INHC 41
GHA 8
Thermal Pad & Vias
VDRAIN 7
16 GHC
21 SPC
VM 6
17 SHC
INLA 35
22 SNC
INLB 40
VCP 5
INHA 34
INHB 39
CPL 3
18 GLC
23 SOC
CPH 4
19 SPC
DVDD 33
24 SOB
INLA 38
FB 1
AGND 32
Current
Sense
Amplifier
Outputs
(To MCU)
INHA 37
PGND 2
20 SNC
CAL 31
(Phase C)
21 SOC
23 SOA
CDVDD
22 SOB
25 nFAULT
Current Sense
Amplifier Outputs
(To MCU)
24 VREF
27 SDI/IDRIVE
26 SDO/MODE
28 SCLK/VDS
30 ENABLE
CDVDD
29 nSCS/GAIN
CVREF
Current Sense Amplifier
Inputs
(Phase A)
Top Layer
Top Layer
Bottom Layer
Bottom Layer
Figure 16. DRV8323 Sense Amplifier Layout
Figure 17. DRV8323R Sense Amplifier Layout
Occasionally, designers want to shield traces by surrounding the traces with additional ground traces. If a
split supply is used, the SPx and SNx pins should exist in the power ground domain because they are
connected to the power stage. Any trace shielding should be done using the power ground. The VREF
and SOx pins should be on the logic ground domain, and shielding should be done using the logic ground.
10
Layout Guide for the DRV832x Family of Three-Phase Smart Gate Drivers
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DC-DC Buck Regulator Layout
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21 SOC
23 SOA
22 SOB
25 nFAULT
24 VREF
27 SDI/IDRIVE
26 SDO/MODE
28 SCLK/VDS
CAL 31
20 SNC
AGND 32
19 SPC
DVDD 33
18 GLC
INHA 34
17 SHC
INLA 35
16 GHC
Thermal Pad & Vias
INHB 36
15 GHB
INLB 37
14 SHB
INHC 38
13 GLB
SNA 10
SPA 9
GLA 8
SHA 7
GHA 6
VDRAIN 5
VM 4
VCP 3
12 SNB
11 SPB
CPL 1
INLC 39
PGND 40
CPH 2
Alternative
Ground
Connection
Point
30 ENABLE
Recommended Ground
Connection Point
29 nSCS/GAIN
Logic Ground
(MCU Side)
Power Ground
(FET Side)
Top Layer
Bottom Layer
Figure 18. Shielding on a Split-Supply System
9
DC-DC Buck Regulator Layout
For best practices on layout of switching power supplies, refer to the following:
• Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application report
• Texas Instruments, LMR16006 SIMPLE SWITCHER™ 60 V 0.6 A Buck Regulators With High
Efficiency ECO Mode data sheet
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DC-DC Buck Regulator Layout
CDVDD
36
35
34
33
32
31
30
29
28
27
26
25
INHB
INLA
INHA
DVDD
AGND
ENABLE
nSCS/NC
SCLK/VDS
SDI/IDRIVE
SDO/MODE
CDVDD
RFB2
nFAULT
GND
SLC
GLC
SHC
GHC
GHB
SHB
GLB
SLB
CBOOT
LSW
DSW
1
2
3
4
5
6
7
8
9
10
DSW
Thermal Pad & Vias
20
19
18
17
16
15
14
13
12
11
COUT
CSW
RFB1
RFB1
PGND
CPL
CPH
VCP
VM
VDRAIN
GHA
SHA
GLA
SLA
CVIN
37
38
39
40
41
42
43
44
45
46
47
48
RFB2
CVIN
CVCP
Thermal Pad & Vias
24
23
22
21
20
19
18
17
16
15
14
13
SOB
SOC
SNC
SPC
GLC
SHC
GHC
GHB
SHB
GLB
SPB
SNB
FB
PGND
CPL
CPH
VCP
VM
VDRAIN
GHA
SHA
GLA
SPA
SNA
CBOOT
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
INHA
INLA
INHB
INLB
INHC
INLC
BGND
CB
SW
NC
VIN
nSHDN
30
29
28
27
26
25
24
23
22
21
LSW
INLB
INHC
INLC
BGND
CB
SW
NC
VIN
nSHDN
FB
DVDD
AGND
CAL
ENABLE
nSCS/GAIN
SCLK/VDS
SDI/IDRIVE
SDO/MODE
nFAULT
DGND
VREF
SOA
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COUT
CVCP
CSW
CVM
CVM
Top Layer
Top Layer
Bottom Layer
Bottom Layer
Figure 20. DRV8323R Buck Regulator Layout
Figure 19. DRV8320R Buck Regulator Layout
The following sections describe some specific concerns regarding the DC-DC regulator present on the
DRV8320R and DRV8323R devices.
9.1
Small Current Loops
A DC/DC system has two key current loops. The primary loop is GND-DSW-SW-LSW-OUT-COUT-GND, and
the secondary loop is GND-CVIN-VIN-SW-LSW-OUT-COUT-GND. Make sure these paths are as small as
possible.
CBOOT
LSW
INHC 41
INLC 42
BGND 43
CB 44
SW 45
NC 46
VIN 47
DSW
FB 1
RFB1
RFB2
PGND 2
nSHDN 48
CVIN
COUT
CSW
Top Layer
Bottom Layer
Figure 21. Small Current Loop Layout
9.2
Continuous Ground Plane
Underneath the two current loops mentioned previously, make sure a solid ground plane exists that is not
cut by traces. Routing traces around these loops is more efficient than routing straight through them (see
Section 9.3).
12
Layout Guide for the DRV832x Family of Three-Phase Smart Gate Drivers
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DC-DC Buck Regulator Layout
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9.3
Feedback Path
The FB pin uses the feedback voltage to control the output of the DC/DC regulator. A resistor divider
(RFB1, RFB2) is tapped from the output and fed into the FB pin. Make sure that the resistor divider is
placed as close to the FB pin as possible. If the resistor divider is far away from the pin, the FB trace may
pick up extra noise because it is high impedance. Another consideration is routing the DC/DC output
voltage back to the resistor divider. Make sure not to interrupt the ground plane underneath the current
loops previously mentioned.
9.4
Split Ground Plane
The BGND pin is actually a very-low current node. The majority of the current into or out of the ground in
the system is sourced through the DSW component or from the COUT and CVIN capacitors. When the logic
ground and power ground are split, the DC/DC buck regulator normally acts as the interface between the
two domains, providing a low voltage logic supply in the logic domain. One strategy to have better noise
immunity is to have BGND on the logic ground, as well as the ground reference for the resistor divider into
the FB pin and COUT capacitor. The power ground can be connected to the DSW diode and CVIN capacitor. If
the grounds are split it is critical to have the ground connection point as close to the CVIN and COUT
capacitors as possible.
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