Texas Instruments | TPS1H200A-Q1 40-V 200-mΩ Single-Channel Smart High-Side Switch (Rev. C) | Datasheet | Texas Instruments TPS1H200A-Q1 40-V 200-mΩ Single-Channel Smart High-Side Switch (Rev. C) Datasheet

Texas Instruments TPS1H200A-Q1 40-V 200-mΩ Single-Channel Smart High-Side Switch (Rev. C) Datasheet
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TPS1H200A-Q1
SLVSEE0C – FEBRUARY 2018 – REVISED DECEMBER 2019
TPS1H200A-Q1 40-V 200-mΩ Single-Channel Smart High-Side Switch
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Functional safety capable
– Documentation available to aid functional
safety system design
Single-Channel 200-mΩ Smart High-Side Switch
Wide Operating Voltage: 3.4 V to 40 V
Ultra-low Standby Current, < 500 nA
Adjustable Current Limit With External Resistor
– ±15% When ≥ 500 mA
– ±10% When ≥ 1.5 A
Configurable Behavior After Current Limit
– Holding Mode
– Latch-Off Mode With Adjustable Delay Time
– Auto-Retry Mode
Supports Stand-Alone Operation Without an MCU
Protection:
– Short-to-GND and Overload Protection
– Thermal Shutdown and Thermal Swing
– Negative Voltage Clamp for Inductive Loads
– Loss of GND and Loss of Battery Protection
Diagnostics:
– Overload and Short-to-GND Detection
– Open-Load and Short-to-Battery Detection in
Typical Block Diagram
ON or OFF State
– Thermal Shutdown and Thermal Swing
2 Applications
•
•
•
•
•
Body Lighting
Infotainment System
Advanced Driver Assistance Systems (ADAS)
Single-Channel High-Side Switch for Submodules
General Resistive, Inductive, and Capacitive
Loads
3 Description
The TPS1H200A-Q1 device is a fully protected
single-channel high-side power switch with an
integrated 200-mΩ NMOS power FET.
An adjustable current limit improves system reliability
by limiting the inrush or overload current. The high
accuracy of the current limit improves overload
protection, simplifying the front-stage power design.
Configurable features besides current limit provide
design flexibility in functionality, cost, and thermal
dissipation.
The device supports full diagnostics with the digital
status output. Open-load detection is available in ON
and OFF states. The device supports operation with
or without an MCU. Stand-alone mode allows isolated
systems to use the device.
Device Information(1)
PART NUMBER
TPS1H200A-Q1
PACKAGE
HVSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Current Limit Protection in Auto-Retry Mode
3.5 ± 40 V
Supply Voltage
VS
Up to 40 V
IN
LED Strings Bulbs
Up to 40 V
DIAG_EN
Relays, Solenoids
FAULT
OUT
CL
DELAY
Submodule
Cameras, Sensors
General Resistive Capacitive,
Inductive Loads
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS1H200A-Q1
SLVSEE0C – FEBRUARY 2018 – REVISED DECEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 24
8
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application ................................................. 25
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
Changes from Revision B (December 2019) to Revision C
•
Page
Added Functional safety capable to the Features section .................................................................................................... 1
Changes from Revision A (April 2018) to Revision B
Page
•
Changed the Logic high-level voltage from 2 V to 1.8 V in the Electrical Characteristics table ............................................ 6
•
Changed the IN and DIAG_EN from high to low in the Standby Mode section ................................................................... 24
Changes from Original (February 2018) to Revision A
•
2
Page
Changed data sheet status from Advanced Information to Production Data ........................................................................ 1
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SLVSEE0C – FEBRUARY 2018 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
DGN PowerPAD™ Package
8-Pin HVSSOP With Exposed Thermal Pad
Top View
IN
1
DIAG_EN
2
8
VS
7
OUT
6
GND
5
DELAY
Thermal
FAULT
3
CL
4
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CL
4
O
Adjustable current limit. Connect to device GND if external current limit is not used.
DELAY
5
I/O
Function configuration when current limit; internal pullup
DIAG_EN
2
I
Enable the diagnostic function
FAULT
3
O
Open-drain diagnostic status output. Leave floating if not used.
GND
6
—
Ground
IN
1
I
Input control for output activation; internal pulldown
OUT
7
O
Output, source of the high-side switch, connected to the load
Power supply, drain for the high-side switch
VS
8
I
Thermal pad
—
—
Thermal pad. Connect to device GND or leave floating.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1) (2)
Supply voltage VS pin
Reverse polarity voltage
t < 400 ms
(3)
MIN
MAX
UNIT
—
42
V
t < 1 minute
–36
—
V
t < 2 minutes
–100
250
mA
–0.3
VS
V
Current on IN and DIAG_EN pins
–10
—
mA
Voltage on DELAY pin
–0.3
7
V
Current on DELAY pin
–60
—
mA
Voltage on FAULT pin
–0.3
7
V
Current on FAULT pin
–30
10
mA
Voltage on CL pin
–0.3
7
V
Current on CL pin
—
6
mA
Voltage on OUT pin
—
42
V
Inductive load switch-off energy dissipation single pulse (4)
—
40
mJ
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Current on GND
Voltage on IN and DIAG_EN pins
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to ground.
Reverse polarity condition: VIN = 0 V, reverse current < IR(2), GND pin 1-kΩ resistor in parallel with diode.
Test condition: VVS = 13.5 V, L = 8 mH, TJ = 150°C. FR4 2s2p board, 2 × 70-μm Cu, 2 × 35-μm Cu. 600 mm2 thermal pad copper area.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC
Q100-002 (1)
All pins except VS, OUT,
and GND
±2000
Pins VS, OUT, and GND
±3000
Charged-device model (CDM), per AEC Q100-011
(1)
4
UNIT
V
±750
AEC-Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications.
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6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
Operating voltage
4
40
V
Voltage on IN and DIAG_EN pins
0
40
V
Voltage on FAULT pin
0
5
V
Io,nom
Nominal DC load current
0
2.5
A
TJ
Operating junction temperature
–40
150
°C
VS
UNIT
6.4 Thermal Information
TPS1H200A-Q1
THERMAL METRIC (1)
DGN (HVSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
47.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.2
°C/W
RθJB
Junction-to-board thermal resistance
18.3
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
18.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING VOLTAGE
VVS(nom)
Nominal operating voltage
40
V
VVS(uvr)
Undervoltage restart
VVS rising
3.5
4
3.7
4
V
VVS(uvf)
Undervoltage shutdown
VVS falling
3
3.2
3.4
V
V(uv,hys)
Undervoltage shutdown, hysteresis
0.5
V
OPERATING CURRENT
I(op)
VVS = 13.5 V, VIN = 5 V
VDIAG_EN = 0 V, IOUT = 0.5 A
ICL = 2 A
Nominal operating current
I(off)
Standby current
Standby current with diagnostics
enabled
I(off,diag)
Standby-mode deglitch time
Ilkg(out)
Output leakage current in OFF state
VVS = 13.5 V
VIN = VDIAG_EN = VCL = VOUT = 0 V
TJ = 25°C
0.5
VVS = 13.5 V
VIN = VDIAG_EN = VCL = VOUT = 0 V
TJ = 125°C
3
VVS = 13.5 V
VIN = 0 V, VDIAG_EN = 5 V
3
mA
µA
IN from high to low
if deglitch time ≥ t(off,deg), then
the device enters into standby
mode.
(1)
t(off,deg)
5
12.5
VVS = 13.5 V
VIN = VDIAG_EN = VOUT = 0 V
mA
ms
3
µA
POWER STAGE
rDS(on)
ON state resistance
ICL(int)
Internal current limit
ICL(TSD)
Current-limit value percentage
during thermal shutdown
VDS(clamp)
Drain−to−source voltage
internally clamped
VVS ≥ 3.5 V, TJ = 25°C
200
VVS ≥ 3.5 V, TJ = 150°C
400
CL pin connected to GND
3.5
4.8
mΩ
6
A
65
V
1
V
60%
45
OUTPUT DIODE CHARACTERISTICS
VF
Drain−to-source diode voltage
IN = 0, IOUT = −0.15 A
IR(1)
Continuous reverse current from
source to drain during a
short-to-battery condition (1)
t < 60 s, VIN= 0 V, TJ = 25°C.
2
A
IR(2)
Continuous reverse current from
source to drain during a
reverse-polarity condition (1)
t < 60 s, VIN= 0 V, TJ = 25°C
GND pin 1-kΩ resistor in
parallel with diode.
2
A
0.3
0.7
LOGIC INPUT (IN, DIAG_EN)
VIH
Logic high-level voltage
VIL
Logic low-level voltage
Rpd,in
1.8
V
0.8
Logic-pin pulldown resistor
IN. VIN = 5 V
150
400
DIAG_EN. VVS = VDIAG_EN = 5 V
350
850
V
kΩ
DIAGNOSTICS
Ilkg(loss,GND)
td(ol,on)
(1)
6
Loss of ground output leakage current
Open-load deglitch time in ON state
VIN = 5 V, VDIAG_EN = 5 V
when IOUT < I(ol,on), duration longer
than td(ol,on), open load is detected.
200
300
100
µA
450
µs
Value specified by design, not subject to production test.
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Electrical Characteristics (continued)
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
I(ol,on)
Open-load detection threshold
in ON state
VIN = 5 V, VDIAG_EN = 5 V
when IOUT < I(ol,on)
duration longer than td(ol,on)
open load is detected.
V(ol,off)
Open-load detection threshold in OFF
state
VIN = 0 V, VDIAG_EN = 5 V
when VVS – VOUT < V(ol,off)
duration longer than td(ol,off)
open load is detected.
1.4
td(ol,off)
Open-load deglitch time
in OFF state
VIN = 0 V, VDIAG_EN = 5 V
when VVS – VOUT < V(ol,off)
duration longer than td(ol,off)
open load is detected.
200
I(ol,off)
OFF state output sink current
VIN = 0 V, VDIAG_EN = 5 V
VVS = VOUT = 13.5 V
–75
VFAULT
FAULT low output voltage
IFAULT = 2 mA
TYP
MAX
10
20
mA
2.6
V
450
µs
300
µA
0.2
(1)
UNIT
V
tFAULT
FAULT signal holding time
8.5
ms
T(SD)
Thermal shutdown threshold (1)
175
°C
T(SD,rst)
Thermal shutdown status reset (1)
155
°C
60
°C
10
°C
T(sw)
Thermal swing shutdown threshold
T(hys)
Hysterisis for resetting the thermal
shutdown and swing (1)
(1)
CURRENT LIMIT AND DELAY CONFIGURATION
K(CL)
Current-limit current ratio (1)
VCL(th)
Current-limit internal threshold voltage (1)
dK(CL) /
K(CL)
2500
External current limit accuracy
(IOUT – ICL × K(CL) × 100 /
(ICL × K(CL))
Idl(chg)
Delay pin charging current
in latch-off mode (1)
Vdl(th)
Pulling up threshold in auto-retry mode
Vdl(ref)
Internal reference voltage
in latch-off mode
tdl1
Internal fixed delay time (1)
tdl2
Adjustable delay time by external
capacitor on DELAY pin (1)
tCL(deg)
Deglitch time when current limit
0.8
V
Ilimit ≥ 0.25 A, VVS – VOUT ≥ 2.5 V
–20%
20%
Ilimit ≥ 0.5 A, VVS – VOUT ≥ 2.5 V
–15%
15%
Ilimit ≥ 1.5 A, Ilimit < 5 A
VVS – VOUT ≥ 2.5 V
–10%
10%
4.5
µA
2.7
V
1.45
300
(1)
400
Connect with 3.3 µF capacitor
as the maximum value.
IN low to high or IN keeps high but
thermal shutdown recovery,
VDIAG_EN = 5 V
the deglitch time from IN rising
edge to FAULT reporting out.
300
IN keeps high, VDIAG_EN = 5 V
the deglitch time from CL start-point
to FAULT reporting out.
80
V
500
µs
1000
ms
550
µs
200
thic(on)
On-time when in auto-retry mode (1)
35
40
45
ms
thic(off)
Off-time when in auto-retry mode (1)
0.8
1
1.2
s
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6.6 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT = 0.1 A
20
50
90
µs
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT = 0.1 A
20
50
90
µs
td(on)
Turnon delay time
IN rising edge to 10% of VOUT
td(off)
Turnoff delay time
IN falling edge to 90% of VOUT
dV/dt(on)
Slew rate on
VOUT from 10% to 90%
(1)
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT = 0.1 A
0.1
0.3
0.6
V/µs
dV/dt(off)
Slew rate off
VOUT from 90% to 10%
(1)
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT = 0.1 A
0.1
0.35
0.6
V/µs
(1)
(1)
Value specified by design, not subject to production test.
VIN
90%
90%
VOUT
dV/dt(off)
dV/dt(on)
10%
10%
td(on)
td(off)
Figure 1. Output Delay Characteristics
Open Load
Open Load
IN
FAULT
td(ol,on)
td(ol,off)
Figure 2. Open-Load Blanking-Time Characteristic
8
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6.7 Typical Characteristics
1.7
4
VVS Rising
VVS Falling
3.9
1.5
IN Voltage (V)
UVLO Voltage (V)
3.8
3.7
3.6
3.5
1.4
1.3
1.2
3.4
1.1
3.3
3.2
-40
IN High
IN Low
1.6
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
1
-40
110 125
-25
-10
Figure 3. UVLO Voltage Threshold
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D002
Figure 4. IN Voltage Threshold
1.7
1
DIAG_EN High
DIAG_EN Low
1.6
0.9
1.5
Diode Voltage (V)
DIAG_EN Voltage (V)
5
D001
1.4
1.3
1.2
0.8
0.7
1.1
1
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
0.6
-40
110 125
-25
Figure 5. DIAG_EN Voltage Threshold
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D004
0.4
rDS(on)_3.5V
rDS(on)_13.5V
rDS(on)_40V
0.35
On-Resistance (:)
54
Clamp Voltage (V)
5
Figure 6. Body-Diode Forward Voltage
55
53
52
51
50
-40
-10
D003
0.3
0.25
0.2
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
0.15
-40
-25
D005
Figure 7. Drain-to-Source Clamp Voltage
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
Figure 8. FET On-Resistance
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D007
D006
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Typical Characteristics (continued)
3
3
2.5
2.5
2
500mA CL Accuracy (%)
250mA CL Accuracy (%)
2
1.5
1
0.5
0
-0.5
-1
-1.5
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2
-2.5
-2.5
-3
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
-3
-40
-25
-10
D007
Figure 9. Current-Limit Accuracy at 250 mA
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D007
Figure 10. Current-Limit Accuracy at 500 mA
3
2.5
1A CL Accuracy (%)
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D007
Figure 11. Current-Limit Accuracy at 1 A
10
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7 Detailed Description
7.1 Overview
The TPS1H200A-Q1 device is a smart high-side switch with an internal charge pump and single-channel
integrated NMOS power FET. The adjustable current limit function improves the reliability of the whole system.
Full diagnostic features enable intelligent control of the load.
The external high-accuracy current limit sets the current limit value for the application. When overcurrent occurs,
the device improves system reliability by clamping the inrush current effectively. The device saves system cost
by reducing the size of PCB traces and connectors, and the capacity of the preceding power stage. The
TPS1H200A-Q1 device allows three modes when a current limit occurs. Users can set the output to consistently
hold the current, to immediately latch off, or to automatically retry through the configuration on the DELAY pin.
The configurable behaviors during a current limit provides design flexibility. This includes functionality, cost, and
thermal dissipation.
This device supports full diagnostics with the digital status output. High-accuracy and low-threshold open-load
detection enables real-time ON state monitoring. The device supports operation without an MCU (stand-alone
mode) which allows the system to locally implement full functionality.
The TPS1H200A-Q1 device is a smart high-side switch for a wide variety of resistive, inductive, and capacitive
loads, including LEDs, bulbs, relays, solenoids, and submodules.
7.2 Functional Block Diagram
VS
Internal Reference
Gate Driver
IN
DIAG_EN
VDS Clamp
Charge Pump
Diagnostics
& Protection
Thermal Monitor
FAULT
OUT
ON/OFF State
Open Load Detection
Short-to-GND and Overload
Current Limit
CL
GND
DELAY
GND
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7.3 Feature Description
7.3.1 Current limit
A high-accuracy current limit allows high reliability of the design. The current limit protects the load and the
power supply from overstressing during short-circuit-to-GND or power-up conditions. The current limit can also
save system cost by reducing the size of PCB traces and connectors, and the capacity of the preceding power
stage.
When a current limit threshold is hit, a closed loop immediately activates. The output current is clamped at the
set value, and a fault is reported. The device heats up because of high power dissipation on the power FET.
The device has two current limit thresholds.
• Internal current limit: The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for
large-transient-current applications.
• External adjustable current limit: An external resistor is used to set the current limit threshold. Use Equation 1
to calculate R(CL). The external adjustable current limit allows the flexibility to set the current limit value by
application.
uK
V
CL(th)
(CL)
RCL
IOUT
where
•
•
•
VCL(th) is the internal band-gap voltage.
K(CL) is the ratio of the output current and the current limit set value.
K(CL) is constant across temperature and supply voltage.
(1)
NOTE
When a GND network is used, that causes a level shift between the device GND and
board GND, so the CL pin must be connected to the device GND.
For better protection from a hard short-to-GND condition (when the IN pin is enabled, a short-to-GND occurs
suddenly), the device will implement a fast-trip protection to turn off the output before the current limit closed loop
is set up. Typically, the fast-trip response time is less than 1 µs. With a fast response like this, the device can
achieve a better inrush current-suppression performance.
vs
IOUT/K(CL)
Internal Current Limit
-
+
+
VCL(th)
+
IOUT
OUT
External Current Limit
VCL(th)
+
CL
Figure 12. Current Limit
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Feature Description (continued)
7.3.2 DELAY Pin Configuration
When a current limit occurs, the TPS1H200A-Q1 device supports three different outcomes of the output. Table 1
lists the current limit configurations and these outcomes behaviors.
Table 1. Current Limit Configurations
MODE
Holding
Latch-off
DELAY
CONFIGURATION
OUTPUT CURRENT BEHAVIOR
FAULT RECOVERY
When hitting a current limit, the output current
FAULT clears when IN turns low for a
holds at the setting current. The device enters into duration of time longer than tFAULT OR when
thermal shutdown mode when TJ > T(SD).
the current limit is removed when IN is high.
Connects to GND
directly
When hitting a current limit, the output current
holds at the setting current, but latches off after a
preset DELAY time (tdl1+ tdl2). tdl1 is the default
delay time, and tdl2 is a capacitor-configurable
delay time.
Connects to GND
through a capacitor
FAULT clears when IN turns low for a
duration of time longer than tFAULT.
The output stays latched off regardless of whether
the current limit is removed. The output recovers
only when IN is toggling.
Auto-retry
When hitting a current limit, the output current
FAULT clears when IN turns low for a
holds at the setting current, but periodically comes duration of time longer than tFAULT OR when
on for thic(on) and turns off for thic(off).
the current limit is removed for thic(on).
External pullup
7.3.2.1 Holding Mode
Holding mode is active when the DELAY pin connects directly to GND. When a current limit is reached, the
output current holds at the setting current. The device then enters thermal shutdown mode when TJ > T(SD).
DELAY
TPS1H200-Q1
GND
Figure 13. Holding Mode Connection
IOUT
tCL(deg)
Holding the current
VFAULT
Current Limit
Figure 14. Holding Mode Example
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7.3.2.2 Latch-Off Mode
Latch-off mode is active when the DELAY pin connects to GND through a capacitor. When a current limit is
reached, the output current holds at the setting current, but latches off after a preset DELAY time (tdl1+ tdl2). tdl1 is
the default delay time, and tdl2 is a configurable delay time set by a capacitor. Regardless of whether the current
limit is removed or not, the output remains latched off. The output only recovers when IN is toggling.
tdl2 can be calculated by Equation 2.
CDELAY
I dl chg u t dl2
Vdl ref
where
•
•
•
•
CDELAY is the capacitor connected on the DELAY pin.
The Idl(chg) is the device that charges the current in latch-off mode.
tdl2 is the user-setting delay time.
Vdl(ref) is the internal reference voltage in latch-off mode.
DELAY
(2)
TPS1H200-Q1
Figure 15. Latch-Off-Mode Connection
IOUT
tCL(deg) tdl1
tdl2
Latch off
VFAULT
Current Limit
Figure 16. Latch-Off-Mode Example
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7.3.2.3 Auto-Retry Mode
Auto-retry mode is active when the DELAY pin is externally pulled up. The pullup voltage must be higher than
Vdl(th). When the current limit is reached, the output current holds at the setting current, but periodically turns on
for thic(on) and turns off for thic(off). The device checks the current limit status at the falling edge of thic(on) clock. If
current limit status is captured, the device shuts down for thic(off). If the current limit status is not captured because
of the off window during the thermal conditions, the device keeps turning on for additional thic(on) or more until the
current limit status is captured.
DELAY
TPS1H200-Q1
Figure 17. Auto-Retry-Mode Connection
IOUT
tCL(deg)
thic(on)
thic(off)
tCL(deg)
thic(on)
thic(off)
VFAULT
Current Limit
Figure 18. Auto-Retry-Mode Example
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7.3.3 Stand-alone Operation
In a typical application, the TPS1H200A-Q1 device is controlled by a microcontroller. The device also supports
stand-alone operation. IN and DIAG_EN have a 40-V maximum DC rating, and can be connected to the VS pin
directly. When in auto-retry mode, the DELAY pin is connected to the VS pin through a 100-kΩ resistor.
3.4 V ± 40 V
VS
IN
DIAG_EN
1
8
2
7
Tab
FAULT
CL
3
6
4
5
OUT
Load
GND
DELAY
Figure 19. Stand-Alone Operation in Latch-Off Mode
3.4 V ± 40 V
IN
DIAG_EN
VS
1
8
2
7
Tab
FAULT
CL
3
6
4
5
OUT
Load
GND
DELAY
Figure 20. Stand-Alone Operation in Auto-Retry Mode
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7.3.4 Fault Truth Table
The DIAG_EN pin enables or disables the diagnostic functions. If multiple devices are used, but the ADC
resource is limited in the microcontroller, the microcontroller uses GPIOs to set DIAG_EN high to enable the
diagnostics of one device, and disables the diagnostics of the other devices by setting DIAG_EN low.
Additionally, the device can keep power consumption to a minimum by setting DIAG_EN and IN low.
Table 2 applies when the DIAG_EN pin is enabled, and Table 3 applies when the DIAG_EN pin is disabled.
Table 2. Fault Truth Table
CONDITION
Normal
Overload or short to GND
IN
OUT
CRITERION
FAULT
L
L
N/A
H
H
H
N/A
H
H
L
current limit triggered
Thermal swing
(1)
N/A
L
See Table 1.
H
H
IOUT < l(ol,on)
L
FAULT clears when IN turns low
for a duration longer than tFAULT.
OR FAULT clears when the open
load is removed.
L (1)
H
VVS – VOUT < V(ol,off)
L
FAULT clears when IN is toggling
OR FAULT clears when the open
load is removed.
L
FAULT clears when IN turns low
for a duration longer than tFAULT.
OR FAULT clears when thermal
shutdown quits.
L
FAULT clears when IN turns low
for a duration longer than tFAULT.
OR FAULT clears when thermal
swing quits.
Open load or short to
battery
Thermal shutdown
FAULT RECOVERY
H
H
N/A
N/A
Thermal shutdown
triggered
Thermal swing triggered
An external pullup is required for open-load detection.
Table 3. DIAG_EN Disabled Condition
DIAG_EN
IN CONDITION
PROTECTIONS AND DIAGNOSTICS
ON
Diagnostics disabled, full protections
OFF
Diagnostics disabled, no protection
LOW
7.3.5 Full Diagnostics
7.3.5.1 Short-to-GND and Overload Detection
When the output is on, a short-to-GND or overload condition causes an overcurrent. If the overcurrent triggers
the internal or external current limit threshold, the fault condition is reported as FAULT pin = low.
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7.3.5.2 Open-Load Detection
7.3.5.2.1 Output On
When the output is on, the device recognizes an open-load fault if the current flowing through the output IOUT <
l(ol,on). For open-load detection when output is on, no external circuitry is required.
7.3.5.2.2 Output Off
When the output is off, the output is pulled down to GND if a load is connected. But if an open load occurs, the
output voltage is close to the supply voltage (VVS – VOUT < V(ol,off)), and the device recognizes an open-load fault.
There is always a leakage current I(ol,off) on the output due to the internal logic control path or external humidity,
corrosion, and so forth. As a result, TI recommends using an external pullup resistor to offset the leakage current
when an open load is detected. The recommended pullup resistance is 15 kΩ.
V(OL,off)
R(PULLUP)
VDS
Load
Figure 21. Open-Load Detection in Output OFF State
7.3.5.3 Short-to-Battery Detection
Short-to-battery has the same detection mechanism and behavior as open-load detection in the ON state and the
OFF state.
7.3.5.4 Thermal Fault Detection
To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing).
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Thermal behaviors after Short to GND
IN
TJ
T(SD)
T(hys)
T(SD,rst)
T(hys)
T(SW)
ICL
ICL(TSD)
IOUT
FAULT
Figure 22. Thermal Behavior Diagram
7.3.5.4.1 Thermal Shutdown
Thermal shutdown is active when the absolute temperature TJ > T(SD). When thermal shutdown occurs, the
output turns off.
7.3.5.4.2 Thermal Swing
Thermal swing activates when the power FET temperature sharply increases, that is, when ΔT = T(FET) – T(Logic) >
T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT = T(FET) –
T(Logic) < T(sw) – T(hys). The thermal swing function improves the reliability of the device when subjected to
repetitively fast thermal variation.
7.3.5.4.3 Fault Report Holding
When using PWM dimming, FAULT is easily cleared by the PWM falling edge. Even if the fault condition remains
all the time, FAULT is discontinuous. To avoid this unexpected fault report behavior, the device implements fault
report holding time. Figure 23 shows an issue that typically occurs during PWM dimming, the FAULT is cleared
unexpectedly even when the short-to-GND still exists. The TPS1H200A-Q1 device with fault-report holding
function allows the right behavior as shown in Figure 24.
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Short-to-GND
IN
Fault cleared
FAULT
Figure 23. Without Fault-Report Holding
Short-to-GND
IN
Fault not cleared
t < tFAULT
FAULT
Figure 24. With Fault-Report Holding
7.3.6 Full Protections
7.3.6.1 UVLO Protection
The device monitors the supply voltage, VVS, to prevent unpredicted behaviors when VVS is too low. When VVS
drops down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.
7.3.6.2 Inductive Load Switching Off Clamp
When an inductive load is switched off, the inductive reactance pulls the output voltage negative. However,
excessive negative voltage can cause the power FET to break down. To protect the power FET from breaking
down, an internal clamp (VDS(clamp)) is implemented.
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VS
VDS(clamp)
OUT
L
R
GND
+
Figure 25. Drain-to-Source Clamping Structure
IN
VVS
VOUT
VDS(clamp)
IOUT
t(decay)
Figure 26. Inductive-Load Switching-Off Diagram
7.3.6.3 Loss-of-GND Protection
When a loss-of-GND occurs, the output shuts down, regardless of whether the IN pin is high or low. The device
can protect against two ground-loss conditions, loss of device GND and loss of module GND.
7.3.6.4 Loss-of-Power-Supply Protection
When a loss-of-power-supply occurs, the output shuts down, regardless of whether the IN pin is high or low. For
a resistive or a capacitive load, the loss-of-power-supply has no risk. But for a charged inductive load, the current
is driven from all the logic control pins to maintain the inductance current. To protect the system in this condition,
TI recommends protection with an external free-wheeling diode.
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Vs
VS
High-Side Switch
IOs
MCU
OUT
D
L
Figure 27. Protection for Loss of Power Supply
7.3.6.5 Reverse-Current Protection
Reverse current occurs in two conditions: short to supply and reverse polarity.
• When a short to the supply occurs, there is only reverse current through the body diode. IR(1) specifies the
limit of the reverse current.
• In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin.
IR(2) specifies the limit of the reverse current.
To protect the device, TI recommends using two types of external circuitry.
• Adding a blocking diode (method 1). The device and load are protected when in reverse polarity.
• Adding a GND network (method 2). The reverse current through the device GND is blocked. The reverse
current through the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a
GND network. The recommended configuration is a 1-kΩ resistor in parallel with a diode that is less than 100
mA.
Load
Figure 28. Reverse-Current External Protection Method 1
22
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Load
Figure 29. Reverse-Current External Protection Method 2
7.3.6.6 MCU I/O Protection
TI recommends using series resistors to protect the microcontroller, for example, 4.7-kΩ when using a 3.3-V
microcontroller and 10-kΩ for a 5-V microcontroller.
IOs
TPS1H200-Q1
MCU
Figure 30. MCU I/O External Protection
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7.4 Device Functional Modes
7.4.1 Working Modes
The device has three working modes, the normal mode, the standby mode, and the standby mode with
diagnostics, as shown in Figure 31.
Standby Mode
(IN low, DIAG_EN low)
DIAG_EN high to low
IN low to high
DIAG_EN low
AND
IN high to low
AND
t > t(off,deg)
DIAG_EN low to high
Standby Mode
With DIAG
IN low to high
Normal Mode
(IN high)
(IN low, DIAG_EN high)
IN high to low
AND
DIAG_EN high
AND
t > t(off,deg)
Figure 31. Working Modes
7.4.1.1 Normal Mode
When IN is high, the device enters normal mode.
7.4.1.2 Standby Mode
When IN is low and DIAG_EN is low, the device enters standby mode with ultra-low power consumption.
7.4.1.3 Standby Mode With Diagnostics
When IN is low and DIAG_EN is high, the device enters standby mode with diagnostics. The device still supports
open-load and short-to-battery detection even when IN is low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS1H200A-Q1 device is a smart high-side switch, with an internal charge pump and single-channel
integrated NMOS power FET. The adjustable current limit function greatly improves the reliability of the whole
system. Full diagnostic features enable intelligent control of the load. The TPS1H200A-Q1 device applies for a
wide variety of resistive, inductive, and capacitive loads, including LEDs, relays, and submodules.
8.2 Typical Application
Figure 32 shows an example of how to design the external circuitry parameters.
Supply Voltage
R(SER)
VS
IN
R(SER)
DIAG_EN
OUT
3.3/5V
MCU
R(SER)
General Resistive, Capacitive,
Inductive Loads
R(pullup)
FAULT
DELAY
C(DELAY)
CL
GND
R(CL)
Figure 32. Typical Application Circuitry
8.2.1 Design Requirements
• VVS range from 6 V to 18 V
• Nominal current of 500 mA
• Expected current limit value of 2 A
• Thermal sensitive system. When current limit occurs, the output latches off after 0.2 seconds. The 0.2
seconds is to ensure the safe start-up for a capacitive load, clamping the inrush current but without latch-off
during start-up.
• Full diagnostics with 5-V MCU, including ON state open-load detection, short-to-GND, or overcurrent
detection, and thermal shutdown detection
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Typical Application (continued)
8.2.2 Detailed Design Procedure
To set the adjustable current limit value at 2 A, calculate R(CL) as follows:
VCL th u K CL
0.8 u 2500
R CL
1000 Ö
I OUT
2
(3)
To set the adjustable latch-off delay at 0.2 s, calculate C(DELAY) as follows:
t dl
t CL
C DELAY
deg
t dl1
t dl2
I dl chg u t dl2
V dl ref
0.2»t dl2
4.5 u 0.2
u 10 -6
1.45
0.62 PF
(4)
TI recommends R(SER) = 10 kΩ for a 5-V MCU, and R(pullup) = 10 kΩ as the pullup resistor.
8.2.3 Application Curves
The following curves are test examples of hard-short conditions. The load is 0.1 A and the current limit value is
0.6 A. Figure 33 shows a waveform of the latch-off mode. Figure 34 shows a waveform of the auto-retry mode.
Figure 33. Hard-Short Condition in Latch-Off Mode
26
Figure 34. Hard-Short Condition in Auto-Retry Mode
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9 Power Supply Recommendations
The device applies to 12-V and 24-V applications. The normal power supply connection is a 12-V or 24-V
system.
10 Layout
10.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 175°C. If the output current is high, the power dissipation
may be large. However, the PCB layout is very important. A good PCB design optimizes heat transfer, which is
essential for the long-term reliability of the device.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heatflow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when no heat sinks are attached to the PCB on the other side of the board opposite the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage must be at least 85%.
10.2 Layout Example
IN
1
8
VS
2
7
OUT
FAULT
3
6
GND
CL
4
5
DELAY
DIAG_EN
Thermal Pad
Figure 35. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS1H000-Q1 Evaluation Module (EVM) User's Guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS1H200AQDGNRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HVSSOP
DGN
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
1EWX
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS1H200AQDGNRQ1 HVSSOP
DGN
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS1H200AQDGNRQ1
HVSSOP
DGN
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.846
1.646
TYPICAL
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.846)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(2.15)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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