Texas Instruments | TPS7A24 200-mA, 18-V, Ultra-Low IQ, Low-Dropout Voltage Regulator (Rev. A) | Datasheet | Texas Instruments TPS7A24 200-mA, 18-V, Ultra-Low IQ, Low-Dropout Voltage Regulator (Rev. A) Datasheet

Texas Instruments TPS7A24 200-mA, 18-V, Ultra-Low IQ, Low-Dropout Voltage Regulator (Rev. A) Datasheet
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TPS7A24
SBVS386A – AUGUST 2019 – REVISED DECEMBER 2019
TPS7A24 200-mA, 18-V, Ultra-Low IQ, Low-Dropout Voltage Regulator
1 Features
3 Description
•
•
•
The TPS7A24 low-dropout (LDO) linear voltage
regulator supports a 2.4-V to 18-V input voltage
range with ultra-low quiescent current (IQ). These
features help modern appliances meet increasingly
stringent energy requirements and help extend
battery life in portable-power solutions.
1
•
•
•
•
•
•
•
Ultra-low IQ: 2.0 µA
Input voltage: 2.4 V to 18 V
Output voltage options available:
– Fixed: 1.25 V to 5.5 V
– Adjustable: 1.24 V to 17.75 V
2% accuracy over temperature
Low dropout: 250 mV (max) at 200 mA
Active overshoot pulldown protection
Thermal shutdown and overcurrent protection
Operating junction temperature: –40°C to +125°C
Stable with 1-µF output capacitors
Package: 5-pin SOT-23
The TPS7A24 LDO operates more efficiently than
standard linear regulators because the maximum
dropout voltage is less than 250 mV at 200 mA of
current. This maximum dropout voltage allows for
92.8% efficiency from a 3.55-V input voltage (VIN) to
a 3.3-V output voltage (VOUT).
2 Applications
•
•
•
•
•
•
•
The TPS7A24 is available in both fixed and
adjustable versions. The fixed-voltage version
eliminates external resistors and minimizes printed
circuit board (PCB) area. For more flexibility or higher
output voltages, the adjustable version uses feedback
resistors to set the output voltage from 1.24 V to
17.75 V. Both versions have 2% output regulation
accuracy that provides precision regulation for
microcontroller (MCU) references.
Smoke and heat detectors
Thermostats
Motion detectors (PIR, uWave, and so forth)
Cordless power tools
Appliance battery packs
Electricity meters
Water meters
Device Information(1)
PART NUMBER
TPS7A24
PACKAGE
SOT-23 (5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the package option addendum
at the end of the datasheet.
Typical Application Circuit
10
VOUT
OUT
IN
R1
EN
TPS7A24
FB/NC
CIN
COUT
R2
GND
Tj
-50qC
-40qC
0qC
25qC
8
Quiescent Current (PA)
VIN
Quiescent Current vs Input Voltage
(VOUT = 1.24 V, IOUT = 0 A)
85qC
125qC
150qC
6
4
2
0
2
4
6
8
10
12
Input Voltage (V)
14
16
18
D005
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A24
SBVS386A – AUGUST 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagrams ....................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 16
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Examples................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2019) to Revision A
•
2
Page
Changed document status from advance information to production data ............................................................................. 1
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5 Pin Configuration and Functions
TPS7A24: DBV Package (Adjustable)
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
5
4
TPS7A24: DBV Package (Fixed)
5-Pin SOT-23
Top View
OUT
IN
1
GND
2
EN
3
FB
Not to scale
5
OUT
4
NC
Not to scale
Pin Functions
PIN
DBV
(Adjustable)
DBV
(Fixed)
I/O
DESCRIPTION
EN
3
3
Input
Enable pin. Drive EN greater than VEN(HI) to enable the regulator. Drive EN
less than VEN(LOW) to put the regulator into low-current shutdown. Do not float
this pin. If not used, connect EN to IN.
FB
4
—
Input
Feedback pin. Input to the control-loop error amplifier. This pin is used to set
the output voltage of the device with the use of external resistors. For
adjustable-voltage version devices only.
GND
2
2
—
NAME
Ground pin.
IN
1
1
Input
Input pin. For best transient response and to minimize input impedance, use
the recommended value or larger capacitor from IN to ground as listed in the
Recommended Operating Conditions table. Place the input capacitor as
close to the IN and GND pins of the device as possible.
NC
—
4
—
No internal connection. For fixed-voltage version devices only. This pin can
be floated but the device has better thermal performance with this pin tied to
GND.
Output
Output pin. A capacitor is required from OUT to ground for stability. For best
transient response, use the nominal recommended value or larger capacitor
from OUT to ground. Follow the recommended capacitor value as listed in
the Recommended Operating Conditions table. Place the output capacitor as
close to the OUT and GND pins of the device as possible.
OUT
5
5
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage (2)
MIN
MAX
VIN
–0.3
20
VOUT
–0.3
VIN + 0.3 (3)
VFB
–0.3
5.5
–0.3
20
VEN
Current
Maximum output
Temperature
(1)
(2)
(3)
Internally limited
UNIT
V
A
Operating junction, TJ
–50
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages with respect to GND.
VIN + 0.3 V or 20 V (whichever is smaller).
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VIN
Input voltage
2.4
18
V
VOUT
Output voltage (adjustable version)
1.24
18 - VDO
V
VOUT
Output voltage (fixed version)
1.25
5.5
V
IOUT
Output current
0
200
mA
VEN
Enable voltage
0
CIN (1)
Input capacitor
COUT (1)
Output capacitor
TJ
Operating junction temperature
(1)
18
1
1
V
μF
2.2
–40
100
μF
125
°C
All capacitor values are assumed to derate to 50% of the nominal capacitor value.
6.4 Thermal Information
TPS7A24
THERMAL METRIC (1)
DBV (SOT23-5)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
167.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
86.7
°C/W
RθJB
Junction-to-board thermal resistance
38.4
°C/W
ψJT
Junction-to-top characterization parameter
14.5
°C/W
ψJB
Junction-to-board characterization parameter
38.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
specified at TJ = –40°C to + 125°C, VIN = VOUT(nom) + 0.5 V or VIN = 2.4 V (whichever is greater), FB tied to OUT, IOUT = 1 mA,
VEN = 2 V, and CIN = 1 μF, COUT = 2.2 μF ceramic (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
Adjustable version, VOUT = VFB
VOUT
Output voltage accuracy
VFB
Feedback voltage
Adjustable version only
ΔVOUT(ΔVIN)
Line regulation (1)
(VOUT(nom) + 0.5 V or 2.4 V) ≤ VIN ≤ 18 V
ΔVOUT(ΔIOUT)
Load regulation
1 mA ≤ IOUT ≤ 200 mA
IGND
Ground pin current
ISHUTDOWN
Shutdown current
VEN ≤ 0.4 V, VIN = 2.4 V, Iout = 0 mA
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
IFB
FB pin current
VDO
Dropout voltage (2)
PSRR
Power-supply rejection
ratio
Fixed output versions
TYP
MAX
UNIT
1.24
1.26
V
2
%
–0.25
0.25
%
–1
1
%
–2
1.24
IOUT = 0 mA
2
IOUT = 1 mA
15
250
V
4.5
µA
325
600
nA
410
620
mA
10
nA
IOUT = 100 mA
110
160
IOUT = 200 mA
160
250
f = 10 Hz
75
f = 100 Hz
70
f = 1 kHz
62
Vn
Output noise voltage
BW = 10 Hz to 100 kHz, VOUT = 1.24 V
VUVLO(RISING)
UVLO threshold rising
VIN rising
VUVLO(HYS)
UVLO hysteresis
VUVLO(FALLING)
UVLO threshold falling
VEN(HI)
Enable pin high-level input
Device enabled
voltage
VEN(LOW)
Enable pin low-level input
voltage
Device disabled
IEN
EN pin current
VEN = 18 V
TSD(shutdown)
Thermal shutdown
temperature
TSD(reset)
Thermal shutdown reset
temperature
(1)
(2)
MIN
1.22
dB
300
1.95
2.15
mV
μVRMS
2.35
70
VIN falling
1.85
2.09
V
mV
2.25
0.9
V
V
0.4
V
10
nA
Shutdown, temperature increasing
165
°C
Reset, temperature decreasing
145
°C
Vout(nom) + 0.5 V or 2.4 V (whichever is greater).
VDO is measured with VIN = 0.97 × VOUT(nom) for fixed output voltage versions. VDO is not measured for fixed output voltage versions
when VOUT ≤ 2.5 V. For the adjustable output device, VDO is measured with VFB = 0.97 × VFB(nom).
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 0.9 V, CIN = 2.2 µF, COUT = 2.2 μF, and VIN = VOUT(typ) + 0.8 V or 2.4 V
(whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
0.4
Output Voltage Accuracy (%)
0.8
0.6
0.4
85qC
125qC
150qC
0.2
0
-0.2
-0.4
-0.6
-0.8
VOUT)
Tj
-50qC
-40qC
0qC
25qC
0.3
Output Voltage Accuracy (
1
0.1
TJ
-50°C
-40°C
0.2
2
-0.1
-0.2
-0.3
-0.4
-0.5
4
6
8
10
12
Input Voltage (V)
14
16
0
18
0.025
0.05
D002
0.075 0.1 0.125
Output Current (A)
0.15
0.175
0.2
VOUT = 1.24 V
Figure 2. Load Regulation vs IOUT
Figure 1. Line Regulation vs VIN
200
135
TJ
120
-50°C
-40°C
105
0°C
25°C
85°C
125°C
TJ
180
150°C
-50°C
-40°C
160
Dropout Voltage (V)
Dropout Voltage (mV)
150°C
0
IOUT = 1 mA
90
75
60
45
0°C
25°C
85°C
125°C
150°C
140
120
100
80
60
30
40
15
20
0
0
2
4
6
8
10
12
Input Voltage (V)
14
16
18
2
4
6
8
10
12
Input Voltage (V)
IOUT = 10 mA
240
225
210
Dropout Voltage (V)
200
175
150
125
100
75
TJ
-50°C
-40°C
25
0°C
25°C
16
18
0.175
0.2
Figure 4. Dropout Voltage vs VIN
250
50
14
IOUT = 100 mA
Figure 3. Dropout Voltage vs VIN
Dropout Voltage (V)
85°C
125°C
-0.6
-1
85°C
125°C
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
180
150
120
90
60
30
150°C
0
0
2
4
6
8
10
12
Input Voltage (V)
14
16
18
0
IOUT = 200 mA
0.025
0.05
0.075 0.1 0.125
Output Current (A)
0.15
VIN = 2.4 V
Figure 5. Dropout Voltage vs VIN
6
0°C
25°C
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Figure 6. Dropout Voltage vs IOUT
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 0.9 V, CIN = 2.2 µF, COUT = 2.2 μF, and VIN = VOUT(typ) + 0.8 V or 2.4 V
(whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
0.54
240
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
180
150
120
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
0.52
0.5
Current Limit (A)
Dropout Voltage (V)
210
90
0.48
0.46
0.44
0.42
60
0.4
30
0.38
0
0.36
0
0.025
0.05
0.075 0.1 0.125
Output Current (A)
0.15
0.175
0.2
2
4
6
8
10
12
Input Voltage (V)
14
16
18
VIN = 18 V
Figure 7. Dropout Voltage vs IOUT
Figure 8. Current Limit vs VIN
30
10
Ground Current (PA)
25
20
85qC
125qC
150qC
Tj
-50qC
-40qC
0qC
25qC
8
Quiescent Current (PA)
Tj
-50qC
-40qC
0qC
25qC
15
10
6
4
2
5
0
2
4
6
8
10
12
Input Voltage (V)
14
16
0
18
2
4
VOUT = 1.24 V, IOUT = 1 mA
6
14
16
18
D005
Figure 10. IQ vs VIN
36
240
28
24
20
16
12
8
Tj
-50qC
-40qC
210
Ground Current (PA)
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
32
0qC
25qC
85qC
125qC
150qC
180
150
120
90
60
30
4
0
2.4
8
10
12
Input Voltage (V)
VOUT = 1.24 V, IOUT = 0 A
Figure 9. IGND vs VIN
Quiescent Current (PA)
85qC
125qC
150qC
0
2.7
3
3.3
3.6
3.9
4.2
Input Voltage (V)
4.5
4.8
5.1
0
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Output Current (A)
VOUT = 3.3 V, IOUT = 0 A
0.2
VOUT = 1.24 V
Figure 11. IQ vs VIN
Figure 12. IGND vs IOUT
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 0.9 V, CIN = 2.2 µF, COUT = 2.2 μF, and VIN = VOUT(typ) + 0.8 V or 2.4 V
(whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
0.8
2.3
VUVLO- (VIN Falling)
VUVLO+ (VIN Rising)
0.7
2.2
Input Voltage (V)
Enable Threshold (V)
VEN(LOW)
VEN(HIGH)
0.6
0.5
0.4
-50
2.1
2
-25
0
25
50
75
Temperature (qC)
100
125
1.9
-50
150
-25
VOUT = 1.24 V, 2.4 V ≤ V IN ≤ 18 V
Figure 13. VEN vs Temperature
100
125
150
Figure 14. UVLO Thresholds vs Temperature
10
IOUT
10 mA
100 mA
200 mA
90
80
70
60
50
40
30
20
10
5
Output Voltage Noise (PV —Hz)
Power Supply Rejection Ratio (dB)
25
50
75
Temperature (qC)
VOUT = 1.24 V, IOUT = 1 mA
100
0
10
0
2
1
0.5
0.2
0.1
0.05
0.02
0.01
100
1k
10k
100k
Frequency (Hz)
1M
VOUT = 1.24 V, CIN = 0 μF, COUT = 1 μF
Figure 15. PSRR vs Frequency and IOUT
10M
0.005
10
IOUT
0.01A, RMS Noise = 280.2 PV RMS
0.1A, RMS Noise = 283.2 PV RMS
0.2 A, RMS Noise = 285.2 PV RMS
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUT = 1.24 V, CIN = 1 μF, COUT = 1 μF, CFF = 10 nF,
VRMS BW = 10 Hz to 100 kHz
Figure 16. Output Noise (Vn) vs Frequency and IOUT
8
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7 Detailed Description
7.1 Overview
The TPS7A24 is an 18-V, low quiescent current, low-dropout (LDO) linear regulator. The low IQ performance
makes the TPS7A24 an excellent choice for battery-powered or line-power applications that are expected to
meet increasingly stringent standby-power standards. The fixed-output versions have the advantage of providing
better accuracy with fewer external components, whereas the adjustable version has the flexibility for a far wider
output voltage range.
The 2% accuracy over temperature makes this device an excellent choice for meeting a wide range of
microcontroller power requirements.
For increased reliability, the TPS7A24 also incorporates overcurrent, overshoot pulldown, and thermal shutdown
protection. The operating junction temperature is –40°C to +125°C, and adds margin for applications concerned
with higher working ambient temperatures.
7.2 Functional Block Diagrams
TPS7A2401
(Adjustable Version)
OUT
IN
Current
Limit
Thermal
Shutdown
±
FB
+
UVLO
EN
Band-Gap
Reference
GND
Logic
Figure 17. Adjustable Version Block Diagram
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Functional Block Diagrams (continued)
TPS7A24
(Fixed Version)
OUT
IN
Current
Limit
Thermal
Shutdown
±
R1
+
UVLO
R2
EN
Band-Gap
Reference
GND
Logic
Figure 18. Fixed Version Block Diagram
7.3 Feature Description
7.3.1 Output Enable
The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable
pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than
the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the
enable pin to the input of the device.
7.3.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.
The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output
voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the
nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
VDO
RDS(ON) =
IRATED
(1)
7.3.3 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme limits
the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns
off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output
current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application report.
10
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Feature Description (continued)
Figure 19 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
IOUT
0V
IRATED
0 mA
ICL
Figure 19. Current Limit
7.3.4 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.5 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
When the thermal limit is triggered with load currents near the value of the current limit, the output may oscillate
prior to the output switching off.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.3.6 Active Overshoot Pulldown Circuitry
This device has pulldown circuitry connected to VOUT. This circuitry is a 100-μA current sink, in series with a
5.5-kΩ resistor, controlled by VEN. When VEN is below VEN(LOW), the pulldown circuitry is disabled and the LDO
output is in high-impedance mode.
If the output voltage is more than 2% above nominal voltage when VEN ≥ VEN(LOW), the pulldown circuitry turns on
and the output is pulled down until the output voltage is within 2% from the nominal voltage. This feature helps
reduce overshoot during the transient response.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to
less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off and internal circuits are shutdown.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Adjustable Device Feedback Resistors
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)
(2)
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series
resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)
(3)
8.1.2 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are
recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0Grated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5Vrated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.3 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast load transient or line transients are anticipated or if the device is located
several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
The effective output capacitance value is recommended to not exceed 50 µF.
8.1.4 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
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Application Information (continued)
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
Figure 20 shows one approach for protecting the device.
Schottky Diode
IN
CIN
Internal Body Diode
OUT
Device
COUT
GND
Figure 20. Example Circuit for Reverse Current Protection Using a Schottky Diode
Figure 21 shows another, more commonly used, approach in high input voltage applications.
IN
CIN
OUT
Device
COUT
GND
Figure 21. Reverse Current Prevention Using a Diode Before the LDO
8.1.5 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to
the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF
can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and
Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.
8.1.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit
board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no
other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. Equation 4 calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(4)
NOTE
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use the
minimum input voltage required for correct output regulation.
14
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Application Information (continued)
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to Equation 5, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA).
TJ = TA + (RθJA × PD)
(5)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.7 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi
metrics are determined to be significantly independent of the copper area available for heat-spreading. The
Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ). As described in , use the junction-to-top characterization parameter
(ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. As
described in , use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm
from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
where:
• PD is the dissipated power
• TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(6)
where
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(7)
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application report.
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Application Information (continued)
8.1.8 Special Consideration for Line Transients
During a line transient, the response of this LDO to a very large or fast input voltage change can cause a brief
shutdown lasting up to a few hundred microseconds from the voltage transition. This shutdown can be avoided
by reducing the voltage step size, increasing the transition time, or a combination of both. Figure 22 provides a
boundary to follow to avoid this behavior. If necessary, reduce slew rate and the voltage step size to stay below
the curve.
2
1.8
Slew Rate (V/Psec)
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
VIN Delta
0
0
1
2
3
4
5 6 7 8 9 10 11 12 13 14 15
Input Voltage Step Size (V)
Figure 22. Recommended Input Voltage Step and Slew Rate in a Line Transient
8.2 Typical Application
VOUT
OUT
IN
VIN
R1
EN
TPS7A24
FB/NC
CIN
COUT
R2
GND
Figure 23. Generating a 3.3-V Rail From a Multicell Power Bank
8.2.1 Design Requirements
Table 2 summarizes the design requirements for Figure 23.
Table 2. Design Parameters
PARAMETER
16
DESIGN VALUES
VIN
5.3 V
VOUT
3.3 V ±2%
I(IN) (no load)
< 5 µA
IOUT (max)
200 mA
TA
57.88°C (max)
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8.2.2 Detailed Design Procedure
Select a 3.3-V output, fixed or adjustable device to generate the 3.3-V rail. The fixed-version LDO has internal
feedback divider resistors, and thus has lower quiescent current. The adjustable-version LDO requires external
feedback divider resistors, and is described in the Selecting Feedback Divider Resistors section.
8.2.2.1 Transient Response
As with any regulator, increasing the output capacitor value reduces over- and undershoot magnitude, but
increases transient response duration.
8.2.2.2 Selecting Feedback Divider Resistors
For this design example, VOUT is set to 5 V. The following equations set the output voltage:
VOUT = VFB × (1 + R1 / R2)
R1 + R2 ≤ VOUT / (IFB × 100)
(8)
(9)
For improved output accuracy, use Equation 9 and IFB(TYP) = 10 nA as listed in the Electrical Characteristics table
to calculate the upper limit for series feedback resistance, R1 + R2 ≤ 5 MΩ.
The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (VFB = 1.24 V as
listed in the Electrical Characteristics table). Use Equation 8 to determine the ratio of R1 / R2 = 1.66. Use this
ratio and solve Equation 9 for R2. Now calculate the upper limit for R2 ≤ 1.24 MΩ. Select a standard value
resistor of R2 = 1.18 MΩ.
Reference Equation 8 and solve for R1:
R1 = (VOUT / VFB – 1) × R2
(10)
From Equation 10, R1 = 1.96 MΩ can be determined. From Equation 8, select VOUT = 3.299 V.
8.2.2.3 Thermal Dissipation
Junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use Equation 11 to calculate the power dissipation. Multiply PD by RθJA and add the
ambient temperature (TA), as Equation 12 shows, to calculate the junction temperature (TJ).
PD = (IGND+ IOUT) × (VIN – VOUT)
TJ = RθJA × PD + TA
(11)
(12)
Equation 13 calculates the maximum ambient temperature. Equation 14 calculates the maximum ambient
temperature for typical design applications.
TA(MAX) = TJ(MAX) – (RθJA × PD)
TA(MAX) = 125°C – [167.8°C/W × (5.3 V – 3.3 V) × 0.2A] = 57.88°C
(13)
(14)
8.2.3 Application Curve
12
10
11
0
10
-10
9
-20
8
-30
7
-40
6
-50
5
-60
Input Voltage (V)
AC-Coupled Output Voltage (mV)
20
4
VOUT
VIN
-70
3
-80
-450 -300 -150
0
150 300 450
Time (µsec)
600
750
2
900 1050
Figure 24. Line Transient (4.3 V to 5.3 V)
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9 Power Supply Recommendations
The device is designed to operate with an input supply range of 2.4 V to 18 V. If the input supply is noisy,
additional input capacitors with low ESR can help improve output noise performance. Connect a low output
impedance power supply to the input pin of the TPS7A24. In order to optimize regulation, refer to the Feature
Description section for more information on operation modes and performance features.
10 Layout
10.1 Layout Guidelines
•
•
•
Place input and output capacitors as close to the device pins as possible
Use copper planes for device connections to optimize thermal performance
Place thermal vias around the device to distribute heat
10.2 Layout Examples
VIN
GND
PLANE
VOUT
COUT
CIN
R1
GND
PLANE
R2
EN
Figure 25. Adjustable Version Layout Example
VOUT
VIN
1
CIN
5
COUT
2
3
4
EN
GND PLANE
Represents via used for
application specific connections
Figure 26. Fixed Version Layout Example
18
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature (1)
(1)
PRODUCT
VOUT
TPS7A24xx(x)yyyz
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are
used in the ordering number; for output voltages with a resolution of 50 mV, three digits are used
(for example, 28 = 2.8 V; 125 = 1.25 V). 01 indicates adjustable output version.
yyy is the package designator.
z is the package quantity. R is for large quantity reel
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
PTPS7A2401DBVR
ACTIVE
SOT-23
DBV
5
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
TBD
Call TI
Call TI
-40 to 125
Device Marking
(4/5)
TPS7A2401DBVR
PREVIEW
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
TPS7A24125DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1XTF
TPS7A2418DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1XLF
TPS7A2425DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1XKF
TPS7A2430DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1XJF
TPS7A2433DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1XHF
TPS7A2436DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1XIF
TPS7A2450DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1XGF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Dec-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS7A24125DBVR
SOT-23
DBV
5
3000
178.0
9.0
TPS7A2418DBVR
SOT-23
DBV
5
3000
178.0
TPS7A2425DBVR
SOT-23
DBV
5
3000
178.0
TPS7A2430DBVR
SOT-23
DBV
5
3000
TPS7A2433DBVR
SOT-23
DBV
5
TPS7A2436DBVR
SOT-23
DBV
TPS7A2450DBVR
SOT-23
DBV
3.3
3.2
1.4
4.0
8.0
Q3
9.0
3.3
3.2
1.4
4.0
8.0
Q3
9.0
3.3
3.2
1.4
4.0
8.0
Q3
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jan-2020
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7A24125DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS7A2418DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS7A2425DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS7A2430DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS7A2433DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS7A2436DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS7A2450DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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