Texas Instruments | UCC21750 10-A Source/Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI (Rev. B) | Datasheet | Texas Instruments UCC21750 10-A Source/Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI (Rev. B) Datasheet

Texas Instruments UCC21750 10-A Source/Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI (Rev. B) Datasheet
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UCC21750
SLUSD78B – OCTOBER 2018 – REVISED DECEMBER 2019
UCC21750 10-A Source/Sink Reinforced Isolated Single Channel Gate Driver
for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI
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5.7-kVRMS single channel isolated gate driver
SiC MOSFETs and IGBTs up to 2121Vpk
33-V maximum output drive voltage (VDD-VEE)
±10-A drive strength and split output
150-V/ns minimum CMTI
200-ns response time fast DESAT protection
4-A Internal active miller clamp
400-mA soft turn-off when fault happens
Isolated analog sensor with PWM output for
– Temperature sensing with NTC, PTC or
thermal diode
– High voltage DC-Link or phase voltage
Alarm FLT on over current and reset from
RST/EN
Fast enable/disable response on RST/EN
Reject <40-ns noise transient and pulse on input
pins
12-V VDD UVLO with power good on RDY
Inputs/outputs with over/under-shoot transient
voltage Immunity up to 5 V
130-ns (maximum) propagation delay and 30-ns
(maximum) pulse/part skew
SOIC-16 DW package with creepage and
clearance distance > 8mm
Operating junction temperature –40°C to 150°C
2 Applications
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Industrial motor drives
Server, telecom, and industrial power supplies
Uninterruptible power supplies (UPS)
Solar inverters
3 Description
The input side is isolated from the output side with
SiO2 capacitive isolation technology, supporting up to
1.5-kVRMS working voltage, 12.8-kVPK surge immunity
with longer than 40 years Isolation barrier life, as well
as providing low part-to-part skew, and >150V/ns
common mode noise immunity (CMTI).
The UCC21750 includes the state-of-art protection
features, such as fast overcurrent and short circuit
detection, shunt current sensing support, fault
reporting, active miller clamp, and input and output
side power supply UVLO to optimize SiC and IGBT
switching behavior and robustness. The isolated
analog to PWM sensor can be utilized for easier
temperature or voltage sensing, further increasing the
drivers' versatility and simplifying the system design
effort, size and cost.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC21750
DW SOIC-16
10.3 mm × 7.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Device Pin Configuration
AIN
1
16
APWM
DESAT
2
15
VCC
COM
3
14
RST/EN
OUTH
4
13
FLT
VDD
5
12
RDY
OUTL
6
11
,1Å
CLMPI
7
10
IN+
VEE
8
ISOLATION BARRIER
1 Features
9
GND
Not to scale
The UCC21750 is a galvanic isolated single channel
gate driver designed for SiC MOSFETs and IGBTs up
to 2121-V DC operating voltage with advanced
protection
features,
best-in-class
dynamic
performance and robustness. UCC21750 has up to
±10-A peak source and sink current.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC21750
SLUSD78B – OCTOBER 2018 – REVISED DECEMBER 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Power Ratings........................................................... 6
Insulation Specifications............................................ 7
Safety-Related Certifications..................................... 8
Safety Limiting Values .............................................. 8
Electrical Characteristics........................................... 9
Switching Characteristics ...................................... 11
Insulation Characteristics Curves ......................... 12
Typical Characteristics .......................................... 13
Parameter Measurement Information ................ 17
7.1 Propagation Delay................................................... 17
7.2 Input Deglitch Filter ................................................. 19
7.3 Active Miller Clamp ................................................. 20
7.4 Under Voltage Lockout (UVLO) .............................. 21
7.5 Desaturation (DESAT) Protection ........................... 23
8
Detailed Description ............................................ 25
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
25
26
26
33
Applications and Implementation ...................... 34
9.1 Application Information............................................ 34
9.2 Typical Application .................................................. 34
10 Power Supply Recommendations ..................... 45
11 Layout................................................................... 46
11.1 Layout Guidelines ................................................. 46
11.2 Layout Example .................................................... 47
12 Device and Documentation Support ................. 48
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
48
48
48
48
48
48
13 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2019) to Revision B
•
2
Page
Changed marketing status from Advance Information to production data. ............................................................................ 1
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5 Pin Configuration and Functions
UCC21750
DW SOIC (16)
Top View
1
16
APWM
DESAT
2
15
VCC
COM
3
14
RST/EN
OUTH
4
13
FLT
VDD
5
12
RDY
OUTL
6
11
,1Å
CLMPI
7
10
IN+
VEE
8
ISOLATION BARRIER
AIN
9
GND
Not to scale
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Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
AIN
1
I
Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity
DESAT
2
I
Desaturation current protection input
COM
3
P
Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET
OUTH
4
O
Gate driver output pull up
VDD
5
P
Positive supply rail for gate drive voltage, Bypassing a >220nF capacitor to COM to support specified gate
driver source peak current capability
OUTL
6
O
Gate driver output pull down
CLMPI
7
I
Internal Active miller clamp, connecting this pin directly to the gate of the power transistor
VEE
8
P
Negative supply rail for gate drive voltage. Bypassing a >220nF capacitor to COM to support specified gate
driver sink peak current capability
GND
9
P
Input power supply and logic ground reference
IN+
10
I
Non-inverting gate driver control input
IN–
11
I
Inverting gate driver control input
RDY
12
O
Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other
RDY signals
FLT
13
O
Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be
paralleled with other faults
I
The RST/EN serves two purposes:
1) Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to
low;
2) Resets the DESAT condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns.
A reset of signal FLT is asserted at the rising edge of terminal RST/EN.
For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The
FET is turned off by a general turn-off, if terminal EN is set to low.
RST/EN
14
VCC
15
P
Input power supply from 3V to 5.5V, bypassing a >100nF capacitor to GND
APWM
16
O
Isolated Analog Sensing PWM output
(1)
4
P = Power, G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
MIN
MAX
UNIT
–0.3
6
V
–0.3
36
V
–17.5
0.3
V
36
V
VCC
VCC – GND
VDD
VDD – COM
VEE
VEE – COM
VMAX
VDD – VEE
–0.3
IN+, IN–, RST/EN
DESAT
Reference to COM
AIN
Reference to COM
OUTH, OUTL , CLMPI
DC
GND–0.3
VCC
V
Transient, less than 100 ns (2)
GND–5.0
VCC+5.0
V
COM–0.3
VDD+0.3
V
–0.3
5
V
DC
VEE–0.3
VDD
V
Transient, less than 100 ns (2)
VEE–5.0
VDD+5.0
V
GND–0.3
VCC
V
RDY, FLT, APWM
IFLT, IRDY
FLT, and RDY pin input current
20
mA
IAPWM
APWM pin output current
20
mA
TJ
Junction temperature range
–40
150
°C
Tstg
Storage temperature range
–65
150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Values are verified by characterization on bench.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
PARAMETER
MIN
MAX
UNIT
VCC
VCC–GND
3.0
5.5
V
VDD
VDD–COM
13
33
V
VMAX
VDD–VEE
–
33
V
IN+, IN–, RST/EN
Reference to GND
AIN
Reference to COM
tRST/EN
Minimum pulse width that reset the fault
TA
Ambient Temperature
–40
125
°C
TJ
Junction temperature
–40
150
°C
High level input voltage
0.7×VCC
VCC
Low level input voltage
0
0.3×VCC
0.6
4.5
V
V
1000
ns
6.4 Thermal Information
UCC21750
THERMAL METRIC (1)
DW (SOIC)
UNIT
16
RθJA
Junction-to-ambient thermal resistance
68.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Thermal Information (continued)
UCC21750
THERMAL METRIC (1)
DW (SOIC)
UNIT
16
RθJB
Junction-to-board thermal resistance
32.9
°C/W
ψJT
Junction-to-top characterization parameter
14.1
°C/W
ψJB
Junction-to-board characterization parameter
32.3
°C/W
6.5 Power Ratings
PARAMETER
PD
Maximum power dissipation (both
sides)
PD1
Maximum power dissipation by
transmitter side
PD2
Maximum power dissipation by
receiver side
6
TEST CONDITIONS
VCC = 5V, VDD-COM = 20V, COM-VEE = 5V, IN+/- = 5V, 150kHz,
50% Duty Cycle for 10nF load, Ta=25oC
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Value
UNIT
985
mW
20
mW
965
mW
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6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
External clearance (1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the
package surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (Internal clearance) of the
double insulation (2 × 0.0085 mm)
> 17
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
According to IEC 60664–1
CLR
Overvoltage Category per IEC 60664–1
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 (2)
VIORM
Maximum repetitive peak isolation voltage AC voltage (bipolar)
VIOWM
Maximum isolation working voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage (3)
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Insulation resistance, input to output (5)
RIO
2121
VPK
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test
1500
VRMS
DC voltage
2121
VDC
VTEST=VIOTM, t = 60 s (qualification test)
8000
VTEST=1.2 x VIOTM, t = 1 s (100% production test)
9600
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
Method a: After I/O safety test subgroup 2/3, Vini =
VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK,
tm = 10 s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394
VPK, tm = 10 s
≤5
Method b1: At routine test (100% production) and
preconditioning (type test) Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
≤5
VIO = 0.5 sin (2πft), f = 1 MHz
~1
VIO = 500 V, TA = 25°C
≥ 1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
≥ 1011
VIO = 500 V at TS = 150°C
≥ 109
Pollution degree
2
Climatic category
40/125/21
VPK
VPK
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%
production)
5700
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device
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6.7 Safety-Related Certifications
VDE
UL
Plan to certify according
to DIN V VDE V 0884-11
(VDE V 0884-11):201701;
DIN EN 61010-1 (VDE
0411-1):2011-07
Plan to certify
according to
UL 1577
Component
Recognition
Program
Reinforced insulation
Maximum transient
isolation voltage, 8000
VPK;
Single
Maximum repetitive peak protection,
isolation voltage, 2121
5700 VRMS
VPK;
Maximum surge isolation
voltage, 8000 VPK
Certification Planned
Certification
Planned
CSA
CQC
TUV
Plan to certify according to
GB4943.1-2011
Plan to certify according to
EN 61010-1:2010 (3rd Ed)
and
EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Isolation Rating of 5700 VRMS;
Reinforced insulation per CSA
60950-1- 07+A1+A2 and IEC
60950-1 (2nd Ed.), 1450 VRMS
max working voltage (pollution
degree 2, material group I) ;
2 MOPP (Means of Patient
Protection) per CSA 606011:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
working voltage
Reinforced Insulation, Altitude
≤ 5000m, Tropical climate,
400 VRMS maximum working
voltage
5700 VRMS Reinforced
insulation per
EN 61010-1:2010 (3rd Ed) up
to working voltage of 1000
VRMS
5700 VRMS Reinforced
insulation per
EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to
working voltage of 1450 VRMS
Certification Planned
Certification Planned
Certification Planned
Plan to certify according to
CSA Component Acceptance
Notice 5A, IEC 60950-1, and
IEC 60601-1
6.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Safety temperature
(1)
8
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA =68.3°C/W, VDD = 15V, VEE=-5V, TJ = 150°C, TA
= 25°C
61
RθJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA
= 25°C
49
RθJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA
= 25°C
1220
mW
150
°C
mA
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air
thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air
thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount
packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
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6.9 Electrical Characteristics
VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD – COM = 20 V, 18 V or 15 V, COM – VEE = 0 V, 5 V, 8 V or
15 V, CL = 100 pF, –40°C < TJ < 150°C (unless otherwise noted) (1) (2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.55
2.7
2.85
2.35
2.5
2.65
UNIT
VCC UVLO THRESHOLD AND DELAY
VVCC_ON
VVCC_OFF
VCC–GND
VVCC_HYS
V
0.2
tVCCFIL
VCC UVLO Deglitch time
tVCC+ to OUT
VCC UVLO on delay to output high
tVCC– to OUT
VCC UVLO off delay to output low
tVCC+ to RDY
VCC UVLO on delay to RDY high
tVCC– to RDY
VCC UVLO off delay to RDY low
10
IN+ = VCC, IN– = GND
RST/EN = VCC
28
37.8
50
5
10
15
30
37.8
50
5
10
15
10.5
12.0
12.8
9.9
10.7
11.8
µs
VDD UVLO THRESHOLD AND DELAY
VVDD_ON
VVDD_OFF
VDD–COM
VVDD_HYS
V
0.8
tVDDFIL
VDD UVLO Deglitch time
tVDD+ to OUT
VDD UVLO on delay to output high
tVDD– to OUT
VDD UVLO off delay to output low
tVDD+ to RDY
VDD UVLO on delay to RDY high
tVDD– to RDY
VDD UVLO off delay to RDY low
5
IN+ = VCC, IN– = GND
2
RST/EN = FLT=High
5
8
5
10
10
15
10
15
µs
VCC, VDD QUIESCENT CURRENT
IVCCQ
VCC quiescent current
IVDDQ
VDD quiescent current
OUT(H) = High, fS = 0Hz, AIN=2V
2.5
3
4
OUT(L) = Low, fS = 0Hz, AIN=2V
1.45
2
2.75
OUT(H) = High, fS = 0Hz, AIN=2V
3.6
4
5.9
OUT(L) = Low, fS = 0Hz, AIN=2V
3.1
3.7
5.3
1.85
2.31
mA
mA
LOGIC INPUTS — IN+, IN– and RST/EN
VINH
Input high threshold
VCC=3.3V
VINL
Input low threshold
VCC=3.3V
VINHYS
Input threshold hysteresis
VCC=3.3V
IIH
Input high level input leakage current
IIL
0.99
1.52
V
V
0.33
V
VIN = VCC
90
µA
Input low level input leakage
VIN = GND
–90
µA
RIND
Input pins pull down resistance
see Detailed Description for more
information
28.5
55
113
RINU
Input pins pull up resistance
see Detailed Description for more
information
28.5
55
113
TINFIL
IN+, IN– and RST/EN deglitch (ON and
OFF) filter time
fS = 50kHz
28
40
60
ns
TRSTFIL
Deglitch filter time to reset /FLT
400
650
800
ns
kΩ
GATE DRIVER STAGE
IOUT, IOUTH
Peak source current
10
IOUT, IOUTL
Peak sink current
ROUTH
Output pull-up resistance
IOUT = –0.1A
1.5
ROUTL
Output pull-down resistance
IOUT = 0.1A
0.1
VOUTH
High level output voltage
IOUT = –0.2A, VDD=18V
VOUTL
Low level output voltage
IOUT = 0.2A
CL=0.18µF, fS=1kHz
A
10
A
2.5
4.9
Ω
0.3
0.7
Ω
17.5
V
60
mV
ACTIVE PULLDOWN
VOUTPD
Output active pull down on OUT, OUTL
IOUTL or IOUT = 0.1×IOUT(L)(tpy),
VDD=OPEN, VEE=COM
1.5
1.5
2
2.5
V
2.0
2.5
V
INTERNAL ACTIVE MILLER CLAMP
VCLMPTH
Miller clamp threshold voltage
Reference to VEE
VCLMPI
Output low clamp voltage
ICLMPI = 1A
(1)
(2)
VEE + 0.5
V
Current are positive into and negative out of the specified terminal.
All voltages are referenced to COM unless otherwise notified.
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Electrical Characteristics (continued)
VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD – COM = 20 V, 18 V or 15 V, COM – VEE = 0 V, 5 V, 8 V or
15 V, CL = 100 pF, –40°C < TJ < 150°C (unless otherwise noted)(1)(2).
PARAMETER
TEST CONDITIONS
ICLMPI
Output low clamp current
VCLMPI = 0V, VEE = –2.5V
RCLMPI
Miller clamp pull down resistance
tDCLMPI
Miller clamp ON delay time
MIN
TYP
MAX
UNIT
4
A
ICLMPI = 0.2A
0.6
Ω
CL = 1.8nF
15
50
ns
SHORT CIRCUIT CLAMPING
VCLP-OUT(H)
VOUT–VDD, VOUTH–VDD
OUT = Low, IOUT(H) = 500mA, tCLP=10us
0.9
0.99
V
VCLP-OUT(L)
VOUT–VDD, VOUTL–VDD
OUT = High, IOUT(L) = 500mA, tCLP=10us
1.8
1.98
V
VCLP-CLMPI
VCLMPI–VDD
OUT = High, ICLMPI = -20mA, tCLP=10us
1.0
V
DESAT PROTECTION
ICHG
Blanking capacitor charge current
VDESAT = 2.0V
445
500
IDCHG
Blanking capacitor discharge current
VDESAT = 6.0V
10
15
VDESAT
Detection Threshold
8.2
9.1
VDESATL
Voltage when OUT(L) = LOW, Reference
to COM
tDESATLEB
Leading edge blank time
tDESATFIL
DESAT deglitch filter
tDESATOFF
DESAT propagation delay to OUT(L) 90%
tDESATFLT
DESAT to FLT low delay
IDESAT = 15mA
570
µA
mA
10
V
1
V
150
200
450
ns
50
150
350
ns
150
200
300
ns
300
600
750
ns
250
400
570
mA
INTERNAL SOFT TURN-OFF
ISTO
Soft turn-off current on fault conditions
ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)
VAIN
Analog sensing voltage range
4.5
V
IAIN
Internal current source
VAIN=2.5V, -40°C< TJ< 150°C
196
200
209
µA
fAPWM
APWM output frequency
VAIN=2.5V
380
400
420
kHz
BWAIN
AIN–APWM bandwidth
DAPWM
APWM Dutycycle
0.5
10
kHz
VAIN = 0.6V
86.5
88
89.5
VAIN = 2.5V
48.5
50
51.5
VAIN = 4.5V
7.5
10
11.5
%
FLT AND RDY REPORTING
tRDYHLD
VDD UVLO RDY low minimum holding
time
tFLTMUTE
Output mute time on fault
Reset fault through RST/EN
RODON
Open drain output on resistance
IODON = 5mA
VODL
Open drain low output voltage
IODON = 5mA
0.55
0.55
1
ms
1
ms
30
Ω
0.3
V
COMMON MODE TRANSIENT IMMUNITY
CMTI
10
Common-mode transient immunity
150
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6.10 Switching Characteristics
VCC=5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE = 3V, 5V or 8V, CL=100pF,
–40°C<TJ<150°C (unless otherwise noted)
MIN
TYP
MAX
tPDHL
Propagation delay time – High to Low
PARAMETER
TEST CONDITIONS
60
90
130
tPDLH
Propagation delay time – Low to High
60
90
130
PWD
Pulse width distortion |tPDHL – tPDLH|
tsk-pp
Part to Part skew
Rising or Falling Propagation Delay
tr
Driver output rise time
CL=10nF
33
tf
Driver output fall time
CL=10nF
27
fMAX
Maximum switching frequency
30
30
1
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ns
MHz
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6.11 Insulation Characteristics Curves
1.E+12
1.E+11
1.E+10
54 Yrs
1.E+09
Time to Fail (sec)
1.E+08
TDDB Line (< 1 ppm Fail Rate)
1.E+07
1.E+06
VDE Safety Margin Zone
1.E+05
1.E+04
1.E+03
1.E+02
1800VRMS
1.E+01
200
1200
2200
3200
4200
5200
6200
Applied Voltage (VRMS)
Figure 1. Reinforced Isolation Capacitor Life Time Projection
80
1400
1200
Safety Limiting Power (mW)
Safety Limiting Current (mA)
VDD=15V; VEE=-5V
VDD=20V; VEE=-5V
60
40
20
1000
800
600
400
200
0
0
0
25
50
75
100
125
Ambient Temperature (oC)
150
0
Safe
Figure 2. Thermal Derating Curve for Limiting Current per
VDE
12
20
40
60
80
100
120
Ambient Temperature (oC)
140
160
Safe
Figure 3. Thermal Derating Curve for Limiting Power per
VDE
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6.12 Typical Characteristics
22
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
20
Peak Output Current Low, I OUTL (A)
Peak Output Current High, I OUTH (A)
22
18
16
14
12
10
8
6
4
-60
-40
-20
0
20 40 60 80
Temperature (qC)
18
16
14
12
10
8
6
4
-60
100 120 140 160
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
D017
Figure 5. Output Low Driver Current vs. Temperature
6
4
VCC = 3.3V
VCC = 5V
5.5
VCC = 3.3V
VCC = 5V
3.5
5
IVCCQ (mA)
3
4.5
2.5
4
2
3.5
1.5
3
-60
-40
-20
0
IN+ = High
20 40 60 80
Temperature (qC)
1
-60
100 120 140 160
-40
-20
0
D015
IN- = Low
IN+ = Low
Figure 6. IVCCQ Supply Current vs. Temperature
20 40 60 80
Temperature (qC)
100 120 140 160
D014
IN- = Low
Figure 7. IVCCQ Supply Current vs. Temperature
5
6
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
4.5
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
5.5
5
IVDDQ (mA)
4
IVCCQ (mA)
-40
D016
Figure 4. Output High Drive Current vs. Temperature
IVCCQ (mA)
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
20
3.5
4.5
3
4
2.5
3.5
2
30
70
110
150
190
230
Frequency (kHz)
270
3
-60
310
-40
-20
D018
IN+ = High
Figure 8. IVCCQ Supply Current vs. Input Frequency
0
20 40 60 80
Temperature (qC)
100 120 140 160
D012
IN- = Low
Figure 9. IVDDQ Supply Current vs. Temperature
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Typical Characteristics (continued)
6
10
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
5.5
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
9
8
IVDDQ (mA)
IVDDQ (mA)
5
4.5
4
7
6
5
4
3.5
3
3
-60
-40
-20
0
IN+ = Low
20 40 60 80
Temperature (qC)
2
30
100 120 140 160
270
310
D019
VDD UVLO Threshold, VDD_ON (V)
14
3.5
3
2.5
2
1.5
-60
-40
-20
0
20 40 60 80
Temperature (qC)
13.5
13
12.5
12
11.5
11
10.5
10
-60
100 120 140 160
-40
-20
0
D001
Figure 12. VCC UVLO vs. Temperature
20 40 60 80
Temperature (qC)
100 120 140 160
D002
Figure 13. VDD UVLO vs. Temperature
100
100
Propagation Delay High-Low, t PDHL (ns)
Propagation Delay Low-High, t PDLH (ns)
150
190
230
Frequency (kHz)
Figure 11. IVDDQ Supply Current vs. Input Frequency
4
90
80
70
60
50
-60
-40
-20
VCC = 3.3V
RON = 0Ω
0
20 40 60 80
Temperature (qC)
VDD=18V
ROFF = 0Ω
100 120 140 160
90
80
70
60
50
-60
-40
-20
D021
CL = 100pF
Figure 14. Propagation Delay tPDLH vs. Temperature
14
110
IN- = Low
Figure 10. IVDDQ Supply Current vs. Temperature
VCC UVLO Threshold, V CC_ON (V)
70
D013
VCC = 3.3V
RON = 0Ω
0
20 40 60 80
Temperature (qC)
VDD=18V
ROFF = 0Ω
100 120 140 160
D022
CL = 100pF
Figure 15. Propagation Delay tPDHL vs. Temperature
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60
60
50
50
Fall Time, t f (ns)
Rise Time, t r (ns)
Typical Characteristics (continued)
40
30
20
40
30
20
10
-60
-40
-20
0
VCC = 3.3V
RON = 0Ω
20 40 60 80
Temperature (qC)
10
-60
100 120 140 160
-40
VDD=18V
ROFF = 0Ω
CL = 10nF
0
VCC = 3.3V
RON = 0Ω
Figure 16. tr Rise Time vs. Temperature
20 40 60 80
Temperature (qC)
100 120 140 160
VDD=18V
ROFF = 0Ω
D024
CL = 10nF
Figure 17. tf Fall Time vs. Temperature
3
2.5
2.75
2.25
VCLP-OUT(H) (V)
2.5
VOUTPD (V)
-20
D023
2.25
2
2
1.75
1.5
1.75
1.25
1.5
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
1
-60
D008
Figure 18. VOUTPD Output Active Pulldown Voltage vs.
Temperature
1.75
VCLP-OUT(L) (V)
1.5
1.25
1
0.75
0.5
0.25
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
0
20 40 60 80
Temperature (qC)
100 120 140 160
D025
2.6
2.45
2.3
2.15
2
1.85
1.7
1.55
1.4
-60
-40
D026
Figure 20. VCLP-OUT(L) Short Circuit Clamping Voltage vs.
Temperature
-20
Figure 19. VCLP-OUT(H) Short Circuit Clamping Voltage vs.
Temperature
Miller Clamp Threshold Voltage, VCLMPTH (V)
2
-40
-20
0
20 40 60 80
Temperature (°C)
100 120 140 160
D007
Figure 21. VCLMPTH Miller Clamp Threshold Voltage vs.
Temperature
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Typical Characteristics (continued)
Miller Clamp ON Delay Time, tDCLMPI (ns)
Peak Clamp Sink Current, ICLMPI (A)
8.5
7.5
6.5
5.5
4.5
3.5
2.5
1.5
0.5
-60
-40
-20
0
20 40 60 80
Temperature (qC)
18
17
16
15
14
13
12
11
10
-60
100 120 140 160
Figure 22. ICLMPI Miller Clamp Sink Current vs. Temperature
9.8
9.6
9.4
9.2
9
8.8
8.6
8.4
8.2
-40
-20
0
20 40 60 80
Temperature (°C)
100 120 140 160
290
280
270
260
250
240
230
220
210
-20
0
20 40 60 80
Temperature (°C)
100 120 140 160
D003
Figure 26. tDESATOFF DESAT Propagation Delay to OUT(L)
90% vs. Temperature
16
20 40 60 80
Temperature (°C)
100 120 140 160
D010
420
380
340
300
260
220
180
140
100
-60
-40
-20
0
20 40 60 80
Temperature (°C)
100 120 140 160
D002
Figure 25. tDESATLEB DESAT Leading Edge Blanking Time vs.
Temperature
DESAT Sense to /FLT Low Delay, tDESATFLT (ns)
DESAT Propagation Delay to OUT(L) 90%, tDESATOFF (ns)
300
-40
0
D001
Figure 24. VDESAT DESAT Threshold Voltage vs.
Temperature
200
-60
-20
Figure 23. tDCLMPI Miller Clamp ON Delay Time vs.
Temperature
Leading Edge Blanking Time, tDESATLEB (ns)
DESAT Threshold Voltage, VDESAT (V)
10
8
-60
-40
D011
680
660
640
620
600
580
560
540
520
500
-60
-40
-20
0
20 40 60 80
Temperature (°C)
100 120 140 160
D004
Figure 27. tDESATFLT DESAT Sense to /FLT Low Delay Time
vs. Temperature
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320
560
310
550
DESAT Charging Current, ICHG (PA)
DESAT Deglitch Filter, tDESATFIL (ns)
Typical Characteristics (continued)
300
290
280
270
260
250
240
230
220
-60
-40
-20
0
20 40 60 80
Temperature (°C)
100 120 140 160
540
530
520
510
500
490
480
470
460
450
440
-60
-40
D005
Figure 28. tDESATFIL DESAT Deglitch Filter vs. Temperature
-20
0
20 40 60 80
Temperature (°C)
100 120 140 160
D008
Figure 29. ICHG DESAT Charging Current vs. Temperature
DESAT Discharge Current, IDCHG (PA)
20
19
18
17
16
15
14
13
12
11
10
-60
-40
-20
0
20 40 60 80
Temperature (°C)
100 120 140 160
D009
Figure 30. IDCHG DESAT Discharge Current vs. Temperature
7 Parameter Measurement Information
7.1 Propagation Delay
7.1.1 Regular Turn-OFF
Figure 31 shows the propagation delay measurement for non-inverting configurations. Figure 32 shows the
propagation delay measurement with the inverting configurations.
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Propagation Delay (continued)
50%
50%
tPDLH
tPDHL
IN+
,1Å
90%
10%
OUT
Figure 31. Non-inverting Logic Propagation Delay Measurement
IN+
,1Å
50%
50%
tPDLH
tPDHL
90%
OUT
10%
Figure 32. Inverting Logic Propagation Delay Measurement
18
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7.2 Input Deglitch Filter
In order to increase the robustness of gate driver over noise transient and accidental small pulses on the input
pins, i.e. IN+, IN–, RST/EN, a 40ns deglitch filter is designed to filter out the transients and make sure there is no
faulty output responses or accidental driver malfunctions. When the IN+ or IN– PWM pulse is smaller than the
input deglitch filter width, TINFIL, there will be no responses on OUT drive signal. Figure 33 and Figure 34 shows
the IN+ pin ON and OFF pulse deglitch filter effect. Figure 35 and Figure 36 shows the IN– pin ON and OFF
pulse deglitch filter effect.
IN+
tPWM < TINFIL
tPWM < TINFIL
IN+
,1Å
,1Å
OUT
OUT
Figure 33. IN+ ON Deglitch Filter
Figure 34. IN+ OFF Deglitch Filter
IN+
IN+
,1Å
tPWM < TINFIL
tPWM < TINFIL
,1Å
OUT
OUT
Figure 35. IN– ON Deglitch Filter
Figure 36. IN– OFF Deglitch Filter
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7.3 Active Miller Clamp
7.3.1 Internal On-chip Active Miller Clamp
For gate driver application with unipolar bias supply or bipolar supply with small negative turn-off voltage, active
miller clamp can help add a additional low impedance path to bypass the miller current and prevent the high
dV/dt introduced unintentional turn-on through the miller capacitance. Figure 37 shows the timing diagram for onchip internal miller clamp function.
IN
(µ,1+¶ Å µ,1Ŷ)
tDCLMPI
VCLMPTH
OUT
HIGH
CLMPI
Ctrl.
LOW
Figure 37. Timing Diagram for Internal Active Miller Clamp Function
20
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7.4 Under Voltage Lockout (UVLO)
UVLO is one of the key protection features designed to protect the system in case of bias supply failures on
VCC — primary side power supply, and VDD — secondary side power supply.
7.4.1 VCC UVLO
The VCC UVLO protection details are discussed in this section. Figure 38 shows the timing diagram illustrating
the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.
IN
(µ,1+¶ Å µ,1Ŷ)
tVCCFIL
t9&&Å WR 287
VVCC_ON
VCC
VVCC_OFF
VDD
COM
VEE
tVCC+ to OUT
90%
VCLMPTH
OUT
10%
tVCC+ to RDY
t9&&Å WR 5'<
tRDYHLD
Hi-Z
RDY
VCC
APWM
Figure 38. VCC UVLO Protection Timing Diagram
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Under Voltage Lockout (UVLO) (continued)
7.4.2 VDD UVLO
The VDD UVLO protection details are discussed in this section. Figure 39 shows the timing diagram illustrating
the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.
IN
(µ,1+¶ Å µ,1Ŷ)
tVDDFIL
VDD
t9''Å WR 287
VVDD_ON
VVDD_OFF
COM
VEE
VCC
tVDD+ to OUT
VCLMPTH
OUT
90%
10%
tVDD+ to RDY
t9''Å WR 5'<
tRDYHLD
RDY
APWM
Hi-Z
VCC
Figure 39. VDD UVLO Protection Timing Diagram
22
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7.5 Desaturation (DESAT) Protection
7.5.1 DESAT Protection with Soft Turn-OFF
DESAT function is used to detect VDS for SiC-MOSFETs or VCE for IGBTs under over current conditions.
Figure 40 shows the timing diagram of DESAT operation with soft turn-off during the turning on transition.
IN
(µ,1+¶ Å µ,1Ŷ)
VDESAT
tDESATLEB
DESAT
tDESATLEB
tDESATFIL
tDESATOFF
90%
GATE
VCLMPTH
tDESATFLT
tFLTMUTE
Hi-Z
FLT
tRSTFIL
tRSTFIL
RST/EN
HIGH
Hi-Z
OUTH
LOW
Hi-Z
OUTL
LOW
Figure 40. DESAT Protection with Soft Turn-OFF During Turn-on Transition
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Desaturation (DESAT) Protection (continued)
Figure 41 shows the timing diagram of DESAT protection while the power device is already turned on.
IN
(µ,1+¶ Å µ,1Ŷ)
VDESAT
tDESATLEB
tDESATFIL
DESAT
tDESATOFF
90%
GATE
VCLMPTH
tDESATFLT
tFLTMUTE
Hi-Z
FLT
tRSTFIL
tRSTFIL
RST/EN
HIGH
Hi-Z
OUTH
LOW
Hi-Z
OUTL
LOW
Figure 41. DESAT Protection with Soft Turn-OFF While Power Device is ON
24
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8 Detailed Description
8.1 Overview
The UCC21750 device is an advanced isolated gate driver with state-of-art protection and sensing features for
SiC MOSFETs and IGBTs. The device can support up to 2121V DC operating voltage based on SiC MOSFETs
and IGBTs, and can be used to above 10kW applications such as HEV/EV traction inverter, motor drive, onboard and off-board battery charger, solar inverter, etc. The galvanic isolation is implemented by the capacitive
isolation technology, which can realize a reliable reinforced isolation between the low voltage DSP/MCU and high
voltage side.
The ±10A peak sink and source current of UCC21750 can drive the SiC MOSFET modules and IGBT modules
directly without an extra buffer. The driver can also be used to drive higher power modules or parallel modules
with external buffer stage. The input side is isolated with the output side with a reinforced isolation barrier based
on capacitive isolation technology. The device can support up to 1.5-kVRMS working voltage, 12.8-kVPK surge
immunity with longer than 40 years isolation barrier life. The strong drive strength helps to switch the device fast
and reduce the switching loss. While the 150V/ns minimum CMTI guarantees the reliability of the system with
fast switching speed. The small propagation delay and part-to-part skew can minimize the deadtime setting, so
the conduction loss can be reduced.
The device includes extensive protection and monitor features to increase the reliability and robustness of the
SiC MOSFET and IGBT based systems. The 12V output side power supply UVLO is suitable for switches with
gate voltage ≥ 15V. The active miller clamp feature prevents the false turn on causing by miller capacitance
during fast switching. The device has the state-of-art DESAT detection time, and fault reporting function to the
low voltage side DSP/MCU. The soft turn off is triggered when the DESAT fault is detected, minimizing the short
circuit energy while reducing the overshoot voltage on the switches.
The isolated analog to PWM sensor can be used as switch temperature sensing, DC bus voltage sensing,
auxiliary power supply sensing, etc. The PWM signal can be fed directly to DSP/MCU or through a low-pass-filter
as an analog signal.
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8.2 Functional Block Diagram
7
CLMPI
4
OUTH
6
OUTL
5
VDD
IN+ 10
55kQ
PWM Inputs
MOD
DEMOD
Output Stage
t
ON/OFF Control
STO
INt 11
55kQ
VCC
VCC 15
VCC Supply
GND
UVLO
9
UVLO
FLT
Fault Decode
13
ISOLATION BARRIER
RDY 12
LDO[s for VEE,
COM and channel
DESAT Protection
3 COM
8
VEE
2
DESAT
1
AIN
Fault Encode
RST/EN 14
50kQ
Analog 2 PWM
APWM 16
PWM Driver
DEMOD
MOD
8.3 Feature Description
8.3.1 Power Supply
The input side power supply VCC can support a wide voltage range from 3V to 5.5V. The device supports both
unipolar and bipolar power supply on the output side, with a wide range from 13V to 33V from VDD to VEE. The
negative power supply with respect to switch source or emitter is usually adopted to avoid false turn on when the
other switch in the phase leg is turned on. The negative voltage is especially important for SiC MOSFET due to
its fast switching speed.
26
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Feature Description (continued)
8.3.2 Driver Stage
UCC21750 has ±10A peak drive strength and is suitable for high power applications. The high drive strength can
drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage.
UCC21750 can also be used to drive higher power modules or parallel modules with extra buffer stage.
Regardless of the values of VDD, the peak sink and source current can be kept at 10A. The driver features an
important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in LOW
state. The split output of the driver stage is depicted in Figure 42. The driver has rail-to-rail output by
implementing a hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and
an N-Channel MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on
resistance RNMOS is the same as ROL. The hybrid pull-up structure delivers the highest peak-source current when
it is most needed, during the miller plateau region of the power semiconductor turn-on transient. The ROH in
represents the on-resistance of the pull-up P-Channel MOSFET. However, the effective pull-up resistance is
much smaller than ROH. Since the pull-up N-Channel MOSFET has much smaller on-resistance than the PChannel MOSFET, the pull-up N-Channel MOSFET dominates most of the turn-on transient, until the voltage on
OUTH pin is about 3V below VDD voltage. The effective resistance of the hybrid pull-up structure during this
period is about 2 x ROL . Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pull-up
impedance results in strong drive strength during the turn-on transient, which shortens the charging time of the
input capacitance of the power semiconductor and reduces the turn on switching loss.
The pull-down structure of the driver stage is implemented solely by a pull-down N-Channel MOSFET. The onresistance of the N-Channel MOSFET ROL can be found in the . This MOSFET can ensure the OUTL voltage be
pulled down to VEE rail. The low pull-down impedance not only results in high sink current to reduce the turn-off
time, but also helps to increase the noise immunity considering the miller effect.
VDD
Input
Signal
Anti Shootthrough
Circuitry
Isolation Barrier
ROH
RNMOS
OUTH
OUTL
ROL
Figure 42. Gate Driver Output Stage
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Feature Description (continued)
8.3.3 VCC and VDD Undervoltage Lockout (UVLO)
UCC21750 implements the internal UVLO protection feature for both input and output power supplies VCC and
VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW. The output
only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature not only
reduces the power consumption of the driver itself during low power supply voltage condition, but also increases
the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the gate-source
voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD value, the
conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the power
stage. UCC21750 implements 12V threshold voltage of VDD UVLO, with 800mV hysteresis. This threshold
voltage is suitable for both SiC MOSFET and IGBT.
The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity
of the power supply. During the turn on and turn off switching transient, the driver sources and sinks a peak
transient current from the power supply, which can result in sudden voltage drop of the power supply. With
hysteresis and UVLO deglitch filter, the internal UVLO protection block will ignore small noises during the normal
switching transients.
The timing diagrams of the UVLO feature of VCC and VDD are shown in Figure 38, and Figure 39. The RDY pin
on the input side is used to indicate the power good condition. The RDY pin is open drain. During UVLO
condition, the RDY pin is held in low status and connected to GND. Normally the pin is pulled up externally to
VCC to indicate the power good. The AIN-APWM function stops working during the UVLO status. The APWM pin
on the input side will be held LOW.
8.3.4 Active Pulldown
UCC21750 implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE when the
VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active pulldown feature
can prevent the output be false turned on before the device is back to control.
VDD
OUTL
Ra
Control
Circuit
VEE
COM
Figure 43. Active Pulldown
8.3.5 Short Circuit Clamping
During short circuit condition, the miller capacitance can cause a current sinking to the OUTH/OUTL/CLMPI pin
due to the high dV/dt and boost the OUTH/OUTL/CLMPI voltage. The short circuit clamping feature of
UCC21750 can clamp the OUTH/OUTL/CLMPI pin voltage to be slightly higher than VDD, which can protect the
power semiconductors from a gate-source and gate-emitter overvoltage breakdown. This feature is realized by
an internal diode from the OUTH/OUTL/CLMPI to VDD.
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Feature Description (continued)
VDD
D1
D2 D3
OUTH
Control
Circuitry
OUTL
CLMPI
Figure 44. Short Circuit Clamping
8.3.6 Internal Active Miller Clamp
Active miller clamp feature is important to prevent the false turn-on while the driver is in OFF state. In
applications which the device can be in synchronous rectifier mode, the body diode conducts the current during
the deadtime while the device is in OFF state, the drain-source or collector-emitter voltage remains the same and
the dV/dt happens when the other power semiconductor of the phase leg turns on. The low internal pull-down
impedance of UCC21750 can provide a strong pulldown to hold the OUTL to VEE. However, external gate
resistance is usually adopted to limit the dV/dt. The miller effect during the turn on transient of the other power
semiconductor can cause a voltage drop on the external gate resistor, which boost the gate-source or gateemitter voltage. If the voltage on VGS or VGE is higher than the threshold voltage of the power semiconductor, a
shoot through can happen and cause catastrophic damage. The active miller clamp feature of UCC21750 drives
an internal MOSFET, which connects to the device gate. The MOSFET is triggered when the gate voltage is
lower than VCLMPTH, which is 2V above VEE, and creates a low impedance path to avoid the false turn on issue.
VCLMPTH
VCC
3V to 5.5V
IN+
µC
MOD
Isolation barrier
+
±
OUTH
Control
Circuitry
CLMPI
OUTL
DEMOD
INVEE
COM
VCC
Figure 45. Active Miller Clamp
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Feature Description (continued)
8.3.7 Desaturation (DESAT) Protection
The UCC21750 implements a fast overcurrent and short circuit protection feature to protect the IGBT module
from catastrophic breakdown during fault. The DESAT pin of the device has a typical 9V threshold with respect to
COM, source or emitter of the power semiconductor. When the input is in floating condition, or the output is held
in low state, the DESAT pin is pulled down by an internal MOSFET and held in LOW state, which prevents the
overcurrent and short circuit fault from false triggering. The internal current source of the DESAT pin is activated
only during the driver ON state, which means the overcurrent and short circuit protection feature only works when
the power semiconductor is in on state. The internal pulldown MOSFET helps to discharge the voltage of DESAT
pin when the power semiconductor is turned off. UCC21750 features a 200ns internal leading edge blanking time
after the OUTH switches to high state. The internal current source is activated to charge the external blanking
capacitor after the internal leading edge blanking time. The typical value of the internal current source is 500µA.
DESAT Fault
150ns
Deglitch Filter
VDD
DESAT
R
DHV
+
CBLK
+
±
VDESAT
Control
Logic
COM
Figure 46. DESAT Protection
8.3.8 Soft Turn-off
UCC21750 initiates a soft turn-off when the overcurrent and short circuit protection is triggered. When the
overcurrent and short circuit fault happens, the IGBT transits from the active region to the desaturation region
very fast. The channel current is controlled by the gate voltage and decreasing in a soft manner, thus the
overshoot of the IGBT is limited and prevents the overvoltage breakdown. There is a tradeoff between the
overshoot voltage and short circuit energy. The turn off speed needs to be slow to limit the overshoot voltage, but
the shutdown time should not be too long that the large energy dissipation can breakdown the device. The
400mA soft turn off current of UCC21750 makes sure the power switches is safely turned off during short circuit
events. The timing diagram of soft turn-off shows in Figure 40.
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Feature Description (continued)
150ns
Deglitch Filter
VDD
DESAT
R
DHV
+
CBLK
+
±
VDESAT
Control
Logic
COM
OUTL
Soft Turn-off
VEE
Figure 47. Soft Turn-off
8.3.9 Fault (FLT, Reset and Enable (RST/EN)
The FLT pin of UCC21750 is open drain and can report a fault signal to the DSP/MCU when the fault is detected
through the DESAT pin. The FLT pin will be pulled down to GND after the fault is detected, and is held low until a
reset signal is received from RST/EN. The device has a fault mute time tFLTMUTE, within which the device ignores
any reset signal.
The RST/EN is pulled down internally by a 50kΩ resistor, and is thus disabled by default when this pin is floating.
It must be pulled up externally to enable the driver. The pin has two purposes:
• To reset the FLT pin. To reset, then RST/EN pin is pulled low; if the pin is set and held in low state for more
than tRSTFIL after the mute time tFLTMUTE, then the fault signal is reset and FLT is reset back to the high
impedance status at the rising edge of the input signal at RST/EN pin.
• Enable and shutdown the device. If the RST/EN pin is pulled low for longer than tRSTFIL, the driver will be
disabled and OUTL will be activated to pull down the gate of the IGBT or SiC MOSFET. The pin must be
pulled up externally to enable the part, otherwise the device is disabled by default.
8.3.10 Isolated Analog to PWM Signal Function
The UCC21750 features an isolated analog to PWM signal function from AIN to APWM pin, which allows the
isolated temperature sensing, high voltage dc bus voltage sensing, etc. An internal current source IAIN in AIN pin
is implemented in the device to bias an external thermal diode or temperature sensing resistor. The UCC21750
encodes the voltage signal VAIN to a PWM signal, passing through the reinforced isolation barrier, and output to
APWM pin on the input side. The PWM signal can either be transferred directly to DSP/MCU to calculate the
duty cycle, or filtered by a simple RC filter as an analog signal. The AIN voltage input range is from 0.6V to 4.5V,
and the corresponding duty cycle of the APWM output ranges from 88% to 10%. The duty cycle increases
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Feature Description (continued)
linearly from 10% to 88% while the AIN voltage decreases from 4.5V to 0.6V. This corresponds to the
temperature coefficient of the negative temperature coefficient (NTC) resistor and thermal diode. When AIN is
floating, the AIN voltage is 5V and the APWM operates at 400kHz with approximately 10% duty cycle. The
accuracy of the duty cycle is ±3% across temperature without one time calibration. The accuracy can be
improved using calibration. The accuracy of the internal current source IAIN is ±3% across temperature.
The isolated analog to PWM signal feature can also support other analog signal sensing, such as the high
voltage dc bus voltage, etc. The internal current source IAIN should be taken into account when designing the
potential divider if sensing a high voltage.
UCC217xx
+
±
3V to 5.5V
APWM
DEMOD
µC
Isolation barrier
+
±
In Module or
Discrete
VDD
VCC
13V to
33V
AIN
+
MOD
Rfilt
Cfilt
OSC
GND
COM
Thermal
Diode
NTC or
PTC
Figure 48. Isolated Analog to PWM Signal
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8.4 Device Functional Modes
Table 1 lists the device function.
Table 1. Function Table
Input
Output
VCC
VDD
VEE
IN+
IN-
RST/EN
AIN
RDY
FLT
OUTH/
OUTL
CLMPI
APWM
PU
PD
PU
X
X
X
X
Low
HiZ
Low
Low
Low
PD
PU
PU
X
X
X
X
HiZ
HiZ
Low
Low
Low
PU
PU
PU
X
X
Low
X
HiZ
HiZ
Low
Low
Low
PU
Open
PU
X
X
X
X
Low
HiZ
HiZ
HiZ
HiZ
PU
PU
Open
X
X
X
X
Low
HiZ
Low
Low
Low
PU
PU
PU
Low
X
High
X
HiZ
HiZ
Low
Low
P*
PU
PU
PU
X
High
High
X
HiZ
HiZ
Low
Low
P*
PU
PU
PU
High
High
High
X
HiZ
HiZ
Low
Low
P*
PU: Power Up (VCC ≥ 2.85V, VDD ≥ 13.1V, VEE ≤ 0V); PD: Power Down (VCC ≤ 2.35V, VDD ≤ 9.9V); X:
Irrelevant; P*: PWM Pulse; HiZ: High Impedance
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC21750 device is very versatile because of the strong drive strength, wide range of output power supply,
high isolation ratings, high CMTI and superior protection and sensing features. The 1.5-kVRMS working voltage
and 12.8-kVPK surge immunity can support up both SiC MOSFET and IGBT modules with DC bus voltage up to
2121V. The device can be used in both low power and high power applications such as the traction inverter in
HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power supplies and etc. The
device can drive the high power SiC MOSFET module, IGBT module or paralleled discrete device directly without
external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which allows the driver
to have more control to the power semiconductor and saves the cost and space of the board design. UCC21750
can also be used to drive very high power modules or paralleled modules with external buffer stage. The input
side can support power supply and microcontroller signal from 3.3V to 5V, and the device level shifts the signal
to output side through reinforced isolation barrier. The device has wide output power supply range from 13V to
33V and support wide range of negative power supply. This allows the driver to be used in SiC MOSFET
applications, IGBT application and many others. The 12V UVLO benefits the power semiconductor with lower
conduction loss and improves the system efficiency. As a reinforced isolated single channel driver, the device
can be used to drive either a low-side or high-side driver.
UCC21750 device features extensive protection and monitoring features, which can monitor, report and protect
the system from various fault conditions.
• Fast detection and protection for the overcurrent and short circuit fault. The semiconductor is shutdown when
the fault is detected and FLT pin is pulled down to indicate the fault detection. The device is latched unless
reset signal is received from the RST/EN pin.
• Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent and
short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is
limited.
• UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to
be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is
back to normal operation mode once the power supply is out of the UVLO status. The power good status can
be monitored from the RDY pin.
• Analog signal seensing with isolated analog to PWM signal feature. This feature allows the device to sense
the temperature of the semiconductor from the thermal diode or temperature sensing resistor, or dc bus
voltage with resistor divider. A PWM signal is generated on the low voltage side with reinforced isolated from
the high voltage side. The signal can be fed back to the microcontroller for the temperature monitoring,
voltage monitoring and etc.
• The active miller clamp feature protects the power semiconductor from false turn on.
• Enable and disable function through the RST/EN pin.
• Short circuit clamping.
• Active pulldown.
9.2 Typical Application
Figure 49 shows the typical application of a half bridge using two UCC21750 isolated gate drivers. The half
bridge is a basic element in various power electronics applications such as in motor drive applications to control
the operating speed and torque of an AC motor.
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Typical Application (continued)
PWM
3-Pha se
Input
µC
APWM
UCC
217 50
UCC
217 50
1
2
3
4
5
6
UCC
217 50
1
2
3
4
5
6
UCC
217 50
UCC
217 50
UCC
217 50
M
FLT
Figure 49. Typical Application Schematic
9.2.1 Design Requirements
The design of the power system for end equipment should consider some design requirements to ensure the
reliable operation of UCC1750 through the load range. The design considerations include the peak source and
sink current, power dissipation, overcurrent and short circuit protection, AIN-APWM function for analog signal
sensing and etc.
A design example for a half bridge based on IGBT is given in this subsection. The design parameters are show
in Table 2.
Table 2. Design Parameters
Parameter
Value
Input Supply Voltage
5V
IN-OUT Configuration
Non-inverting
Positive Output Voltage VDD
15V
Negative Output Voltage VEE
-5V
DC Bus Voltage
800V
Peak Drain Current
300A
Switching Frequency
50kHz
Switch Type
IGBT Module
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9.2.2 Detailed Design Procedure
9.2.2.1 Input filters for IN+, IN- and RST/EN
In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With
the strong drive strength of UCC21750, the dV/dt can be high, especially for SiC MOSFET. Noise can not only
be coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal PCB
layout and coupled capacitance.
UCC21750 features a 40ns internal deglitch filter to IN+, IN- and RST/EN pin. Any signal less than 40ns can be
filtered out from the input pins. For noisy systems, external low pass filter can be added externally to the input
pins. Adding low pass filters to IN+, IN- and RST/EN pins can effectively increase the noise immunity and
increase the signal integrity. When not in use, the IN+, IN- and RST/EN pins should not be floating. IN- should be
tied to GND if only IN+ is used for non-inverting input to output configuration. The purpose of the low pass filter is
to filter out the high frequency noise generated by the layout parasitics. While choosing the low pass filter
resistors and capacitors, both the noise immunity effect and delay time should be considered according to the
system requirements.
9.2.2.2 PWM Interlock of IN+ and INUCC21750 features the PWM interlock for IN+ and IN- pins, which can be used to prevent the phase leg shoot
through issue. As shown in Table 1, the output is logic low while both IN+ and IN- are logic high. When only IN+
is used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other switch in the
phase leg can be sent to the IN- pin. As shown in Figure 50, the PWM_T is the PWM signal to top side switch,
the PWM_B is the PWM signal to bottom side switch. For the top side gate driver, the PWM_T signal is given to
the IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom side gate driver, the PWM_B signal is
given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and PWM_B signals are
high, the outputs of both gate drivers are logic low to prevent the shoot through condition.
IN+
IN-
RON
OUTH
Microcontroller
OUTL
ROFF
PWM_T
PWM_B
RON
IN+
OUTH
INOUTL
ROFF
Figure 50. PWM Interlock for a Half Bridge
9.2.2.3 FLT, RDY and RST/EN Pin Circuitry
Both FLT and RDY pin are open-drain output. The RST/EN pin has 50kΩ internal pulldown resistor, so the driver
is in OFF status if the RST/EN pin is not pulled up externally. A 5kΩ resistor can be used as pullup resistor for
the FLT, RDY and RST/EN pins.
To improve the noise immunity due to the parasitic coupling and common mode noise, low pass filters can be
added between the FLT, RDY and RST/EN pins and the microcontroller. A filter capacitor between 100pF to
300pF can be added.
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3.3V to 5V
VCC
15
0.1µF
1µF
GND
9
IN+
10
INt
Micro-controller
(MCU)
11
5kQ
100pF
5kQ
5kQ
12
13
FLT
RDY
100pF
100pF
14
RST/EN
APWM
16
Figure 51. FLT, RDY and RST/EN Pins Circuitry
9.2.2.4 RST/EN Pin Control
RST/EN pin has two functions. It is used to enable or shutdown the outputs of the driver and to reset the fault
signaled on the FLT pin after DESAT is detected. RST/EN pin needs to be pulled up to enable the device; when
the pin is pulled down, the device is in disabled status. By default the driver is disabled with the internal 50kΩ
pulldown resistor at this pin.
When the driver is latched after DESAT is detected, the FLT pin and output are latched low and need to be reset
by the RST/EN pin. The microcontroller must send a signal to RST/EN pin after the fault to reset the driver. The
driver will not respond until after the mute time tFLTMUTE. The reset signal must be held low for at least tRSTFIL after
the mute time.
This pin can also be used to automatically reset the driver. The continuous input signal IN+ or IN- can be applied
to RST/EN pin. There is no separate reset signal from the microcontroller when configuring the driver this way. If
the PWM is applied to the non-inverting input IN+, then IN+ can also be tied to RST/EN pin. If the PWM is
applied to the inverting input IN-, then a NOT logic is needed between the PWM signal from the microcontroller
and the RST/EN pin. Using either configuration results in the driver being reset in every switching cycle without
an extra control signal from microcontroller tied to RST/EN pin. One must ensure the PWM off-time is greater
than tRSTFIL in order to reset the driver in cause of a DESAT fault.
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3.3V to 5V
3.3V to 5V
VCC
VCC
15
15
1µF
0.1µF
0.1µF
1µF
GND
9
9
INt
5kQ
5kQ
11
FLT
12
13
100pF
IN+
10
Micro-controller
(MCU)
Micro-controller
(MCU)
IN+
10
GND
INt
5kQ
5kQ
11
FLT
100pF
12
13
RDY
RDY
100pF
100pF
14
16
RST/EN
14
APWM
16
RST/EN
APWM
Figure 52. Automatic Reset Control
9.2.2.5 Turn on and turn off gate resistors
UCC21750 features split outputs OUTH and OUTL, which enables the independent control of the turn on and
turn off switching speed. The turn on and turn off resistance determine the peak source and sink current, which
controls the switching speed in turn. Meanwhile, the power dissipation in the gate driver should be considered to
ensure the device is in the thermal limit. At first, the peak source and sink current are calculated as:
Is ource _ pk
Isink _ pk
min(10A,
min(10A,
VDD VEE
)
ROH _ EFF RON RG _ Int
VDD VEE
)
ROL ROFF RG _ Int
(1)
Where
• ROH_EFF is the effective internal pull up resistance of the hybrid pull-up structure, which is approximately 2 x
ROL, about 0.7 Ω
• ROL is the internal pulldown resistance, about 0.3 Ω
• RON is the external turn on gate resistance
• ROFF is the external turn off gate resistance
• RG_Int is the internal resistance of the SiC MOSFET or IGBT module
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VDD
ROH_EFF
Cies=Cgc+Cge
+
t
Cgc
VDD
OUTH
RON
RG_Int
OUTL
ROFF
+
ROL
Cge
VEE
t
VEE
COM
Figure 53. Output Model for Calculating Peak Gate Current
For example, for an IGBT module based system with the following parameters:
• Qg = 3300 nC
• RG_Int = 1.7 Ω
• RON=ROFF= 1 Ω
The peak source and sink current in this case are:
Is ource _ pk
Isink _ pk
min(10A,
min(10A,
VDD VEE
) | 5.9A
ROH _ EFF RON RG _ Int
VDD VEE
) | 6.7A
ROL ROFF RG _ Int
(2)
Thus by using 1Ω external gate resistance, the peak source current is 5.9A, the peak sink current is 6.7A. The
collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the miller
plateau voltage. The hybrid pullup structure ensures the peak source current at the miller plateau voltage, unless
the turn on gate resistor is too high. The faster the collector-to-emitter, Vce, voltage rises to VDC, the smaller the
turn on switching loss is. The dV/dt can be estimated as Qgc/Isource_pk. For the turn off switching transient, the
drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After Vce
reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled
by Vge. The peak sink current determines the dI/dt, which dominates the Vce voltage overshoot accordingly. If
using relatively large turn off gate resistance, the Vce overshoot can be limited. The overshoot can be estimated
by:
'Vce
Lstray ˜ Iload / ((ROFF ROL RG _Int ) ˜ Cies ˜ ln(Vplat / Vth ))
(3)
Where
• Lstray is the stray inductance in power switching loop, as shown in Figure 54
• Iload is the load current, which is the turn off current of the power semiconductor
• Cies is the input capacitance of the power semiconductor
• Vplat is the plateau voltage of the power semiconductor
• Vth is the threshold voltage of the power semiconductor
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LDC
Lstray=LDC+Le1+Lc1+Le1+Lc1
Lc1
RG
Lload
t
+
Le1
+
t
VDC
Lc2
VDD
OUTH
Cgc
Cies=Cgc+Cge
RG
OUTL
Cge
COM
Le2
Figure 54. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration
The power dissipation should be taken into account to maintain the gate driver within the thermal limit. The
power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:
PDR
PQ
PSW
(4)
PQ is the quiescent power loss for the driver, which is Iq x (VDD-VEE) = 5mA x 20V = 0.100W. The quiescent
power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic
circuits, protection circuits when the driver is swithing when the driver is biased with VDD and VEE, and also the
charging and discharing current of the internal circuit when the driver is switching. The power dissipation when
the driver is switching can be calculated as:
PSW
ROH _ EFF
1
˜(
2 ROH _ EFF RON RG _ Int
ROL
ROL
) ˜ (VDD VEE) ˜ fsw ˜ Qg
ROFF RG _ Int
(5)
Where
• Qg is the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD
• fsw is the switching frequency
In this example, the PSW can be calculated as:
PSW
40
ROH _ EFF
1
˜(
2 ROH _ EFF RON RG _ Int
ROL
ROL
) ˜ (VDD VEE) ˜ fsw ˜ Qg
ROFF RG _ Int
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0.505W
(6)
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Thus, the total power loss is:
PDR
PQ PSW
0.10W 0.505W 0.605W
(7)
When the board temperature is 125°C, the junction temperature can be estimated as:
Tj
Tb
\ jb ˜ PDR | 150 o C
(8)
Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency
is ~50kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing
external gate resistance, the gate driver can be operated at a higher switching frequency.
9.2.2.6 Overcurrent and Short Circuit Protection
A standard desaturation circuit can be applied to the DESAT pin. If the voltage of the DESAT pin is higher than
the threshold VDESAT, the soft turn-off is initiated. A fault will be reported to the input side to DSP/MCU. The
output is held to LOW after the fault is detected, and can only be reset by the RST/EN pin. The state-of-art
overcurrent and short circuit detection time helps to ensure a short shutdown time for SiC MOSFET and IGBT.
If DESAT pin is not in use, it must be tied to COM to avoid overcurrent fault false triggering.
• Fast reverse recovery high voltage diode is recommended in the desaturation circuit. A resistor is
recommended in series with the high voltage diode to limit the inrush current.
• A Schottky diode is recommended from COM to DESAT to prevent driver damage caused by negative
voltage.
• A Zener diode is recommended from COM to DESAT to prevent driver damage caused by positive voltage.
9.2.2.7 Isolated Analog Signal Sensing
The isolated analog signal sensing feature provides a simple isolated channel for the isolated temperature
detection, voltage sensing and etc. One typical application of this function is the temperature monitor of the
power semiconductor. Thermal diodes or temperature sensing resistors are integrated in the SiC MOSFET or
IGBT module close to the dies to monitor the junction temperature. UCC21750 has an internal 200uA current
source with ±3% accuracy across temperature, which can forward bias the thermal diodes or create a voltage
drop on the temperature sensing resistors. The sensed voltage from the AIN pin is passed through the isolation
barrier to the input side and transformed to a PWM signal. The duty cycle of the PWM changes linearly from 10%
to 88% when the AIN voltage changes from 4.5V to 0.6V and can be represented using Equation 9.
DAPWM (%)
20 * VAIN 100
(9)
9.2.2.7.1 Isolated Temperature Sensing
A typical application circuit is shown in Figure 55. To sense temperature, the AIN pin is connected to the thermal
diode or thermistor which can be discrete or integrated within the power module. A low pass filter is
recommended for the AIN input. Since the temperature signal does not have a high bandwidth, the low pass filter
is mainly used for filtering the noise introduced by the switching of the power device, which does not require
stringent control for propagation delay. The filter capacitance for Cfilt can be chosen between 1nF to 100nF and
the filter resistance Rfilt between 1Ω to 10Ω according to the noise level.
The output of APWM is directly connected to the microcontroller to measure the duty cycle dependent on the
voltage input at AIN, using Equation 9.
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UCC217xx
+
±
3V to 5.5V
APWM
DEMOD
µC
Isolation barrier
+
±
In Module or
Discrete
VDD
VCC
13V to
33V
AIN
+
MOD
Rfilt
Cfilt
OSC
GND
COM
Thermal
Diode
NTC or
PTC
Figure 55. Thermal Diode or Thermistor Temperature Sensing Configuration
When a high-precision voltage supply for VCC is used on the primary side of UCC21750 the duty cycle output of
APWM may also be filtered and the voltage measured using the microcontroller's ADC input pin, as shown in
Figure 56. The frequency of APWM is 400kHz, so the value for Rfilt_2 and Cfilt_2 should be such that the cutoff
frequency is below 400kHz. Temperature does not change rapidly, thus the rise time due to the RC constant of
the filter is not under a strict requirement.
UCC217xx
VDD
In Module or
Discrete
VCC
+
±
3V to 5.5V
APWM
µC
DEMOD
Rfilt_2
Isolation barrier
+
±
13V to
33V
AIN
+
MOD
Rfilt_1
OSC
Cfilt_2
Cfilt_1
GND
COM
Thermal
Diode
NTC or
PTC
Figure 56. APWM Channel with Filtered Output
The example below shows the results using a 4.7kΩ NTC, NTCS0805E3472FMT, in series with a 3kΩ resistor
and also the thermal diode using four diode-connected MMBT3904 NPN transistors. The sensed voltage of the 4
MMBT3904 thermal diodes connected in series ranges from about 2.5V to 1.6V from 25°C to 135°C,
corresponding to 50% to 68% duty cycle. The sensed voltage of the NTC thermistor connected in series with the
3kΩ resistor ranges from about 1.5V to 0.6V from 25°C to 135°C, corresponding to 70% to 88% duty cycle. The
voltage at VAIN of both sensors and the corresponding measured duty cycle at APWM is shown in Figure 57.
42
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2.7
90
2.4
2.1
84
Thermal Diode VAIN
NTC VAIN
Thermal Diode APWM
NTC APWM
78
1.8
72
1.5
66
1.2
60
0.9
54
0.6
20
40
60
80
Temperature (qC)
100
120
APWM (%)
VAIN (V)
www.ti.com
48
140
VAIN
Figure 57. Thermal diode and NTC VAIN and Corresponding Duty Cycle at APWM
The duty cycle output has an accuracy of ±3% throughout temperature without any calibration, as shown in
Figure 58 but with single-point calibration at 25°C, the duty accuracy can be improved to ±1%, as shown in
Figure 59.
1.5
Thermal Diode APWM Duty Error
NTC APWM Duty Error
1.25
APWM Duty Error (%)
1
0.75
0.5
0.25
0
-0.25
20
40
60
80
Temperature (qC)
100
120
140
APWM
Figure 58. APWM Duty Error Without Calibration
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0.8
Thermal Diode APWM Duty Error
NTC APWM Duty Error
APWM Duty Error (%)
0.6
0.4
0.2
0
-0.2
20
40
60
80
Temperature (qC)
100
120
140
APWM
Figure 59. APWM Duty Error with Single-Point Calibration
9.2.2.7.2 Isolated DC Bus Voltage Sensing
The AIN to APWM channel may be used for other applications such as the DC-link voltage sensing, as shown in
Figure 60. The same filtering requirements as given above may be used in this case, as well. The number of
attenuation resistors, Ratten_1 through Ratten_n, is dependent on the voltage level and power rating of the resistor.
The voltage is finally measured across RLV_DC to monitor the stepped-down voltage of the HV DC-link which must
fall within the voltage range of AIN from 0.6V to 4.5V. The driver should be referenced to the same point as the
measurement reference, thus in the case shown below the UCC21750 is driving the lower IGBT in the half-bridge
and the DC-link voltage measurement is referenced to COM. The internal current source IAIN should be taken into
account when designing the resistor divider. The AIN pin voltage is:
RLV _ DC
VAIN
˜ VDC RLV _ DC ˜ IAIN
n
¦R
RLV _ DC
atten _ i
(10)
i 1
Ratten_1
Ratten_2
UCC217xx
VDD
VCC
+
±
3V to 5.5V
APWM
µC
DEMOD
Rfilt_2
Isolation barrier
+
±
13V to
33V
Ratten_n
CDC
+
MOD
AIN
Rfilt
Cfilt
OSC
RLV_DC
Cfilt_2
COM
GND
Figure 60. DC-link Voltage Sensing Configuration
44
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9.2.2.8 Higher Output Current Using an External Current Buffer
To increase the IGBT gate drive current, a non-inverting current buffer (such as the NPN/PNP buffer shown in
Figure 61) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and
must be avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the D44VH10/
D45VH10 pair is up to 20 A peak.
In the case of a over-current detection, the soft turn off (STO) is activated. External components must be added
to implement STO instead of normal turn off speed when an external buffer is used. CSTO sets the timing for soft
turn off and RSTO limits the inrush current to below the current rating of the internal FET (10A). RSTO should be at
least (VDD-VEE)/10. The soft turn off timing is determined by the internal current source of 400mA and the
capacitor CSTO. CSTO is calculated using Equation 11.
CSTO
•
•
ISTO ˜ t STO
VDD VEE
(11)
ISTO is the the internal STO current source, 400mA
tSTO is the desired STO timing
UCC217xx
VDD
VDD
ROH
RNMOS
Cies=Cgc+Cge
OUTH
Cgc
Cgc
RG_1
RG_2
RG_Int
RG_Int
OUTL
Cge
Cge
ROL
CSTO
COM
RSTO
VEE
Figure 61. Current Buffer for Increased Drive Strength
10 Power Supply Recommendations
During the turn on and turn off switching transient, the peak source and sink current is provided by the VDD and
VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause a
voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, a set of
decoupling capacitors are recommended at the power supplies. Considering UCC21750 has ±10A peak drive
strength and can generate high dV/dt, a 10µF bypass cap is recommended between VDD and COM, VEE and
COM. A 1µF bypass cap is recommended between VCC and GND due to less current comparing with output
side power supplies. A 0.1µF decoupling cap is also recommended for each power supply to filter out high
frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and
should be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system
parasitics of PCB layout.
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11 Layout
11.1 Layout Guidelines
Due to the strong drive strength of UCC21750, careful considerations must be taken in PCB design. Below are
some key points:
• The driver should be placed as close as possible to the power semiconductor to reduce the parasitic
inductance of the gate loop on the PCB traces
• The decoupling capacitors of the input and output power supplies should be placed as close as possible to
the power supply pins. The peak current generated at each switching transient can cause high dI/dt and
voltage spike on the parasitic inductance of PCB traces
• The driver COM pin should be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If
the power device does not have a split Kelvin source or emitter, the COM pin should be connected as close
as possible to the source or emitter terminal of the power device package to separate the gate loop from the
high power switching loop
• Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the
high frequency noise generated by the output side switching transients. The ground plane provides a lowinductance filter for the return current flow
• If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the
ground plane on the output side to shield the output signals from the noise generated by the switch node; if
the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground
plane is not recommended
• If ground plane is not used on the output side, separate the return path of the DESAT and AIN ground loop
from the gate loop ground which has large peak source and sink current
• No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise
coupling between the input and output side which can contaminate the isolation barrier
46
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11.2 Layout Example
Figure 62. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Isolation Glossary
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC21750DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21750
UCC21750DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21750
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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9-Jan-2020
OTHER QUALIFIED VERSIONS OF UCC21750 :
• Automotive: UCC21750-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
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PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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