Texas Instruments | TPS7A03 Nanopower IQ, 200-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response (Rev. A) | Datasheet | Texas Instruments TPS7A03 Nanopower IQ, 200-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response (Rev. A) Datasheet

Texas Instruments TPS7A03 Nanopower IQ, 200-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response (Rev. A) Datasheet
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TPS7A03
SBVS375A – JULY 2019 – REVISED DECEMBER 2019
TPS7A03 Nanopower IQ, 200-nA, 200-mA, Low-Dropout Voltage Regulator With Fast
Transient Response
1 Features
3 Description
•
•
•
The TPS7A03 is an ultra-small, ultra-low quiescent
current low-dropout linear regulator (LDO) that can
source 200 mA with excellent transient performance.
1
•
•
•
•
•
•
•
Ultra-low IQ: 200 nA (typ), even in dropout
Shutdown IQ: 3 nA (typ)
Excellent transient response (1 mA to 50 mA)
– < 10-µs settling time
– 80-mv undershoot
Packages:
– 1.0-mm × 1.0-mm X2SON
– SOT23-5 (preview)
– 0.64-mm x 0.64-mm DSBGA (preview)
Input voltage range: 1.5 V to 6.0 V
Output voltage range: 0.8 V to 5.0 V (fixed)
Output accuracy: 1.5% over temperature
Smart enable pulldown
Very low dropout:
– 270 mV (max) at 200 mA (VOUT = 3.3 V)
Stable with a 1-µF or larger capacitor
The TPS7A03, with an ultra-low IQ of 200 nA, is
designed specifically for applications where very-low
quiescent current is a critical parameter. This device
maintains low IQ consumption even in dropout mode
to further increase the battery life. When in shutdown
or disabled mode, the device consumes ultra-low,
3-nA IQ that helps increase the shelf life of the
battery. The TPS7A03 has an output range of 0.8 V
to 5.0 V available in 50-mV steps to support the lower
core voltages of modern microcontrollers (MCUs).
The TPS7A03 features a smart enable circuit with an
internally controlled pulldown resistor that keeps the
LDO disabled even when the EN pin is left floating
and helps minimize the external components used to
pulldown the EN pin. This circuit also helps minimize
the current drawn through the external pulldown
circuit when the device is enabled.
2 Applications
•
•
•
•
•
•
•
Wearables electronics
Thermostats, smoke and heat detectors
Gas, heat, and water meters
Blood glucose monitors and pulse oximeters
Residential circuit breakers and fault indicators
Building security and video surveillance devices
EPOS card readers
The TPS7A03 is fully specified for TJ = –40°C to
+125°C operation.
Device Information(1)
PART NUMBER
PACKAGE
X2SON (4)
TPS7A03
BODY SIZE (NOM)
1.00 mm × 1.00 mm
DSBGA (4)(2)
0.64 mm × 0.64 mm
(2)
2.90 mm × 1.60 mm
SOT-23 (5)
(1) For all available packages, see the package option addendum
at the end of the data sheet.
(2) Preview package.
Typical Application Circuit
IN
OUT
TPS7A03
CIN
EN
COUT
GND
ON
OFF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A03
SBVS375A – JULY 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 22
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 26
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Examples................................................... 28
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2019) to Revision A
•
2
Page
Changed device status from advance information to production data ................................................................................... 1
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TPS7A03
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SBVS375A – JULY 2019 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
DQN Package
1-mm × 1-mm, 4-pin X2SON
Top View
OUT
1
4
DBV Package (Preview)
5-Pin SOT-23
Top View
IN
IN
1
GND
2
EN
3
Thermal Pad
GND
2
3
5
OUT
4
NC
EN
Not to scale
Not to scale
Pin Functions: DQN, DBV
PIN
NAME
DQN
DBV (2)
I/O (1)
EN
3
3
Input
GND
2
2
—
DESCRIPTION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low
or floating this pin disables the device. This pin features an internal pulldown resistor,
which is disconnected when EN is driven high externally and the device has started up.
Ground pin. This pin must be connected to ground on the board.
Input pin. For best transient response and to minimize input impedance, use the
recommended value or larger ceramic capacitor from IN to ground; see the
Recommended Operating Conditions table. Place the input capacitor as close to the
input of the device as possible.
IN
4
1
Input
NC
—
4
—
No connect pin. This pin is not internally connected. Connect to ground or leave floating.
OUT
1
5
Output
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to
ground for stability. For best transient response, use a 1-µF or larger ceramic capacitor
from OUT to ground. Place the output capacitor as close to output of the device as
possible; see the Recommended Operating Conditions table.
––
—
Thermal
pad
(1)
(2)
Connect the thermal pad to a large-area ground plane. The thermal pad is internally
connect to ground.
NC = No internal connection.
Preview package.
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SBVS375A – JULY 2019 – REVISED DECEMBER 2019
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YCH Package
4-Pin DSBGA, 0.35-mm Pitch
Top View
1
2
A
IN
OUT
B
EN
GND
YCH Package
4-Pin DSBGA, 0.35-mm Pitch
Bottom View
1
2
B
EN
GND
A
IN
OUT
Not to scale
Not to scale
Pin Functions: YCH
PIN
NAME
YCH (1)
I/O
DESCRIPTION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low or floating
this pin disables the device. This pin features an internal pulldown resistor, which is disconnected
when EN is driven high externally and the device has started up.
EN
B1
Input
GND
B2
—
IN
A1
Input
Input pin. For best transient response and to minimize input impedance, use the recommended
value or larger ceramic capacitor from IN to ground; see the Recommended Operating
Conditions table. Place the input capacitor as close to input of the device as possible.
OUT
A2
Output
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to ground
for stability. For best transient response, use a 1-µF or larger ceramic capacitor from OUT to
ground. Place the output capacitor as close to output of the device as possible; see the
Recommended Operating Conditions table.
(1)
4
Ground pin. This pin must be connected to ground and the thermal pad.
Preview package.
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SBVS375A – JULY 2019 – REVISED DECEMBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage
Current
(2)
MAX
–0.3
6.5
VEN
–0.3
6.5
VOUT
–0.3
VIN + 0.3 or 5.5 (2)
Maximum output
Temperature
(1)
MIN
VIN
UNIT
V
Internally limited
A
Operating junction, TJ
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Maximum is VIN + 0.3 V or 5.5 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VEN
NOM
MAX
UNIT
1.5
6.0
V
Enable voltage
0
6.0
V
VOUT
Output voltage
0.8
5.0
V
IOUT
Output current
0
200
mA
CIN
Input capacitor
COUT
Output capacitor (1)
FEN
EN toggle frequency
TJ
Operating junction temperature
(1)
(2)
1
(2)
1
µF
1
–40
22
µF
10
kHz
125
°C
Effective output capacitance of 0.5 µF minimum required for stability.
22 µF is the maximum derated capacitance that can be used for stability.
6.4 Thermal Information
TPS7A03
THERMAL METRIC
(1)
DQN (X2SON)
DBV (SOT-23-5)
YCH (DSBGA)
4 PINS
5 PINS
4 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
179.1
TBD
TBD
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
137.6
TBD
TBD
°C/W
RθJB
Junction-to-board thermal resistance
116.3
TBD
TBD
°C/W
ψJT
Junction-to-top characterization parameter
6.1
TBD
TBD
°C/W
ψJB
Junction-to-board characterization parameter
116.3
TBD
TBD
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
112.3
TBD
TBD
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
Nominal accuracy
Accuracy over
temperature
TEST CONDITIONS
MIN
TJ = 25°C, VOUT ≥ 1.5 V, 1 µA (1) ≤ IOUT ≤ 1 mA
15
1.5
%
–20
20
mV
5
mV
VOUT < 1.5 V
Load regulation (3)
1 mA ≤ IOUT ≤ 200 mA,
VIN = VOUT(nom) + 0.5 V (2)
IGND
Ground current
IOUT = 0 mA
IGND/IOUT
Ground current vs
load current
TJ = –40°C to +125°C
TJ = –40°C to +125°C
TJ = –40°C to +85°C
20
TJ = –40°C to +125°C
1 mA ≤ IOUT ≤ 100 mA
TJ = 25°C
200
TJ = –40°C to +85°C
Ground current in
dropout (1)
IOUT = 0 mA, VIN = 95% x VOUT(NOM)
ISHDN
Shutdown current
VEN = 0 V, 1.5 V ≤ VIN ≤ 5.0 V, TJ = 25°C
VOUT = 90% × VOUT(nom)
Dropout voltage (4)
TJ = –40°C to +125°C
nA
0.25
%
0.15
TJ = 25°C
220
nA
3
10
nA
VOUT < 2.5V,
VIN = VOUT(nom) +
VDO(max) + 1.0 V
240
450
750
mA
VOUT ≥ 2.5V,
VIN = VOUT(nom) +
VDO(max) + 0.5 V
240
450
750
mA
65
mA
0.8 V ≤ VOUT < 1.0 V
1050
1.0 V ≤ VOUT < 1.2 V
790
1.2 V ≤ VOUT < 1.5 V
650
1.5 V ≤ VOUT < 1.8 V
490
1.8 V ≤ VOUT < 2.5 V
400
2.5 V ≤ VOUT < 3.3 V
310
3.3 V ≤ VOUT ≤ 5.0 V
270
0.8 V ≤ VOUT < 1.0 V
1100
1.0 V ≤ VOUT < 1.2 V
850
1.2 V ≤ VOUT < 1.5 V
700
1.5 V ≤ VOUT < 1.8 V
560
1.8 V ≤ VOUT < 2.5 V
450
2.5 V ≤ VOUT < 3.3 V
360
3.3 V ≤ VOUT ≤ 5.0 V
310
PSRR
Power-supply
rejection ratio
f = 1 kHz, IOUT = 30 mA
VN
Output voltage
noise
BW = 10 Hz to 100 kHz, VOUT = 0.8 V, IOUT = 30 mA
VUVLO
UVLO threshold
6
mV
1
TJ = 25°C
Short-circuit current
VOUT = 0 V
limit
TJ = –40°C to +85°C
250
300
IOUT ≥ 100 mA
IGND(DO)
38
50
20 µA ≤ IOUT < 1 mA
(1)
(2)
(3)
(4)
mV
–15
ΔVOUT(ΔIOUT)
VDO
%
–1.5
VOUT(nom) + 0.5 V ≤ VIN ≤ 6.0 V (2)
ISC
UNIT
1
VOUT ≥ 1.5 V
Line regulation
Output current limit
MAX
TJ = 25°C; VOUT < 1.5 V
ΔVOUT(ΔVIN)
ICL
TYP
–1
mV
55
dB
130
µVRMS
VIN rising
1.23
1.3
1.47
VIN falling
1.0
1.12
1.41
V
Specified by design
VIN = 2.0 V for VOUT ≤ 1.5 V.
Load Regulation is normalized to the output voltage at IOUT = 1 mA.
Dropout is measured by ramping VIN down until VOUT = VOUT(nom) x 95%, with IOUT = 200 mA.
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Electrical Characteristics (continued)
Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
VIN hysteresis
TYP
VUVLO(HYST)
UVLO hysteresis
VEN(HI)
EN pin logic high
voltage
VEN(LOW)
EN pin logic low
voltage
IEN
EN pin leakage
current
VEN = VIN = 6.0 V
REN(PULLDOWN)
Smart enable
pulldown resistor
VEN = 0.3 V
RPULLDOWN
Pulldown resistor
VIN = 3.3 V, device disabled
TSD(shutdown)
Thermal shutdown
temperature
Shutdown, temperature increasing
170
TSD(reset)
Thermal shutdown
reset temperature
Reset, temperature decreasing
145
MAX
180
UNIT
mV
1.1
V
0.3
V
10
nA
500
KΩ
60
Ω
°C
6.6 Switching Characteristics
Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
500
800
1.5V < VOUT ≤ 3.0 V
750
1200
3.0V < VOUT ≤ 5.0 V
1200
1600
0.8V ≤ VOUT ≤ 1.5 V
tSTR
Start-up time
From EN assertion to VOUT = 90% × VOUT(nom)
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UNIT
µs
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6.7 Typical Characteristics
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
300
-55°C
-40°C
85°C
Quiescent Current (nA)
Quiescent Current (nA)
250
TJ
0°C
25°C
200
150
100
50
0
1.5
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
1.5
TJ
125°C
140°C
2
2.5
VOUT = 1.8 V, VIN = VEN = 2.3 V
3.5
4
4.5
Input Voltage (V)
5
5.5
6
IOUT = 0 mA, VEN = VIN
Figure 1. IQ vs VIN and Temperature
Figure 2. IQ vs VIN and Temperature
500
500000
TJ
25°C
85°C
125°C
TJ
450
140°C
-55°C
-40°C
400
Ground Current (PA)
-55°C
-40°C
0°C
100000
Ground Current (nA)
3
10000
1000
0°C
25°C
85°C
125°C
140°C
350
300
250
200
150
100
100
50
0.001
50
0
0.01
0.1
1
Output Current (mA)
10
0
100200
20
40
80 100 120 140
Output Current (mA)
160
180
200
VOUT = 1.8 V, VIN = VEN = 2.3 V
VOUT = 1.8 V, VIN = VEN = 2.3 V
Figure 4. IQ vs IOUT and Temperature Up to 200 mA
Figure 3. IQ vs IOUT and Temperature up to 200 mA
25
6000
TJ
TJ
5500
-55°C
-40°C
5000
0°C
25°C
85°C
125°C
-55°C
-40°C
140°C
20
4500
Ground Current (PA)
Ground Current (nA)
60
4000
3500
3000
2500
2000
1500
0°C
25°C
85°C
125°C
140°C
15
10
5
1000
500
0
0
0
0.2
0.4
0.6
Output Current (mA)
0.8
VOUT = 1.8 V, VIN = VEN = 2.3 V
Figure 5. IQ vs IOUT and Temperature Up to 1 mA
8
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1
2
3
4
5
6
7
Output Current (mA)
8
9
10
VOUT = 1.8 V, VIN = VEN = 2.3 V
Figure 6. IQ vs IOUT and Temperature for 1 mA to 10 mA
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
1.5
300
-55°C
-40°C
85°C
Quiescent Current (nA)
Quiescent Current (nA)
250
TJ
0°C
25°C
200
150
100
50
0
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
TJ
125°C
140°C
2
2.5
VOUT = 5.0 V, VIN = VEN
4
4.5
5
VOUT = 5.0 V, VIN = VEN
Figure 7. IQ in Dropout vs VIN and Temperature
Figure 8. IQ in Dropout vs VIN and Temperature
4000
6
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
TJ
-55°C
-40°C
5
3000
Quiescent Current (nA)
Quiescent Current (nA)
3
3.5
Input Voltage (V)
2000
1000
0°C
25°C
4
3
2
1
0
1.5
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
0
1.5
6
2
2.5
3
IOUT = 0 mA, VEN = 1.1 V
Figure 9. IQ vs VIN and Temperature
AC-Coupled Output Voltage (mV)
140°C
250
200
150
100
50
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
VEN = 0 V
Figure 11. ISHDN vs VIN and Temperature
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6
Figure 10. ISHDN vs VIN and Temperature
300
0
1.5
5.5
5.5
6
150
30
125
20
100
10
75
0
50
-10
25
-20
0
-30
-25
-40
-50
-50
-75
VOUT -60
IOUT
-70
300 350
-100
-150 -100
-50
0
50
100 150
Time (µs)
200
250
Output Current (mA)
Quiescent Current (nA)
TJ
85°C
125°C
5
VEN = 0 V
400
350
3.5
4
4.5
Input Voltage (V)
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 12. IOUT Transient From 1 mA to 10 mA
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Typical Characteristics (continued)
400
250
75
350
200
200
50
300
150
250
100
200
50
150
0
100
-50
150
25
100
0
50
-25
0
-50
-50
-75
-100
-100
-150
VOUT -125
IOUT
-150
300 350
-200
-150 -100
-50
0
50
100 150
Time (µs)
200
250
AC-Coupled Output Voltage (mV)
100
250
50
-100
0
-150
-50
-200
-100
-250
-150
-200
-150 -100
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
100 150
Time (µs)
200
250
TPS7
Figure 14. IOUT Transient From 1 mA to 100 mA
100
350
200
250
75
300
150
200
50
250
100
150
25
100
0
200
50
150
0
100
-50
50
-100
0
-150
-50
-200
-100
-200
-300 -250 -200 -150 -100 -50
0
Time (µs)
50
100
-250
VOUT
IOUT -300
-350
150 200
AC-Coupled Output Voltage (mV)
300
50
-25
0
-50
-50
-75
-100
-100
-150
VOUT -125
IOUT
-150
60
70
-200
-30
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
50
25
100
0
75
-25
50
-50
25
-75
0
-100
-25
-125
20
40
60
Time (ms)
80
100
120
-150
140
TPS7
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 17. IOUT Transient From 50 mA to 0 mA
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Output Current (mA)
125
Output Current (mA)
150
0
10
20
30
Time (µs)
40
50
TPS7
400
300
350
250
300
200
250
150
200
100
150
50
100
0
50
-50
0
-100
-50
-150
-100
-200
-150
-200
-20
-15
-10
-5
0
Time (µs)
5
10
VOUT
IOUT -250
-300
15
20
AC-Coupled Output Voltage (mV)
VOUT
IOUT 75
175
-20
0
Figure 16. IOUT Transient From 0 mA to 50 mA
100
-40
-10
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 15. IOUT Transient From 1 mA to 200 mA
200
-50
-60
-20
TPS7
Output Current (mA)
250
Output Current (mA)
AC-Coupled Output Voltage (mV)
50
400
-150
AC-Coupled Output Voltage (mV)
0
VOUT
IOUT -300
-350
300 350
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 13. IOUT Transient From 1 mA to 50 mA
10
-50
TPS7
Output Current (mA)
300
Output Current (mA)
AC-Coupled Output Voltage (mV)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
TPS7
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 18. IOUT Transient From 0 mA to 100 mA
Copyright © 2019, Texas Instruments Incorporated
TPS7A03
www.ti.com
SBVS375A – JULY 2019 – REVISED DECEMBER 2019
Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
200
VOUT
IOUT 150
150
100
50
100
0
75
-50
50
-100
25
-150
0
-200
-25
-250
-50
-50
-25
0
25
50
75
Time (ms)
100
250
250
200
200
150
150
100
100
50
50
-50
-50
-100
-100
-150
-150
-200
-200
-250
VOUT
IOUT -300
-350
60
70
-300
-30
-20
-10
0
10
TPS7
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
20
30
Time (µs)
40
50
TPS7
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 19. IOUT Transient From 100 mA to 0 mA
Figure 20. IOUT Transient From 0 mA to 200 mA
300
150
6
350
VOUT
IOUT 240
125
4.5
300
180
250
120
60
150
0
100
-60
50
-120
0
-180
-50
-240
-100
-60
-40
-20
0
20
40
60
Time (ms)
80
100
120
100
1.5
50
0
25
-1.5
0
-25
-50
-40
-300
140
3
75
Input Voltage (V)
200
AC-Coupled Output Voltage (mV)
400
Output Current (mA)
AC-Coupled Output Voltage (mV)
0
0
-250
-300
150
125
300
Output Current (mA)
125
AC-Coupled Output Voltage (mV)
175
AC-Coupled Output Voltage (mV)
Output Current (mA)
200
-3
-4.5
VOUT
VIN
0
40
80
120 160 200
Time (µs)
240
280
320
-6
360
Line
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, slew rate = 1 V/µs
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 22. VIN Transient From 2.8 V to 4.8 V
7.5
300
5
250
2.5
200
0
150
-2.5
100
-5
50
-7.5
0
-10
-50
-100
-150
-200
-200
-12.5
-15
VOUT
VIN
-100
-17.5
0
100
200 300
Time (µs)
400
500
600
-20
700
Line
VOUT = 1.8 V, IOUT = 1 mA, COUT = 1 µF, slew rate = 1 V/µs
Figure 23. VIN Transient From 2.8 V to 6.0 V
Copyright © 2019, Texas Instruments Incorporated
AC-Coupled Output Voltage (mV)
10
350
150
10
125
7.5
100
5
75
2.5
50
0
25
-2.5
0
-25
-50
-40
Input Voltage (V)
400
Input Voltage (V)
AC-Coupled Output Voltage (mV)
Figure 21. IOUT Transient From 200 mA to 0 mA
-5
-7.5
VOUT
VIN
-20
0
20
40
60
80
Time (µs)
100
120
140
-10
160
Line
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, slew rate = 1 V/µs
Figure 24. VIN Transient From 2.8 V to 6.0 V
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
5
5
4
3.5
3.5
3
3
2.5
2.5
2
2
1.5
1.5
1
0
-40
1
VOUT
VIN
0
0.5
40
80
120 160 200
Time (µs)
240
280
320
TJ
8
Input Voltage (V)
Output Voltage (V)
4
0.5
10
4.5
Change in Output Voltage (mV)
4.5
-55°C
-40°C
6
0°C
25°C
85°C
125°C
140°C
4
2
0
-2
-4
-6
-8
0
360
-10
2
Drop
2.5
3
3.5
4
4.5
Input Voltage (V)
VOUT = 1.8 V, IOUT = 100 mA, COUT = 1 µF, slew rate = 1 V/µs
5
5.5
6
VOUT = 1.8 V, IOUT = 1 mA
Figure 25. VIN Transient From 1.5 V to 4.5 V
Figure 26. Line Regulation vs VIN and Temperature
0.3
0.3
VOUT %
0°C
25°C
85°C
125°C
140°C
Output Voltage Accuracy %)
Output Voltage Accuracy (%)
TJ
-55°C
-40°C
0.1
-0.1
-0.3
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
-0.1
-0.3
-0.5
-60
-0.5
2
0.1
6
VOUT = 1.8 V, IOUT = 1 mA
-40
-20
0
20
40
60
80
Temperature (qC)
Figure 27. Output Accuracy vs VIN and Temperature
140150
Figure 28. Output Accuracy vs Temperature
0.5
TJ
-55°C
-40°C
15
0°C
25°C
TJ
85°C
125°C
140°C
Output Voltage Accuracy (%)
Change in Output Voltage (mV)
120
VOUT = 1.8 V, IOUT = 1 mA
20
10
5
0
-5
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
0.3
0.1
-0.1
-10
-15
-0.3
5
5.2
5.4
5.6
Input Voltage (V)
5.8
VOUT = 5.0 V, IOUT = 1 mA
Figure 29. Line Regulation vs VIN and Temperature
12
100
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6
5
5.2
5.4
5.6
Input Voltage (V)
5.8
6
VOUT = 5.0 V, IOUT = 1 mA
Figure 30. Output Accuracy vs VIN and Temperature
Copyright © 2019, Texas Instruments Incorporated
TPS7A03
www.ti.com
SBVS375A – JULY 2019 – REVISED DECEMBER 2019
Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
10
0.5
TJ
Change in Output Voltage (mV)
Output Voltage Accuracy %)
VOUT %
0.3
0.1
-0.1
-0.3
-0.5
-60
-55°C
-40°C
5
-5
-10
-15
-20
0
20
40
60
80
Temperature (qC)
100
120
140150
0
20
40
85°C
125°C
140°C
Dropout Voltage (mV)
Dropout Voltage (mV)
0°C
25°C
400
350
300
250
200
150
100
50
0
20
40
60
80 100 120 140
Output Current (mA)
80 100 120 140
Output Current (mA)
160
180
200
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
180
200
TJ
-55°C
-40°C
0
20
40
0°C
25°C
60
VOUT = 1.8 V
85°C
125°C
140°C
80 100 120 140
Output Current (mA)
160
180
200
VOUT = 5.0 V
Figure 33. Dropout vs IOUT and Temperature
Figure 34. Dropout vs IOUT and Temperature
300
600
TJ
TJ
0°C
25°C
85°C
125°C
140°C
-55°C
-40°C
250
Dropout Voltage (mV)
-55°C
-40°C
Dropout Voltage (mV)
160
Figure 32. Load Regulation vs VIN and Temperature
TJ
-55°C
-40°C
60
VOUT = 1.8 V
Figure 31. Output Accuracy vs Temperature
0
140°C
-20
-40
550
450
85°C
125°C
0
VOUT = 5.0 V, IOUT = 1 mA
500
0°C
25°C
400
200
0°C
25°C
85°C
125°C
140°C
200
150
100
50
0
1.5
0
2
2.5
3
3.5
4
Input Voltage (V)
4.5
IOUT = 200 mA
5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
IOUT = 50 mA
Figure 36. Dropout vs VIN and Temperature
Figure 35. Dropout vs VIN and Temperature
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
2.5
1.2
TJ
-55°C
-40°C
85°C
125°C
140°C
-55°C
-40°C
2
Output Voltage (V)
Output Voltage (V)
1
0°C
25°C
0.8
0.6
0.4
TJ
0°C
25°C
85°C
125°C
1.5
1
0.5
0.2
0
0
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
VOUT = 0.8 V
VOUT = 1.8 V
Figure 37. Foldback Current Limit vs IOUT and Temperature
Figure 38. Foldback Current Limit vs IOUT and Temperature
0.9
1.1
VEN(LOW)
VEN(HIGH)
0.85
VEN(LOW)
VEN(HIGH)
1.05
Enable Voltage (V)
Enable Voltage (V)
1
0.8
0.75
0.7
0.95
0.9
0.85
0.8
0.65
0.75
0.6
-60
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
0.7
-60
140150
-40
-20
0
VOUT = 0.8 V
Figure 39. EN High and Low Threshold vs Temperature
120
140150
Figure 40. EN High and Low Threshold vs Temperature
70
VUVLO(HIGH)
VUVLO(LOW)
0.8V
Pulldown Resistor (ohm)
65
1.4
UVLO Voltage (V)
100
VOUT = 5.0 V
1.5
1.45
20
40
60
80
Temperature (qC)
1.35
1.3
1.25
1.2
VOUT
1.8V
5.0V
60
55
50
45
1.15
1.1
-60
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140150
40
-60
-40
-20
0
20
40
60
80
Temperature (qC)
100 120 140 160
VOUT = 5.0 V, IOUT = 1 mA
Figure 41. UVLO Rising and Falling Threshold vs
Temperature
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Figure 42. Pulldown Resistor vs Temperature and VOUT
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TPS7A03
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SBVS375A – JULY 2019 – REVISED DECEMBER 2019
Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
100
580
0.8V
5.0V
Power Supply Rejection Ratio (dB)
Pulldown Resistor (ohm)
570
VOUT
1.8V
560
550
540
530
520
510
500
490
480
-60
-40
-20
0
20
40
60
80
Temperature (qC)
90
80
IOUT
10 mA
100 mA
200 mA
70
60
50
40
30
20
10
0
10
100 120 140 160
0 mA
1 mA
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 2.8 V, VOUT = 1.8 V, COUT = 1 µF
Figure 44. PSRR vs Frequency and IOUT
100
100
90
90
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
Figure 43. Smart Enable Pulldown Resistor vs Temperature
and VOUT
80
70
60
50
40
30
20
10
0
10
VIN
2.3 V
2.8 V
100
3.8 V
6.0 V
1k
10k
100k
Frequency (Hz)
1M
80
70
60
50
40
30
20
10
0
10
10M
90
50
80
70
60
50
40
30
20
2.3 V
100
1k
1M
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
Figure 47. PSRR vs Frequency and VIN
Copyright © 2019, Texas Instruments Incorporated
10k
100k
Frequency (Hz)
1M
10M
D001
VOUT
1.8 V, RMS Noise = 269.5 PV RMS
5.0 V, RMS Noise = 710 PV RMS
20
10
5
2
1
0.5
0.2
0.1
3.8 V
10k
100k
Frequency (Hz)
1k
Figure 46. PSRR vs Frequency and VIN
100
Output Voltage Noise (PV —Hz)
Power Supply Rejection Ratio (dB)
Figure 45. PSRR vs Frequency and VIN
0
10
100
6.0 V
VOUT = 1.8 V, IOUT = 100 mA, COUT = 1 µF
100
VIN
2.8 V
VIN
3.8 V
4.8 V
D001
VOUT = 1.8 V, IOUT = 10 mA, COUT = 1 µF
10
2.3 V
2.8 V
10M
D001
0.05
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = VOUT+ 1.0 V, IOUT = 1 mA, COUT = 1 µF
Figure 48. Output Noise vs Frequency and VOUT
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Typical Characteristics (continued)
50
30
20
IOUT
100 PA, RMS Noise = 117.5 PV RMS
1 mA, RMS Noise = 269.5 PV RMS
10
5
3
2
1
0.5
0.3
0.2
Output Voltage Noise (PV —Hz)
Output Voltage Noise (PV —Hz)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
50
30
20
COUT
1 PF, RMS Noise = 269.5 PVRMS
22 PF, RMS Noise = 301.1 PVRMS
10
5
3
2
1
0.5
0.3
0.2
0.1
0.1
0.05
10
0.05
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
100
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF
Figure 49. Output Noise vs Frequency and IOUT
4
VOUT
VEN
VIN
3
Voltage (V)
Voltage (V)
10M
Figure 50. Output Noise vs Frequency and COUT
VOUT
VEN = VIN
2
1
2
1
0
0
-1
-1
-2
-450 -300 -150
0
150 300 450
Time (ms)
600
750
-2
-450 -300 -150
900 1050
0
Star
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
150 300 450
Time (ms)
600
750
900 1050
Star
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
Figure 51. Startup With VEN = VIN
Figure 52. Startup With VEN Before VIN
5.5
6
VOUT
VEN
VIN
5
4.5
VOUT
VEN
VIN
4
4
3.5
Voltage (V)
Voltage (V)
1M
5
3
5
10k
100k
Frequency (Hz)
VOUT = 1.8 V, VIN = 2.8 V, IOUT = 1 mA
5
4
1k
3
2
3
2.5
2
1.5
1
1
0.5
0
0
-1
-600 -400 -200
0
200 400 600
Time (ms)
800 1000 1200 1400
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
Figure 53. Startup With VEN After VIN
16
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Star
-0.5
-450 -300 -150
0
150 300 450
Time (Ps)
600
750
900 1050
Star
VOUT = 1.8 V, IOUT = 0 mA, COUT = 1 µF
Figure 54. Startup With VEN After VIN
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TPS7A03
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SBVS375A – JULY 2019 – REVISED DECEMBER 2019
Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
9
10
9
8
VOUT
VEN
VIN
7
7
40
30
6
20
5
10
4
0
3
-10
2
-20
1
1
-30
0
0
Voltage (V)
6
5
4
3
2
-1
-800 -400
0
400
-40
-1
-400
800 1200 1600 2000 2400 2800 3200
Time (ms)
Star
-200
VOUT = 5.0 V, IOUT = 200 mA, COUT = 1 µF
0
200
400
600
Time (Ps)
800
1000
-50
1200
Star
VOUT = 1.8 V, IOUT = 0 mA
Figure 55. Startup With VEN After VIN
Figure 56. Startup Inrush Current With COUT= 1 µF
9
400
VIN
VEN
VOUT
IIN
8
7
300
200
6
100
5
0
4
-100
3
-200
2
-300
1
-400
0
Current (mA)
Voltage (V)
Current (mA)
Voltage (V)
50
VIN
VEN
VOUT
IIN
8
-500
-1
-400
-200
0
200
400
600
Time (Ps)
800
1000
-600
1200
VOUT = 1.8 V, IOUT = 0 mA
Figure 57. Startup Inrush Current With COUT= 22 µF
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7 Detailed Description
7.1 Overview
The TPS7A03 is a ultra-low IQ linear voltage regulator that is optimized for excellent transient performance.
These characteristics make the device ideal for most battery-powered applications.
This low-dropout linear regulator (LDO) offers active discharge, foldback current limit, shutdown, and thermal
protection capability.
7.2 Functional Block Diagram
Current
Limit
IN
1.2-V
Bandgap
OUT
+
Active Discharge
P-Version Only
±
±
Error
Amp
+
UVLO
Thermal
Shutdown
EN
Internal
Controller
Smart
Enable
Resistor
GND
18
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TPS7A03
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SBVS375A – JULY 2019 – REVISED DECEMBER 2019
7.3 Feature Description
7.3.1 Excellent Transient Response
The TPS7A03 includes several innovative circuits to ensure excellent transient response. Dynamic biasing
increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the
output response time to transients.
Adaptive biasing increases the IQ as the DC load current increases, extending the bandwidth of the loop. The
response time across the output voltage range is constant because a buffered reference topology is used, which
keeps the control loop in unity gain at any output voltage.
These features give the device a wide loop bandwidth during transients that ensures excellent transient response
while maintaining low IQ in steady-state conditions.
7.3.2 Active Discharge (P-Version Only)
The device has an internal pulldown MOSFET that connects a RPULLDOWN resistor to ground when the device is
disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin or by
the undervoltage lockout (UVLO).
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.
7.3.3 Low IQ in Dropout
In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for
low IQ LDOs. The TPS7A03 helps to reduce the battery discharge by detecting when the device is operating in
dropout conditions and maintaining a low IQ.
7.3.4 Smart Enable
The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable
pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than
the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the
enable pin to the input of the device.
This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven
above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable internal
pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is
connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical
Characteristics table.
This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the
output voltage.
7.3.5 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.
The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output
voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the
nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
VDO
RDS(ON) =
IRATED
(1)
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Feature Description (continued)
7.3.6 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the
voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output
voltage approaches GND. When the output is shorted, the device supplies a typical current called the shortcircuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 0.5 V.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the
device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If
the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
Figure 58 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
IOUT
0V
0 mA
IRATED
ISC
ICL
Figure 58. Foldback Current Limit
7.3.7 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.8 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
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Feature Description (continued)
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to
less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located
several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
8.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in
Figure 59 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.
tAt
tCt
tDt
B
tEt
tGt
tHt
F
Figure 59. Load Transient Waveform
During transitions from a light load to a heavy load, the:
•
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C)
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Application Information (continued)
During transitions from a heavy load to a light load, the:
•
•
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.4 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational
voltage range, and ensures that the device shuts down when the input supply collapses. Figure 60 shows the
UVLO circuit response to various input voltage events. The diagram can be separated into the following parts:
•
•
•
•
•
•
•
Region A: The device does not start until the input reaches the UVLO rising threshold.
Region B: Normal operation, regulating device.
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device remains enabled.
Region D: Normal operation, regulating device.
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
Region F: Normal operation followed by the input falling to the UVLO falling threshold.
Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 60. Typical UVLO Operation
8.1.5 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT
(2)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A03 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
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Application Information (continued)
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA). Equation 4 rearranges Equation 3 for output current.
TJ = TA + (RθJA × PD)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
(3)
(4)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and
copper-spreading area, and is only used as a relative measure of package thermal performance. For a welldesigned thermal layout, RθJA is actually the sum of the X2SON package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.5.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
where:
•
•
•
PD is the power dissipated as explained in Equation 2
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(5)
8.1.5.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 61 and can be
separated into the following parts:
•
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See the Dropout Operation section for more details.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum rated
junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN –
VOUT increases the output current must decrease.
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
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Application Information (continued)
Output Current (A)
Figure 61 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
RθJA as given in the Thermal Information table.
Output current limited by
dropout
Rated output
current
Output current limited by thermals
Limited by
maximum VIN
Limited by
minimum VIN
VIN ± VOUT (V)
Figure 61. Region Description of Continuous Operation Regime
8.2 Typical Application
CIN
IN
OUT
COUT
Device
VBAT
Load
EN
GND
Figure 62. Operation From a Battery Input Supply
8.2.1 Design Requirements
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
1.8 V to 3.0 V (two 1.5-V batteries)
Output voltage
1.0 V, ±1%
Input current
200 mA, maximum
Output load
10-mA DC
Maximum ambient temperature
70°C
8.2.2 Detailed Design Procedure
For this design example, the 1.0-V, fixed-version TPS7A0310 is selected. A dual AA Alkaline battery was used,
thus a 1.0-µF input capacitor is recommended to minimize transient currents drawn from the battery. A 1.0-µF
output capacitor is also recommended for excellent load transient response. The dropout voltage (VDO) is kept
within the TPS7A02 dropout voltage specification for the 1.0-V output voltage option to keep the device in
regulation under all load and temperature conditions for this design. Use the recommend 1-µF input and output
capacitor because the input source has a high equivalent series resistor (ESR) of 600 mΩ (typ). The very small
ground current consumed by the regulator maintains a high current efficiency as compared to the load current
consumed by the system, as shown in Figure 63 which allows for long battery life. Equation 6 can be used to
calculate the current efficiency (Iη) of this system.
Iη(%) = IOUT / (IOUT + IQ) × 100
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8.2.3 Application Curve
105
100
Current Efficiency (%)
95
90
85
80
75
70
65
TJ
-55°C
-40°C
60
55
0.001
0.01
0°C
25°C
85°C
125°C
0.1
1
Output Current (mA)
10
140°C
100
TPS7
Figure 63. Current Efficiency vs IOUT and Temperature
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.5 V to 6.0 V. The input supply must
be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic
performance is optimum, the input supply must be at least VOUT(nom) + 0.5 V. TI highly recommends using a 1-µF
or greater input capacitor to reduce the impedance of the input supply, especially during transients.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
10.2 Layout Examples
VOUT
VIN
1
4
COUT
CIN
3
2
GND PLANE
Represents via used for
application specific connections
Figure 64. Layout Example for the DQN Package
VOUT
VIN
5
1
CIN
COUT
2
4
3
GND PLANE
Represents via used for
application specific connections
Figure 65. Layout Example for the DBV Package
IN
A1
CIN
OUT
A2
COUT
Via
B1
EN
B2
GND
Figure 66. Layout Example for the YCH Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature (1) (2)
(1)
(2)
PRODUCT
VOUT
TPS7A03xx(x)Pyyyz
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TPS7A03 family actively discharge
the output when the device is disabled.
YYY is the package designator.
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PTPS7A0315PDQNR
ACTIVE
X2SON
DQN
4
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A03185PDQNR
ACTIVE
X2SON
DQN
4
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0318PDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0320PDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0320PDQNR
ACTIVE
X2SON
DQN
4
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0322PDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0325PDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0325PDQNR
ACTIVE
X2SON
DQN
4
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0328PDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0328PDQNR
ACTIVE
X2SON
DQN
4
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0330PDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0333PDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
PTPS7A0336PDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
TPS7A0310PDQNR
PREVIEW
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TPS7A03185PDQNR
PREVIEW
X2SON
DQN
4
3000
TBD
Call TI
Call TI
-40 to 125
TPS7A0318PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
G3
TPS7A0320PDQNR
PREVIEW
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
GK
TPS7A0322PDQNR
PREVIEW
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
GP
TPS7A0323PDQNR
PREVIEW
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
GQ
Addendum-Page 1
GO
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
13-Jan-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7A0325PDQNR
PREVIEW
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
GN
TPS7A0328PDQNR
PREVIEW
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
GL
TPS7A0330PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
G4
TPS7A0331PDQNR
PREVIEW
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
GR
TPS7A0333PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
G5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jan-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS7A0318PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q2
TPS7A0330PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q2
TPS7A0333PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7A0318PDQNR
X2SON
DQN
4
3000
184.0
184.0
19.0
TPS7A0330PDQNR
X2SON
DQN
4
3000
184.0
184.0
19.0
TPS7A0333PDQNR
X2SON
DQN
4
3000
184.0
184.0
19.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DQN0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
A
1.05
0.95
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
0.48+0.12
-0.1
(0.05) TYP
2
0.05
0.00
NOTE 6
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
1
PIN 1 ID
(OPTIONAL)
NOTE 4
4
4X 0.28
0.15
0.3
0.2
0.1
0.05
C A B
C
(0.11)
3X 0.30
0.15
4215302/E 12/2016
NOTES:
1.
2.
3.
4.
5.
6.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
Shape of exposed side leads may differ.
Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DQN0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
(0.03)
4X (0.36)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7.
8.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DQN0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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