Texas Instruments | TPSM53604 36-V Input, 4-A Power Module in RLF QFN Package (Rev. A) | Datasheet | Texas Instruments TPSM53604 36-V Input, 4-A Power Module in RLF QFN Package (Rev. A) Datasheet

Texas Instruments TPSM53604 36-V Input, 4-A Power Module in RLF QFN Package (Rev. A) Datasheet
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TPSM53604
SNVSBC9A – NOVEMBER 2019 – REVISED DECEMBER 2019
TPSM53604 36-V Input, 4-A Power Module in RLF QFN Package
1 Features
3 Description
•
The TPSM53604 power module is a highly integrated
4-A power solution that combines a 36-V input, stepdown, DC/DC converter with power MOSFETs, a
shielded inductor, and passives in a thermallyenhanced QFN package. The 5 mm x 5.5 mm x
4 mm, 15-pin QFN package uses routable lead-frame
technology for enhanced thermal performance, small
footprint, and low EMI. The package footprint has all
pins accessible from the perimeter and a single large
thermal pad for simple layout and easy handling in
manufacturing.
1
•
•
•
•
•
•
•
•
•
•
•
5 mm × 5.5 mm × 4 mm routable lead-frame
(RLF) QFN package
– Industry’s smallest 36-V, 4-A footprint:
85 mm2 solution size (single sided)
– Low EMI: Meets CISPR11 radiated emissions
– Excellent thermal performance:
Up to 20 W output power at 85ºC, no airflow
– Standard footprint: single large thermal pad
and all pins accessible from perimeter
3.8 V to 36 V input voltage range
Output voltage range: 1 V to 7 V
Efficiency up to 95%
Power-good flag
Precision enable
Built-in hiccup-mode short-circuit protection, overtemperature protection, start-up into pre-bias
output, soft start, and UVLO
Operating IC junction range: –40°C to +125°C
Operating ambient range: –40°C to +105°C
Shock and vibration tested to Mil-STD-883D
Pin compatible with: 3-A TPSM53603
and 2-A TPSM53602
Create a custom design using the TPSM53604
with the WEBENCH® Power Designer
The total solution requires as few as four external
components and eliminates the loop compensation
and magnetics part selection from the design
process. The full feature set includes power good,
programmable UVLO, prebias start-up, overcurrent,
and overtemperature protections, making the
TPSM53604 an excellent device for powering a wide
range of applications.
Device Information(1)
DEVICE NUMBER
TPSM53604
PACKAGE
QFN-RLFMOD (15)
BODY SIZE (NOM)
5.0 mm × 5.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
General purpose wide VIN power supplies
Factory automation and control
Test and measurement
Aerospace and defense
Negative output voltage applications
RLF Package and Typical Layout
Simplified Schematic
CIN
EN
VOUT
VOUT
TPSM53604
RFBT
V5V
FB
RFBB
PGND
AGND
COUT
Efficiency (%)
PGOOD
VIN
VIN
5 VOUT Efficiency
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VOUT = 5 V
VIN
12 V
24 V
0
1
2
Output Current (A)
3
4
EFF5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM53604
SNVSBC9A – NOVEMBER 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Typical Characteristics (VIN = 5 V)............................ 7
Typical Characteristics (VIN = 12 V).......................... 8
Typical Characteristics (VIN = 24 V).......................... 9
Typical Characteristics (VIN = 36 V)........................ 10
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1
10.2
10.3
10.4
10.5
Layout Guidelines .................................................
Layout Examples...................................................
Theta JA versus PCB Area ...................................
Package Specifications .........................................
EMI........................................................................
23
23
24
25
25
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2019) to Revision A
•
2
Page
Changed device status from Advance Information to Production Data ................................................................................. 1
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SNVSBC9A – NOVEMBER 2019 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
RDA Package
15-Pin QFN
Top View
VIN
1
EN
2
13
V5V
NC
3
12
AGND
DNC
4
11
NC
VIN
14
15
PGND
DNC
5
10
NC
PGOOD
6
9
FB
VOUT
7
8
VOUT
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
12
AGND
G
Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are
measured with respect to this pin. This pin must be connected to PGND at a single point. See the
Layout section for a recommended layout.
4, 5
DNC
—
Do not connect. Do not connect these pins to ground, to another DNC pin, or to any other voltage. These
pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
2
EN
I
Enable pin. This pin turns the converter on when pulled high and turns off the converter when pulled low.
This pin can be connected directly to VIN. Do not float. This pin can be used to set the input under
voltage lockout with two resistors. See the Programmable Undervoltage Lockout (UVLO) section.
9
FB
I
Feedback input. Connect the mid-point of the feedback resistor divider to this pin. Connect the upper
resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower
resistor (RFBB) of the feedback divider to AGND.
3, 10,
11
NC
—
Not connected. These pins are not connected to any circuitry within the module. It is recommended that
these pins be connected to the PGND plane on the application board to enhance shielding and thermal
performance.
15
PGND
G
Power ground. This is the return current path for the power stage of the device. Connect this pad to the
input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See the
Layout section for a recommended layout.
6
PGOOD
O
Power-good pin. Open-drain output that asserts low if the feedback voltage is not within the specified
window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required and can be tied to the V5V pin or other
DC voltage less than 22 V. If not used, this pin can be left open or connected to PGND.
1, 14
VIN
I
Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these
pins and PGND in close proximity to the device.
7, 8
VOUT
O
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output
load and connect external output capacitors between these pins and PGND.
13
V5V
O
Internal 5-V LDO output. Supplies internal control circuits. Do not connect to external loads. This pin can
be used as logic supply for PGOOD pin.
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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range (1)
MIN
MAX
VIN to PGND
PARAMETER
–0.3
38
EN to AGND (2)
–0.3
VIN + 0.3
PGOOD to AGND (2)
–0.3
22
FB to AGND
–0.3
5.5
AGND to PGND
–0.3
0.3
VOUT to PGND (2)
-0.3
VIN + 0.3
0
5.5
Operating IC junction temperature, TJ (3)
–40
150
°C
Storage temperature, Tstg
–55
150
°C
245
°C
Input voltage
Output voltage
V5V to AGND
Peak reflow case temperature
Maximum number or reflows allowed
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
(2)
(3)
V
V
3
Mechanical vibration
(1)
UNIT
20
G
500
G
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the
internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area
(SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the
module is never exceeded.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM) (1)
±2500
Charged-device model (CDM) (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
(1)
Input voltage, VIN
MIN
MAX
(2)
36
V
(3)
V
3.8
Output voltage, VOUT
1
Output current, IOUT
0
4
A
EN voltage, VEN (4)
0
VIN
V
PGOOD pullup voltage, VPGOOD (4)
0
18
V
3
mA
PGOOD sink current
Operating ambient temperature, TA
–40
Input capacitance, CIN
Output capacitance, COUT
(1)
(2)
(3)
(4)
(5)
(6)
4
20
(5)
min
(6)
7
UNIT
105
°C
µF
1000
µF
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
The recommended minimum VIN is 3.8 V or (VOUT + 1 V), whichever is greater. See the Voltage Dropout section for more information.
The recommended maximum output voltage varies depending input voltage. See the Voltage Dropout section for more information.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
Minimum CIN of 20 µF must be ceramic type.
The minimum amount of required output capacitance varies depending on the output voltage (see Table 1).
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6.4 Thermal Information
TPSM53604
THERMAL METRIC (1)
RDA (QFN)
UNIT
15 PINS
RθJA
Junction-to-ambient thermal resistance
(2)
19.5
°C/W
1.0
°C/W
5.5
°C/W
Thermal shutdown temperature
165
°C
Recovery temperature
148
°C
(3)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
TSHDN
(1)
(2)
(3)
(4)
(4)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 75 mm x 75 mm four-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow and PCB copper area reduces RθJA. For more information, see the Theta JA
versus PCB Area section.
The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
6.5 Electrical Characteristics
Limits apply over TA = –40°C to +105°C, VIN = 12 V, VOUT = 3.3 V, IOUT = IOUT maximum, (unless otherwise noted); CIN1 =
2x10 µF, 50-V, 1206 ceramic; CIN2 = 100 nF, 50-V, 0603 ceramic; COUT = 3x22 µF, 25-V, 1210 ceramic. Minimum and
maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm
and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (VIN)
Over IOUT range
VIN turn on
VIN increasing, IOUT = 0.2 A
3.55
VIN turn off
VIN decreasing, IOUT = 0.2 A
3.05
V
IQ
Quiescient current
Non-switching, VFB = 1.2 V
24
µA
ISHDN
Shutdown supply current
VEN = 0 V, IOUT = 0 A
VIN
3.8
(1)
Input voltage range
36
V
V
5
10
µA
4.75
5
5.25
V
0.985
1
1.015
V
INTERNAL LDO (V5V)
Internal LDO output voltage appearing
at the V5V pin
6 V ≤ VIN ≤ 36 V
Feedback voltage (2)
–40°C ≤ TJ ≤ +125°C, IOUT = 0.75 A
Load regulation
TA = +25°C, 0.8 A ≤ IOUT ≤ 4 A
0.06
Line regulation
TA = +25°C, IOUT = 0.75 A, Over VIN range
0.15
Current into FB pin
FB = 1 V
IOUT
Output current
TA = 25ºC
IOUT
Over-current threshold
5.5
A
VHC
FB pin voltage required to trip shortcircuit hiccup mode
0.4
V
tHC
Time between current-limit hiccup burst
94
ms
V5V
FEEDBACK
VFB
IFB
0.2
%
%
50
nA
4
A
CURRENT
0
ENABLE (EN PIN)
VEN-LDO-H
EN input level required to turn on
internal LDO
Rising threshold
VEN-LDO-L
EN input level required to turn off
internal LDO
Falling threshold
0.3
VEN-H
EN input level required to start switching Rising threshold
1.2
VEN-HYS
Hysteresis below VEN-H
Falling
100
mV
ILKG-EN
Enable input leakage current
VEN = 3.3 V
0.2
nA
(1)
(2)
1
V
V
1.23
1.26
V
The recommended minimum VIN is 3.8 V or (VOUT + 1 V), whichever is greater. See the Voltage Dropout section for more information.
The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
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Electrical Characteristics (continued)
Limits apply over TA = –40°C to +105°C, VIN = 12 V, VOUT = 3.3 V, IOUT = IOUT maximum, (unless otherwise noted); CIN1 =
2x10 µF, 50-V, 1206 ceramic; CIN2 = 100 nF, 50-V, 0603 ceramic; COUT = 3x22 µF, 25-V, 1210 ceramic. Minimum and
maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm
and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP
VOUT rising (fault)
% of FB voltage
107
%
VPG-HIGH-DN
VOUT falling (good)
% of FB voltage
105
%
VPG-LOW-UP
VOUT rising (good)
% of FB voltage
94
%
VPG-LOW-DN
VOUT falling (fault)
% of FB voltage
92
%
RPG
Power-good flag RDSON
VEN = 0 V
35
Ω
VIN-PG
Minimum input voltage for proper
PGOOD function
50-µA, EN = 0 V
VPG
PGOOD logic low output
50-µA, EN = 0 V, VIN = 2 V
2
V
0.2
V
PERFORMANCE
Efficiency
η
IOUT = 2 A, TA = 25ºC
91
%
4
ms
SOFT START
tSS
Internal soft-start time
SWITCHING FREQUENCY
ƒSW
(3)
6
Switching frequency
IOUT = 2 A, TA = 25ºC
1.4 (3)
MHz
The typical switching frequency of this device will change based on operating conditions. See the Auto Mode section for more
information.
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6.6 Typical Characteristics (VIN = 5 V)
100
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
90
80
70
Efficiency (%)
Efficiency (%)
The typical characteristic data has been developed from actual products tested at TA = 25°C. This data is considered typical
for the device.
0.5
1
1.5
2
2.5
Output Current (A)
VIN = 5 V
3
3.5
50
40
30
VOUT
3.3 V
2.5 V
1.8 V
1.0 V
0
60
VOUT
3.3 V
2.5 V
1.8 V
1.0 V
20
10
0
0.001
4
Linear Scale
Figure 1. Efficiency versus Output Current
1
4
D002
Log Scale
Figure 2. Efficiency versus Output Current
24
2.0
Output Voltage Ripple (mVpp)
VOUT
3.3 V
2.5 V
1.8 V
1.0 V
2.4
1.6
1.2
0.8
0.4
0.0
VOUT
3.3 V
2.5 V
1.8 V
1.0 V
20
16
12
8
4
0
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
0
0.5
VIN = 5 V
Figure 3. Power Dissipation versus Output Current
105
105
Ambient Temperature (°C)
115
95
85
75
65
Airflow
400LFM
200LFM
100LFM
Nat conv
45
35
3
3.5
4
D004
COUT = 4x 47µF
95
85
75
65
55
Airflow
400LFM
200LFM
100LFM
Nat conv
45
35
25
1.5
2
2.5
Output Current (A)
Figure 4. Voltage Ripple versus Output Current
115
55
1
D003
VIN = 5 V
Ambient Temperature (°C)
0.1
Output Current (A)
VIN = 5 V
2.8
Power Dissipation (W)
0.01
D001
25
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
0
0.5
D005
VIN = 5 V
VOUT = 1.0 V
PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper
1
1.5
2
2.5
Output Current (A)
3
3.5
4
D006
VIN = 5 V
VOUT = 3.3 V
PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper
Figure 5. Safe Operating Area
Figure 6. Safe Operating Area
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6.7 Typical Characteristics (VIN = 12 V)
100
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
90
80
70
Efficiency (%)
Efficiency (%)
The typical characteristic data has been developed from actual products tested at TA = 25°C. This data is considered typical
for the device.
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
1.8 V
1.0 V
0
0.5
1
1.5
2
2.5
Output Current (A)
VIN = 12 V
3
3.5
60
50
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
1.8 V
1.0 V
40
30
20
10
0
0.001
4
Linear Scale
Figure 7. Efficiency versus Output Current
4
D008
Log Scale
Figure 8. Efficiency versus Output Current
2.0
1.6
Output Voltage Ripple (mV)
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
1.8 V
1.0 V
1.2
0.8
0.4
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
1.8 V
1.0 V
20
16
12
8
4
0
0.0
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
0
4
0.5
Figure 9. Power Dissipation versus Output Current
105
Ambient Temperature (°C)
105
95
85
75
65
Airflow
400LFM
200LFM
100LFM
Nat conv
35
3.5
4
D010
COUT = 4x 47µF
95
85
75
65
55
Airflow
400LFM
200LFM
100LFM
Nat conv
45
35
25
3
Figure 10. Voltage Ripple versus Output Current
115
45
1.5
2
2.5
Output Current (A)
VIN = 12 V
115
55
1
D009
VIN = 12 V
Ambient Temperature (°C)
1
24
2.4
25
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
0
0.5
D010
VIN = 12 V
VOUT = 1.8 V
PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper
1
1.5
2
2.5
Output Current (A)
3
3.5
4
D011
VIN = 12 V
VOUT = 5 V
PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper
Figure 11. Safe Operating Area
8
0.1
Output Current (A)
VIN = 12 V
2.8
Power Dissipation (W)
0.01
D007
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Figure 12. Safe Operating Area
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6.8 Typical Characteristics (VIN = 24 V)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
90
80
70
Efficiency (%)
Efficiency (%)
The typical characteristic data has been developed from actual products tested at TA = 25°C. This data is considered typical
for the device.
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
1.8 V
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
60
50
40
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
1.8 V
30
20
10
0
0.001
4
0.01
D013
VIN = 24 V
Figure 13. Efficiency versus Output Current
4
D014
Figure 14. Efficiency versus Output Current
24
2.4
2.0
Output Voltage Ripple (mVpp)
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
1.8 V
2.8
Power Dissipation (W)
1
VIN = 24 V
3.2
1.6
1.2
0.8
0.4
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
1.8 V
20
16
12
8
4
0
0.0
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
0
4
0.5
VIN = 24 V
Figure 15. Power Dissipation versus Output Current
105
105
Ambient Temperature (°C)
115
95
85
75
65
Airflow
400LFM
200LFM
100LFM
Nat conv
45
35
3
3.5
4
D016
COUT = 4x 47µF
95
85
75
65
55
Airflow
400LFM
200LFM
100LFM
Nat conv
45
35
25
1.5
2
2.5
Output Current (A)
Figure 16. Voltage Ripple versus Output Current
115
55
1
D015
VIN = 24 V
Ambient Temperature (°C)
0.1
Output Current (A)
25
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
0
0.5
D016
VIN = 24 V
VOUT = 1.8 V
PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper
1
1.5
2
2.5
Output Current (A)
3
3.5
4
D017
VIN = 24 V
VOUT = 5 V
PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper
Figure 17. Safe Operating Area
Figure 18. Safe Operating Area
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6.9 Typical Characteristics (VIN = 36 V)
100
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
90
80
70
Efficiency (%)
Efficiency (%)
The typical characteristic data has been developed from actual products tested at TA = 25°C. This data is considered typical
for the device.
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
50
40
30
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
0
60
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
20
10
0
0.001
4
0.01
D019
VIN = 36 V
1
4
D020
VIN = 36 V
Figure 19. Efficiency versus Output Current
Figure 20. Efficiency versus Output Current
24
4.0
3.2
2.8
Output Voltage Ripple (mVpp)
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
3.6
Power Dissipation (W)
0.1
Output Current (A)
2.4
2.0
1.6
1.2
0.8
VOUT
7.0 V
5.0 V
3.3 V
2.5 V
20
16
12
8
4
0.4
0
0.0
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
0
4
0.5
VIN = 36 V
105
105
95
85
75
65
Airflow
400LFM
200LFM
100LFM
Nat conv
35
3.5
4
D022
COUT = 4x 47µF
95
85
75
65
55
Airflow
400LFM
200LFM
100LFM
Nat conv
45
35
25
25
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
0
0.5
D022
VIN = 36 V
VOUT = 1.8 V
PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper
1
1.5
2
2.5
Output Current (A)
3
3.5
4
D023
VIN = 36 V
VOUT = 5 V
PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper
Figure 23. Safe Operating Area
10
3
Figure 22. Voltage Ripple versus Output Current
115
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 21. Power Dissipation versus Output Current
45
1.5
2
2.5
Output Current (A)
VIN = 36 V
115
55
1
D021
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7 Detailed Description
7.1 Overview
The TPSM53604 is a full-featured, 36-V input, 4-A, synchronous step-down converter with PWM, MOSFETs,
shielded inductor, and control circuitry integrated into a low-profile, over-molded package. The device integration
enables small designs while providing the ability to adjust key parameters to meet specific design requirements.
The TPSM53604 provides an output voltage range of 1 V to 7 V. An external resistor divider is used to adjust the
output voltage to the desired value. The device provides accurate voltage regulation over a wide load range by
using a precision internal voltage reference. Input undervoltage lockout is internally set at 3.55 V (typical), but
can be adjusted upward using a resistor divider on the EN pin of the device. The EN pin can also be pulled low
to put the device into standby mode to reduce input current draw. A power-good signal is provided to indicate
when the output is within its nominal voltage range. Thermal shutdown and current limit features protect the
device during an overload condition. A 15-pin, QFN package that includes exposed bottom pads provides a
thermally enhanced solution for space-constrained applications.
7.2 Functional Block Diagram
Thermal
Shutdown
UVLO
LDO
V5V
Shutdown
Logic
Enable
Logic
EN
VIN
OCP
PGOOD
PGOOD
Logic
FB
Oscillator
±
+
+
Soft Start
VREF
Power
Stage
and
Control
Logic
2.2 µH
VOUT
Comp
AGND
PGND
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7.3 Feature Description
7.3.1 Adjusting the Output Voltage
A resistor divider connected to the FB pin (pin 9) sets the output voltage of the TPSM53604. The output voltage
adjustment range is from 1 V to 7 V. Figure 25 shows the feedback resistor connections for setting the output
voltage. The recommended value of RFBT is 10 kΩ. Use Equation 1 to calculate the value for RFBB. Table 1 lists
the standard resistor values for several output voltages. The minimum required output capacitance for each
output voltage is also included in Table 1. The capacitance values listed represent the effective capacitance,
taking into account the effects of DC bias and temperature variation.
RFBB =
10
(k )
(VOUT ± 1)
(1)
VOUT
RFBT
10k
FB
RFBB
AGND
Figure 25. Setting the Output Voltage
Table 1. Setting the Output Voltage
(1)
VOUT (V)
RFBB (kΩ) (1)
COUT(MIN) (µF)
(EFFECTIVE)
VOUT (V)
RFBB (kΩ) (1)
COUT(MIN) (µF)
(EFFECTIVE)
1.0
open
150
3.0
4.99
57
1.1
100
143
3.3
4.32
52
1.2
49.9
132
4.0
3.32
43
1.3
33.2
123
4.5
2.87
39
1.4
24.9
115
5.0
2.49
35
1.5
20.0
107
5.5
2.21
32
1.8
12.4
91
6.0
2.00
30
2.0
10.0
82
6.5
1.82
28
2.5
6.65
67
7.0
1.65
26
RFBT = 10.0 kΩ
7.3.2 Switching Frequency
The switching frequency of the TPSM53604 is set to 1.4 MHz, internal to the device. The switching frequency
cannot be adjusted. When the load current is high enough and the device is operating in PWM mode, the device
operates at a fixed frequency. As the load current drops and the device switches to PFM mode, the switching
frequency is reduced, resulting in reduced power dissipation. See the Auto Mode section for typical information
on when the device switches from PWM mode to PFM mode.
12
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7.3.3 Input Capacitors
The TPSM53604 requires a minimum input capacitance of 20 μF (2 × 10 μF) of ceramic type. High-quality,
ceramic-type X5R or X7R capacitors with sufficient voltage rating are recommended. TI recommends an
additional 47 µF of non-ceramic capacitance for applications with transient load requirements. The voltage rating
of input capacitors must be greater than the maximum input voltage.
Table 2. Recommended Input Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
SIZE
Murata
X5R
1206
GRT31CR61H106ME01L
50
10
TDK
X5R
1206
CGA5L3X5R1H106M160AB
50
10
TDK
X7R
1206
CGA5L1X7R1H106K160AC
50
10
Murata
X7R
1210
GRM32ER71H106KA12L
50
10
TDK
X7R
1210
C3225X7R1H106M250AC
50
10
(1)
(2)
PART NUMBER
VOLTAGE RATING
(V)
CAPACITANCE
(µF)
(2)
Capacitor Supplier Verification, RoHS, Lead-free, and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Standard capacitance values
7.3.4 Output Capacitors
Table 1 lists the TPSM53604 minimum output capacitance. The effects of DC bias and temperature variation
must be considered when using ceramic capacitance. For ceramic capacitors, the package size, voltage rating,
and dielectric material contributes to differences between the standard rated value and the actual effective value
of the capacitance.
When adding additional capacitance above COUT(min), the capacitance can be ceramic type, low-ESR polymer
type, or a combination of the two. See Table 3 for a preferred list of output capacitors by vendor.
Table 3. Recommended Output Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
VOLTAGE RATING
(V)
CAPACITANCE
(µF)
(2)
ESR (3)
(mΩ)
TDK
X5R
C3225X5R0J476K
6.3
47
2
Murata
X7R
GCM32ER70J476KE19L
6.3
47
2
Murata
X5R
GRM21BR61A476ME15L
10
47
2
TDK
X5R
C3216X5R1A476M160AB
10
47
2
Murata
X7R
GRM32ER71A476KE15L
10
47
2
Murata
X5R
GRM32ER61C476K
16
47
3
TDK
X5R
C3225X5R0J107M
6.3
100
2
Murata
X5R
GRM32ER60J107M
6.3
100
2
Murata
X5R
GRM32ER61A107M
10
100
2
Kemet
X5R
C1210C107M4PAC7800
16
100
2
6.3
100
18
Panasonic
POSCAP
6TPE100MI
Panasonic
POSCAP
10TPF150ML
10
150
15
Panasonic
POSCAP
6TPF220M9L
6.3
220
9
Panasonic
POSCAP
6TPF330M9L
6.3
330
9
Panasonic
POSCAP
6TPE470MAZU
6.3
470
35
(1)
(2)
(3)
Capacitor Supplier Verification, RoHS, Lead-free, and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Standard capacitance values.
Maximum ESR at 100 kHz, 25°C.
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7.3.5 Output On/Off Enable (EN)
The voltage on the EN pin provides electrical ON/OFF control of the device. This input features precision
thresholds, allowing the use of an external voltage divider to provide a programmable UVLO (see the
Programmable Undervoltage Lockout (UVLO) section). Applying a voltage of VEN ≥ VEN-LDO_H causes the device
to enter standby mode, powering the internal LDO, but not producing an output voltage. Increasing the EN
voltage to VEN-H fully enables the device, allowing it to enter start-up mode and starting the soft-start period.
When the EN input is brought below VEN-H by VEN-HYS, the regulator stops running and enters standby mode.
Further decrease in the EN voltage to below VEN-LDO-L completely shuts down the device. Figure 26 shows this
behavior. The values for the various EN thresholds can be found in the Electrical Characteristics table.
EN
VEN-H
VEN-H ± VEN-HYS
VEN-LDO-H
VEN-LDO-L
V5V
5V
0
VOUT
VOUT
0
Figure 26. Precision Enable Behavior
The EN pin cannot be open circuit or floating. The simplest way to enable the operation of the TPSM53604 is to
connect the EN pin to VIN directly as shown in Figure 27. This allows self start-up of the TPSM53604 when VIN
is within the operation range.
If an application requires controlling the EN pin, an external logic signal can be used to drive EN pin as shown in
Figure 28. Applications using an open drain/collector device to interface with this pin require a pullup resistor to a
voltage above the enable threshold.
VIN
VIN
EN
EN
PGND
PGND
Figure 27. Enabling the Device
Figure 28. Typical Enable Control
7.3.6 Programmable Undervoltage Lockout (UVLO)
The TPSM53604 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin
voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 3.55 V (typical)
with a typical hysteresis of 500 mV.
14
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If an application requires a higher UVLO threshold, a resistor divider can be placed between VIN, the EN pin,
and AGND as shown in Figure 29. The enable rising threshold (VEN-H) is 1.23 V (typ) with 100 mV (typ)
hysteresis. Table 4 lists recommended resistor values for RENT and RENB to adjust the ULVO voltage.
To ensure proper start-up and reduce input current surges, TI recommends setting the UVLO threshold to
approximately 80% to 85% of the minimum expected input voltage.
VIN
VIN
RENT
EN
RENB
AGND
Figure 29. Adjustable UVLO
Table 4. Resistor Values for Adjusting UVLO
VIN UVLO (V)
6.5
10
15
20
25
30
RENT (kΩ)
100
100
100
100
100
100
RENB (kΩ)
23.7
14.3
9.09
6.65
5.23
4.32
7.3.7 Power Good (PGOOD)
The TPSM53604 has a built-in power-good signal (PGOOD) which indicates whether the output voltage is within
its regulation range. The PGOOD pin is an open-drain output that requires a pullup resistor to a nominal voltage
source of 18 V or less. The internal 5-V LDO output (V5V pin), can be used as the pullup voltage source. A
typical pull-up resistor value is between 10 kΩ and 100 kΩ. The maximum recommended PGOOD sink current is
3 mA.
Once the output voltage rises above 94% of the set voltage, the PGOOD pin rises to the pullup voltage level.
The PGOOD pin is pulled low when the output voltage drops lower than 92% or rises higher than 107% of the
nominal set voltage. See Figure 30 for typical power-good thresholds.
VFB
107%
105%
94%
92%
PGOOD
High
Low
Figure 30. Power-good Flag
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7.3.8 Light Load Operation
In light load conditions, the device turns on the high-side MOSFET until the inductor current reaches a controlled
minimum value of approximately 1 A. As the input voltage decreases, reducing the voltage headroom between
VIN and VOUT, the amount of time required to reach this minimum current increases. During this time, additional
energy flows from VIN to VOUT, resulting in increased output voltage ripple. To eliminate this behavior, the EN
UVLO function must be used to maintain at least 1 V of headroom above VOUT. Alternatively, additional output
capacitance can be added to reduce the output voltage ripple in applications that operate at light loads with very
low VIN to VOUT headroom.
7.3.9 Voltage Dropout
Voltage dropout is the difference between the input voltage and output voltage that is required to maintain output
voltage regulation while providing the rated output current.
To ensure the TPSM53604 maintains output voltage regulation over the operating temperature range, the
minimum VIN is 3.8 V or (VOUT + 1 V), whichever is greater.
The TPSM53604 operates in a frequency foldback mode when the dropout voltage is less than the
recommendation above. Frequency foldback reduces the switching frequency to allow the output voltage to
maintain regulation as input voltage decreases. At light load, the TPSM53604 operates in PFM mode which is a
reduced frequency operation, see the Auto Mode section for more information on PFM mode. Figure 31 through
Figure 36 show typical dropout voltage and frequency foldback curves for 3.3 V, 5 V, and 7 V outputs at TA =
25°C.
NOTE
As ambient temperature increases, dropout voltage and frequency foldback occur at
higher input voltage.
1500
3.6
3.5
IOUT
IOUT
0A
2A
4A
Switching Frequency (kHz)
3.4
1400
Output Voltage (V)
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
2A
4A
1300
1200
1100
1000
900
800
2.5
700
2.4
2.3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Input Voltage (V)
4
4.1
4.2
600
3.5
3.6
D041
3.8
3.9
4
4.1
Input Voltage (V)
4.2
4.3
D044
VOUT = 3.3 V
VOUT = 3.3 V
Figure 32. Frequency Foldback
Figure 31. Voltage Dropout
16
3.7
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5.2
5.1
1500
IOUT
IOUT
0A
2A
4A
5
Switching Frequency (kHz)
4.9
4.8
Output Voltage (V)
2A
4A
1400
4.7
4.6
4.5
4.4
4.3
4.2
4.1
1300
1200
1100
1000
900
800
4
3.9
700
3.8
3.7
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Input Voltage (V)
600
5.4
5.8
5.5
5.6
5.9
6
D045
Figure 34. Frequency Foldback
Figure 33. Voltage Dropout
1500
7.2
IOUT
IOUT
0A
2A
4A
7
1400
Switching Frequency (kHz)
6.9
6.8
Output Voltage (V)
5.8
VOUT = 5 V
VOUT = 5 V
7.1
5.7
Input Voltage (V)
D042
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6
2A
4A
1300
1200
1100
1000
900
800
5.9
700
5.8
5.7
6.5
6.6
6.7
6.8
6.9
7
7.1
7.2
7.3
7.4
7.5
7.6
Input Voltage (V)
7.7
7.8
7.9
8
600
7.6
D043
VOUT = 7 V
7.7
7.8
7.9
8
8.1
Input Voltage (V)
8.2
D046
VOUT = 7 V
Figure 35. Voltage Dropout
Figure 36. Frequency Foldback
7.3.10 Overcurrent Protection (OCP)
The TPSM53604 is protected from overcurrent conditions. Cycle-by-cycle current limit is used for overloads while
hiccup mode is used for short circuits. Hiccup mode is activated if a fault condition persists on the output. Hiccup
mode reduces power dissipation under severe overcurrent conditions and prevents overheating and potential
damage to the device. In hiccup mode, the regulator is shut down and kept off for 94 ms typical before the
TPSM53604 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup repeats until the
fault condition is removed. Once the fault is removed, the module automatically recovers with a normal soft-start
power up.
The typical current limit threshold for the TPSM53604 varies slightly as a function of input voltage and output
voltage. Figure 37 shows the typical current limit threshold for several output voltages over the input voltage
range.
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5.8
5.6
Typical Current Limit (A)
5.4
5.2
5.0
4.8
4.6
VOUT
1V
1.8 V
3.3 V
5V
7V
4.4
4.2
4.0
0
5
10
15
20
25
30
35
Input Voltage (V)
40
D024
Figure 37. Current Limit Threshold
7.3.11 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
165°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 148°C
typically.
18
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7.4 Device Functional Modes
7.4.1 Active Mode
The TPSM53604 is in active mode when VIN is above the turn-on threshold and the EN pin voltage is above the
EN high threshold. The most direct way to enable the TPSM53604 is to connect the EN pin to VIN. This allows
self start-up of the TPSM53604 when the input voltage is in the operation range of 3.8 V to 36 V. Connecting a
resistor divider between VIN, EN, and AGND adjusts the UVLO to delay the turn on until VIN is closer to its
regulated voltage.
7.4.2 Auto Mode
In auto mode, the device moves between Pulse-Width Modulation (PWM) and Pulse-Frequency Modulation
(PFM) as the load changes. At light loads, the regulator operates in PFM mode. At higher loads, the mode
changes to PWM mode. The typical load current for which the device moves from PFM to PWM can be found in
Figure 38 and Figure 39. The output current at which the device changes modes depends on the input voltage
and the output voltage. For output currents above the curve, the device is in PWM mode. If the curve is a solid
line, the PWM switching frequency is 1.4 MHz nominal. If the curve is a dashed line, the PWM switching
frequency is reduced due to the minimum on-time of the internal controller to maintain output voltage regulation.
For currents below the curves, the device is in PFM mode. For applications where the switching frequency must
be known for a given condition, the above mentioned effects must be carefully tested before the design is
finalized.
In PWM mode, the regulator operates at a constant frequency using PWM to regulate the output voltage. While
operating in this mode, the output voltage is regulated by switching at a constant frequency and modulating the
duty cycle to control the power to the load. This provides excellent line and load regulation and low output
voltage ripple.
In PFM mode, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load.
The duration of the burst and the actual switching frequency depends on the input voltage, output voltage, and
load current. The frequency of these bursts is adjusted to regulate the output while diode emulation is used to
maximize efficiency. This mode provides high light-load efficiency by reducing the amount of input supply current
required to regulate the output voltage at small loads. However, in this mode, expect larger output voltage ripple
and variable switching frequency.
Figure 38. PFM/PWM Thresholds (3.3 V, 5 V, and 7 V)
Figure 39. PFM/PWM Thresholds (1 V and 1.8 V)
7.4.3 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPSM53604. When the EN pin voltage is below the
EN low threshold, the device is in shutdown mode. In shutdown mode, the standby current is 5 μA typical.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPSM53604 is a synchronous, step-down, DC/DC power module. It is used to convert a higher DC voltage
to a lower DC voltage with a maximum output current of 4 A. The TPSM53604 can be configured in a negative
output voltage, inverting buck-boost (IBB) topology. For more details, see the Negative Output Voltage using the
TPSM53602/3/4 application note. The following design procedure can be used to select components for the
TPSM53604. Alternately, the WEBENCH® software can be used to generate complete designs. When generating
a design, the WEBENCH® software uses an iterative design procedure and accesses comprehensive databases
of components. See www.ti.com for more details.
8.2 Typical Application
The TPSM53604 only requires a few external components to convert from a wide input voltage supply range to a
wide range of output voltages. Figure 40 shows a basic TPSM53604 schematic for a typical design.
V5V
100 kO
VIN = 24 V
PGOOD
VIN
VOUT = 5 V
VOUT
10 µF
50 V
10 µF
50 V
TPSM53604
10 kO
100 kO
47 µF
10 V
FB
47 µF
10 V
EN
PGND
AGND
2.49 kO
Figure 40. TPSM53604 Typical Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 5 as the input parameters and follow the design
procedures in the Detailed Design Procedure section.
Table 5. Design Example Parameters
20
DESIGN PARAMETER
VALUE
Input voltage VIN
24 V typical
Output voltage VOUT
5V
Output current rating
4A
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM53604 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the TPSM53604 device is externally adjustable using a resistor divider. The recommended
value of RFBT is 10 kΩ. The value for RFBB can be selected from Table 1 or calculated using Equation 2:
RFBB =
10
(VOUT ± 1)
(k )
(2)
For the desired output voltage of 5 V, the formula yields a value of 2.5 kΩ. Choose the closest available value of
2.49 kΩ for RFBB.
8.2.2.3 Input Capacitors
The TPSM53604 requires a minimum input capacitance of 20 µF (or 2 × 10 μF) ceramic type. High-quality
ceramic type X5R or X7R capacitors with sufficient voltage rating are recommended. An additional 47 µF of nonceramic capacitance is recommended for applications with transient load requirements. The voltage rating of the
input capacitors must be greater than the maximum input voltage.
For this design example, two 10-µF, 50-V, ceramic capacitors are used.
8.2.2.4 Output Capacitor Selection
The TPSM53604 requires a minimum amount of output capacitance for proper operation. The minimum amount
of required output varies depending on the output voltage. See Table 1 for the required output capacitance.
For this design example, two 47-µF, 10-V, ceramic capacitors are used.
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8.2.3 Application Curves
VIN
VIN
EN
EN
VOUT
VOUT
PGOOD
PGOOD
VIN = 24 V
VOUT = 5 V
COUT = 2 × 47 µF
VIN = 24 V
VOUT = 5 V
COUT = 2 × 47 µF
Figure 42. Enable Turn-OFF
Figure 41. Enable Turn-ON
VOUT
IOUT
VIN = 24 V
IOUT = 1 A to 3 A
VOUT = 5 V
Slew rate: 1 A/µs
COUT = 2 × 47 µF
Figure 43. Transient Response
9 Power Supply Recommendations
The TPSM53604 is designed to operate from an input voltage supply range between 3.8 V and 36 V. This input
supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the TPSM53604 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few centimeters from the TPSM53604, additional bulk capacitance can
be required in addition to the ceramic bypass capacitors. The typical amount of bulk capacitance is a 47-µF
electrolytic capacitor.
22
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10 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. The following guidelines help users design a PCB with the best power conversion performance,
optimal thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 44 through
Figure 46 show a typical PCB layout. The following are some considerations for an optimized layout.
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Connect AGND to PGND at a single point.
• Place RFBT and RFBB as close as possible to the FB pin.
• Use multiple vias to connect the power planes to internal layers.
10.2 Layout Examples
Figure 44. Typical Top-Layer Layout
Figure 45. Typical Layer-2 Layout
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Layout Examples (continued)
Figure 46. Typical PGND Layer
10.3 Theta JA versus PCB Area
The amount of PCB copper affects the thermal performance of the device. Figure 47 shows the effects of copper
area on the junction-to-ambient thermal resistance (RθJA) of the TPSM53604. The junction-to-ambient thermal
resistance is plotted for a 4-layer PCB with PCB area from 30 cm2 to 80 cm2.
To determine the required copper area for an application:
1. Determine the maximum power dissipation of the device in the application by referencing the power
dissipation graphs in sections Typical Characteristics (VIN = 5 V) through Typical Characteristics (VIN = 36 V).
2. Calculate the maximum RθJA using Equation 3 and the maximum ambient temperature of the application.
TA(max) )
(125qC
RTJA
(qC / W)
PD(max)
(3)
3. Reference Figure 47 to determine the minimum required PCB area for the application conditions.
24
4-layer PCB
23
Theta JA (°C/W)
22
21
20
19
18
30
40
50
60
70
80
PCB Area (cm²)
D047
Figure 47. RθJA versus PCB Area (per Layer)
24
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10.4 Package Specifications
TPSM53604
Weight
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
VALUE
UNIT
429
mg
89.3
MHrs
10.5 EMI
The TPSM53604 is compliant with EN55011 Class-B radiated emissions. Figure 48 and Figure 49 show typical
examples of radiated emissions plots for the TPSM53604. The graphs include the plots of the antenna in the
horizontal and vertical positions.
EMI plots were measured using the standard TPSM53604EVM with no input filter.
Figure 48. Radiated Emissions 24-V Input, 5-V Output, 4-A Load
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EMI (continued)
Figure 49. Radiated Emissions 12-V Input, 5-V Output, 4-A Load
26
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SNVSBC9A – NOVEMBER 2019 – REVISED DECEMBER 2019
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM53604 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, Negative Output Voltage Using the TPSM53602/3/4 application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPSM53604RDAR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
B3QFN
RDA
15
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
TPSM53604
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
RDA0015A
B3QFN - 4.1 mm max height
SCALE 1.800
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.6
5.4
4.1 MAX
0.08 C
C
SEATING PLANE
2.5 0.05
3X
0.45
0.25
0.1
C A B
0.05
C
2X
1.5 0.05
1.3
1.1
10X
PKG
7
(0.16) TYP
8
2X 0.725
1.43
PKG
2.6 TYP
4.6 0.05
15
2.5 0.05
8X 0.65
2X 0.975
14
1
10X
0.6
0.4
PIN 1 ID
4X
1.3
1.1
0.6
0.4
0.1
0.05
C A B
C
4224086/C 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RDA0015A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.5)
(1.5)
4X (1.4)
PKG
4X (0.5)
14
1
2X (0.975)
10X (0.7)
10X (0.35)
(4.6)
PKG
15
(1)
TYP
(2.5)
2X (1.43)
8X (0.65)
2X (0.725)
7
8
(R0.05) TYP
(1) TYP
( 0.2) VIA
TYP
2X (4)
(4.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 16X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL EDGE
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK DEFINED
SOLDER MASK DETAILS
SCALE 30.000
4224086/C 03/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RDA0015A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
PKG
4X (1.35)
4X (0.6)
4X (0.45)
14
1
4X
(1.15)
10X (0.65)
2X (0.975)
15
10X (0.3)
PKG
4X
(0.65)
2X (1.43)
4X (0.475)
4X
(0.95)
4X (1.675)
8X (0.65)
2X (0.725)
7
8
(R0.05) TYP
4X (0.425)
4X (0.625)
2X (4)
(4.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15:
56% PRINTED SOLDER COVERAGE BY AREA
SCALE: 16X
4224086/C 03/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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