Texas Instruments | CSD17484F4 30-V N-Channel FemtoFET MOSFET (Rev. C) | Datasheet | Texas Instruments CSD17484F4 30-V N-Channel FemtoFET MOSFET (Rev. C) Datasheet

Texas Instruments CSD17484F4 30-V N-Channel FemtoFET MOSFET (Rev. C) Datasheet
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CSD17484F4
SLPS550C – MAY 2015 – REVISED DECEMBER 2019
CSD17484F4 30-V N-Channel FemtoFET™ MOSFET
1 Features
•
•
•
•
1
•
•
•
•
Product Summary
Low On-Resistance
Ultra-Low Qg and Qgd
Low-Threshold Voltage
Ultra-Small Footprint (0402 Case Size)
– 1.0 mm × 0.6 mm
Ultra-Low Profile
– 0.2-mm Height
Integrated ESD Protection Diode
– Rated > 4-kV HBM
– Rated > 2-kV CDM
Lead and Halogen Free
RoHS Compliant
TA = 25°C
TYPICAL VALUE
UNIT
VDS
Drain-to-Source Voltage
30
V
Qg
Gate Charge Total (4.5 V)
920
pC
Qgd
Gate Charge Gate-to-Drain
75
RDS(on)
Drain-to-Source On-Resistance
VGS(th)
Threshold Voltage
DEVICE
QTY
CSD17484F4
3000
CSD17484F4T
•
•
170
VGS = 2.5 V
125
VGS = 4.5 V
107
VGS = 8.0 V
99
0.85
mΩ
V
Device Information(1)
2 Applications
•
•
pC
VGS = 1.8 V
250
MEDIA
PACKAGE
SHIP
7-Inch Reel
Femto (0402)
1.00-mm × 0.60-mm
Land Grid Array (LGA)
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Optimized for Load Switch Applications
Optimized for General Purpose Switching
Applications
Battery Applications
Handheld and Mobile Applications
Absolute Maximum Ratings
TA = 25°C
3 Description
This 99-mΩ, 30-V, N-Channel FemtoFET™ MOSFET
is designed and optimized to minimize the footprint in
many handheld and mobile applications. This
technology is capable of replacing standard small
signal MOSFETs while providing at least a 60%
reduction in footprint size.
VALUE
UNIT
VDS
Drain-to-Source Voltage
30
V
VGS
Gate-to-Source Voltage
12
V
ID
Continuous Drain Current(1)
3.0
A
IDM
Pulsed Drain Current(1)(2)
18
A
Continuous Gate Clamp Current
35
Pulsed Gate Clamp Current(2)
350
Power Dissipation
500
IG
PD
V(ESD)
Human-Body Model (HBM)
4
Charged-Device Model (CDM)
2
TJ,
Tstg
Operating Junction,
Storage Temperature
EAS
Avalanche Energy, Single Pulse ID = 7.1 A,
L = 0.1 mH, RG = 25 Ω
mA
mW
kV
–55 to 150
°C
2.5
mJ
(1) Typical RθJA = 85°C/W on 1-in2 (6.45-cm2), 2-oz
(0.071-mm) thick Cu pad on a 0.06-in (1.52-mm) thick FR4
PCB.
(2) Pulse duration ≤ 100 μs, duty cycle ≤ 1%.
Typical Part Dimensions
Top View
D
mm
G
S
60
0.
1.
0
0
m
m
0
0.2
m
m
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD17484F4
SLPS550C – MAY 2015 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Device and Documentation Support.................... 7
6.1
6.2
6.3
6.4
6.5
7
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1 Mechanical Dimensions ............................................ 8
7.2 Recommended Minimum PCB Layout...................... 9
7.3 Recommended Stencil Pattern ................................. 9
4 Revision History
Changes from Revision B (September 2017) to Revision C
•
Changed On-State Resistance vs Gate-to-Source Voltage by truncating VGS from 20 V to 12 V ......................................... 4
Changes from Revision A (August 2017) to Revision B
•
Page
Page
Deleted the CSD68830F4 Embossed Carrier Tape Dimensions section............................................................................... 9
Changes from Original (May 2015) to Revision A
Page
•
Added the Receiving Notification of Documentation Updates and the Community Resources sections to Device and
Documentation Support .......................................................................................................................................................... 7
•
Updated the Mechanical, Packaging, and Orderable Information section ............................................................................. 8
2
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SLPS550C – MAY 2015 – REVISED DECEMBER 2019
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 24 V
100
nA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 12 V
50
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, IDS = 250 μA
V
RDS(on)
Drain-to-source on-resistance
gfs
Transconductance
30
0.65
V
0.85
1.10
VGS = 1.8 V, IDS = 0.5 A
170
270
VGS = 2.5 V, IDS = 0.5 A
125
160
VGS = 4.5 V, IDS = 0.5 A
107
128
VGS = 8 V, IDS = 0.5 A
99
121
VDS = 15 V, IDS = 0.5 A
4
mΩ
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
150
195
pF
44
57
Crss
Reverse transfer capacitance
pF
2.2
2.9
pF
RG
Series gate resistance
Qg
Gate charge total (4.5 V)
920
1200
pC
Qg
Gate charge total (8.0 V)
1570
2040
pC
Qgd
Gate charge gate-to-drain
75
pC
Qgs
Gate charge gate-to-source
280
pC
Qg(th)
Gate charge at Vth
140
pC
Qoss
Output charge
1400
pC
td(on)
Turnon delay time
3
ns
tr
Rise time
1
ns
td(off)
Turnoff delay time
11
ns
tf
Fall time
4
ns
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
Ω
8
VDS = 15 V, IDS = 0.5 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 0.5 A, RG = 2 Ω
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
ISD = 0.5 A, VGS = 0 V
VDS= 15 V, IF = 0.5 A, di/dt = 300 A/μs
0.73
0.9
V
1300
pC
6.2
ns
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
(1)
(2)
Junction-to-ambient thermal resistance
(1)
TYPICAL VALUES
85
Junction-to-ambient thermal resistance (2)
245
UNIT
°C/W
Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
Device mounted on FR4 material with minimum Cu mounting area.
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SLPS550C – MAY 2015 – REVISED DECEMBER 2019
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
10
VGS = 1.8 V
VGS = 2.5 V
VGS = 3.8 V
VGS = 4.5 V
9
8
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
10
7
6
5
4
3
2
1
TC = 125°C
TC = 25°C
TC = -55°C
9
8
7
6
5
4
3
2
1
0
0
0
0.25
0.5
0.75
1
1.25
1.5
VDS - Drain-to-Source Voltage (V)
1.75
2
0
0.5
D002
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage (V)
3.5
4
D003
VDS = 5 V
Figure 2. Saturation Characteristics
4
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Figure 3. Transfer Characteristics
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CSD17484F4
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SLPS550C – MAY 2015 – REVISED DECEMBER 2019
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
1000
7
6
C - Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
8
5
4
3
2
100
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
10
1
1
0
0
0.2
0.4
0.6
0.8
1
Qg - Gate Charge (nC)
ID = 0.5 A
1.2
1.4
0
1.6
3
6
D004
30
D005
Figure 5. Capacitance
1.15
250
RDS(on) - On-State Resistance (m:)
VGS(th) - Threshold Voltage (V)
27
VDS = 15 V
Figure 4. Gate Charge
1.05
0.95
0.85
0.75
0.65
0.55
0.45
0.35
-75
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
TC = 25qC, ID = 0.5 A
TC = 125qC, ID = 0.5 A
225
200
175
150
125
100
75
50
-50
-25
0
25
50
75 100
TC - Case Temperature (°C)
125
150
175
0
2
D006
4
6
8
VGS - Gate-to-Source Voltage (V)
10
12
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
10
1.4
VGS = 2.5 V
VGS = 4.5 V
ISD - Source-To-Drain Current (A)
Normalized On-State Resistance
1.5
1.3
1.2
1.1
1
0.9
0.8
0.7
-75
TC = 25qC
TC = 125qC
1
0.1
0.01
0.001
0.0001
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
175
0
0.2
0.4
0.6
0.8
VSD - Source-To-Drain Voltage (V)
D008
1
D009
ID = 0.5 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
IAV - Peak Avalanche Current (A)
IDS - Drain-To-Source Current (A)
100
10
1
0.1
100 ms
10 ms
0.01
0.01
1 ms
100 µs
10 µs
0.1
1
10
VDS - Drain-To-Source Voltage (V)
50
TC = 25q C
TC = 125q C
10
1
0.1
0.001
0.01
0.1
TAV - Time in Avalanche (ms)
D010
1
D011
Single pulse, typical RθJA = 85°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain-to-Source Current (A)
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100 125
TA - Ambient Temperature (°C)
150
175
D012
Figure 12. Maximum Drain Current vs Temperature
6
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CSD17484F4
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SLPS550C – MAY 2015 – REVISED DECEMBER 2019
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
6.3 Trademarks
FemtoFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD17484F4
SLPS550C – MAY 2015 – REVISED DECEMBER 2019
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
(1)
All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
(2)
This drawing is subject to change without notice.
(3)
This package is a PB-free solder land design.
Table 1. Pin Configuration
8
POSITION
DESIGNATION
Pin 1
Gate
Pin 2
Source
Pin 3
Drain
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SLPS550C – MAY 2015 – REVISED DECEMBER 2019
7.2 Recommended Minimum PCB Layout
(0.25)
2X (0.25)
PKG
0.05 MIN
ALL AROUND
2X (0.15)
1
3
SYMM
(0.35)
(0.5)
2
(R0.05) TYP
SOLDER MASK
OPENING
(0.65)
LAND PATTERN EXAMPLE
(1)
METAL UNDER
SOLDER MASK
All dimensions are in millimeters.
7.3 Recommended Stencil Pattern
2X (0.25)
2X (0.2)
PKG
(0.25)
1
SYMM
(0.4)
(0.5)
3
2
2X (0.15)
(R0.05) TYP
(0.65)
2X SOLDER MASK EDGE
(1)
All dimensions are in millimeters.
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PACKAGE OPTION ADDENDUM
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15-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD17484F4
ACTIVE
PICOSTAR
YJJ
3
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-55 to 150
G2
CSD17484F4T
ACTIVE
PICOSTAR
YJJ
3
250
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-55 to 150
G2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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16-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
CSD17484F4
PICOST
AR
YJJ
3
3000
178.0
9.2
CSD17484F4T
PICOST
AR
YJJ
3
250
178.0
9.2
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
0.7
1.1
0.28
4.0
8.0
Q2
0.7
1.1
0.28
4.0
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD17484F4
PICOSTAR
YJJ
3
3000
220.0
220.0
35.0
CSD17484F4T
PICOSTAR
YJJ
3
250
220.0
220.0
35.0
Pack Materials-Page 2
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