Texas Instruments | LMR36506 3 V–65 V, 0.6-A Ultra-Small Synchronous Buck Converter with 4 µA IQ | Datasheet | Texas Instruments LMR36506 3 V–65 V, 0.6-A Ultra-Small Synchronous Buck Converter with 4 µA IQ Datasheet

Texas Instruments LMR36506 3 V–65 V, 0.6-A Ultra-Small Synchronous Buck Converter with 4 µA IQ Datasheet
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1 Features
3 Description
•
The LMR36506 is the industry's smallest 65 V, 0.6 A
synchronous step-down DC/DC converter in 2-mm x
2-mm HotRod™ package. This robust and highly
reliable converter can handle input voltage transients
up to 70 V, provide excellent EMI performance and
support fixed 3.3 V and other adjustable output
voltages. The transient tolerance reduces the
necessary design effort to protect against input
overvoltage and meets the surge immunity
requirements of IEC 61000-4-5.
1
•
•
•
•
Designed for rugged industrial applications:
– Junction temperature range –40°C to +150°C
– Input transient protection up to 70 V
– Wide input voltage range: 3.0 V (falling
threshold) to 65 V
– Low EMI and minimized switch node ringing
– Adjustable fixed output voltage options
available
Suited for scalable industrial power supplies:
– Pin compatible with LMR36503 (65 V, 300 mA)
– Adjustable switching frequency: 200 kHz to 2.2
MHz with RT pin variant
Minimized solution size and cost:
– Highest power density with internal
compensation and reduced external
component count
– Ultra-small, 2-mm × 2-mm HotRod™ package
with wettable flanks
High efficiency across load range with low power
dissipation:
– 93% peak efficiency at 400 kHz (12 VIN, 3.3
VOUT fixed)
– 90% peak efficiency at 400 kHz (24 VIN, 3.3
VOUT fixed)
Ultra-low operating quiescent current at no load
– 4 µA at 24 VIN to 3.3 VOUT (fixed output option)
The LMR36506 uses the peak current mode control
architecture with internal compensation to maintain
stable operation with minimal output capacitance. The
LMR36506 with the right resistor selection from the
RT pin to ground can be externally programmed to
any desired switching frequency of operation over a
wide range from 200 kHz to 2.2 MHz. The precision
EN/UVLO feature allows precise control of the device
during the start-up and shutdown. The power-good
flag, with built-in glitch filter and delayed release,
offers a true indication of the system status,
eliminating the requirement for an external
supervisor. The compact solution size and rich
feature set of LMR36506 simplifies implementation
for a wide range of industrial applications.
Device Information(1)
PART NUMBER
LMR36506
PACKAGE
VQFN-HR (9)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
Factory automation: Field transmitters and
process sensors
Building automation: HVAC and fire safety
Appliances: Garden and power tools
Simplified Schematic
Efficiency vs Output Current
VOUT = 3.3 V (Fixed), 400 kHz
BOOT
VIN
VIN
CIN
100
CBOOT
EN/
UVLO
SW
VOUT
LIND
90
COUT
VCC
PGOOD
RFBT
CVCC
FB
GND
Efficiency (%)
80
RT
70
60
50
RFBB
40
30
0.001 0.002
VIN = 12V
VIN = 24V
0.005 0.01 0.02
0.05 0.1
Load Current (A)
0.2 0.3 0.5
1
D002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
LMR36506 3 V–65 V, 0.6-A Ultra-Small Synchronous Buck Converter with 4 µA IQ
LMR36506
SNVSBB6 – DECEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
5
5
5
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD (Commercial) Ratings.......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Characteristics...............................................
Switching Characteristics ..........................................
System Characteristics .............................................
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
9.3 What to Do and What Not to Do ............................. 21
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Detailed Description .............................................. 9
ADVANCE INFORMATION
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2019
*
Initial release
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5 Device Comparison Table
OUTPUT VOLTAGE
EXTERNAL SYNC
FSW
SPREAD SPECTRUM
LMR36506RFRPER
Adjustable
No
(Default FPWM at light
load)
Adjustable
with RT resistor
No
LMR36506R3RPER
3.3-V Fixed
No
(Default PFM at light load)
Adjustable
with RT resistor
No
LMR36506RF3RPER
3.3-V Fixed
No
(Default FPWM at light
load)
Adjustable
with RT resistor
No
LMR36506RRPER
Adjustable
No
(Default PFM at light load)
Adjustable
with RT resistor
No
ADVANCE INFORMATION
ORDERABLE PART
NUMBER
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6 Pin Configuration and Functions
RPE Package
9-Pin VQFN-HR
Top View (All variants)
GND
RT
1
PGOOD
GND
8
VOUT/BIAS
2
7
VCC
EN/UVLO
3
6
BOOT
VIN
4
5
SW
9
RT
1
PGOOD
8
FB
2
7
VCC
EN/UVLO
3
6
BOOT
VIN
4
5
SW
9
Pin Functions
PIN
ADVANCE INFORMATION
I/O
DESCRIPTION
RT
A
When the part is trimmed as the RT pin variant, the switching frequency in the part can be adjusted
from 200 kHz to 2.2 MHz based on the resistor value connected between RT and GND.
Do not float this pin.
2
PGOOD
A
Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. It goes low when EN = low. It can be open or
grounded when not used.
3
EN
A
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN. Do not float.
4
VIN
P
Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin
and GND.
5
SW
P
Regulator switch node. Connect to power inductor.
6
BOOT
P
Bootstrap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from
this pin to the SW pin.
7
VCC
P
Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads.
Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this
pin to GND.
8
VOUT/BIAS or FB
A
Fixed output options are available with the VOUT/BIAS pin variant. Connect to output voltage node
for fixed VOUT. Check the Device Comparison Table for more details.
The FB pin variant can help adjust the output voltage. Connect to tap point of feedback voltage
divider. Do not float the pin.
9
GND
G
Power ground terminal. Connect to system ground. Connect to CIN with short, wide traces.
NO.
NAME
1
A = Analog, P = Power, G = Ground
4
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range (1)
MAX
–0.3
70
V
EN to GND
–0.3
70.3
V
SW to GND
–0.3
70.3
V
RT to GND (RT variant)
–0.3
5.5
V
PGOOD to GND
UNIT
0
20
V
BIAS to GND (Fixed output variant)
–0.3
20
V
FB to GND - (Adjustable VOUT)
–0.3
20
V
BOOT to SW
–0.3
5.5
V
VCC to GND
–0.3
5.5
V
TJ
Junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD (Commercial) Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101 (2)
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40 °C to 150 °C (unless otherwise noted) (1) (2)
MIN
Input
voltage
Input Voltage Range after startup
Output
current
Load current range (3)
Selectable Frequency Range with RT (with RT variant only)
Frequency
Set Frequency Value with RT connected to GND (with RT variant only)
setting
Set Frequency Value with RT connected to VCC (with RT variant only)
(1)
(2)
(3)
TYP
MAX
UNIT
3.6
65
V
0
0.6
A
2.2
MHz
0.2
2.2
MHz
1
MHz
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics table.
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125℃
Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature. See
Application section for details.
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ADVANCE INFORMATION
PARAMETER
Voltages
MIN
VIN to GND
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7.4 Thermal Information
LMR36506
THERMAL METRIC (1)
VQFN (RPE)
UNIT
9 Pins
RθJA
Junction-to-ambient thermal resistance
84.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.5
°C/W
RθJB
Junction-to-board thermal resistance
26.1
°C/W
ΨJT
Junction-to-top characterization parameter
0.9
°C/W
ΨJB
Junction-to-board characterization parameter
25.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report. The value of RΘJA given in this table is only valid for comparison with other packages and can not be used for design purposes.
This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent the
performance obtained in an actual application. For design information see the Maximum Ambient Temperature section.
7.5 Electrical Characteristics
ADVANCE INFORMATION
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.4
3.5
3.6
UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN_R
Minimum operating Input Voltage
(Rising)
Rising Threshold
VIN_F
Minimum operating Input Voltage
(Falling)
Once Operating; Falling Threshold
2.87
3.0
IQ_13p5_Fixed
Non-switching input current;
measured at VIN pin (3)
VIN = VEN = 13.5V ; VOUT/BIAS = 5.25V,
VRT = 0V; Fixed Output Option
0.55
0.7
0.855
µA
IQ_13p5_Adj
Non-switching input current;
measured at VIN pin (3)
VIN = VEN = 13.5V ; VFB = 1.5V, VRT =
0V; Adjustable Output Option
13.5
17.5
21.5
µA
IQ_24p0_Fixed
Non-switching input current;
measured at VIN pin (3)
VIN = VEN = 24V ; VOUT/BIAS = 5.25V, VRT
= 0V; Fixed Output Option
1.05
1.2
1.4
µA
IQ_24p0_Adj
Non-switching input current;
measured at VIN pin (3)
VIN = VEN = 24V ; VFB = 1.5V, VRT = 0V;
Adjustable Output Option
14.9
18
21.5
µA
IB_13p5
Current into VOUT/BIAS pin (not
switching)(3)
VIN = 13.5V, VOUT/BIAS = 5.25V, VRT =
0V; Fixed Output Option
14.75
17
20.65
µA
IB_24p0
Current into VOUT/BIAS pin (not
switching)(3)
VIN = 24V, VOUT/BIAS = 5.25V, VRT = 0V;
Fixed Output Option
14.5
17.5
20.5
µA
ISD_13p5
Shutdown quiescent current;
measured at VIN pin
VEN = 0; VIN = 13.5V
0.4
0.5
0.685
µA
ISD_24p0
Shutdown quiescent current;
measured at VIN pin
VEN = 0; VIN = 24V
0.873
1
1.2
µA
V
V
ENABLE (EN PIN)
VEN-WAKE
Enable wake-up threshold
VEN-VOUT
Precision enable high level for
VOUT
0.4
VEN-HYST
Enable threshold hysteresis below
VEN-VOUT
ILKG-EN
Enable input leakage current
VEN = 3.3 V
VCC
Internal VCC voltage
VCC
Internal VCC voltage
ICC
Bias regulator current limit
VCC-UVLO
Internal VCC undervoltage lockout VCC rising under voltage threshold
V
1.16
1.263
1.36
V
0.3
0.35
0.38
V
0.1
0.2
2
nA
3.6 V ≤ VIN ≤ 65 V; Adjustable Output
Option
3.125
3.15
3.22
V
3.6 V ≤ VIN ≤ 65 V; VOUT/BIAS = 3.3 V
3.12
3.15
3.24
V
25
85
135
mA
3.1
3.2
3.5
V
INTERNAL LDO
6
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
Internal VCC under voltage lockout hysteresis
VCC-UVLO-HYST
TEST CONDITIONS
Hysteresis below VCC-UVLO
MIN
TYP
MAX
UNIT
0.54
0.7
1.1
V
CURRENT LIMITS
ISC-0p6
Short circuit high side current Limit 0.6A Version
0.87
1
1.11
A
ILS-LIMIT-0p6
Low side current limit
0.6A Version
0.64
0.7
0.752
A
IPEAK-MIN-0p6
Minimum Peak Inductor Current
PFM operation, 0.6A Version; Duty
Factor = 0
0.14
0.18
0.225
A
IZC
Zero Cross Current
PFM Operation
0
0.01
0.022
A
IL-NEG
Negative current limit
FPWM operation
–0.4
–0.5
–0.6
A
VPG-OV
PGOOD upper threshold - Rising
% of FB voltage
105
107
110
%
VPG-UV
PGOOD lower threshold - Falling
% of FB voltage
92
94
96.5
%
VPG-HYS
PGOOD hysteresis
% of FB voltage
1
1.5
2
%
VPG-VALID
Minimum input voltage for proper
PG function
0.75
1
2
V
RPG-EN5p0
RDS(ON) PG output
VEN = 5.0V, 1mA pull-up current
20
40
70
Ω
RPG-EN0
RDS(ON) PG output
VEN = 0 V, 1mA pull-up current
10
17
30
Ω
RDS-ON-HS
High-side MOSFET on-resistance
Load = 0.3 A
550
860
mΩ
RDS-ON-LS
Low-side MOSFET on-resistance
Load = 0.3 A
275
430
mΩ
VCBOOT-UVLO
Cboot - SW UVLO threshold
2.2
2.3
2.4
V
ADVANCE INFORMATION
POWER GOOD
MOSFETS
VOLTAGE REFERENCE
VFB_Fixed3p3
Initial VOUT voltage accuracy for
3.3 V
VIN = 3.6V to 60V FPWM Mode
3.25
3.3
3.34
V
VREF
Internal reference voltage
VIN = 3.6V to 60V FPWM Mode
0.985
1
1.015
V
FB input current
Adjsutable output voltage versions only,
FB = 1V
85
100
nA
IFB
7.6 Timing Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.2
2.67
3.21
ms
SOFT START
tSS
Time from first SW pulse to VFB at
90%, of VREF
VIN ≥ 3.6V
POWER GOOD
tRESET_FILTER
Glitch filter time constant for PG
function
15
25
40
µs
tPGOOD_ACT
Delay time to PG high signal
1.7
2
2.1
ms
7.7 Switching Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
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Switching Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
45
55
82
ns
45
50
77
ns
HS timeout in dropout
7.4
8.5
9.4
µs
2.2
2.3
MHz
PWM LIMITS (SW)
tON-MIN
Minimum switch on-time
tOFF-MIN
Minimum switch off-time
tON-MAX
Maximum switch on-time
VIN =24V IOUT = 0.3A
OSCILLATOR (RT)
fOSC_2p2MHz
Internal oscillator frequency
RT = GND
2.1
fOSC_1p0MHz
Internal oscillator frequency
RT = VCC
0.95
1
1.05
MHz
RT = 39.2kΩ (with RT variant only)
0.34
0.4
0.46
MHz
fADJ_400kHz
7.8 System Characteristics
ADVANCE INFORMATION
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the
case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN)
Input supply current when in
regulation
ISUPPLY
VIN = 24 V, VOUT/BIAS = 3.3 V, IOUT = 0
A, PFM mode
4
(2)
DMAX
Maximum switch duty cycle
µA
98%
VOLTAGE REFERENCE (FB or VOUT/BIAS)
VOUT_3p3V_ACC
VOUT = 3.3 V, VIN = 3.6 V to 65 V,
IOUT = 0 to full load (1)
FPWM Operation
–1.5
1.5
VOUT = 3.3 V, VIN = 3.6V to 65 V,
IOUT = 0 A to full load (1)
PFM operation
–1.5
2.5
%
THERMAL SHUTDOWN
TSD-R
Thermal shutdown rising
Shutdown threshold
158
168
180
°C
TSD-F
Thermal shutdown falling
Recovery threshold
150
158
165
°C
TSD-HYS
Thermal shutdown hysteresis
8
10
15
°C
8
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8 Detailed Description
8.1 Overview
The LMR36506 is a wide input, low-quiescent current, high-performance regulator that can operate over a wide
range of switching frequencies and duty ratios. If the minimum ON-time or OFF-time cannot support the desired
duty ratio, the switching frequency gets reduced automatically, maintaining the output voltage regulation. With the
right internal loop compensation the system design time with the LMR36506 reduces significantly with minimal
external components compared to other externally compensated buck regulators.
The LMR36506 is designed to minimize end-product component cost and solution size while operating in all
demanding industrial environments. The LMR36506 can be set to operate from 200 kHz through 2.2 MHz with
the correct resistor selection from RT pin to ground. In addition, the PGOOD output feature with built-in delayed
release allows the elimination of the reset supervisor in many applications.
To be reliably used in all environments, the LMR36506 has a package designed with enlarged corner terminals
for improved BLR performance over varied PCB thickness. In addition, the LMR36506 in a 2-mm x 2-mm QFN
package comes with wettable flanks as well, allowing for quick optical inspection of all solder joints.
ADVANCE INFORMATION
8.2 Functional Block Diagram
VCC
Clock
VCC
Oscillator
RT
VCC UVLO
Slope
compensation
LDO
Over
Temperature
detect
Frequency Foldback
System enable
Enable
EN
VIN
OTP
HS Current
sense
Error
amplifier
±
Comp Node
Output
low
System enable
FB
Clock
High and
low limiting
circuit
+
OTP
Soft start
circuit and
bandgap
VCC UVLO
GND
VIN
+
+
±
+
HS
±
Current
Limit
SW
Drivers and
logic
LS
Current
Limit
±
+
Voltage Reference
±
FPWM/Auto
PGOOD
PGOOD
Logic with
filter and
release delay
LS
Current
Min
GND
+
GND
Vout OV
LS Current
sense
System enable
8.3 Feature Description
8.3.1 Output Voltage Selection
For adjustable output voltage variants in the LMR36506, a resistor divider between the output voltage and the IC
FB pin can be used to set the output voltage value. The LMR36506 uses a 1-V internal reference voltage.
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Feature Description (continued)
RFBB =
RFBT
VOUT Å 1
(1)
When using the LMR36506 as fixed-output options, simply connect FB (or VOUT/BIAS here) to the output.
Check the Device Comparison Table for more details about the fixed-output variants.
VOUT
RFBT
FB
ADVANCE INFORMATION
RFBB
AGND
Figure 1. Setting Output Voltage for Adjustable Output Variant
For adjustable output options, an addition feedforward capacitor, CFF, in parallel with the RFBT can be needed to
optimize the transient response. No additional resistor divider or feedforward capacitor, CFF, is needed in case of
fixed-output variants.
8.3.2 Enable and Start-up
Voltage on the EN pin controls the ON or OFF functionality of the LMR36506. The part stays in shutdown mode
as long as the EN pin voltage is less than VEN-WAKE = 0.4 V. During the shutdown mode, the input current drawn
by the device typically drops down to 1 µA. Applying a voltage at the EN pin greater than the VEN-WAKE causes
the device to enter the standby mode, powering up the internal LDO to generate VCC. As the EN voltage further
approaches VEN-VOUT, the device finally starts switching, allowing it to enter the start-up mode and begin the softstart period. During the shutdown process, when the EN input is brought below VEN-VOUT by VEN-HYST, the
regulator stops switching and re-enters the standby mode. Any further decrease in the EN pin voltage below VENWAKE finally shuts down the device. The EN input pin can be connected directly to VIN input pin if remote
precision control is not needed. The EN input pin must not be allowed to float. The limits of various EN
thresholds values listed here can be found in the Electrical Characteristics table.
VIN
RENT
EN
RENB
AGND
Figure 2. VIN UVLO Using the EN pin
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Feature Description (continued)
8.3.3 Adjustable Switching Frequency (with RT)
A resistor tied to the LMR36506 RT pin and GND is used to set the desired operating frequency between 200
kHz and 2.2 MHz. See Figure 3 to determine the resistor value needed for the desired switching frequency.
1. Connecting the RT pin directly to GND sets the LMR36506 default FSW to 2.2 MHz.
2. Connecting the RT pin directly to VCC sets the LMR36506 default FSW to 1 MHz.
70
60
Rt (kOhm)
50
40
30
20
10
0
200
400
600
800 1000 1200 1400 1600 1800 2000 2200
Frequency (kHz)
RTvs
8.3.4 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR36506 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. Output voltage excursions
lasting less than tRESET_FILTER do not trip the power-good flag. Power-good operation can best be understood in
reference to Figure 4. During initial power up, a total delay of 5 ms (typical) is encountered from the time the VENVOUT is triggered to the time that the power-good flag goes high. This delay only occurs during start-up and is not
encountered during normal operation of the power-good function.
The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup
resistor connected to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an
appropriate resistor, as desired. If this function is not needed, the PGOOD pin must be grounded. When the EN
pin is pulled low, the power-good flag output is also forced low. With EN low, power-good remains valid as long
as the input voltage is ≥ 2 V (maximum). Limit the current into this pin to ≤ 4 mA.
Input
Voltage
Output
Voltage
tRESET_FILTER
tPGOOD_ACT
VPG-HYS
Input Voltage
tPGOOD_ACT
tRESET_FILTER
tRESET_FILTER
tRESET_FILTER
VPG-UV (falling)
VIN_R (rising)
VIN_F (falling)
VPG_VALID
GND
VOUT
PGOOD
PGOOD may
not be valid if
input is below
VPG-VALID
Startup
delay
Small glitches do not
reset tPGOOD_ACT timer
Small glitches
do not cause
reset to signal
a fault
PGOOD may not
be valid if input is
below VPG-VALID
Figure 4. Power-Good Operation
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Figure 3. Setting Clock Frequency
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Feature Description (continued)
8.3.5 Internal LDO, VCC UVLO, and VOUT/BIAS Input
The LMR36506 uses the VCC pin for all the internal power supply. The VCC pin draws power either from the
VIN (for adjustable output variants) or the VOUT/BIAS (for fixed output variants). In fixed output variants, once
the LMR36506 is active, the VCC continues to draw power from the input voltage, VIN, when the VOUT/BIAS
voltage measures less than 3.15 V (during start-up and other transient conditions) or from the VOUT/BIAS itself
when VOUT/BIAS measures is more than 3.15 V (once the device has reached steady state). VCC typically
measures 3.3 V under most conditions. To prevent unsafe operation, VCC has an undervoltage lockout, which
prevents switching if the internal voltage is too low. See VVCC_UVLO and VVCC_UVLO_HYST in the Electrical
Characteristics table. During start-up, VCC momentarily exceeds the normal operating voltage until
VCC_UVLO_HYST is exceeded, then drops to the normal operating voltage. Note that these undervoltage
lockout values, when combined with the LDO dropout and while powering the LMR36506, are used to derive the
minimum rising operating voltage and the subsequent falling threshold.
8.3.6 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Terminal)
8.3.7 Soft Start and Recovery from Dropout
When designing with the LMR36506, slow rise in output voltage due to recovery from dropout and soft start must
be considered a separate phenomena. Soft start is triggered by any of the following conditions:
• EN is used to turn on the device.
• Recovery from shutdown due to overtemperature protection.
• Power is applied to the VIN of the IC or VCC pin, releasing undervoltage lockout.
Once soft start is triggered, the IC takes the following actions:
• The reference used by the IC to regulate output voltage is slowly ramped up. The net result is that output
voltage, if previously 0 V, takes tSS to reach 90% of the desired value.
• Operating mode is set to auto mode of operation, activating the diode emulation mode for the low-side
MOSFET. This allows start-up without pulling the output low. This is true even when there is a voltage already
present at the output during a pre-bias start-up.
tEN
V
tSS
If selected, FPWM
is enabled only
after completion of
tSS
VEN
VOUT Set
Point
VOUT
90% of
VOUT Set
Point
0V
Time
t
Triggering event
tEN
EN and Output Voltages
Triggering event
EN and Output Voltages
ADVANCE INFORMATION
The driver of the power switch (HS switch) requires bias higher than VIN when the HS switch is turned ON. The
capacitor connected between CBOOT and SW works as a charge pump to boost voltage on the CBOOT terminal
to (SW+VCC). The boot diode is integrated on the LMR36506 die to minimize physical solution size. A 100 nF
capacitor rated for 6.3-V or higher is recommended for CBOOT. The CBOOT rail has a UVLO to protect the chip
from operation with too little bias. This UVLO has a threshold of VCBOOT_UVLO and is typically set at 2.1 V. If the
CBOOT capacitor is not charged above this voltage with respect to SW, then the part initiates a charging
sequence using the low-side FET before attempting to turn on the high-side device.
V
tSS
VOUT Set
Point
If selected, FPWM
is enabled only
after completion of
tSS
VEN
VOUT
90% of
VOUT Set
Point
0V
Time
t
Figure 5. Soft Start with and without Prebias Voltage
8.3.7.1 Recovery from Dropout
Any time output voltage is more than a few percent low for any reason, output voltage slowly ramps up. This
condition, called graceful recovery from dropout in this document, differs from soft start in two important ways:
• FPWM mode is allowed during recovery from dropout. If output voltage were to suddenly be pulled up by an
external supply, the LMR36506 can pull down on the output. Note that all protections that are present during
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Feature Description (continued)
•
normal operation are in place, preventing destruction if output is shorted to a high voltage or ground.
The reference voltage is set to approximately 1% above that needed to achieve the current output voltage. It
is not started from zero.
Output Voltage
and Current
V
Load
current
VOUT Set
Point
and max
output
current
VOUT
Slope
the same
as during
soft start
t
Time
Whether output voltage falls due to high load or low input voltage, once the condition that causes output to fall
below its set point is removed, output climbs at the same speed as during start-up.
8.3.8 Current Limit and Short Circuit
The LMR36506 is protected from overcurrent conditions by cycle-by-cycle current limiting on both high-side and
low-side MOSFETs.
High-side MOSFET overcurrent protection is implemented by the typical peak-current mode control scheme. The
HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is
compared to either the minimum of a fixed current set point or the output of the internal error amplifier loop minus
the slope compensation every switching cycle. Since the output of the internal error amplifier loop has a
maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased
duty factor if duty factor is typically above 35%.
When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side
device, the low-side device has a turnoff commanded by the internal error amplifier loop. In the case of the lowside device, turnoff is prevented if the current exceeds this value, even if the oscillator normally starts a new
switching cycle. Also like the high-side device, there is a limit on how high the turnoff current is allowed to be.
This is called the low-side current limit, ILS-LIMIT (or IL-LS in Figure 7). If the LS current limit is exceeded, the LS
MOSFET stays on and the HS switch is not be turned on. The LS switch is turned off once the LS current falls
below this limit and the HS switch is turned on again as long as at least one clock period has passed since the
last time the HS device has turned on.
SW Voltage
VSW
VIN
tON < tON_MAX
0
t
Inductor Current
Typically, tSW > Clock setting
iL
IL-HS
IOUT
IL-LS
0
t
Figure 7. Current Limit Waveforms
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Figure 6. Recovery from Dropout
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Feature Description (continued)
The net effect of the operation of high-side and low-side current limit is that the IC operates in hysteretic control.
Also, since the current waveform assumes values between ISC (or IL-HS in Figure 7) and ILS-LIMIT, output current is
very close to the average of these two values unless duty factor is very high. Once operating in current limit,
hysteretic control is used and current does not increase as output voltage approaches zero.
If duty factor is very high, current ripple must be very low in order to prevent instability. Since current ripple is
low, the part is able to deliver full current. The current delivered is very close to ILS-LIMIT.
VOUT
IL-LS
Output Voltage
IOUT rated
IL-HS
VOUT Setting
VIN > 2 Â 9OUT Setting
VIN ~ VOUT Setting
IOUT
0
0
Output Current
ADVANCE INFORMATION
Figure 8. Output Voltage versus Output Current
Under most conditions, current is limited to the average of IL-HS and IL-LS, which is approximately 1.4 times the
maximum-rated current. If input voltage is low, current can be limited to approximately IL-LS. Also note that
current does not exceed the average of IL-HS and IL-LS. Once the overload is removed, the part recovers as though
in soft start.
8.3.9 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the internal switches when the IC junction
temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal
shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to
approximately 158°C (typical). When the junction temperature falls below 158°C (typical), the LMR36506
attempts another soft start.
While the LMR36506 is shut down due to high junction temperature, power continues to be provided to VCC. To
prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced
current limit while the part is disabled due to high junction temperature. The LDO only provides a few
milliamperes during thermal shutdown.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides ON/OFF control of the device. When the EN pin voltage is below the VEN-WAKE threshold,
both the regulator and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown
mode, the input current drops down to 1 µA (typical).
8.4.2 Standby Mode
The internal LDO has a lower EN threshold than the output of the regulator. When the EN pin voltage is above
the VEN-WAKE threshold but below the precision enable rising threshold for the output voltage, the internal LDO
clamps the VCC voltage at 5.5 V typically. The precision enable circuitry is ON once VCC is above its VCCUVLO. The internal power MOSFET of the SW node remains off unless the voltage on the EN terminal goes
above its precision enable threshold. The LMR36506 also employs undervoltage lockout protection. If the VCC
voltage is below its UVLO level, the output of the regulator is turned off.
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Device Functional Modes (continued)
8.4.3 Active Mode
The LMR36506 is in active mode whenever the EN pin and UVLO high threshold levels are satisfied. The
simplest way to enable the operation of any of these devices is to connect the EN pin to VIN, which allows self
start-up when the applied input voltage exceeds internal UVLO levels. Refer to the External UVLO section and
precision enable feature section for details on setting these operating levels.
8.4.4 Continuous Conduction Mode (CCM)
Continuous Conduction Mode (CCM) operation is employed when the load current is higher than a half of the
peak-to-peak inductor current. If the load current is decreased, the part enters DCM mode. In CCM operation, the
frequency of operation is constant and fixed unless the minimum tON_MIN or tOFF_MIN are exceeded, which causes
the part to enter foldback mode. In both these cases, CCM operation is still maintained, but the frequency of
operation is folded back (reduced) to maintain proper regulation.
8.4.5 Discontinuous Conduction Mode (DCM)
Discontinuous Conduction Mode (DCM) operation is employed when the load current is lower than half of the
peak-to-peak inductor current. In DCM operation, also known as Diode Emulation Mode, the LS FET is turned off
when the inductor current drops below 0 A to keep operation as efficient as possible by reducing switching
losses and preventing negative current conduction.
8.4.6 Pulse Frequency Modulation (PFM)
At light output current loads, Pulse Frequency Modulation (PFM) mode is activated for the highest possible
efficiency. When the inductor current does not reach IPEAK-MIN during a switching cycle, the on-time is increased
and the switching frequency reduces as needed to maintain proper regulation. The on-time has a maximum
value of approximately 8 µs to avoid large output voltage ripple in dropout conditions. Efficiency is greatly
improved by reducing switching and gate drive losses. During this mode of operation, the LMR36506 can convert
with a minimum quiescent current of 6.5 µA (typical) when unloaded.
8.4.7 Forced Pulse Width Modulation Mode (FPWM)
The part operates in Forced Pulse Width Modulation (FPWM) mode when the RT pin variants are factory pre-set
with the inductor zero cross disabled. In this mode, diode emulation is turned off and the part remains in CCM
over the full-load range. In FPWM operation, the frequency of operation is constant and fixed unless the
minimum tON_MIN or tOFF_MIN are exceeded, which causes the part to enter DCM. In these cases, the FPWM
operation is still maintained, but the switching frequency is folded back (reduced) in order to maintain proper
output voltage regulation.
8.4.8 Dropout Mode
Foldback protection modes are entered when the duty cycle exceeds the minimum on and off times of the part.
At very high duty cycles, where the minimum off-time is not satisfied, the frequency folds back to allow more time
for the peak current command to be reached. The maximum on-time is 8 µs (typical), which limits the maximum
duty cycle in dropout to 98% (typical).
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In active mode, depending on the load current, the LMR36506 is in one of six sub-modes:
• Continuous conduction mode (CCM) with fixed switching frequency
• Discontinuous conduction mode (DCM) when the load current is lower than half of the inductor current ripple
• Light Load Mode where the parts uses Pulse Frequency Modulation (PFM) and lowers the switching
frequency at load under half of IPEAK-MIN to improve efficiency
• Forced Pulse Width Modulation (FPWM) is similar to CCM with fixed switching frequency, but extends the
fixed frequency range of operation from full to no load.
• Dropout mode when switching frequency is reduced to minimize drop out
• Recovery from dropout is similar to other modes of operation except the output voltage set point is gradually
moved up until the programmed set point is reached.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMR36506 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 0.6 A. The following design procedure can be used to select
components for the LMR36506.
ADVANCE INFORMATION
NOTE
All of the capacitance values given in the following application information refer to effective
values unless otherwise stated. The effective value is defined as the actual capacitance
under DC bias and temperature, not the rated or nameplate values. Use high-quality, lowESR, ceramic capacitors with an X7R or better dielectric throughout. All high value
ceramic capacitors have a large voltage coefficient in addition to normal tolerances and
temperature effects. Under DC bias the capacitance drops considerably. Large case sizes
and higher voltage ratings are better in this regard. To help mitigate these effects, multiple
capacitors can be used in parallel to bring the minimum effective capacitance up to the
required value. This can also ease the RMS current requirements on a single capacitor. A
careful study of bias and temperature variation of any capacitor bank must be made to
ensure that the minimum value of effective capacitance is provided.
9.2 Typical Application
Figure 9 shows a typical application circuit for the LMR36506. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick-start guide, Table 1 provides typical
component values for a range of the most common output voltages.
L
VIN
CIN
2.2 µF
VOUT
SW
VIN
CHF
100 nF
CBOOT
COUT
BOOT
EN
0.1 µF
LMR36506
CFF
MODE
PG
VCC
FB
CVCC
1 µF
GND
RFBT
100 NŸ
RFBB
Figure 9. Example Application Circuit
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Typical Application (continued)
Table 1. Typical External Component Values (1)
ƒSW
(kHz)
VOUT
(V)
L (µH)
NOMINAL COUT
(RATED
CAPACITANCE)
400
3.3
33
1 x 47 µF + 1 x
22 µF
1 x 47 µF
1000
3.3
15
2 x 22 µF
400
5
47
1 x 47 µF + 1 x
22 µF
1000
5
22
2 x 22 µF
(1)
MINIMUM COUT
(RATED
RFBT (Ω)
CAPACITANCE)
RFBB (Ω)
CIN
CBOOT
CVCC
100 k
43.2 k
2.2 µF + 1 × 100 nF
100 nF
1 µF
1 x 22 µF
100 k
43.2 k
2.2 µF + 1 × 100 nF
100 nF
1 µF
1 x 47 µF
100 k
24.9 k
2.2 µF + 1 × 100 nF
100 nF
1 µF
1 x 22 µF
100 k
24.9 k
2.2 µF + 1 × 100 nF
100 nF
1 µF
Inductor values are calculated based on typical VIN = 24 V.
9.2.1 Design Requirements
Detailed Design Procedure provides a detailed design procedure based on Table 2.
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
24 V (6 V to 60 V)
Output voltage
5V
Maximum output current
0 A to 0.6 A
Switching frequency
1000 kHz
9.2.2 Detailed Design Procedure
The following design procedure applies to Figure 9 and Table 1.
9.2.2.1 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more
compact design. For this example, 1000 kHz is used.
9.2.2.2 Setting the Output Voltage
For the fixed output voltage versions, pin 8 (VOUT/BIAS) of the device must be connected directly to the output
voltage node. This output sensing point is normally located near the top of the output capacitor. If the sensing
point is located further away from the output capacitors (that is, remote sensing), then a small 100-nF capacitor
can be needed at the sensing point.
9.2.2.2.1 FB for Adjustable Output
In an adjustable output voltage version, pin 8 of the device is FB. The output voltage of LMR36506 is externally
adjustable using an external resistor divider network. The range of recommended output voltage is found in the .
The divider network is comprised of RFBT and RFBB, and closes the loop between the output voltage and the
converter. The converter regulates the output voltage by holding the voltage on the FB pin equal to the internal
reference voltage, VREF. The resistance of the divider is a compromise between excessive noise pickup and
excessive loading of the output. Smaller values of resistance reduce noise sensitivity but also reduce the lightload efficiency. The recommended value for RFBT is 100 kΩ with a maximum value of 1 MΩ. Once RFBT is
selected, Equation 2 is used to select RFBB. VREF is nominally 1 V.
RFBT
RFBB
ª VOUT
º
1»
«
¬ VREF
¼
(2)
For this 5-V example, RFBT = 100 kΩ and RFBB = 24.9 kΩ.
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Table 2. Detailed Design Parameters
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9.2.2.3 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum
output current. Experience shows that the best value for inductor ripple current is 30% of the maximum load
current. Note that when selecting the ripple current for applications with much smaller maximum load than the
maximum available from the device, use the maximum device current. Equation 3 can be used to determine the
value of inductance. The constant K is the percentage of inductor current ripple. For this example, choose K =
0.3 and find an inductance of L = 22 µH. Select the next standard value of L = 22 µH.
VIN VOUT
V
˜ OUT
fSW ˜ K ˜ IOUT max VIN
L
(3)
ADVANCE INFORMATION
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, ISC.
This ensures that the inductor does not saturate, even during a short circuit on the output. When the inductor
core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly.
Although the valley current limit, ILIMIT, is designed to reduce the risk of current runaway, a saturated inductor can
cause the current to rise to high values very rapidly. This can lead to component damage. Do not allow the
inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually
have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some
relaxation in the current rating of the inductor. However, they have more core losses at frequencies above about
1 MHz. In any case, the inductor saturation current must not be less than the maximum peak inductor current at
full load.
To avoid subharmonic oscillation, the inductance value must not be less than that given in :
LMIN t 0.28 ˜
VOUT
fSW
(4)
The maximum inductance is limited by the minimum current ripple for the current mode control to perform
correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device
maximum rated current under nominal conditions.
9.2.2.4 Output Capacitor Selection
The value of the output capacitor and its ESR determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements and stability rather
than the output voltage ripple. Equation 5 can be used to estimate a lower bound on the total output capacitance
and an upper bound on the ESR, which is required to meet a specified load transient. Use as a starting point to
determine the required output capacitor for each design.
º
ª
'IOUT
K2
COUT t
˜«1 D ˜ 1 K
˜ 2 D»
12
fSW ˜ 'VOUT ˜ K «¬
»¼
ESR d
D
2 K ˜ 'VOUT
ª
2 ˜ 'IOUT «1 K
«¬
K2
12
§
1 ·º
¸¸»
˜ ¨¨1
© (1 D) ¹»¼
VOUT
VIN
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = ripple factor from Inductor Selection
(5)
Once the output capacitor and ESR have been calculated, use Equation 6 to check the output voltage ripple.
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Vr # 'IL ˜ ESR 2
1
8 ˜ fSW ˜ COUT
2
where
•
Vr = peak-to-peak output voltage ripple
(6)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1
nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
9.2.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum ceramic capacitance of 2.2-µF is required on
the input of the LMR36506. This must be rated for at least the maximum input voltage that the application
requires, preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple and maintain the input voltage during load transients. In addition, a small case size 100-nF ceramic
capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency bypass
for the control circuits internal to the device. For this example a 2.2-µF, 100-V, X7R (or better) ceramic capacitor
is chosen. The 100 nF must also be rated at 100-V with an X7R dielectric.
It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially
true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate
RMS value of this current can be calculated from Equation 7 and must be checked against the manufacturers'
maximum ratings.
I
IRMS # OUT
2
(7)
9.2.2.6 CBOOT
The LMR36506 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor
stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of
100 nF and at least 16 V is required.
9.2.2.7 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this output
must not be loaded with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see the Power-Good Flag Output section). A value in the range of 10 kΩ to 100 kΩ is a
good choice in this case. The nominal output voltage on VCC is 5 V.
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Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever
is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well
as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load
and loop stability must be performed.
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9.2.2.8 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help mitigate this effect. Use Equation 8 to estimate the value of CFF. The value
found with Equation 8 is a starting point; use lower values to determine if any advantage is gained by the use of
a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters with
Feedforward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.
VOUT ˜ COUT
CFF
VREF
120 ˜ RFBT ˜
VOUT
(8)
9.2.2.8.1 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in Figure 10. The input voltage at which the device turns on is
designated as VON while the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100
kΩ, then Equation 9 is used to calculate RENT and VOFF.
ADVANCE INFORMATION
VIN
RENT
EN
RENB
Figure 10. Setup for External UVLO Application
RENT
§ VON
¨¨
© VEN H
VOFF
§
VEN HYS
VON ˜ ¨¨1
VEN
©
·
1¸¸ ˜ RENB
¹
·
¸¸
¹
where
•
•
VON = VIN turnon voltage
VOFF = VIN turnoff voltage
(9)
9.2.2.9 Maximum Ambient Temperature
As with any power conversion device, the LMR36506 dissipates internal power while operating. The effect of this
power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,
RθJA, of the device and PCB combination. The maximum junction temperature for the LMR36506 must be limited
to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load current.
Equation 10 shows the relationships between the important parameters. It is easy to see that larger ambient
temperatures (TA) and larger values of RθJA reduce the maximum available output current. The converter
efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions
cannot be found in one of the curves, interpolation can be used to estimate the efficiency. Alternatively, the EVM
can be adjusted to match the desired application requirements and the efficiency can be measured directly. The
correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal
Metrics Application Report, the values given in the Thermal Information section are not valid for design purposes
and must not be used to estimate the thermal performance of the application. The values reported in that table
were measured under a specific set of conditions that are rarely obtained in an actual application.
20
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IOUT
SNVSBB6 – DECEMBER 2019
MAX
TJ TA
1
K
˜
˜
R TJA
1 K VOUT
where
•
η = efficiency
(10)
The effective RθJA is a critical parameter and depends on many factors such as the following:
• Power dissipation
• Air temperature/flow
• PCB area
• Copper heat-sink area
• Number of thermal vias under the package
• Adjacent component placement
Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given application
environment:
• Thermal Design by Insight not Hindsight Application Report
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
• Semiconductor and IC Package Thermal Metrics Application Report
• Thermal Design Made Simple with LM43603 and LM43602 Application Report
• PowerPAD™ Thermally Enhanced Package Application Report
• PowerPAD™ Made Easy Application Report
• Using New Thermal Metrics Application Report
9.3 What to Do and What Not to Do
•
•
Do not allow the EN input to float.
Do not allow the output voltage to exceed the input voltage, nor go below ground.
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Due to the ultra-miniature size of the VQFN-HR (RPE) package, a DAP is not available. This means that this
package exhibits a somewhat greater RθJA.
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10 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Specifications found in this data sheet. In
addition, the input supply must be capable of delivering the required input current to the loaded regulator. The
average input current can be estimated with Equation 11.
VOUT ˜ IOUT
IIN
VIN ˜ K
where
•
η is the efficiency
(11)
ADVANCE INFORMATION
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the
regulator to momentarily shut down and reset. The best way to solve these kind of issues is to limit the distance
from the input supply to the regulator or plan to use an aluminum or tantalum input capacitor in parallel with the
ceramics. The moderate ESR of these types of capacitors help dampen the input resonant circuit and reduce any
overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DC/DC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
22
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11 Layout
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad
PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck
converter, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power
ground, as shown in Figure 11. This loop carries large transient currents that can cause large transient voltages
when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the
converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible
to reduce the parasitic inductance. Figure 12 shows a recommended layout for the critical components of the
LMR36506.
1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are
adjacent, simplifying the input capacitor placement.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and
routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the BOOT
and SW pins. Route the SW pin to the N/C pin and used to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, the latter trace must not be routed
near any noise source (such as the SW node) that can capacitively couple into the feedback path of the
regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat
dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat-sinking. As stated in the Maximum Ambient Temperature section,
enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and
ambient temperature. The top and bottom PCB layers must be made with two ounce copper and no less than
one ounce. If the PCB design uses multiple copper layers (recommended), these thermal vias can also be
connected to the inner layer heat-spreading ground planes.
8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies Application Report
• Simple Switcher PCB Layout Guidelines Application Report
• Construction Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
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ADVANCE INFORMATION
11.1 Layout Guidelines
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Layout Guidelines (continued)
VIN
CIN
SW
GND
ADVANCE INFORMATION
Figure 11. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control circuitry.
Connect the AGND and PGND pins to the ground planes using vias next to the bypass capacitors. PGND pins
are connected directly to the source of the low-side MOSFET switch and also connected directly to the grounds
of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due
to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one side of the
ground planes. The other side of the ground plane contains much less noise; use for sensitive routes.
TI recommends providing adequate device heat-sinking by using the thermal pad (PAD) of the device as the
primary thermal path. Use a minimum 4 × 3 array of 10-mil thermal vias to connect the PAD to the system
ground plane heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible, for
system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the
copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with
enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding and
lower thermal resistance.
24
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11.2 Layout Example
RFBB
CFF
RFBT
RENB
CVCC
CBOOT
RENT
CIN
L1
ADVANCE INFORMATION
CIN
COUT
GND
Figure 12. Example Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
ADVANCE INFORMATION
For related documentation see the following:
• Texas Instruments, Thermal Design by Insight not Hindsight Application Report
• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package Application Report
• Texas Instruments, PowerPAD™ Made Easy Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
• Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report
• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
HotRod, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
PLMR36506RRPET
PREVIEW
Package Type Package Pins Package
Drawing
Qty
VQFN-HR
RPE
9
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 150
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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