Texas Instruments | TLV62585 3-A High Efficiency Synchronous Buck Converter in QFN or SOT563 Package (Rev. F) | Datasheet | Texas Instruments TLV62585 3-A High Efficiency Synchronous Buck Converter in QFN or SOT563 Package (Rev. F) Datasheet

Texas Instruments TLV62585 3-A High Efficiency Synchronous Buck Converter in QFN or SOT563 Package (Rev. F) Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
TLV62585 3-A High Efficiency Synchronous Buck Converter in
QFN or SOT563 Package
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
The TLV62585 device is a high-frequency
synchronous step-down converter optimized for
compact solution size and high efficiency. The device
integrates switches capable of delivering an output
current up to 3 A. At medium to heavy loads, the
converter operates in pulse width modulation (PWM)
mode with typical 1.5-MHz switching frequency. At
light load, the device automatically enters Power
Save Mode (PSM) to maintain high efficiency over
the entire load current range. In shutdown, the
current consumption is reduced to less than 2 μA.
1
•
Up to 95% efficiency
Low RDS(ON) power switches 56 mΩ / 32 mΩ
2.5-V to 5.5-V input voltage range
Adjustable output voltage from 0.6-V to VIN
Power save mode for light load efficiency
100% duty cycle for lowest dropout
35-μA operating quiescent current
1.5-MHz typical switching frequency
Short circuit protection (HICCUP)
Output discharge
Power good output
Thermal shutdown protection
Available in 2-mm × 2-mm QFN or 1.6-mm x 1.6mm SOT563 package
Create a custom design using the TLV62585 with
the WEBENCH® Power Designer
The internal compensation circuit allows a compact
solution and small external components. An internal
soft start circuit limits the inrush current during
startup. Other features like short circuit protection,
thermal shutdown protection, output discharge and
power good are built-in.
The device is available in a 2-mm × 2-mm QFN or
1.6-mm x 1-6-mm SOT563 package.
Device Information(1)
2 Applications
•
•
•
•
•
PART NUMBER
General purpose point-of-load supply
Battery-powered application
Wireless router, solid state drive
Set-top box, multi functional printer
Motor control
TLV62585RWT
TLV62585DRL
TLV62585PDRL
PACKAGE
BODY SIZE (NOM)
QFN (12)
2.00 mm × 2.00 mm
SOT563 (6)
1.60 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Spacer
Spacer
Spacer
Typical Application Schematic
5-V Input Voltage Efficiency
VPG
TLV62585
PG
VIN
2.5 V to 5.5 V
C1
10 µF
95
SW
C2
10 µF
EN
PGND
AGND
C3: Optional
VOUT
1.8 V / 3.0 A
C3*
R1
200 k
FB
R2
100 k
Efficiency (%)
VIN
100
R3
1M
L1
1.0 µH
90
85
80
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
75
70
0
0.5
1
1.5
Load (A)
2
2.5
3
D008
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
7
7
7
8
8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Considerations ........................................ 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2018) to Revision F
•
Page
Changed Temperature Range for 1% Accuracy from 25°C to 0°C-85°C............................................................................... 6
Changes from Revision D (April 2018) to Revision E
Page
•
Changed TLV62585DRL and TLV62585PDRL From: Product Preview To: Production data................................................ 1
•
Added PCB layout recommendation for TLV62585PDRL.................................................................................................... 15
Changes from Revision C (November 2017) to Revision D
Page
•
Added TLV62585DRL and TLV62585PDRL to the Device Information table ........................................................................ 1
•
Added DRL and PDRL devices to the Pin Configurations and Functions.............................................................................. 4
•
Added the DRL Thermal Information ..................................................................................................................................... 5
•
Added Figure 22 .................................................................................................................................................................. 14
Changes from Revision B (September 2017) to Revision C
•
Page
Changed HBM From: ±1000 To: ±2000 in the ESD Ratings table......................................................................................... 5
Changes from Revision A (August 2017) to Revision B
Page
•
Changed the device status From: Advanced Information To: Production Data .................................................................... 1
•
Changed HBM From: TBD To: ±1000 in the ESD Ratings table ........................................................................................... 5
2
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
TLV62585
www.ti.com
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
Changes from Original (July 2017) to Revision A
Page
•
Changed the device status From: Production To: Advanced Information ............................................................................. 1
•
Changed HBM From: ±2000 To: TBD in the ESD Ratings table ........................................................................................... 5
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
3
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
5 Pin Configuration and Functions
DRL Package
6-Pin (SOT563)
Top View
PDRL Package
6-Pin (SOT563)
Top View
GND
1
6
NC
SW
2
5
FB
VIN
3
4
EN
GND
1
6
PG
SW
2
5
FB
VIN
3
4
EN
Not to scale
Not to scale
VIN
RWT Package
12-Pin (QFN)
Top View
VIN
1
SW
2
10
SW
9
PG
8
EN
7
FB
6
NC
11
PGND
3
PGND
12
4
5
NC
AGND
Not to scale
Pin Functions
PIN
NAME
RWT
(QFN)
DRL
(SOT563)
PDRL
(SOT563)
I/O
VIN
1, 10
3
3
PWR
Power supply voltage pin.
SW
2, 11
2
2
PWR
Switch pin connected to the internal FET switches and inductor terminal. Connect the
inductor of the output filter to this pin.
GND
DESCRIPTION
-
1
1
PWR
Ground pin.
PGND
3, 12
-
-
PWR
Power ground pin.
AGND
4
-
-
-
Ground pin.
NC
5, 6
6
-
-
No connection pin. Leave these pins open, or connect those pins to the output or to
AGND.
FB
7
5
5
I
Feedback pin for the internal control loop. Connect this pin to an external feedback
divider.
EN
8
4
4
I
Device enable logic input. Logic high enables the device, logic low disables the device
and turns it into shutdown. Do not leave floating.
PG
9
-
6
O
Power good open drain output pin. The pull-up resistor can not be connected to any
voltage higher than 5.5 V. If unused, leave it floating or connect to AGND.
4
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
TLV62585
www.ti.com
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
Voltage at Pins (1)
Temperature
(1)
(2)
MIN
MAX
VIN, EN, PG
–0.3
6
UNIT
FB
–0.3
3
SW (DC)
–0.3
VIN + 0.3
SW (AC, less than 10ns) (2)
–3.0
9
Operating Junction, TJ
–40
150
°C
Storage, Tstg
–65
150
°C
V
All voltage values are with respect to network ground terminal.
While switching
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
V
VIN
Input voltage range
2.5
5.5
VOUT
Output voltage range
0.6
VIN
V
ISINK_PG
Sink current at PG pin
1
mA
IOUT
Output current
0
3
A
TJ
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TLV62585
THERMAL METRIC (1)
RWT [QFN]
DRL [SOT]
UNIT
RθJA
Junction-to-ambient thermal resistance
95.7
132.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
74.1
43.8
°C/W
RθJB
Junction-to-board thermal resistance
29.4
27.3
°C/W
ψJT
Junction-to-top characterization parameter
5.8
1.2
°C/W
ψJB
Junction-to-board characterization parameter
29.7
26.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
5
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
6.5
www.ti.com
Electrical Characteristics
TJ = 25 °C, and VIN = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Quiescent current into VIN
No load, device not switching
35
ISD
Shutdown current into VIN
EN = Low
0.7
2
µA
Under voltage lock out threshold
VIN falling
2.3
2.45
V
VUVLO
Under voltage lock out hysteresis
Thermal shutdown threshold
TJSD
TJ rising
Thermal shutdown hysteresis
µA
150
mV
150
°C
20
°C
LOGIC INTERFACE EN
VIH
High-level input voltage
VIN = 2.5 V to 5.5 V
VIL
Low-level input voltage
VIN = 2.5 V to 5.5 V
1.2
V
0.4
V
SOFT START, POWER GOOD
tSS
Soft start time
Time from EN high to 95% of VOUT nominal
900
VOUT rising, referenced to VOUT nominal
95%
VOUT falling, referenced to VOUT nominal
90%
VPG
Power good threshold
VPG,OL
Low-level output voltage
Isink = 1 mA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V
tPG,DLY
Power good delay
VFB falling
µs
0.4
V
0.01
µA
40
µs
OUTPUT
PWM mode, 2.5 V ≤ VIN ≤ 5.5 V, 0°C to 85°C
594
600
606
PWM mode, 2.5 V ≤ VIN ≤ 5.5 V, -40°C to 125°C
588
600
612
VFB
Feedback regulation voltage
IFB,LKG
Feedback input leakage current
VFB = 0.6 V
RDIS
Output discharge FET on-resistance
EN = Low, VOUT = 1.8 V
mV
0.01
µA
10
Ω
56
mΩ
32
mΩ
POWER SWITCH
High-side FET on-resistance
RDS(on)
Low-side FET on-resistance
ILIM
High-side FET switch current limit
fSW
PWM switching frequency
4
VOUT = 1.8V, IOUT = 1 A
4.6
A
1.5
MHz
6.6 Typical Characteristics
1.0
50
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 5.0V
45
0.8
$
35
30
25
20
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
15
10
5
0
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
0.6
0.4
0.2
5.5
0.0
-40
D001
Figure 1. Quiescent Current vs Input Voltage
6
6KXWGRZQ &XUUHQW
4XLHVFHQW &XUUHQW
$
40
-10
20
50
80
Junction Temperature (°C)
110
140
D002
Figure 2. Shutdown Current vs Junction Temperature
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
TLV62585
www.ti.com
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
7 Detailed Description
7.1 Overview
The TLV62585 is a high-efficiency synchronous step-down converter. The device operates with an adaptive offtime with peak current control scheme. The device operates at typically 1.5-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the
required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the
variation of input voltage, output voltage, and load current.
7.2 Functional Block Diagram
PG
Soft Start
EN
Thermal
Shutdown
UVLO
Hiccup
Counter
Control Logic
VPG
+
VFB
±
VIN
GND
Peak Current Detect
VREF
+
_
FB
Modulator
Gate
Drive
SW
Output
Discharge
EN
VSW
TOFF
VIN
Zero Current Detect
GND
GND
Figure 3. Functional Block Diagram
7.3 Feature Description
7.3.1 Power Save Mode
The device automatically enters Power Save Mode to improve efficiency at light load when the inductor current
becomes discontinuous. In Power Save Mode, the converter reduces switching frequency and minimizes current
consumption. In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect
is minimized by increasing the output capacitor, or adding a feed forward capacitor, as shown in Figure 14.
7.3.2 100% Duty Cycle Low Dropout Operation
The device offers low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input
voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:
VIN(MIN) = VOUT + IOUT x RDS(ON) + RL
Where
•
RDS(ON) = High side FET on-resistance
•
RL = Inductor ohmic resistance (DCR)
(1)
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
7
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
Feature Description (continued)
7.3.3 Soft Start
After enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output
voltage during a startup time. This avoids excessive inrush current and creates a smooth output voltage rise
slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal
impedance.
The TLV62585 is able to start into a pre-biased output capacitor. The converter starts with the applied bias
voltage and ramps the output voltage to its nominal value.
7.3.4 Switch Current Limit and Short Circuit Protection (HICCUP)
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a over load
or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET is
turned off and the low-side MOSFET is turned on to ramp down the inductor current with an adaptive off-time.
When this switch current limits is triggered 32 times, the device reduces the current limit for further 32 cycles and
then stops switching to protect the output. The device then automatically start a new startup after a typical delay
time of 500 μs has passed. This is named HICCUP short circuit protection. The devices repeat this mode until
the high load condition disappears. HICCUP protection is also enabled during the startup.
7.3.5 Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented,
which shuts down the device at voltages lower than VUVLO with a hysteresis of 150 mV.
7.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
7.4 Device Functional Modes
7.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic HIGH. Accordingly, shutdown mode is forced if the EN pin
is pulled LOW with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
output discharge FET discharges the output through the SW pin smoothly.
7.4.2 Power Good
The TLV62585 has a power good output. The power good goes high impedance once the output is above 95%
of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails
by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used.
Table 1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH Z
EN = High, VFB ≥ VPG
Enable
Shutdown
EN = High, VFB ≤ VPG
√
EN = Low
√
√
Thermal Shutdown
UVLO
1.4 V < VIN < 2.3 V
Power Supply Removal
VIN ≤ 1.4 V
8
LOW
√
√
√
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
TLV62585
www.ti.com
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV62585 is a synchronous step-down converter in which output voltage is adjusted by component
selection. The following section discusses the design of the external components to complete the power supply
design for several input and output voltage options by using typical applications as a reference.
8.2 Typical Application
VPG
TLV62585
PG
VIN
2.5 V to 5.5 V
VIN
C1
10 µF
R3
1M
L1
1.0 µH
VOUT
1.8 V / 3.0 A
SW
C2
10 µF
EN
PGND
C3*
R1
200 k
FB
AGND
R2
100 k
C3: Optional
Figure 4. 1.8-V Output Voltage Application
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.5 V to 5.5 V
Output voltage
1.8 V
Maximum output current
3A
Table 3 lists the components used for the example.
Table 3. List of Components (1)
REFERENCE
(1)
DESCRIPTION
MANUFACTURER
C1
10 µF, Ceramic capacitor, 10 V, X7R, size 0805, GRM21BR71A106ME51
Murata
C2
22 µF, Ceramic capacitor, 6.3 V, X7T, size 0805, GRM21BD70J226ME44
Murata
C3
Optional
L1
1 µH, Power Inductor, size 4 mm × 4 mm × 1.5 mm, XFL4020-102ME
R1
Depending on the output voltage, 1%, size 0603;
Std
R2
100 kΩ, Chip resistor, 1/16 W, 1%, size 0603;
Std
R3
1 MΩ, Chip resistor, 1/16 W, 1%, size 0603
Std
Std
Coilcraft
See Third-Party Products disclaimer.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
9
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62585 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Setting The Output Voltage
The output voltage is set by an external resistor divider according to Equation 2:
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç 1 +
÷
÷ = 0.6V ´ ç 1 +
R2 ø
R2 ø
è
è
(2)
R2 must not be higher than 100 kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity.
8.2.2.3 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process,
Table 4 outlines possible inductor and capacitor value combinations for most applications.
Table 4. Matrix of Output Capacitor and Inductor Combinations
NOMINAL L [µH] (1)
NOMINAL COUT [µF] (2) (3)
10
22
47
+
+ (4)
+
100
0.47
1
2.2
(1)
(2)
(3)
(4)
10
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and
–30%.
For low output voltage applications (< 1.8 V), more output capacitance is recommended (usually ≥ 22
μF) for smaller ripple. For output capacitance higher than 47 µF, a feed forward capacitor is needed.
Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by
20% and –50%.
Typical application configuration. Other '+' mark indicates recommended filter combinations.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
TLV62585
www.ti.com
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
8.2.2.4 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 3 is given.
DI
IL,MAX = IOUT,MAX + L
2
VOUT
VIN
DIL = VOUT ´
L ´ fSW
1-
where
•
•
•
•
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
(3)
TI recommends choosing the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of
Equation 3. A higher inductor value is also useful to lower ripple current but increases the transient response
time as well.
8.2.2.5 Input and Output Capacitor Selection
The architecture of the TLV62585 allows use of tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep its
resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is
recommended to use X7R or X5R dielectric.
The input capacitor is the low impedance energy source for the converter that helps provide stable operation. A
low ESR multilayer ceramic capacitor is recommended for best filtering. For most applications, 10-μF input
capacitor is sufficient; a larger value reduces input voltage ripple.
The TLV62585 is designed to operate with an output capacitor of 10 μF to 47 μF, as outlined in Table 4.
A feed forward capacitor reduces the output ripple in PSM and improves the load transient response. A 22-pF
capacitor is good for the 1.8-V output typical application.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
11
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
8.2.3 Application Curves
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
VIN = 5 V, VOUT = 1.8 V, TA = 25 ºC, unless otherwise noted.
85
80
75
80
75
70
70
65
85
VIN = 2.5V
VIN = 3.3V
VIN = 5.0V
60
1m
65
10m
100m
Load (A)
1
VIN = 2.5V
VIN = 3.3V
VIN = 5.0V
60
1m
3
10m
D004
VOUT = 1.2 V
3
D005
Figure 6. Efficiency
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
1
VOUT = 1.8 V
Figure 5. Efficiency
85
80
75
70
65
100m
Load (A)
85
80
75
70
65
VIN = 3.3V
VIN = 5.0V
60
1m
VIN = 5 V
10m
100m
Load (A)
1
60
1m
3
10m
D006
VOUT = 2.5 V
100m
Load (A)
1
3
D007
VOUT = 3.3 V
Figure 7. Efficiency
Figure 8. Efficiency
0.5
1.0
0.4
Line Regulation (%)
Load Regulation (%)
0.3
0.2
0.1
0
-0.1
-0.2
0.5
0.0
-0.5
-0.3
-0.4
-0.5
0.5
IOUT = 0.5A
IOUT = 1.0A
IOUT = 3.0A
VOUT = 1.8 V
VOUT = 3.3 V
1
1.5
2
2.5
Load (A)
VIN = 5 V
3
-1.0
2.5
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
D010
VOUT = 1.8 V
Figure 9. Load Regulation
12
3.0
D009
Figure 10. Line Regulation
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
TLV62585
www.ti.com
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
2000
Switching Frequency (kHz)
Switching Frequency (kHz)
2000
1500
1000
500
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
1500
1000
500
0
2.5
0
0
0.3
0.6
0.9
1.2
1.5 1.8
Load (A)
2.1
2.4
2.7
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
3
3
3.5
D011
VIN = 5 V
4
4.5
Input Voltage (V)
5
5.5
D012
IOUT = 1 A
Figure 11. Switching Frequency
Figure 12. Switching Frequency
ICOIL
0.5A/DIV
ICOIL
0.5A/DIV
VOUT
50mV/DIV
AC
VOUT
50mV/DIV
AC
VSW
5V/DIV
VSW
5V/DIV
7LPH
V ',9
7LPH
V ',9
D014
D019
IOUT = 0.1 A
IOUT = 0.1 A
Figure 13. PSM Operation
C3 = 22 pF
Figure 14. PSM Operation with A Feedforward Capacitor
VEN
2V/DIV
ICOIL
0.5A/DIV
VOUT
1V/DIV
VOUT
10mV/DIV
AC
ICOIL
2A/DIV
VSW
5V/DIV
Time - 500ns/DIV
7LPH
V ',9
D013
IOUT = 3 A
D015
ROUT = 0.6 Ω
Figure 15. PWM Operation
Figure 16. Start-Up and Shut-Down with Load
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
13
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
VEN
2V/DIV
ILOAD
2A/DIV
VOUT
1V/DIV
VOUT
0.1V/DIV
ICOIL
0.5A/DIV
7LPH
V ',9
7LPH
V ',9
D016
No Load
D017
IOUT = 0.1 A to 3 A
Figure 17. Start-Up and Shut-Down without Load
Figure 18. Load Transient
Entry
Recovery
ILOAD
2A/DIV
VOUT
1V/DIV
VOUT
0.1V/DIV
ILOAD
2A/DIV
7LPH
V ',9
7LPH
V ',9
D018
IOUT = 0.1 A to 3 A
C3 = 22 pF
D020
IOUT = 0.1 A
Figure 19. Load Transient with A Feedforward Capacitor
Figure 20. Output Short Protection (HICCUP)
Entry
VOUT
1V/DIV
ILOAD
2A/DIV
7LPH
V ',9
D021
IOUT = 0.1 A
Figure 21. Output Short Protection (HICCUP) - Zoom In
14
Figure 22. Temperature Rise of DRL Package on EVM
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
TLV62585
www.ti.com
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.5 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.
10 Layout
10.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the TLV62585
device.
• The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
• The low side of the input and output capacitors must be connected properly to the GND pin to avoid a ground
potential shift.
• The sense traces connected to FB is a signal trace. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes.
• A common ground should be used. GND layers might be used for shielding.
See Figure 23 and Figure 24 for the recommended PCB layout.
10.2 Layout Example
Vin
C1
L1
U1
R2 R1
C2
Vout
GND
Figure 23. PCB Layout Recommendation (TLV62585RWT)
Figure 24. PCB Layout Recommendation (TLV62585PDRL)
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
15
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
The big copper planes connecting to the pads of the IC on the PCB improve the thermal performance of the
device. For more details on how to use the thermal parameters, see: .
• Thermal Characteristics Application Notes, SZZA017 and SPRA953
16
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
TLV62585
www.ti.com
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62585 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Thermal Characteristics Application Note
• Thermal Characteristics Application Note
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
17
TLV62585
SLVSDE5F – NOVEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV62585
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV62585DRLR
ACTIVE
SOT-5X3
DRL
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1BQ
TLV62585DRLT
ACTIVE
SOT-5X3
DRL
6
250
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-1-260C-UNLIM
-40 to 125
1BQ
TLV62585PDRLR
ACTIVE
SOT-5X3
DRL
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1BP
TLV62585PDRLT
ACTIVE
SOT-5X3
DRL
6
250
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-1-260C-UNLIM
-40 to 125
1BP
TLV62585RWTR
ACTIVE
VQFN-HR
RWT
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
17BI
TLV62585RWTT
ACTIVE
VQFN-HR
RWT
12
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
17BI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2020
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TLV62585DRLR
SOT-5X3
DRL
6
3000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.0
1.8
0.75
4.0
8.0
Q3
TLV62585DRLT
SOT-5X3
DRL
6
250
180.0
8.4
2.0
1.8
0.75
4.0
8.0
Q3
TLV62585PDRLR
SOT-5X3
DRL
6
3000
180.0
8.4
2.0
1.8
0.75
4.0
8.0
Q3
TLV62585PDRLT
SOT-5X3
DRL
6
250
180.0
8.4
2.0
1.8
0.75
4.0
8.0
Q3
TLV62585RWTR
VQFNHR
RWT
12
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV62585RWTT
VQFNHR
RWT
12
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV62585DRLR
SOT-5X3
DRL
6
3000
210.0
185.0
35.0
TLV62585DRLT
SOT-5X3
DRL
6
250
210.0
185.0
35.0
TLV62585PDRLR
SOT-5X3
DRL
6
3000
210.0
185.0
35.0
TLV62585PDRLT
SOT-5X3
DRL
6
250
210.0
185.0
35.0
TLV62585RWTR
VQFN-HR
RWT
12
3000
182.0
182.0
20.0
TLV62585RWTT
VQFN-HR
RWT
12
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
RWT0012A
VQFN-HR - 1 mm max height
SCALE 5.000
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2X
0.4
0.3
2X
0.55
0.45
(0.1) TYP
5
6X 0.5
4
6
12
2X
1.5
SYMM
0.5
PIN 1 ID
11
9
1
10
2X
0.24
0.20
10X
SYMM
8X
0.3
0.2
0.1
0.05
C A B
0.45
0.35
4223084/B 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RWT0012A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
2X (0.55)
10
8X (0.6)
10X (0.25)
1
9
(0.5)
11
SYMM
(R0.05) TYP
(1.85)
12
2X (0.22)
6X (0.5)
6
4
5
2X (0.5)
(1.8)
LAND PATTERN EXAMPLE
SCALE:30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223084/B 10/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, it is recommended that vias under
paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RWT0012A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.55)
10
8X (0.6)
10X (0.25)
9
1
(0.5)
11
SYMM
(R0.05) TYP
(1.85)
12
6X (0.5)
2X (0.22)
6
4
5
SYMM
2X (0.5)
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223084/B 10/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
SCALE 8.000
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
1
A
6
4X 0.5
1.7
1.5
NOTE 3
2X 1
4
3
B
1.3
1.1
6X
0.3
0.1
0.6 MAX
0.05
TYP
0.00
C
SEATING PLANE
6X
0.18
0.08
0.05 C
SYMM
SYMM
6X
6X
0.4
0.2
0.27
0.15
0.1
0.05
C A B
4223266/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4223266/A 09/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/A 09/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising