Texas Instruments | TPSM8282x 1-A and 2-A High Efficiency Step-Down Converter MicroSiP Power Module with Integrated Inductor (Rev. A) | Datasheet | Texas Instruments TPSM8282x 1-A and 2-A High Efficiency Step-Down Converter MicroSiP Power Module with Integrated Inductor (Rev. A) Datasheet

Texas Instruments TPSM8282x 1-A and 2-A High Efficiency Step-Down Converter MicroSiP Power Module with Integrated Inductor (Rev. A) Datasheet
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TPSM82822, TPSM82821
SLVSEP0A – AUGUST 2019 – REVISED DECEMBER 2019
TPSM8282x 1-A and 2-A High Efficiency Step-Down Converter MicroSiP™ Power Module
with Integrated Inductor
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The TPSM8282x device family consists of a 1-A and
2-A step-down converter MicroSiP™ power module
optimized for small solution size and high efficiency.
1
Low profile MicroSiP™ power module
Up to 95% efficiency
2.4-V to 5.5-V input voltage range
0.6-V to 4-V adjustable output voltage
4-µA operating quiescent current
DCS-control topology
Power save mode for light load efficiency
100% duty cycle for lowest dropout
Hiccup short circuit protection
Output discharge
Power good output
Integrated soft startup
Overtemperature protection
2.0-mm x 2.5-mm x 1.1-mm 10-Pin µSiL package
29mm2 total solution size
2 Applications
•
•
•
•
Optical modules
Machine vision
Embedded camera system
Patient monitoring and diagnostics
The power modules integrate a synchronous stepdown converter and an inductor to simplify design,
reduce external components and save PCB area. The
low profile and compact solution is suitable for
automated assembly by standard surface mount
equipment.
To maximize efficiency, the converter operates in
PWM mode with a nominal switching frequency of
4MHz and automatically enters Power Save Mode
operation at light load currents.
In Power Save Mode, the device operates with
typically 4-µA quiescent current. Using the DCSControl topology, the device achieves excellent load
transient performance and accurate output voltage
regulation. The EN and PG pins, which support
sequencing configurations, bring a flexible system
design. An integrated soft startup reduces the inrush
current required from the input supply. Over
temperature protection and hiccup short circuit
protection deliver a robust and reliable solution.
Device Information
PART NUMBER (1)
PACKAGE
BODY SIZE (NOM)
TPSM82821SIL
µSiL (10)
2.0 mm x 2.5 mm
TPSM82822SIL
µSiL (10)
2.0 mm x 2.5 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
1.8-V Output Application
1.8-V Output Efficiency
TPSM82822
VIN
C2
2 x 10 µF
C1
EN
FB
GND
100
1.8V/2A
VOUT
PG
95
C3
120 pF
90
85
R3
POWER
GOOD
Efficiency (%)
2.4V to 5.5V
VOUT
VIN
80
75
70
65
VIN
VIN
VIN
VIN
60
55
50
100P
1m
10m
Load (A)
100m
=
=
=
=
1
2.4V
3.3V
4.2V
5.0V
3
D035
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM82822, TPSM82821
SLVSEP0A – AUGUST 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
5
5
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommend Operating Conditions...........................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics.......................................... 7
Detailed Description .............................................. 8
9.1
9.2
9.3
9.4
Overview ................................................................... 8
Functional Block Diagram ......................................... 8
Feature Description................................................... 8
Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Applications .............................................. 11
11 Power Supply Recommendations ..................... 19
12 Layout................................................................... 19
12.1 Layout Guidelines ................................................. 19
12.2 Layout Example .................................................... 20
12.3 Thermal Consideration.......................................... 21
13 Device and Documentation Support ................. 22
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
22
22
14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Original (August 2019) to Revision A
Page
•
Change device status from Advance Information to Production Data.................................................................................... 1
•
Added planned device spins to Device Comparison Table ................................................................................................... 3
2
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5 Device Comparison Table
DEVICE NUMBER
(1)
(1)
OUTPUT CURRENT
OUTPUT VOLTAGE
TPSM82821SIL
1A
adjustable
TPSM82822SIL
2A
adjustable
For all available packages, see the orderable addendum at the end of the data sheet.
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6 Pin Configuration and Functions
µSiL Package
(Top View)
VIN
1
10
GND
VIN
2
9
GND
EN
3
8
FB
PG
4
7
VOUT
VOUT
5
6
VOUT
Pin Functions
PIN
NAME
EN
FB
GND
PG
VIN
VOUT
4
NO.
3
I/O
DESCRIPTION
I
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low
disables the device. Do not leave floating.
Feedback pin. This pin must be connected to the center of the output voltage resistor divider.
8
I
9, 10
PWR
4
O
1, 2
PWR
Input voltage pin.
5, 6, 7
PWR
Output voltage pin.
Ground pin.
Power good open drain output pin. The pull-up resistor can be connected to voltages up to
5.5 V. If unused, leave it floating.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN
MAX
-0.3
6
V
Module operating temperature range
-40
125
°C
Storage temperature range
-40
125
°C
Voltage at pins (2)
(1)
(2)
EN, PG, VIN, FB, VOUT
UNIT
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommend Operating Conditions
VIN
Input voltage range
VPG
Power good pull-up resistor voltage
VOUT
Output voltage range
ISINK_PG
Sink current at PG pin
IOUT
TPSM82821 Output current range (1)
IOUT
TPSM82822 Output current range (1)
TJ
Module operating temperature range (1)
(1)
MIN
MAX
UNIT
2.4
5.5
V
5.5
V
0.6
4
V
1
mA
0
1
A
0
2
A
-40
125
°C
The module operating temperature range includes module self temperature rise and IC junction temperature rise. In applications where
high power dissipation is present, the maximum operating temperature or maximum output current must be derated.
7.4 Thermal Information
THERMAL METRIC (1)
µSiL (JEDEC 51-7)
10-Pin
TPSM82822EVM-080
RθJA
Junction-to-ambient thermal resistance
92.5
63.9
RθJC(top)
Junction-to-case (top) thermal resistance
43.3
n/a (2)
RθJB
Junction-to-board thermal resistance
27.9
n/a (2)
ψJT
Junction-to-top characterization parameter
11.8
9.6
ψJB
Junction-to-board characterization parameter
27.5
27.0
(1)
(2)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
Not applicable to an EVM.
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7.5 Electrical Characteristics
TJ = –40°C to 125°C and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Quiescent current into VIN
EN = High, no load, device not switching
ISD
Shutdown current into VIN
EN = Low, TJ = -40°C to 85°C
Under voltage lock out threshold
VIN falling
Under voltage lock out hysteresis
VIN rising
160
mV
Thermal shutdown threshold
TJ rising
150
°C
Thermal shutdown hysteresis
TJ falling
20
°C
VUVLO
TJSD
2.1
4
10
µA
0.05
0.5
µA
2.2
2.3
V
LOGIC INTERFACE EN
VIH
High-level input voltage
VIL
Low-level input voltage
Ilkg(EN)
Input leakage current into EN pin
1.0
EN = High
V
0.01
0.4
V
0.1
µA
SOFT START, POWER GOOD
tSS
Soft start time
Power good lower threshold
VPG
Power good upper threshold
Time from EN high to 95% of VOUT nominal
1.25
ms
VPG rising, VFB referenced to VFB nominal
94
96
98
%
VPG falling, VFB referenced to VFB nominal
90
92
94
%
VPG rising, VFB referenced to VFB nominal
103
105
107
%
VPG falling, VFB referenced to VFB nominal
108
110
112
%
VPG,OL
Low-level output voltage
Isink = 1mA
Ilkg(PG)
Input leakage current into PG pin
VPG = 5V
VFB
Feedback regulation voltage
PWM mode
Ilkg(FB)
Feedback input leakage current
VFB = 0.6 V
iDIS
Output discharge current
EN = Low, VOUT = 0.4V
0.4
V
0.1
µA
600
606
mV
0.01
0.05
0.01
OUTPUT
594
75
µA
400
mA
High-side FET on-resistance
26
mΩ
Low-side FET on-resistance
26
POWER SWITCH
RDS(on)
mΩ
RDP
Dropout resistance
TPSM82821, 100% mode. VIN = 2.7V, TJ = 25°C
115
145
mΩ
RDP
Dropout resistance
TPSM82822, 100% mode. VIN = 2.7V, TJ = 25°C
90
120
mΩ
ILIMF
High-side FET switch current limit
TPSM82821
1.75
2.2
2.75
A
ILIMF
High-side FET switch current limit
TPSM82822
2.7
3.3
3.9
A
fSW
PWM switching frequency
IOUT = 1 A
6
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4
MHz
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8 Typical Characteristics
160.0
130.0
TJ = -40 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
140.0
130.0
120.0
110.0
100.0
90.0
80.0
70.0
2.4
110.0
100.0
90.0
80.0
70.0
60.0
50.0
2.9
3.4
3.9
4.4
Input Voltage (V)
4.9
40.0
2.4
5.4
Figure 1. TPSM82821 Dropout Resistance
3.9
4.4
Input Voltage (V)
4.9
5.4
D030
Figure 2. TPSM82822 Dropout Resistance
0.4
Shutdown Current (PA)
Quiescent Current (PA)
3.4
0.5
6.0
4.0
0.0
2.5
2.9
D030
8.0
2.0
TJ = -40 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
120.0
Dropout Resistance (m:)
Dropout Resistance (m:)
150.0
TJ = -40 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
3.0
TJ = -40 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
0.3
0.2
0.1
3.5
4.0
4.5
Input Voltage (V)
Figure 3. Quiescent Current
5.0
5.5
0.0
2.5
3.0
3.5
D031
4.0
4.5
Input Voltage (V)
5.0
5.5
D032
Figure 4. Shutdown Current
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9 Detailed Description
9.1 Overview
The TPSM8282x synchronous step-down converter power module is based on DCS-Control™ (Direct Control
with Seamless transition into Power-Save Mode). This is an advanced regulation topology that combines the
advantages of hysteretic, voltage and current mode control.
The DCS-Control™ topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in PSM (Power-Save Mode) at light load currents. In PWM, the converter operates with its
nominal switching frequency of 4 MHz having a controlled frequency variation over the input voltage range. As
the load current decreases, the converter enters Power-Save Mode, reducing the switching frequency and
minimizing the IC's quiescent current to achieve high efficiency over the entire load current range. DCS-Control™
supports both operation modes using a single building block and therefore has a seamless transition from PWM
to PSM without effects on the output voltage. The TPSM8282x offers excellent DC voltage regulation and load
transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.
9.2 Functional Block Diagram
PG
Hi ccu p
Co unter
V FB
V REF
VIN
Hi gh Side
Cu rre nt Se nse
Ban dgap
Un dervol ta ge Locko ut
Thermal Sh utd own
EN
L(1)
MOSFET D river
Co ntro l Log ic
GND
Ra mp
Di rect Co ntrol
an d
Co mp ensa ti on
Co mp arator
VOUT
Timer
ton
FB
V REF
Error Ampli fi er
DC S - Co ntro l
TM
EN
(1)
Output D ischarg e
Lo gic
Inductance value is 0.47 µH in TPSM82821 and 0.24 µH in TPSM82822.
9.3 Feature Description
9.3.1 PWM and PSM Operation
The TPSM8282x includes a fixed on-time (tON) circuitry. This tON, in steady-state operation in PWM and PSM
modes, is estimated as:
tON
8
250ns u
VOUT
VIN
(1)
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Feature Description (continued)
In PWM mode, the TPSM8282x operates with pulse width modulation in continuous conduction mode (CCM)
with a tON shown in Equation 1 at medium and heavy load currents. A PWM switching frequency of typically
4MHz is achieved by this tON circuitry.
To maintain high efficiency at light loads, the device enters Power-Save Mode seamlessly when the load current
decreases. This happens when the load current becomes smaller than half the inductor's ripple current. In PSM,
the converter operates with a reduced switching frequency and with a minimum quiescent current to maintain
high efficiency. The on-time in PSM is also based on the same tON circuitry. The switching frequency in PSM is
estimated as:
2 u IOUT
fPSM
V
VOUT
V
t ON2 u IN u IN
VOUT
L
(2)
In PSM, the output voltage rises slightly above the nominal output voltage in PWM mode. This effect is reduced
by increasing the output capacitance.
9.3.2 Low Dropout Operation (100% Duty Cycle)
The device offers a low input to output voltage differential by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to
achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input
voltage to maintain a minimum output voltage is given by:
VIN(min) = VOUT(min) + IOUT x RDP
(3)
Where
RDP = Resistance from VIN to VOUT, including high-side FET on-resistance and DC resistance of the inductor.
VOUT(min) = Minimum output voltage the load can accept.
9.3.3 Soft Startup
After enabling the device, there is a 250µs delay before switching starts. Then, an internal soft startup circuitry
ramps up the output voltage which reaches nominal output voltage during the startup time of 1ms. This avoids
excessive inrush current and creates a smooth output voltage rise slope. It also prevents excessive voltage
drops of primary cells and rechargeable batteries with high internal impedance.
The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the
output voltage to its nominal value.
9.3.4 Switch Current Limit and Hiccup Short Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold of ILIMF the high-side
MOSFET is turned off and the low-side MOSFET remains off, while the inductor current flows through its body
diode and quickly ramps down.
When this switch current limit is triggered 32 times, the device stops switching. The device then automatically
starts a new start-up after a typical delay time of 128 µs has passed. This is named HICCUP short-circuit
protection. The device repeats this mode until the high load condition disappears.
9.3.5 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down
the device at voltages lower than VUVLO.
9.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops the power stage switching when the junction temperature
exceeds TJSD. When the device temperature falls below the threshold by 20°C, the device returns to normal
operation automatically by switching the power stage again.
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9.4 Device Functional Modes
9.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is
pulled low with a shutdown current of typically 50nA. In shutdown mode, the internal power switches as well as
the entire control circuitry are turned off. An internal switch smoothly discharges the output through the VOUT pin
in shutdown mode. Do not leave the EN pin floating.
The typical threshold value of the EN pin is 0.89V for rising input signal, and 0.62V for falling input signal.
9.4.2 Output Discharge
The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage when the
device is disabled and to keep the output voltage close to 0 V. The output discharge is active when the EN pin is
set to a logic low and during thermal shutdown. The discharge is not active in UVLO.
9.4.3 Power Good Output
The device has a power good output. The PG pin goes high impedance once the FB pin voltage is above 96%
and less than 105% of the nominal voltage, and is driven low once the voltage falls below typically 92% or higher
than 110% of the nominal voltage. Table 1 shows the typical PG pin logic.
The PG pin is an open-drain output and is specified to sink up to 1mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 5.5V. The PG signal can be used for sequencing of multiple rails
by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used.
The PG rising edge has a 100 µs blanking time and the PG falling edge has a deglitch delay 20us.
Table 1. PG Pin Logic
DEVICE CONDITIONS
LOGIC STATUS
HIGH IMPEDANCE
EN = High, VFB ≤ 0.552 V
EN = High, 0.576 V ≤ VFB ≤ 0.63 V
Enable
LOW
√
√
EN = High, VFB ≥ 0.66 V
√
Shutdown
EN = Low
√
Thermal Shutdown
TJ > TJSD
√
UVLO
0.7 V < VIN < VUVLO
√
Power Supply Removal
VIN < 0.7 V
10
undefined
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPSM8282x is a synchronous step-down converter power module whose output voltage is adjusted by
component selection. The following section discusses the design of the external components to complete the
power supply design. The required power inductor is integrated inside the TPSM8282x. The inductor is shielded
and has an inductance of 0.47 µH for the TPSM82821 and 0.24 µH for the TPSM82822, with a +/- 20%
tolerance. The TPSM82821 and TPSM82822 are pin-to-pin and BOM-to-BOM compatible.
10.2 Typical Applications
10.2.1
1.8-V Output Application
TPSM82822
VIN
2.4V to 5.5V
VOUT
VIN
1.8V/2A
VOUT
C2
2 x 10 µF
C1
EN
C3
120 pF
FB
GND
R3
PG
POWER
GOOD
Figure 5. 1.8-V Output Application
10.2.1.1 Design Requirements
For this design example, use the input parameters shown in Table 2.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.4V to 5.5V
Output voltage
1.8V
Output ripple voltage
< 20mV
Output current rating
2A
Table 3 lists the components used for the example.
Table 3. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
C1
Ceramic capacitor, 4.7-µF, 6.3 V, X7R, size (0603), JMK107BB7475MA
C2
Ceramic capacitor, 10-µF , 10 V, X7R, size (0603), GRM188Z71A106MA73D
Taiyo Yuden
muRata
C3
Ceramic capacitor, 120-pF , 50 V, size (0603), GRM1885C1H121JA01D
muRata
R1
Resistor, 200-kΩ, 1% accuracy
std
R2
Resistor, 100 kΩ, 1% accuracy
std
R3
Resistor, 100 kΩ, 1% accuracy
std
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10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Setting the Output Voltage
Choose resistors R1 and R2 to set the output voltage within a range of 0.6-V to 4-V, according to Equation 4. To
keep the feedback (FB) net robust from noise, set R2 equal to or lower than 100kΩ to have at least 3µA of
current in the voltage divider. Lower values of FB resistors achieve better noise immunity, and lower light load
efficiency, as explained in SLYT469.
§V
R1 R2 u ¨ OUT
© VFB
·
1¸
¹
§V
R2 u ¨ OUT
© 0.6V
·
1¸
¹
(4)
10.2.1.2.2 Feedforward capacitor
A feedforward capacitor (C3) is recommended in parallel with R1. Equation 5 calculates the C3 value.
C3
10.2.1.2.3
12Ps
R2
(5)
Input and Output Capacitor Selection
For best output and input voltage filtering, ceramic capacitors are required. The input capacitor minimizes input
voltage ripple, suppresses input voltage spikes and provides a stable system rail for the device. A 4.7µF or larger
input capacitor is required. The output capacitor value can range from 10µF up to more than 47µF. The
recommended typical output capacitor value is 10µF. Values over 47µF may degrade the converter's regulation
loop stability. A feed forward capacitor is required for best transient performance.
Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance.
Choose the right capacitor carefully in combination with considering its package size and voltage rating. Ensure
that the input effective capacitance is at least 3µF and the output effective capacitance is at least 5µF.
12
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10.2.1.3 Application Performance Curves
TA = 25°C, VIN = 5 V, VOUT = 1.8 V, BOM = Table 3 unless otherwise noted.
10.2.1.3.1 TPSM82821 Performance Curves
90
100
85
95
90
80
Efficiency (%)
Efficiency (%)
85
75
70
65
80
75
70
65
60
VIN = 2.4V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
55
50
100P
1m
10m
Load (A)
100m
VIN = 2.4V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
60
55
50
100P
1
1m
D033
VOUT = 0.6 V
TPSM82821
95
90
90
85
85
Efficiency (%)
Efficiency (%)
100
95
80
75
70
65
55
1m
10m
Load (A)
100m
80
75
70
60
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
55
50
100P
1
1m
D033
VOUT = 1.8 V
TPSM82821
100m
1
D033
TPSM82821
Figure 9. Efficiency
0.612
1.212
0.609
1.209
0.606
1.206
0.603
1.203
Vout (V)
Vout (V)
10m
Load (A)
VOUT = 3.3 V
Figure 8. Efficiency
0.6
0.597
0.588
100P
D033
TPSM82821
65
VIN = 2.4V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
60
0.591
1
Figure 7. Efficiency
100
0.594
100m
VOUT = 1.2 V
Figure 6. Efficiency
50
100P
10m
Load (A)
1.2
1.197
1.194
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1m
1.191
10m
Load (A)
100m
1
1.188
100P
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1m
D037
VOUT = 0.6 V
TPSM82821
Figure 10. Load Regulation
10m
Load (A)
100m
VOUT = 1.2 V
1
D037
TPSM82821
Figure 11. Load Regulation
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1.819
3.344
1.816
3.333
3.322
1.813
3.311
Vout (V)
Vout (V)
1.81
1.807
1.804
1.801
1.798
3.3
3.289
3.278
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1.795
100P
3.267
3.256
1m
10m
Load (A)
100m
VIN = 4.2V
VIN = 5.0 V
3.245
100P
1
1m
VOUT = 1.8 V
TPSM82821
100m
1
D037
VOUT = 3.3 V
TPSM82821
Figure 12. Load Regulation
Figure 13. Load Regulation
0.611
0.609
10m
Load (A)
D037
1.205
IOUT = 0A
IOUT = 1A
IOUT = 0A
IOUT = 1A
1.203
Vout (V)
Vout (V)
0.607
0.605
0.603
1.201
1.199
0.601
1.197
0.599
0.597
2.4
2.93
3.4
3.9
Vin (V)
4.4
4.9
1.195
2.4
5.4
2.93
VOUT = 0.6 V
TPSM82821
3.9
Vin (V)
4.4
4.9
5.4
D041
VOUT = 1.2 V
TPSM82821
Figure 14. Line Regulation
Figure 15. Line Regulation
3.35
1.810
1.808
3.4
D041
IOUT = 0A
IOUT = 1A
3.33
3.31
1.806
3.29
Vout (V)
Vout (V)
1.804
1.802
1.800
3.27
3.25
3.23
3.21
1.798
3.19
1.796
1.794
2.4
IOUT = 0A
IOUT = 1A
3.17
2.93
3.4
3.9
Vin (V)
4.4
4.9
3.15
3.3
5.4
3.8
D041
VOUT = 1.8 V
TPSM82821
4.8
VOUT = 3.3 V
Figure 16. Line Regulation
14
4.3
Vin (V)
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5.3
D041
TPSM82821
Figure 17. Line Regulation
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VOUT
20mV/DIV
VOUT
20mV/DIV
IOUT
0.25A/DIV
IOUT
0.5A/DIV
Time - 10Ps/DIV
IOUT = 0 A to 1 A
Time - 10Ps/DIV
Slew Rate = 2
A/µs
TPSM82821
IOUT = 0.5 A to 1 A
Figure 18. Load Transient
Slew Rate = 2
A/µs
TPSM82821
Figure 19. Load Transient
80.0
70.0
PSRR (dB)
60.0
50.0
40.0
30.0
IOUT = 0.5 A
IOUT = 1 A
IOUT = 2 A
20.0
10.0
1.0E+2
1.0E+3
1.0E+4
Frequency (Hz)
1.0E+5
1.0E+6
D053
TPSM82821
Figure 20. Power Supply Rejection Ratio (PSRR)
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10.2.1.3.2 TPSM82822 Performance Curves
90
100
85
95
90
80
Efficiency (%)
Efficiency (%)
85
75
70
65
80
75
70
65
60
VIN
VIN
VIN
VIN
55
50
100P
1m
10m
Load (A)
100m
=
=
=
=
2.4V
3.3V
4.2V
5.0V
1
VIN
VIN
VIN
VIN
60
55
50
100P
3
1m
10m
Load (A)
D033
VOUT = 0.6 V
TPSM82822
95
90
90
85
85
Efficiency (%)
100
95
Efficiency (%)
1
3
TPSM82822
Figure 22. Efficiency
100
80
75
70
80
75
70
65
65
VIN
VIN
VIN
VIN
60
55
50
100P
1m
10m
Load (A)
100m
=
=
=
=
2.4V
3.3V
4.2V
5.0V
1
60
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
55
50
100P
3
1m
10m
Load (A)
D035
VOUT = 1.8 V
TPSM82822
0.609
1.209
0.606
1.206
0.603
1.203
Vout (V)
1.212
0.6
0.597
0.591
0.588
100P
1
3
D036
TPSM82822
Figure 24. Efficiency
0.612
0.594
100m
VOUT = 3.3 V
Figure 23. Efficiency
Vout (V)
2.4V
3.3V
4.2V
5.0V
D034
VOUT = 1.2 V
Figure 21. Efficiency
1.2
1.197
1.194
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1m
1.191
10m
Load (A)
100m
1.188
100P
1
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1m
D037
VOUT = 0.6 V
TPSM82822
Figure 25. Load Regulation
16
100m
=
=
=
=
10m
Load (A)
100m
VOUT = 1.2 V
1
D038
TPSM82822
Figure 26. Load Regulation
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3.333
1.822
3.322
1.816
3.3
1.81
Vout (V)
Vout (V)
3.311
1.804
1.798
3.289
3.278
3.267
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1.792
100P
3.256
1m
10m
Load (A)
100m
VIN = 4.2V
VIN = 5.0V
3.245
100P
1
1m
VOUT = 1.8 V
TPSM82822
1
D040
TPSM82822
Figure 28. Load Regulation
1.205
0.611
IOUT = 0A
IOUT = 1A
IOUT = 2A
1.204
1.203
0.607
IOUT = 0A
IOUT = 1A
IOUT = 2A
1.202
Vout (V)
Vout (V)
100m
VOUT = 3.3 V
Figure 27. Load Regulation
0.609
10m
Load (A)
D039
0.605
0.603
1.201
1.200
1.199
1.198
0.601
1.197
0.599
0.597
2.4
1.196
2.93
3.4
3.9
Vin (V)
4.4
4.9
1.195
2.4
5.4
2.93
VOUT = 0.6 V
TPSM82822
4.4
4.9
5.4
D042
TPSM82822
Figure 30. Line Regulation
3.35
IOUT = 0A
IOUT = 1A
IOUT = 2A
3.33
3.31
3.29
Vout (V)
Vout (V)
3.9
Vin (V)
VOUT = 1.2 V
Figure 29. Line Regulation
1.815
1.814
1.813
1.812
1.811
1.810
1.809
1.808
1.807
1.806
1.805
1.804
1.803
1.802
1.801
1.800
2.4
3.4
D041
3.27
3.25
3.23
3.21
3.19
IOUT = 0A
IOUT = 1A
IOUT = 2A
3.17
2.93
3.4
3.9
Vin (V)
4.4
4.9
3.15
3.3
5.4
3.8
D043
VOUT = 1.8 V
TPSM82822
4.3
Vin (V)
4.8
VOUT = 3.3 V
Figure 31. Line Regulation
5.3
D044
TPSM82822
Figure 32. Line Regulation
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VIN
10mV/DIV
AC
VIN
10mV/DIV
AC
VOUT
10mV/DIV
AC
VOUT
10mV/DIV
AC
VSW
2V/DIV
VSW
2V/DIV
Time - 200ns/DIV
Time - 2Ps/DIV
D045
IOUT = 2 A
TPSM82822
D046
IOUT = 25 mA
Figure 33. Input and Output Ripple in PWM Mode
TPSM82822
Figure 34. Input and Output Ripple in PSM Mode
VOUT
20mV/DIV
VOUT
20mV/DIV
IOUT
0.5A/DIV
IOUT
0.5A/DIV
Time - 20Ps/DIV
Time - 10Ps/DIV
D047
IOUT = 25 mA to 2 A
TPSM82822
D048
IOUT = 0 A to 2 A
Slew Rate = 2
A/µs
TPSM82822
Figure 35. Load Sweep
Figure 36. Load Transient
VEN
5V/DIV
VPG
2V/DIV
VOUT
20mV/DIV
IOUT
0.5A/DIV
VOUT
0.4V/DIV
Time - 10Ps/DIV
Time - 500Ps/DIV
D049
IOUT = 0.5 A to 2 A
Slew Rate = 2
A/µs
Figure 37. Load Transient
18
TPSM82822
D050
IOUT = no load
TPSM82822
Figure 38. Startup / Shutdown without Load
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VPG
2V/DIV
VEN
5V/DIV
VPG
2V/DIV
VOUT
0.4V/DIV
VOUT
0.4V/DIV
Iload
2A/DIV
Time - 500Ps/DIV
Time - 500Ps/DIV
D051
IOUT = 2 A
D052
TPSM82822
Figure 39. Startup / Shutdown with Resistive Load
TPSM82822
Figure 40. Short Circuit, HICCUP Protection Entry / Exit
80.0
70.0
PSRR (dB)
60.0
50.0
40.0
30.0
IOUT = 0.5 A
IOUT = 1 A
IOUT = 2 A
20.0
10.0
1.0E+2
1.0E+3
1.0E+4
Frequency (Hz)
1.0E+5
1.0E+6
D053
TPSM82822
Figure 41. Power Supply Rejection Ratio (PSRR)
11 Power Supply Recommendations
The devices are designed to operate from an input supply voltage range between 2.4V and 5.5V. The average
input current of the TPSM8282x is calculated as:
´I
1 V
IIN = ´ OUT OUT
h
VIN
(6)
Ensure that the power supply has a sufficient current rating for the application.
12 Layout
12.1 Layout Guidelines
•
•
•
•
It is recommended to place all components as close as possible to the IC. Specially, the input capacitor
placement must be closest to the VIN and GND pins of the device.
Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
Refer to Figure 42 for an example of component placement, routing and thermal design.
The recommended land pattern for the TPSM8282x is shown at the end of this data sheet. For best
manufacturing results, it is important to create the pads as solder mask defined (SMD). This keeps each pad
the same size and avoids solder pulling the device during reflow.
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12.2 Layout Example
Solution size
29 mm2
Vout
FB
VOUT
VOUT
GND
VOUT
PG
GND
VIN
EN
VIN
GND
GND
Vin
Figure 42. TPSM8282x PCB Layout
20
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12.3 Thermal Consideration
The TPSM8282x module temperature must be kept less than the maximum rating of 125°C. Three basic
approaches for enhancing thermal performance are listed below:
• Improve the power dissipation capability of the PCB design.
• Improve the thermal coupling of the component to the PCB.
• Introduce airflow into the system.
To estimate the approximate module temperature of the TPSM8282x, apply the typical efficiency stated in this
datasheet to the desired application condition to compute the module's power dissipation. Then calculate the
module temperature rise by multiplying the power dissipation by its thermal resistance. For more details on how
to use the thermal parameters in real applications, see the application notes: SZZA017 and SPRA953.
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• TPSM82821EVM-005 Evaluation Module, SLVUBG0
• TPSM82822EVM-005 Evaluation Module, SLVUBG0
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
13.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.6 Trademarks
MicroSiP, DCS-Control, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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SLVSEP0A – AUGUST 2019 – REVISED DECEMBER 2019
PACKAGE OUTLINE
SIL0010D
uSIP
TM
- 1.1 mm max height
SCALE 6.000
MICRO SYSTEM IN PACKAGE
2.1
1.9
B
A
PIN 1 INDEX
AREA
(2)
PICK AREA
NOTE 3
2.6
2.4
(1.25)
1.1 MAX
C
SEATING PLANE
0.08 C
SYMM
SOLDER MASK
10X EXPOSED COPPER
10X
0.7
0.6
5
6
8X 0.5
SYMM
2
10
1
(0.05) TYP
COPPER PULLBACK
PIN 1 ID
10X
0.3
0.2
0.1
0.05
C A B
C
4223961/D 09/2019
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 0.33 mm or smaller recommended.
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EXAMPLE BOARD LAYOUT
SIL0010D
uSIP
TM
- 1.1 mm max height
MICRO SYSTEM IN PACKAGE
10X (0.65)
10X (0.25)
10
1
(R0.05) TYP
SYMM
8X (0.5)
6
5
SYMM
SEE SOLDER MASK
DETAILS
(1.25)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL EDGE
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223961/D 09/2019
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
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SLVSEP0A – AUGUST 2019 – REVISED DECEMBER 2019
EXAMPLE STENCIL DESIGN
SIL0010D
uSIP
TM
- 1.1 mm max height
MICRO SYSTEM IN PACKAGE
7X (0.65)
10
7X (0.25) 1
SYMM
8X (0.5)
5
6
(R0.05) TYP
SYMM
(1.25)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:25X
4223961/D 09/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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19-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPSM82821SILR
PREVIEW
uSiP
SIL
10
3000
RoHS (In
Work) & Green
(In Work)
Call TI
Call TI
-40 to 125
XPSM82822SILR
ACTIVE
uSiP
SIL
10
3000
TBD
Call TI
Call TI
-40 to 125
GA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2019
Addendum-Page 2
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