Texas Instruments | TPS62864/6 2.4-V to 5.5-V Input, 4-A and 6-A Synchronous Step-Down Converter with I2C Interface in 1.05-mm x 1.78-mm WCSP Package (Rev. A) | Datasheet | Texas Instruments TPS62864/6 2.4-V to 5.5-V Input, 4-A and 6-A Synchronous Step-Down Converter with I2C Interface in 1.05-mm x 1.78-mm WCSP Package (Rev. A) Datasheet

Texas Instruments TPS62864/6 2.4-V to 5.5-V Input, 4-A and 6-A Synchronous Step-Down Converter with I2C Interface in 1.05-mm x 1.78-mm WCSP Package (Rev. A) Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
TPS62864/6 2.4-V to 5.5-V Input, 4-A and 6-A Synchronous Step-Down Converter
with I2C Interface in 1.05-mm x 1.78-mm WCSP Package
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
7-mΩ and 6.5-mΩ internal power MOSFETs
>90% efficiency (0.9-V output)
DCS-control topology for fast transient response
Output voltage from 0.4 V to 1.675 V with 5-mV
step size for adaptive voltage scaling (AVS)
1% output voltage accuracy
4-µA operating quiescent current
2.4-V to 5.5-V input voltage range
2.4-MHz switching frequency
Selection by external resistor
– Start-up output voltage
– I2C slave address
Selection by I2C interface
– Power save mode or forced PWM mode
– Output discharge
– Hiccup or latching short-circuit protection
– Output voltage ramp speed
VID pin for dynamic voltage scaling (DVS)
Thermal pre-warning and thermal shutdown
Power good indicator pin option
I2C-compatible interface up to 3.4 Mbps
Available in 1.05-mm x 1.78-mm x 0.5-mm 15-pin
WCSP package with 0.35-mm pitch
Create a custom design using the TPS62866 with
the WEBENCH® Power Designer
•
•
•
Core supply for FPGAs, CPUs, ASICs or video
chipsets
Camera modules
Solid-state drives
Optical modules
3 Description
The TPS62864/6 devices are high-frequency
synchronous step-down converters with I2C interface
which provide an efficient, adaptive, and high powerdensity solution. At medium to heavy loads, the
converter operates in PWM mode and automatically
enters Power Save Mode operation at light load to
maintain high efficiency over the entire load current
range. The device can also be forced in PWM mode
operation for smallest output voltage ripple. Together
with its DCS-control architecture, excellent load
transient performance and tight output voltage
accuracy are achieved. Via the I2C interface and a
dedicated VID pin, the output voltage is quickly
adjusted to adapt the load’s power consumption to
the ever-changing performance needs of the
application.
Device Information(1)
PART NUMBER
TPS62864
TPS6286x
C1
2x10 µF
I2C
Efficiency at VIN = 3.3 V
L1
0.24 µH
VOUT
0.9 V
C2
2x22 µF
VOS
EN
AGND
PGND
1.05 x 1.78 x 0.5 mm
100
95
SW
VSET/VID
SCL
or
SDA VSET/PG
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
R1
90
Efficiency (%)
VIN
WCSP (15)
TPS62866
Typical Application
VIN
2.4 V to 5.5 V
PACKAGE
85
80
75
70
65
60
100P
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
1m
10m
100m
Load (A)
1
6
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C InterfaceTiming Characteristics ..........................
I2C Timing Diagram...................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 12
8.5 Programming........................................................... 14
8.6 Register Map........................................................... 17
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Applications ................................................ 20
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 27
11.3 Thermal Considerations ........................................ 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Documentation Support ........................................
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2019) to Revision A
•
2
Page
Change device status from Advance Information to Production Data.................................................................................... 1
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
5 Device Options
(1)
PART NUMBER (1)
STARTUP OUTPUT VOLTAGE
OUTPUT CURRENT
VID or PG PIN
TPS628640AYCG
0.4V to 1.15V, Selectable
4A
VID
TPS628640BYCG
0.4V to 1.15V, Selectable
4A
PG
TPS628660AYCG
0.4V to 1.15V, Selectable
6A
VID
TPS628660BYCG
0.4V to 1.15V, Selectable
6A
PG
TPS6286612YCG
Fixed 1.2V
6A
VID
For all available packages, see the orderable addendum at the end of the data sheet.
6 Pin Configuration and Functions
YCG (15 Pin)
TOP VIEW
BOTTOM VIEW
1
2
3
3
2
1
AGND
VSET/
VID
VOS
A
VOS
VSET/
VID
AGND
PGND
PGND
PGND
B
PGND
PGND
PGND
SW
SW
SW
C
SW
SW
SW
VIN
VIN
VIN
D
VIN
VIN
VIN
EN
SDA
SCL
E
SCL
SDA
EN
Pin Functions
PIN
DESCRIPTION
NAME
NO.
AGND
A1
Analog ground pin.
VSET/VID
A2
Startup output voltage and device address selection pin. An external resistor must be connected.
After startup, the pin can be used to select the VOUT registers for the output voltage. (Low = VOUT
register 1; High = VOUT register 2). See Select Output Voltage Registers (VID) .
VSET/PG
A2
Startup output voltage and device address selection pin. An external resistor must be connected.
After startup, the pin is used for the power good indicator. When the output voltage is not regulated, the
pin is driven high. When the output voltage is regulated, the pin is pulled low through the external
resistor.
The function after startup depends on the device option. See Device Options.
VOS
A3
Output voltage sense pin. This pin must be directly connected to the output capacitor.
PGND
B1,B2,B3
Power ground pin.
SW
C1,C2,C3
Switch pin of the power stage.
VIN
D1,D2,D3
Power supply input voltage pin.
EN
E1
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables
the device. Do not leave floating.
SDA
E2
I2C serial data pin. Do not leave it floating.
SCL
E3
I2C serial clock pin. Do not leave it floating.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
3
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings (1)
Voltage (2)
MIN
MAX
VIN, EN, SDA, SCL, VOS, VSET/VID, VSET/PG
-0.3
6
SW (DC)
-0.3
VIN + 0.3
SW (AC, less than 10ns) (3)
-2.5
10
UNIT
V
ISOURCE_PG
Source current at VSET/PG
1
mA
ISINK_SDA,SCL
Sink current at SDA, SCL
2
mA
TJ
Junction temperature
-40
150
°C
Tstg
Storage temperature
-65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
While switching.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VIN
Input voltage
tF_VIN
Falling transition time at VIN (1)
IOUT
TJ
(1)
(2)
(3)
NOM
MAX
2.4
5.5
V
10
mV/µs
Output current, TPS62864
(2)
0
4
Output current, TPS62866
(3)
0
6
-40
125
Junction temperature
UNIT
A
°C
The falling slew rate of VIN should be limited if VIN goes below VUVLO.
Lifetime is reduced when operating continuously at 4-A output current and the junction temperature is higher than 105 °C.
Lifetime is reduced when operating continuously at 6-A output current and the junction temperature is higher than 85 °C.
7.4 Thermal Information
TPS6286x YCG
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
JEDEC 51-7
TPS62866EVM-051
15 PINS
15 PINS
UNIT
91.8
56.5
°C/W
(2)
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.8
n/a
RθJB
Junction-to-board thermal resistance
23.5
n/a (2)
°C/W
ΨJT
Junction-to-top characterization parameter
0.4
0.4
°C/W
ΨJB
Junction-to-board characterization parameter
23.3
27.3
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Not applicable to an EVM.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
7.5 Electrical Characteristics
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Quiescent current
EN = High, no load, device not switching
ISD
Shutdown current
EN = Low, TJ = -40℃ to 85℃
VUVLO
TJW
TJSD
Under voltage lock out threshold
VIN rising
2.2
VIN falling
2.1
4
10
µA
0.1
1
µA
2.3
2.4
V
2.2
2.3
V
Thermal warning threshold
TJ rising
130
°C
Thermal warning hysteresis
TJ falling
20
°C
Thermal shutdown threshold
TJ rising
150
°C
Thermal shutdown hysteresis
TJ falling
20
°C
LOGIC INTERFACE EN, SDA, SCL
VIH
High-level input threshold voltage at EN,
SCL, SDA, VSET/VID
VIL
Low-level input threshold voltage at EN,
SCL, SDA, VSET/VID
1.0
V
0.4
V
ISCL,LKG Input leakage current into SCL pin
0.01
0.2
µA
ISDA,LKG Input leakage current into SDA pin
0.01
0.1
µA
IEN,LKG
Input leakage current into EN pin
0.01
0.1
µA
CSCL
Parasitic capacitance at SCL
1
pF
CSDA
Parasitic capacitance at SCL
2.4
pF
STARTUP, POWER GOOD
tDelay
Enable delay time
Time from EN high to device starts switching, R1
= 249kΩ
420
tRamp
Output voltage ramp time
Time from device starts switching to power good
Power good lower threshold
VVOS referenced to VOUT nominal
Power good upper threshold
VVOS referenced to VOUT nominal
Power good deglitch delay
Rising and falling edges
VPG
tPG,DLY
600
1100
µs
0.9
1
1.5
ms
85
91
96
%
103
111
120
34
%
µs
OUTPUT
VOUT
Output voltage accuracy (1)
IVOS,LKG Input leakage current into VOS pin
RDIS
VOUT ≥ 0.59 V, FPWM, no Load, TJ = 25℃ to
125℃
-1
1
%
VOUT < 0.59 V, FPWM, no Load, TJ = 25℃ to
125℃
-2
2
%
EN = High, VVOS = 1.8 V
18
EN = Low, Output discharge disabled, VVOS =
1.8 V
0.2
Output discharge resistor at VOS pin
Load regulation
µA
2.5
Ω
15
VOUT = 0.9 V, FPWM
µA
0.04
%/A
7
mΩ
POWER SWITCH
RDS(on)
High-side FET on-resistance
Low-side FET on-resistance
High-side FET forward current limit
ILIM
fSW
(1)
Low-side FET forward current limit
6.5
mΩ
TPS62864
5
5.5
6
A
TPS62866
7
7.7
8.5
A
TPS62864
4.5
A
TPS62866
6.5
A
Low-side FET negative current limit
TPS62864, TPS62866
PWM switching frequency
IOUT = 1 A, VOUT = 0.9 V
-3
A
2.4
MHz
Exclude codes: 0x20 (560 mV), 0x40 (720 mV), 0x60 (880 mV), 0x80 (1040 mV), 0xC4 (1360 mV), 0xE0 (1520 mV).
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
5
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
7.6 I2C InterfaceTiming Characteristics (1) (2)
PARAMETER
MAX
UNIT
Standard mode
TEST CONDITIONS
MIN
100
kHz
Fast mode
400
kHz
1
MHz
High-speed mode (write operation), CB – 100 pF max
3.4
MHz
High-speed mode (read operation), CB – 100 pF max
3.4
MHz
High-speed mode (write operation), CB – 400 pF max
1.7
MHz
1.7
MHz
Fast mode plus
f(SCL)
SCL Clock Frequency
High-speed mode (read operation), CB – 400 pF max
Bus Free Time Between a STOP and
START Condition
tBUF
tHD, tSTA
tLOW
Hold Time (Repeated) START
condition
LOW Period of the SCL Clock
Standard mode
4.7
µs
Fast mode
1.3
µs
Fast mode plus
0.5
µs
Standard mode
4
µs
Fast mode
600
ns
Fast mode plus
260
ns
High-speed mode
160
ns
Standard mode
4.7
µs
Fast mode
1.3
µs
Fast mode plus
0.5
µs
High-speed mode, CB – 100 pF max
160
ns
High-speed mode, CB – 400 pF max
320
ns
Standard mode
tHIGH
HIGH Period of the SCL Clock
tSU, tSTA
Setup Time for a Repeated START
Condition
tSU, tDAT Data Setup Time
tHD, tDAT Data Hold Time
4
µs
Fast mode
600
ns
Fast mode plus
260
ns
High-speed mode, CB – 100 pF max
60
ns
High-speed mode, CB – 400 pF max
120
ns
Standard mode
4.7
µs
Fast mode
600
ns
Fast mode plus
260
ns
High-speed mode
160
ns
Standard mode
250
ns
Fast mode
100
ns
Fast mode plus
50
ns
High-speed mode
10
0
3.45
µs
Fast mode
0
0.9
µs
Fast mode plus
0
High-speed mode, CB – 100 pF max
0
High-speed mode, CB – 400 pF max
0
Standard mode
20 +
0.1 CB
Fast mode
tRCL
(1)
(2)
6
Rise Time of SCL Signal
ns
Standard mode
Fast mode plus
µs
70
ns
150
ns
1000
ns
300
ns
120
ns
High-speed mode, CB – 100 pF max
10
40
ns
High-speed mode, CB – 400 pF max
20
80
ns
All values referred to VIL MAX and VIH MIN levels in ELECTRICAL CHARACTERISTICS table.
For bus line loads CB between 100 pF and 400 pF, the timing parameters must be linearly interpolated.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
I2C InterfaceTiming Characteristics(1)(2) (continued)
PARAMETER
tRCL1
TEST CONDITIONS
Rise Time of SCL Signal After a
Repeated START Condition and After
an Acknowledge BIT
MIN
MAX
UNIT
Standard mode
20 +
0.1 CB
1000
ns
Fast mode
20 +
0.1 CB
300
ns
Fast mode plus
120
ns
10
80
ns
20
160
ns
20 +
0.1 CB
300
ns
Fast mode
300
ns
Fast mode plus
120
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
tFCL
Fall Time of SCL Signal
High-speed mode, CB – 100 pF max
10
40
ns
High-speed mode, CB – 400 pF max
20
80
ns
1000
ns
300
ns
Standard mode
20 +
0.1 CB
Fast mode
tRDA
Rise Time of SDA Signal
Fast mode plus
120
ns
High-speed mode, CB – 100 pF max
10
80
ns
High-speed mode, CB – 400 pF max
20
160
ns
300
ns
300
ns
120
ns
ns
Standard mode
20 +
0.1 CB
Fast mode
tFDA
Fall Time of SDA Signal
Fast mode plus
High-speed mode, CB – 100 pF max
10
80
High-speed mode, CB – 400 pF max
20
160
Standard mode
tSU, tSTO Setup Time of STOP Condition
CB
Capacitive Load for SDA and SCL
ns
4
µs
Fast mode
600
ns
Fast mode plus
260
ns
High-Speed mode
160
ns
Standard mode
400
pF
Fast mode
400
pF
Fast mode plus
550
pF
High-Speed mode
400
pF
7.7 I2C Timing Diagram
SDA
tf
tLOW
tr
tsu;DAT
tf
tBUF
tr
thd;STA
SCL
S
thd;STA
thd;DAT
tsu;STA
HIGH
tsu;STO
Sr
P
S
Figure 1. Serial Interface timing Diagram for Standard-, Fast- and Fast Plus-Mode
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
7
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
I2C Timing Diagram (continued)
Sr
Sr P
tfDA
trDA
SDAH
thd;DAT
thd;STA
tsu;STA
tsu;STO
tsu;DAT
SCLH
tfCL
trCL1
See Note A
trCL1
trCL
tHIGH
tLOW
tLOW
tHIGH
See Note A
= MCS Current Source Pull-Up
= R(P) Resistor Pull-Up
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
Figure 2. Serial Interface Timing Diagram for H/S-Mode
7.8 Typical Characteristics
30
TJ
TJ
TJ
TJ
=
=
=
=
-40 °C
25 °C
85 °C
125 °C
20
10
0
2.4
2.8
3.2
3.6
4.0
4.4
Input Voltage (V)
4.8
5.2
5.6
TJ
TJ
TJ
TJ
=
=
=
=
-40 °C
25 °C
85 °C
125 °C
20
10
0
2.4
2.8
3.2
D002
Figure 3. High-Side FET On-Resistance
8
On-Resistance (m:)
On-Resistance (m:)
30
3.6
4.0
4.4
Input Voltage (V)
4.8
5.2
5.6
D003
Figure 4. Low-Side FET On-Resistance
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
Typical Characteristics (continued)
0.15
7.0
$
5.0
6KXWGRZQ &XUUHQW
4XLHVFHQW &XUUHQW
$
6.0
4.0
3.0
2.0
1.0
0.0
2.4
TJ
TJ
TJ
TJ
2.8
=
=
=
=
-40 °C
25 °C
85 °C
125 °C
3.2
0.10
0.05
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
3.6
4.0
4.4
Input Voltage (V)
4.8
5.2
5.6
0.00
2.4
2.8
3.2
D000
Figure 5. Quiescent Current
3.6
4.0
4.4
Input Voltage (V)
4.8
5.2
Product Folder Links: TPS62864 TPS62866
D001
Figure 6. Shutdown Current
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
5.6
9
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
8 Detailed Description
8.1 Overview
The TPS62864/6 synchronous step-down converter uses the DCS-Control (Direct Control with Seamless
transition into Power Save Mode) topology. This is an advanced regulation topology that combines the
advantages of hysteretic and current-mode control schemes.
The DCS-Control™ topology operates in PWM (pulse width modulation) mode for medium to heavy load
conditions and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal
switching frequency of 2.4 MHz, having a controlled frequency variation over the input voltage range. Because
DCS-Control supports both operation modes (PWM and PFM) within a single building block, the transition from
PWM mode to Power Save Mode is seamless and without effects on the output voltage. The devices offer both
excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple.
8.2 Functional Block Diagram
VIN
EN
Control Logic
Reference Selection
UVLO
Thermal Shutdown
Startup Ramp
VSET/VID
or
VSET/PG
SDA
I2C Interface
SCL
VIN
VPG_H
VFB
VPG_L
+
±
+
±
PG
HS-FET
Forward Current Limit
VSW
TON
VIN
VSW
HICCUP (1)
Direct Control
&
Compensation
Modulator
VREF
VOS
+
_EA
SW
Gate
Drive
Comparator
LS-FET
Forward Current Limit
Zero Current Detect
Negative Current Limit
RDIS(1)
PGND
AGND
(1) enabled via I2C
PGND
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device enters Power Save Mode (PSM) operation. PSM occurs when the
inductor current becomes discontinuous, which is when it reaches 0 A during a switching cycle. Power Save
Mode is based on a fixed on-time architecture, as shown in Equation 1.
tON
VOUT
VIN
˜ 416ns
(1)
In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitor or inductor value.
10
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
Feature Description (continued)
8.3.2 Forced PWM Mode
Via I2C, set the device in forced PWM (FPWM) mode by the CONTROL register. The device switches at 2.4
MHz, even with a light load. This reduces the output voltage ripple and allows simple filtering of the switching
frequency for noise-sensitive applications. Efficiency at light load is lower in FPWM mode.
8.3.3 Startup
After enabling the device, there is an enable delay (tDelay) before the device starts switching. During this period,
the device sets the internal reference voltage, and determines the startup output voltage via the resistor
connected to the VSET/VID or VSET/PG pin. After tdelay, all registers can be read and written by the I2C interface.
VIN
EN
VOUT
ttDelayt
ttRampt
ttStartupt
Figure 7. Startup Sequence
After the enable delay, an internal soft startup circuitry ramps up the output voltage with a period of 1 ms (tRamp).
This avoids excessive inrush current and creates a smooth output voltage rising-slope. It also prevents excessive
voltage drops of primary cells and rechargeable batteries with high internal impedance.
The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the
output voltage to its nominal value.
8.3.4 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, cycle by cycle, the highside MOSFET is turned off and the low-side MOSFET is turned on, while the inductor current ramps down to the
low-side MOSFET current limit.
When the high-side MOSFET current limit is triggered 32 times, the device stops switching. The device then
automatically re-starts, with an internal soft startup, after a typical delay time of 128 µs has passed. This is
named HICCUP short-circuit protection. The device repeats this mode until the high load condition disappears.
The HICCUP is disabled by the CONTROL register bit Enable HICCUP. Disabling HICCUP changes the over
current protection to latching protection. The device stops switching after the high-side MOSFET current limit is
triggered 32 times. Toggling the EN pin, removing and reapplying the input voltage, or writing to the CONTROL
register bit Software Enable Device unlatch the device.
8.3.5 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, under voltage lockout (UVLO) is implemented when
the input voltage is lower than VUVLO. The device stops switching and the output voltage discharge is active (if
enabled via I2C) when the device is in UVLO. When the input voltage recovers, the device automatically returns
to operation with an internal soft startup. During UVLO, the internal register values are kept.
The UVLO bit in the STATUS Register is set when the input voltage is less than the UVLO falling threshold.
When the input voltage is below 1.8 V (typ), all registers are reset, except for the Enable Output Discharge bit.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
11
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
Feature Description (continued)
8.3.6 Thermal Warning and Shutdown
When the junction temperature goes up to TJW, the device gives a pre-warning indicator in the STATUS register.
The device keeps running.
When the junction temperature exceeds TJSD, the device goes into thermal shutdown, stops switching, and
actives the output voltage discharge. When the device temperature falls below the threshold by 20°C, the device
returns to normal operation automatically with an internal soft startup. During thermal shutdown, the internal
register values are kept.
8.4 Device Functional Modes
8.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic High. In shutdown mode (EN = Low), the internal power
switches as well as the entire control circuitry are turned off, and all the registers are reset, except for the Enable
Output Discharge bit. Do not leave the EN pin floating.
In shutdown mode (EN = Low), all registers can not be read and written by the I2C interface.
The typical threshold value of the EN pin is 0.89 V for rising input signals, and 0.62 V for falling input signals.
The device is also enabled or disabled by setting the bit, Software Enable Device in CONTROL register while EN
= High. After being disabled/enabled by this bit, the device stops switching and has a new startup beginning with
tRamp. There is no TDelay time and the registers are not reset.
8.4.2 Output Discharge
An internal MOSFET switch smoothly discharges the output through the VOS pin in shutdown mode (EN = Low
or Software Enable Device bit = 0). The output discharge is also active when the device is in thermal shutdown
and UVLO.
When the Enable Output Discharge bit is set to 0, the output discharge function is disabled. The input voltage
must remain higher than 1 V (TYP) in order to keep the output discharge function operational and the Enable
Output Discharge bit's status retained. The Enable Output Discharge bit is reset on the rising edge of the EN pin.
8.4.3 Startup Output Voltage and I2C Slave Address Selection (VSET)
During the enable delay (tDelay), the startup output voltage and device I2C slave address are set by an external
resistor connected to the VSET/VID or VSET/PG pin, via an internal R2D (resistor to digital) converter. Table 1
shows the options.
Table 1. Startup Output Voltage and I2C Slave Address Options
12
Resistor (E96 Series, ±1% Accuracy) at
VSET/VID or VSET/PG pin
Startup Output Voltage (TYP)
I2C Slave Address
249 kΩ
1.15 V
1000 110
205 kΩ
1.10 V
1000 101
162 kΩ
1.05 V
1000 100
133 kΩ
1.00 V
1000 011
105 kΩ
0.95 V
1000 010
86.6 kΩ
0.90 V
1000 001
68.1 kΩ
0.85 V
1001 000
56.2 kΩ
0.80 V
1001 001
44.2 kΩ
0.75 V
1001 010
36.5 kΩ
0.70 V
1001 011
28.7 kΩ
0.65 V
1001 100
23.7 kΩ
0.60 V
1001 101
18.7 kΩ
0.55 V
1001 110
15.4 kΩ
0.50 V
1001 111
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
Device Functional Modes (continued)
Table 1. Startup Output Voltage and I2C Slave Address Options (continued)
Resistor (E96 Series, ±1% Accuracy) at
VSET/VID or VSET/PG pin
Startup Output Voltage (TYP)
I2C Slave Address
12.1 kΩ
0.45 V
1000 000
10 kΩ
0.40 V
1000 111
The R2D converter has an internal current source which applies current through the external resistor, and an
internal ADC which reads back the resulting voltage level. Depending on the level, the correct startup output
voltage and I2C slave address are set. Once this R2D conversion is finished, the current source is turned off to
avoid current flowing through the external resistor. Ensure that there is no additional current path or capacitance
greater than 30pF from this pin to GND during R2D conversion. Otherwise a false value is set.
For the fixed startup output voltage versions, shown in Figure 8, the external resistor only sets the I2C slave
address by the options shown in Table 2.
VIN
2.4 V to 5.5 V
TPS6286612
VIN
C1
2x10 µF
I2C
L1
0.24 µH
SW
C2
2x22 µF
VOS
EN
SCL VSET/VID
SDA
AGND
VOUT
1.2 V
R1
PGND
Figure 8. Fixed Startup Output Voltage Application Circuit
Table 2. I2C Slave Address for the Fixed Startup Output Voltage
Resistor (E96 Series, ±1% Accuracy) at
VSET/VID pin
Fixed Startup Output Voltage (TYP)
I2C Slave Address
249 kΩ
1000 110
205 kΩ
1000 101
162 kΩ
1000 100
133 kΩ
1000 011
105 kΩ
1000 010
86.6 kΩ
1000 001
68.1 kΩ
1001 000
56.2 kΩ
44.2 kΩ
1.2 V - TPS6286612
1001 001
1001 010
36.5 kΩ
1001 011
28.7 kΩ
1001 100
23.7 kΩ
1001 101
18.7 kΩ
1001 110
15.4 kΩ
1001 111
12.1 kΩ
1000 000
10 kΩ
1000 111
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
13
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
During the ramp up period (tRamp), the output voltage ramps to the target value set by VSET first, then ramps up
or down to the new value when the output register's value is changed by I2C interface commands.
8.4.4 Select Output Voltage Registers (VID)
After the startup period (tStartup), the output voltage can be selected between two output voltage registers by the
VID pin. When VID is pulled low, the output voltage is set by Table 5. When VID is pulled high, the output voltage
is set by Table 6. This is also called dynamic voltage scaling (DVS).
During an output voltage change via I2C or the VSET/VID pin, the device can be set in FPWM by the Enable
FPWM Mode during Output Voltage Change bit in CONTROL register. The output voltage change speed is set
by the Voltage Ramp Speed bit.
8.4.5 Power Good (PG)
TPS62864/6 family provides device options with the VSET/PG pin, instead of a VSET/VID pin, shown in
Figure 16.
After the enable delay (tDelay), the device starts to compare the output voltage with the nominal value set by the
external resistor or the output voltage registers. Table 3 shows the logic level of the PG pin. The pin is driven up
to the input voltage for a logic high. The pin is pulled down to GND by the external resistor R1 for a logic low.
For the VSET/PG option devices, be aware of the following.
• VSET/PG can not be connected to GND. A resistor, R1, must be connected between VSET/PG and GND, for
the startup output voltage and I2C slave address setup.
• The source current of the VSET/PG pin is up to 1mA.
• VOUT Register 2 is disabled.
• When the device is in shutdown, the shutdown current is high because of the leakage current through the
external resistor, R1, when the VSET/PG pin is high.
The VSET/PG has a deglitch time, before the signal goes high or low, during normal operation. For startup, the
VSET/PG has a delay time of 200 µs after the output voltage reaches the nominal voltage.
Table 3. VSET/PG Pin Logic
DEVICE CONDITIONS
PG LOGIC STATUS
HIGH
LOW
0.91 x VOUT_NOM ≤ VVOS ≤ 1.11 x VOUT_NOM
Enable
√
VVOS < 0.91 x VOUT_NOM or VVOS > 1.11 x VOUT_NOM
√
Shutdown
EN = Low
√
Thermal Shutdown
TJ > TJSD
√
UVLO
1.8 V < VIN < VUVLO
√
Power Supply
Removal
VIN < 1.8 V
undefined
8.5 Programming
8.5.1 Serial Interface Description
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors. The bus
consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and
SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device.
14
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
Programming (continued)
The device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps) and fast mode (400 kbps), fast mode plus (1 Mbps) and high-speed
mode (3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as the input voltage remains above 1.8V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/Smode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HSmode.
It is recommended that the I2C master initiates a STOP condition on the I2C bus after the initial power up of SDA
and SCL pull-up voltages to ensure reset of the I2C engine.
8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 9. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 9. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 10). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 11) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
Figure 10. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 9). This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
15
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
Programming (continued)
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Figure 11. Acknowledge on the I2C Bus
Figure 12. Bus Protocol
8.5.3 HS-Mode Protocol
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
8.5.4 I2C Update Sequence
The sequence requires a start condition, a valid I2C slave address, a register address byte, and a data byte for a
single update. After the receipt of each byte, device acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I2C address selects the device. The device performs an update on the
falling edge of the acknowledge signal that follows the LSB byte.
16
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
Programming (continued)
1
7
1
1
8
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A/A
P
³0´ :ULWH
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
From Master to Slave
From Slave to Master
Figure 13. : “Write” Data Transfer Format in Standard-, Fast, Fast-Plus Modes
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
³0´ :ULWH
³1´ 5HDG
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
From Master to Slave
From Slave to Master
Figure 14. “Read” Data Transfer Format in Standard-, Fast, Fast-Plus Modes
F/S Mode
HS Mode
F/S Mode
1
8
1
1
7
1
1
8
1
8
1
1
S
HS-Master Code
A
Sr
Slave Address
R/W
A
Register Address
A
Data
A/A
P
(n x Bytes + Acknowledge)
HS Mode continues
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
From Master to Slave
From Slave to Master
Sr
Slave Address
Figure 15. Data Transfer Format in HS-Mode
8.5.5 I2C Register Reset
The I2C registers can be reset by:
• pulling the input voltage below 1.8 V (typ).
• or a high to low transition on EN. The previous "Enable Output Discharge" bit's value is latched until the next
EN rising edge or pulling the input voltage below 1.0 V (typ).
• or setting the Reset bit in the CONTROL register. When Reset is set to 1, all registers are reset to the default
values and a new startup is begun immediately. After tDelay, the I2C registers can be programmed again.
8.6 Register Map
Table 4. Register Map
Register Address (Hex)
Register Name
Factory Default (Hex)
Description
0x01
VOUT Register 1
0x64
Sets the target output voltage
0x02
VOUT Register 2
0x64
Sets the target output voltage
0x03
CONTROL Register
0x6F
Sets miscellaneous configuration bits
0x05
STATUS Register
0x00
Returns status flags
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
17
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
8.6.1 Slave Address Byte
7
6
5
4
3
2
1
0
1
x
x
x
x
x
x
R/W
The slave address byte is the first byte received following the START condition from the master device. The
slave addresses can be assigned by an external resistor, see Table 1.
8.6.2 Register Address Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master will send a byte to the device,
which will contain the address of the register to be accessed.
8.6.3 VOUT Register 1
Table 5. VOUT Register 1 Description
Register Address 0x01 Read/Write
Bit
Field
7:0
VO1_SET
Output Voltage (TYP) (1)
Value (Hex)
0x00
400 mV
0x01
405 mV
...
0x64
900 mV
...
(1)
0xFE
1670 mV
0xFF
1675 mV
It is not recommended to use the following codes, as their output voltage accuracy may have a wider tolerance than the specification:
0x20 (560 mV), 0x40 (720 mV), 0x60 (880 mV), 0x80 (1040 mV), 0xC4 (1360 mV), 0xE0 (1520 mV).
8.6.4 VOUT Register 2
Table 6. VOUT Register 2 Description
Register Address 0x02 Read/Write
Bit
Field
7:0
VO2_SET
Output Voltage (TYP) (1)
Value (Hex)
0x00
400 mV
0x01
405 mV
...
0x64
900 mV (default value)
...
(1)
0xFE
1670 mV
0xFF
1675 mV
It is not recommended to use the following codes, as their output voltage accuracy may have a wider tolerance than the specification:
0x20 (560 mV), 0x40 (720 mV), 0x60 (880 mV), 0x80 (1040 mV), 0xC4 (1360 mV), 0xE0 (1520 mV).
8.6.5 CONTROL Register
Table 7. CONTROL Register Description
Register Address 0x03 Write Only
18
Bit
Field
Type
Default
7
Reset
R/W
0
Description
1 - Reset all registers to default.
6
Enable FPWM Mode during Output
Voltage Change
R/W
1
0 - Keep the current mode status during output voltage change
1 - Force the device in FPWM during output voltage change
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
Table 7. CONTROL Register Description (continued)
Register Address 0x03 Write Only
Bit
Field
Type
Default
5
Software Enable Device
R/W
1
0 - Disable the device. All registers values are still kept.
1 - Re-enable the device with a new startup without the tDelay
period.
4
Enable FPWM Mode
R/W
0
0 - set the device in power save mode at light loads.
1 - set the device in forced PWM mode at light loads.
3
Enable Output Discharge
R/W
1
0 - Disable output discharge
1 - Enable output discharge
2
Enable HICCUP
R/W
1
0 - Disable HICCUP. Enable latching protection.
1 - Enable HICCUP, Disable latching protection.
Voltage Ramp Speed
R/W
11
00
01
10
11
0:1
Description
- 20mV/µs (0.25 µs/step)
- 10 mV/µs (0.5 µs/step)
- 5 mV/µs (1 µs/step)
- 1 mV/µs (5 µs/step, default)
8.6.6 STATUS Register
Table 8. STATUS Register Description
Register Address 0x05 Read Only
(1)
Bit
Field
7:5
Reserved
(1)
Type
Default
Description
4
Thermal Warning
R
0
1: Junction temperature is higher than 130°C
3
HICCUP
R
0
1: Device has HICCUP status once
2
Reserved
1
Reserved
0
UVLO
R
0
1: The input voltage is less than UVLO threshold (falling edge)
All bit values are latched until the device is reset, or the STATUS register is read. Then, the STATUS register is reset to its default
values.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
19
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Applications
9.2.1 6-A Output Current Application
TPS6286x
VIN
2.4 V to 5.5 V
VIN
C1
2x10 µF
I2C
L1
0.24 µH
SW
C2
2x22 µF
VOS
EN
VSET/VID
SCL
or
SDA VSET/PG
AGND
VOUT
0.9 V
R1
PGND
Figure 16. Typical Application
9.2.1.1
Design Requirements
For this design example, use the parameters listed in Table 9 as the input parameters.
Table 9. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.4 V to 5.5 V
Output voltage
0.9 V
Maximum output current
6A
Table 10 lists the components used for the example.
Table 10. List of Components of Figure 16
REFERENCE
(1)
MANUFACTURER (1)
DESCRIPTION
Samsung ElectroMechanics
C1
10 µF, Ceramic capacitor, 6.3 V, X7R, size 0603, CL10B106MQ8NRNC
C2
22 µF, Ceramic capacitor, 6.3V, X7R, size 0805, GRM21BZ70J226ME44L
Murata
L1
0.22 µH, Power inductor, XAL4020-221ME (12A, 5.81mΩ)
Coilcraft
R1
Depending on the startup output voltage, size 0603
Std
See Third-party Products disclaimer.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62866 device with the WEBENCH® Power Designer.
20
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Setting The Output Voltage
The initial output voltage is set by an external resistor connected to the VSET/VID or VSET/PG pin, according to
Table 1. After the soft startup, the output voltage can be changed in the VOUT Registers. Please refer to Table 5
and Table 6.
9.2.1.2.3 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify this process, Table 11
outlines possible inductor and capacitor value combinations for most applications. Checked cells represent
combinations that are proven for stability by simulation and lab test. Further combinations should be checked for
each individual application.
Table 11. Matrix of Output Capacitor and Inductor Combinations
NOMINAL L [µH] (1)
NOMINAL COUT [µF] (2)
22
0.24
(1)
(2)
(3)
2 x 22 or 47
+
(3)
3 x 22
150
+
+
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –30%.
This LC combination is the standard value and recommended for most applications.
9.2.1.2.4 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 2 is given.
DI
IL,MAX = IOUT,MAX + L
2
VOUT
VIN
DIL = VOUT ´
L ´ fSW
1-
where
•
•
•
•
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
(2)
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate
inductor. Table 12 lists recommended inductors.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
21
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
Table 12. List of Recommended Inductors (1)
Inductance
[µH]
Current Rating, ISAT
[A]
Dimensions
[L x W x H mm]
DC Resistance [mΩ]
Part Number
0.22
18.7
4x4x2
5.81
Coilcraft, XAL4020-221ME
0.24
6.6
2 x 1.6 x 1.2
13
Murata, DFE201612E-R24M
(1)
See Third-party Products disclaimer.
9.2.1.2.5 Capacitor Selection
The input capacitor is the low-impedance energy source for the converter which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and must be placed between
VIN and PGND as close as possible to those pins. For most applications, 8 μF is a sufficient value for the
effective input capacitance, though a larger value reduces input current ripple.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended minimum output effective capacitance is 30 μF; this
capacitance can vary over a wide range as outline in the output filter selection table.
9.2.1.3 Application Curves
VIN = 5.0 V, VOUT = 0.9 V, TA = 25 ºC, BOM = Table 10, unless otherwise noted.
90
0.612
85
80
0.606
70
Vout (V)
Efficiency (%)
75
65
60
VIN
VIN
VIN
VIN
VIN
VIN
55
50
45
40
100P
=
=
=
=
=
=
3.3V,
3.3V,
4.2V,
4.2V,
5.0V,
5.0V,
1m
VOUT = 0.6 V
PSM
PWM
PSM
PWM
PSM
PWM
0.600
VIN
VIN
VIN
VIN
VIN
VIN
0.594
10m
100m
Load (A)
1
0.588
100P
6
D005
=
=
=
=
=
=
3.3V,
3.3V,
4.2V,
4.2V,
5.0V,
5.0V,
1m
10m
100m
Load (A)
VOUT = 0.6 V
Power Save Mode
PSM
PWM
PSM
PWM
PSM
PWM
1
6
D008
Power Save Mode
Figure 18. Load Regulation
Figure 17. Efficiency
95
0.918
90
0.909
85
75
Vout (V)
Efficiency (%)
80
70
65
VIN
VIN
VIN
VIN
VIN
VIN
60
55
50
45
100P
=
=
=
=
=
=
3.3V,
3.3V,
4.2V,
4.2V,
5.0V,
5.0V,
1m
PSM
PWM
PSM
PWM
PSM
PWM
0.900
0.891
VIN
VIN
VIN
VIN
VIN
VIN
0.882
10m
100m
Load (A)
1
6
D006
VOUT = 0.9 V
0.873
100P
=
=
=
=
=
=
3.3V,
3.3V,
4.2V,
4.2V,
5.0V,
5.0V,
1m
10m
100m
Load (A)
1
6
D009
VOUT = 0.9 V
Figure 19. Efficiency
22
PSM
PWM
PSM
PWM
PSM
PWM
Submit Documentation Feedback
Figure 20. Load Regulation
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
VIN = 5.0 V, VOUT = 0.9 V, TA = 25 ºC, BOM = Table 10, unless otherwise noted.
95
1.212
90
85
1.200
75
Vout (V)
Efficiency (%)
80
70
65
VIN
VIN
VIN
VIN
VIN
VIN
60
55
50
45
100P
=
=
=
=
=
=
3.3V,
3.3V,
4.2V,
4.2V,
5.0V,
5.0V,
1m
PSM
PWM
PSM
PWM
PSM
PWM
VIN
VIN
VIN
VIN
VIN
VIN
1.176
10m
100m
Load (A)
VOUT = 1.2 V
1.188
1
1.164
100P
6
D007
=
=
=
=
=
=
3.3V,
3.3V,
4.2V,
4.2V,
5.0V,
5.0V,
1m
Switching Frequency (MHz)
Switching Frequency (MHz)
D010
3.0
2.0
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
1.0
=
=
=
=
=
=
0.6V,
0.6V,
0.9V,
0.9V,
1.2V,
1.2V,
PSM
FPWM
PSM
FPWM
PSM
FPWM
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Load (A)
D017
2.0
1.0
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
0.0
2.4
VIN = 5.0 V
2.8 3 3.2
6
6
5
5
Output Current (A)
7
4
3
2
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
65
VOUT = 0.9 V
4.8
5.2
5.6
D018
Figure 24. Switching Frequency
7
55
3.6
4.0
4.4
Input Voltage (V)
IOUT = 1.0 A
Figure 23. Switching Frequency
Output Current (A)
6
Figure 22. Load Regulation
3.0
0
45
1
Power Save Mode
Figure 21. Efficiency
1
10m
100m
Load (A)
VOUT = 1.2 V
Power Save Mode
PSM
PWM
PSM
PWM
PSM
PWM
4
3
2
1
75
85
95
105
Ambient Temperature (°C)
θJA = 56.5 °C/W
115
125
0
45
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
55
65
D019
VOUT = 1.675 V
Figure 25. Thermal Derating
75
85
95
105
Ambient Temperature (°C)
115
Product Folder Links: TPS62864 TPS62866
D020
θJA = 56.5 °C/W
Figure 26. Thermal Derating
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
125
23
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
VIN = 5.0 V, VOUT = 0.9 V, TA = 25 ºC, BOM = Table 10, unless otherwise noted.
VSW
5V/DIV
VSW
5V/DIV
VOUT
5mV/DIV
AC
VOUT
10mV/DIV
AC
ICOIL
1A/DIV
9A Offset
ICOIL
1A/DIV
Time - 200ns/DIV
7LPH
V ',9
D030
D031
IOUT = 6.0 A
IOUT = 0.1 A
Figure 27. PWM Operation
Figure 28. PSM Operation
VEN
2V/DIV
VSW
5V/DIV
_
VPG
5V/DIV
VOUT
10mV/DIV
AC
VOUT
0.5V/DIV
ICOIL
1A/DIV
ICOIL
1A/DIV
7LPH
V ',9
Time - 0.5ms/DIV
D032
D033
IOUT = 0.1 A
No Load
Figure 29. Forced PWM Operation
Figure 30. Startup and Shutdown by EN Pin
VSDA
2V/DIV
VVID
2V/DIV
_
VPG
5V/DIV
VOUT
0.5V/DIV
VOUT
100mV/DIV
AC
ICOIL
1A/DIV
7LPH
Time - 0.2ms/DIV
D034
No Load
Figure 31. Startup by Software Enable Device Bit
24
V ',9
D035
IOUT = 1 A
VOUT = 0.9 V to 1.1 V
Figure 32. VOUT Transition with Different Slew Rate
Settings
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
VIN = 5.0 V, VOUT = 0.9 V, TA = 25 ºC, BOM = Table 10, unless otherwise noted.
ILOAD
2A/DIV
ILOAD
2A/DIV
VOUT
50mV/DIV
AC
VOUT
50mV/DIV
AC
7LPH
V ',9
7LPH
V ',9
D036
IOUT = 0.05 A to 4 A
D037
PSM
IOUT = 0.05 A to 4 A
Figure 33. Load Transient
Forced PWM
Figure 34. Load Transient
_
VPG
5V/DIV
VOUT
0.5V/DIV
ICOIL
5A/DIV
Time - 0.2ms/DIV
D038
IOUT = 2.5 A
TPS62866
Figure 35. HICCUP Protection
9.2.2 Smaller Application Solution
VIN
2.4 V to 5.5 V
TPS6286x
VIN
C1
22 µF
I2C
L1
0.24 µH
SW
C2
2x22 µF
VOS
EN
VSET/VID
SCL
or
SDA VSET/PG
AGND
VOUT
0.9 V
R1
PGND
Figure 36. Smaller Application
9.2.2.1 Design Requirements
For this design, use the parameters listed in Table 13 as the input parameters. And the design (Table 14) is
optimized for the smallest solution size.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
25
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
Table 13. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.3 V
Output voltage
0.9 V
Maximum output current
4A
Ambient temperature
25 °C
Table 14. List of Components of Table 13
REFERENCE
C1, C2
(1)
MANUFACTURER (1)
DESCRIPTION
22 µF, Ceramic capacitor, 6.3 V, X5R, size 0402, GRM155R60J226ME11
Murata
L1
0.24 µH, Power inductor, size 0806, DFE201612E-R24M
Murata
R1
Depending on the startup output voltage, size 0402
Std
See Third-party Products disclaimer.
9.2.2.2 Application Curves
VIN = 5.0 V, VOUT = 0.9 V, TA = 25 ºC, BOM = Table 14, unless otherwise noted.
95
90
85
Efficiency (%)
80
75
70
65
60
55
50
45
100P
VIN = 3.3V, PSM
VIN = 4.2V, PSM
VIN = 5.0V, PSM
1m
10m
Load (A)
100m
1
4
D011
VOUT = 0.9 V
Figure 37. Efficiency
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application. The power supply should avoid a fast ramp down.
The falling ramp speed must be slower than 10 mV/µs, if the input voltage drops below VUVLO.
11 Layout
11.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the device.
• The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
• The low side of the input and output capacitors must be connected properly to the PGND to avoid a GND
potential shift.
• The sense traces connected to the VOS pin is a signal trace. Special care should be taken to avoid noise
being induced. Keep the trace away from SW.
• Refer to Figure 38 for an example of component placement, routing and thermal design.
26
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
11.2 Layout Example
GND
VIN
VOUT
Figure 38. Layout Example
11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are improving the power dissipation capability of the
PCB design and introducing airflow in the system. For more details on how to use the thermal parameters, see
Semiconductor and IC Package Thermal Metrics.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
27
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• Semiconductor and IC Package Thermal Metrics
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
PACKAGE OUTLINE
YCG0015
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.28
0.23
C
0.5 MAX
SEATING PLANE
BALL TYP
0.16
0.10
0.05 C
0.7 TYP
SYMM
E
D
1.4
TYP
SYMM
D: Max=1.8mm, Min=1.76mm
C
E: Max=1.07mm, Min=1.03mm
0.35
TYP
B
A
2
15X
0.015
0.225
0.185
C A B
3
0.35 TYP
4224261/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
29
TPS62864, TPS62866
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
EXAMPLE BOARD LAYOUT
YCG0015
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
15X ( 0.2)
1
3
2
A
(0.35) TYP
B
SYMM
C
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.0325 MAX
0.0325 MIN
METAL UNDER
SOLDER MASK
( 0.2)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
( 0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224261/B 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
30
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
TPS62864, TPS62866
www.ti.com
SLVSEI1A – JUNE 2019 – REVISED DECEMBER 2019
EXAMPLE STENCIL DESIGN
YCG0015
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
(R0.05) TYP
15X ( 0.21)
1
2
3
A
(0.35) TYP
B
SYMM
C
METAL
TYP
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4224261/B 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS62864 TPS62866
31
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS628640AYCGR
PREVIEW
DSBGA
YCG
15
3000
TBD
Call TI
Call TI
-40 to 125
8640A
TPS628660AYCGR
PREVIEW
DSBGA
YCG
15
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
8660A
TPS6286612YCGR
PREVIEW
DSBGA
YCG
15
3000
TBD
Call TI
Call TI
-40 to 125
86612
XPS628660AYCGR
ACTIVE
DSBGA
YCG
15
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
X660A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising