Texas Instruments | TPS63810 and TPS63811 – 2.5-A Buck-Boost Converters with I2C Interface (Rev. B) | Datasheet | Texas Instruments TPS63810 and TPS63811 – 2.5-A Buck-Boost Converters with I2C Interface (Rev. B) Datasheet

Texas Instruments TPS63810 and TPS63811 – 2.5-A Buck-Boost Converters with I2C Interface (Rev. B) Datasheet
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TPS63810, TPS63811
SLVSEK4B – JULY 2019 – REVISED NOVEMBER 2019
TPS63810 and TPS63811 – 2.5-A Buck-Boost Converters with I2C Interface
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
Input voltage range: 2.2 V to 5.5 V
Output voltage range: 1.8 V to 5.2 V
– I2C-configurable during operation and
shutdown
– VSEL pin to toggle between two output voltage
presets
Output current
– Up to 2.5 A for VI ≥ 2.5 V, VO = 3.3 V
– Up to 2.5 A for VI ≥ 2.8 V, VO = 3.5 V
High efficiency over entire load range
– Low 13-μA operating quiescent current
– Automatic power save mode and forced PWM
mode (I2C-configurable)
Peak current mode buck-boost architecture
– Defined transitions between buck, buck-boost
and boost operation
– Forward and reverse current operation
– Start-up into pre-biased outputs
Safety and robust operation features
– Integrated soft start
– Overtemperature and overvoltage protection
– True load disconnect during shutdown
– Forward and backward current limit
Two device options:
– TPS63810: Pre-programmed output voltages
(3.3 V, 3.45 V)
– TPS63811: Program output voltages prior to
start-up
Solution size of < 20 mm2 with only four external
components
System pre-regulator (smartphone, tablet, tracking
and telematics, EPOS, TWS earphones, medical
hearing aids)
Point-of-load regulation (Time-of-Flight camera
sensors, port/cable adapter and dongle)
Thermoelectric device supply (TEC, optical
modules)
Broadband network radio or SoC supply (IoT,
home automation, EPOS)
•
•
•
3 Description
The TPS63810 and TPS63811 are high efficiency,
high output current buck-boost converters fully
programmable through I2C. Depending on the input
voltage, they automatically operate in boost, buck or
in a novel 4-cycle buck-boost mode when the input
voltage is approximately equal to the output voltage.
The transitions between modes happen at defined
thresholds and avoid unwanted toggling within the
modes to reduce output voltage ripple.
Two registers, accessible through I2C, set the output
voltage, and a VSEL pin selects which output voltage
register is active. Thus the devices can support
dynamic voltage scaling. If the output voltage register
is changed during operation or the VSEL pin is
toggled, the device transits in a defined,
programmable ramp-rate.
Device Information(1)
PART NUMBER
TPS63810
TPS63811
PACKAGE
BODY SIZE (NOM)
DSBGA (15)
2.3 mm × 1.4 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Efficiency versus Output Current
0.47 µH
100
90
LX1
VIN
LX2
VOUT
EN
10 µF
2 × 22 µF
TPS63810 /
TPS63811
SCL
SDA
GND
VSEL
AGND
80
VO
3.3 V
70
Efficiency (%)
VI
2.2 V to 5.5 V
60
50
40
30
20
VI = 3.6 V
10 TA = 25°C
Power-save mode enabled
0
0.01
0.1
Output Current (A)
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
1
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS63810, TPS63811
SLVSEK4B – JULY 2019 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
6
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 17
8.6 Register Map........................................................... 21
9
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Applications ............................................... 25
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 34
12 Device and Documentation Support ................. 35
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Glossary ................................................................
35
35
35
35
35
35
35
13 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2019) to Revision B
•
Page
Changed product status from Advance Information to Production Data ............................................................................... 1
5 Device Comparison Table
2
PART NUMBER
OUTPUT START-UP STATE
OUTPUT VOLTAGE
TPS63810
Enabled
VSEL = Low: 3.3 V
VSEL = High: 3.45 V
TPS63811
Disabled
Programmable at start-up
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SLVSEK4B – JULY 2019 – REVISED NOVEMBER 2019
6 Pin Configuration and Functions
YFF Package
15-Ball DSBGA
Top View
1
2
3
A
EN
VIN
VIN
B
VSEL
LX1
LX1
C
AGND
GND
GND
D
SCL
LX2
LX2
E
SDA
VOUT
VOUT
Not to scale
BGA Package (YFF) Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
Device enable. A high logic level on this pin enables the device; a low logic level on this pin
disables the device.
A1
EN
I
A2
VIN
—
Supply voltage for power stage
A3
VIN
—
Supply voltage for power stage
B1
VSEL
I
B2
LX1
—
Inductor connection
B3
LX1
—
Inductor connection
C1
AGND
—
Analog ground
C2
GND
—
Power ground
C3
GND
—
Power ground
D1
SCL
I/O
I2C serial interface clock. Pull this pin up to the I2C bus voltage with a resistor or a current source.
D2
LX2
—
Inductor connection
This pin selects which VOUT register is active. When a low logic level is applied to this pin, the
VOUT1 register sets the output voltage. When a high logic level is applied to this pin, the VOUT2
register sets the output voltage.
D3
LX2
—
Inductor connection
E1
SDA
I/O
I2C serial interface data. Pull this pin up to the I2C bus voltage with a resistor or a current source.
E2
VOUT
—
Converter output
E3
VOUT
—
Converter output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
Input voltage (VIN, LX1, LX2, VOUT, SCL, SDA, EN, VSEL) (2)
VI
MAX
6
(2)
UNIT
V
–3
9
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Input voltage for less than 10 ns (LX1, LX2)
MIN
–0.3
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal, unless otherwise noted.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VI
Supply voltage
NOM
MAX
2.2
5.5
Low range
1.8
4.975
High range
2.025
5.2
UNIT
V
VO
Output voltage
VIH
High-level input voltage
SCL, SDA, VSEL
1.3
VI
V
VIL
Low-level input voltage
SCL, SDA, VSEL
0
0.3
V
V(EN)
Input voltage
EN
0
VI
V
VO = 3.3 V, VI ≥ 2.5 V
IO
Output current (1)
2.5
VO = 3.5 V, VI ≥ 2.5 V
2
VO = 3.5 V, VI ≥ 2.8 V
2.5
VO = 3.3 V, VI ≥ 3 V
(2)
CI
Input capacitance
CO
Output capacitance (2)
L
5
µF
16
Inductance
390
470
TA
Operating free-air temperature range
TJ
Operating junction temperature range
(2)
4
A
3
13
(1)
V
µF
560
nH
–40
85
°C
–40
125
°C
The device can sustain the maximum recommended output current only for short durations before its junction temperature gets too hot.
Users must verify that the thermal performance of the end application can support the maximum output current.
Effective capacitance after DC bias effects have been considered.
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7.4 Thermal Information
TPS63810,
TPS63811
THERMAL METRIC (1)
UNIT
YFF (DSBGA)
15 PINS
RθJA
Junction-to-ambient thermal resistance
80.5
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
0.6
°C/W
Junction-to-board thermal resistance
20.5
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
20.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted). Typical values
are at VI = 3.6 V, VO = 3.3 V and TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Supply current into VIN
VI = 3.6 V, VO = 3.3 V, V(EN) = 3.6 V,
not switching, TJ = 25°C
13
µA
Supply current into VIN
VI = 3.6 V, VO = 0 V, V(EN) = 3.6 V, Output
disabled with ENABLE bit in Control
Register
TJ = 25°C
15
µA
ISD
Shutdown current into VIN
VI = 3.6 V, VO = 0 V, V(EN) = 0 V
TJ = 25°C
0.35
µA
VIT+
Positive-going UVLO threshold voltage
Vhys
UVLO threshold voltage hysteresis
IQ;VIN
2
2.1
2.2
200
V
mV
I/O SIGNALS
VIT+
VIT–
Vhys
Positive-going input
threshold voltage
Negative-going input
threshold voltage
SCL, SDA,
VSEL
1.2
EN
1.07
SCL, SDA,
VSEL
1.1
1.13
1
1.03
0.4
EN
0.97
V
V
Hysteresis voltage
EN
IIH
High-level input current
SCL, SDA,
VSEL
V(SCL) = V(SDA) = V(VSEL) = 1.8 V,
no pullup resistor
40
mV
±0.01
±0.1
µA
IIL
Low-level input current
SCL, SDA,
VSEL
V(SCL) = V(SDA) = V(VSEL) = 0 V,
no pullup resistor
±0.01
±0.1
µA
IOL
Low-level output current
SCL, SDA
VOL = 0.4 V
IIB
Input bias current
EN
V(EN) = 0 V to 5.5 V
±0.01
±0.1
20
mA
µA
POWER STAGE
VO
Output voltage range
Output voltage accuracy
Default output voltage (RANGE = 0)
Switch current limit
IT–(PSM)
PSM entry threshold (peak) current
Low range
1.8
4.975
High range
2.025
5.2
PWM operation
–1.5
1.5
PSM operation
–1.5
3.5
VSEL = low
3.3
VSEL = high
3.45
VI = 2.9 V, VO = 3.6 V,
boost operation, output sourcing current
5.2
VI = 4.1 V, VO = 3.3 V,
buck operation, output sourcing current
3.8
VI = 5 V, VO = 3.3 V,
reverse-boost operation, output sinking
current
–1.3
VI = 4.2 V; VO = 3.3 V
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%
V
6.5
4.3
5.2
A
–0.35
0.85
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A
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Electrical Characteristics (continued)
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted). Typical values
are at VI = 3.6 V, VO = 3.3 V and TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VI = 3.6 V, VO ≥ 0.8 V
Output discharge current
MIN
TYP
MAX
50
UNIT
mA
VT+(PG)
Positive-going power-good threshold
voltage
95
%
VT–(PG)
Negative-going power-good
threshold voltage
90
%
5.7
V
Positive-going input overvoltage threshold
Reverse current operation
I2C INTERFACE
7-Bit slave address
75h
THERMAL SHUTDOWN
Thermal shutdown threshold temperature
TJ rising
Thermal shutdown hysteresis
150
°C
20
°C
7.6 Timing Requirements
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted)
PARAMETER
fSCL
tLOW
tHIGH
tBUF
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
Bus free time between a STOP and
a START condition
Set-up time for a repeated START
condition
Hold time (repeated) START
condition
Data set-up time
Data hold time
TEST CONDITIONS
MIN
Rise time of both SDA and SCL
signals
100
Fast mode
0
400
Fast mode plus
0
1000
Standard mode
4.7
Fast mode
1.3
Fast mode plus
0.5
Standard mode
4.0
Fast mode
0.26
Standard mode
4.7
Fast mode
1.3
Fast mode plus
0.5
Standard mode
4.7
Fast mode
0.26
Standard mode
4.0
Fast mode
0.26
Standard mode
250
Fast mode
100
Fast mode plus
50
Standard mode
0
Fast mode
0
Fast mode plus
0
Fast mode
tsu;STO
Set-up time for STOP condition
µs
ns
µs
300
300
20×VDD/5.5
300
Fast mode plus
20×VDD/5.5
120
Standard mode
4.0
Fast mode
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ns
120
Fast mode
Fast mode plus
6
µs
1000
20
Standard mode
Fall time of both SDA and SCL
signals
µs
0.6
Fast mode plus
kHz
µs
0.6
Fast mode plus
UNIT
µs
0.6
Fast mode plus
Fast mode plus
tf
MAX
0
Standard mode
tr
TYP
Standard mode
0.6
ns
µs
0.26
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Timing Requirements (continued)
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Standard mode
tVD;DAT
Data valid time
tVD;ACK
MAX
Fast mode
Data valid acknowledge time
Cb
Capacitive load for each bus line
tw(VSEL)
VSEL pulse duration
UNIT
3.45
0.9
Fast mode plus
0.45
Standard mode
3.45
Fast mode
µs
0.9
Fast mode plus
0.45
Standard mode
400
Fast mode
400
Fast mode plus
µs
550
VSEL = high or low
5
µs
7.7 Switching Characteristics
Over operating junction temperature range and recommended input voltage range (unless otherwise noted). Typical values
are at VI = 3.6 V, VO = 3.3 V, and TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
229
440
µs
td(EN)
Delay between a rising edge on the
EN pin and the start of the output
voltage ramp
TJ = 25°C, VI = 3.6 V
td(PG)
Power-good delay
VO falling
50
SLEW = 00b, forced-PWM operation
±1
SLEW = 01b, forced-PWM operation
±2.5
SLEW = 10b, forced-PWM operation
±5
SLEW = 11b, forced-PWM operation
±10
Inductor Switching Frequency, Boost
Mode
VI = 2.3 V, VO = 3.3 V, no Load, PWM
operation
2.6
MHz
Inductor Switching Frequency, BuckBoost Mode
VI = 3.3 V, VO = 3.3 V, no Load, PWM
operation
1.6
MHz
Inductor Switching Frequency, Buck
Mode
VI = 4.3 V, VO = 3.3 V, no Load, PWM
operation
2.0
MHz
Delay between rising edge of VSEL and
start of DVS ramp
Measured from rising edge of VSEL to
start of ramp.
Slew rate of internal ramp during dynamic
voltage scaling
SR
fSW
td(VSEL)
µs
V/ms
5
µs
7.8 Typical Characteristics
1.2
20
1
Shutdown Current (mA)
Quiescent Current (PA)
18
VI = 2.2 V
VI = 3.6 V
VI = 5.5 V
16
14
12
10
8
-40
VI = 2.2 V
VI = 3.6 V
VI = 5.5 V
0.8
0.6
0.4
0.2
0
-20
MODE = LOW
0
20
40
60
80
Temperature (qC)
100
120
VO = 3.3 V
IO = 0 mA, not
switching
Figure 1. Quiescent Current versus Temperature
140
-0.2
-40
-20
0
20
40
60
80
Temperatur (qC)
100
120
140
EN = LOW
Figure 2. Shutdown Current versus Temperature
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8 Detailed Description
8.1 Overview
The TPS63810 and TPS63811 devices are high-efficiency buck-boost converters. Each device uses four
switches to maintain synchronous power conversion under all operating conditions, so that the device achieves
high efficiency power conversion over a wide range of input voltages and output currents. The device
automatically switches between buck, boost, and buck-boost operation as required by the operating conditions.
The device operates as a true buck converter when VI > VO and as a true boost converter when VI < VO. When
VI ≈ VO, the device operates in a 4-cycle buck-boost mode. The RMS current through the switches and the
inductor is thus kept to a minimum, minimizing switching and conduction losses. Controlling the switches this way
lets the converter achieve high efficiency over the whole input voltage range.
8.2 Functional Block Diagram
LX1
LX2
Q1
VIN
Q4
VOUT
ISNS
Gate
Drivers
Q2
Gate
Drivers
Q3
PGND
Overvoltage
Protection
VSEL
Control Logic
EN
SCL
Output
Discharge
Interface
Control
SDA
+
ISNS
±
±
Current
Comparator
Error +
Amplifier
AGND
Vref
Clamp
8.3 Feature Description
8.3.1 Control Scheme
The device automatically selects the best switching scheme for the operating conditions. To make sure of stable
operation, the selection logic includes hysteresis (see Figure 3).
Boost
Buck-Boost
VI < VO
Buck
VI § 9O
Hysteresis
V I > VO
Hysteresis
Figure 3. Switching Scheme Selection
8
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Feature Description (continued)
8.3.1.1 Buck Operation
When VI > VO, the device switches like a buck converter:
• Q1 is the switch.
• Q2 is the rectifier.
• Q3 is permanently off.
• Q4 is permanently on.
See Figure 4. During buck operation, one switching cycle comprises two phases: on–off.
I(SNS)
L
Q1
CI
Q2
Q4
Q3
CO
On phase
Off phase
Figure 4. Buck Switch Configuration
8.3.1.2 Boost Operation
When VI < VO, the device switches like a boost converter:
• Q1 is permanently on.
• Q2 is permanently off.
• Q3 is the switch.
• Q4 is the rectifier.
See Figure 5. During boost operation, one switching cycle comprises two phases: on–off.
I(SNS)
Q1
CI
L
Q2
Q4
Q3
CO
On phase
Off phase
Figure 5. Boost Switch Configuration
8.3.1.3 Buck-Boost Operation
When VI ≈ VO, all four transistors switch continuously (see Figure 6). During buck-boost operation, one switching
cycle comprises four phases: on–commutate–off–commutate.
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Feature Description (continued)
I(SNS)
Q1
L
CI
Q2
Q4
Q3
CO
On phase
Off phase
Commutate phase
Figure 6. Buck-Boost Switch Configuration
8.3.2 Control Scheme
The device uses a constant off-time, peak-current-mode control scheme where an outer voltage control loop
generates the demand signal for an inner current control loop. During the on-time, the inner current control loop
monitors the inductor current, and when the inductor current equals the demand signal from the error amplifier,
the on-time stops and the next part of the switching cycle starts.
The off-time is a function of VI and VO and the operating mode (buck, boost, or buck-boost) of the converter.
Inductor
Current
Peak inductor current
during the on time
Off phase
On phase
0
Time
Figure 7. Peak Current Control (Buck and Boost Operation)
Inductor
Current
Peak inductor current
during the on time
Commutate
phase
Off phase
Commutate
phase
On phase
0
Time
Figure 8. Peak Current Control – Buck-Boost Operation with VI < VO
10
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Feature Description (continued)
Inductor
Current
Peak inductor current
during the on time
Commutate
phase
Off phase
Commutate
phase
On phase
0
Time
Figure 9. Peak Current Control – Buck-Boost Operation with VI > VO
Inductor
Current
Peak inductor current
during the on time
Commutate
phase
Off phase
Commutate
phase
On phase
0
Time
Figure 10. Peak Current Control – Buck-Boost Operation with VI = VO
During PWM operation, current can flow in the reverse direction (from output to input). In this case, the error
amplifier provides a negative peak current target. Note that the average reverse current is greater (more
negative) than the peak current (see Figure 11 and Figure 12).
Inductor
Current
Time
0
Peak inductor current
during the on time
Off phase
On phase
Average inductor current
Figure 11. Reverse Peak Current Control – Buck and Boost Operation
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Feature Description (continued)
Inductor
Current
Time
0
Commutate
phase
Off phase
Commutate
phase
On phase
Peak inductor current
during the on time
Average inductor current
Figure 12. Reverse Peak Current Control – Buck-Boost Operation, with VI > VO
8.3.3 Power-Save Mode Operation (PSM)
To increase efficiency across a wide range of operating conditions, the device automatically changes from pulsewidth modulation (PWM) at medium and high output currents to pulse-frequency modulation (PFM) at low output
currents.
• During PWM operation, the device switches continuously and adjusts the duty cycle of each switching cycle
to regulate the output voltage.
• During PFM operation, the device switches in bursts of a few switching cycles, separated by periods when the
device does not switch (see Figure 13). PFM operation increases efficiency at low output currents because
when the device does not switch, there are no switching losses and most of the internal circuitry is disabled,
which reduces quiescent power consumption. A comparator with hysteresis compares the output voltage of
the error amplifier to a predefined PFM threshold voltage. When the output voltage of the error amplifier is
greater than the burst threshold voltage, the device starts switching. When the output voltage of the error
amplifier is less than the burst threshold voltage, the device stops switching. This scheme automatically
adjusts the frequency and the duration of the switching bursts to regulate the output voltage. During PFM
operation, the output voltage ripple can be higher and the transient response is not as good as during PWM
operation (see Table 1).
To enable power-save mode, clear the FPWM bit in the Control register to 0.
Converter
output voltage
Output voltage ripple
Burst start threshold
Error amplifier
output voltage
Burst stop threshold
Inductor
current
tBurst
tdurationt
Time
tBurst periodt
Figure 13. Pulse-Frequency Modulation
WHITESPACE
12
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Table 1. Forced-PWM versus Power-Save Mode
Performance Comparison
PERFORMANCE PARAMETER
BEST OPERATING MODE
Low-power efficiency
Power-Save Mode (PSM)
Medium- and high-power efficiency
No difference
DC Output voltage accuracy
Forced-PWM
Transient response
Forced-PWM
Output voltage ripple
Forced-PWM
WHITESPACE
8.3.4 Forced-PWM Operation (FPWM)
During forced-PWM operation, the device uses PWM for all operating conditions. Forced-PWM operation has
lower output voltage ripple and better transient response than power-save mode operation, but lower efficiency at
low output currents (see Table 1).
Note that the device inhibits forced-PWM operation during start-up (that is, until the converter output has reached
power-good for the first time).
To enable forced-PWM operation, set the FPWM bit in the Control register to 1.
8.3.5 Ramp-PWM Operation (RPWM)
If Ramp-PWM operation is enabled, the device operates in forced-PWM when it ramps from one output voltage
to another during dynamic voltage scaling. This function is useful if you want the device to operate in power-save
mode, but you want to make sure that dynamic voltage scaling ramps the output voltage up and down in a
controlled way. If the device operates in power-save mode and Ramp-PWM is disabled, the device cannot
always control the ramp from a higher output voltage to a lower output voltage, because in power-save mode the
device cannot sink current (see Figure 14).
To enable Ramp-PWM operation, set the RAMP bit in the Control register to 1. To disable Ramp-PWM
operation, clear the RAMP bit in the Control register to 0.
VO(2)
Forced-PWM /
Ramp-PWM
VO(1)
VO(2)
Power-Save
Mode
VO(1)
Figure 14. Ramp-PWM Operation
8.3.6 Device Enable (EN)
The EN pin enables and disables the device.
• When the EN pin is high, the device is enabled.
• When the EN pin is low, the device is disabled.
You can also use the ENABLE bit in the Control register to enable and disable the output of the converter (see
the Register Map).
Table 2. Device Enable Truth Table
ENABLE PIN (EN)
ENABLE BIT
DEVICE STATE
OUTPUT STATE
0
X
Device in Shutdown
Output Discharge Active
1
0
Programming Interface Active
Output Disabled (Hi-Z)
1
1
Device Active
Output Enabled
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8.3.7 Undervoltage Lockout (UVLO)
The device has an undervoltage lockout function that disables the device when the supply voltage is too low for
correct operation.
8.3.8 Soft Start
To minimize inrush current and output voltage overshoot during start-up, the device has a soft-start function. At
turn on, the switch current limit ramps gradually to its maximum value and the device starts up in a controlled
way. The gradual increase of the current limit generates the smallest inrush current for no-load conditions. It is
also possible to start into a high load as long as the load does not exceed the device current limit.
The rise time of the output voltage changes with the application circuit and the operating conditions. The output
voltage rise time increases if the following occurs:
• The output capacitance is large.
• The load current is large.
• The device operates in boost mode.
See the Application and Implementation section for output voltage rise times in a typical application.
WHITESPACE
EN
VIT
ttr(SS)t
Peak Inductor
Current Limit
max
ttd(EN)t
min
0
Inductor
Current
Output
Voltage
Figure 15. Device Start-Up
8.3.9 Output Voltage Control
The device can generate output voltages from 1.8 V to 5.2 V with a resolution of 25 mV. To set the output
voltage, you must first program the RANGE bit in the Control register to select the output voltage range:
• When RANGE = 0, you can program the output voltage from 1.8 V to 4.975 V.
• When RANGE = 1, you can program the output voltage from 2.025 V to 5.2 V.
WHITESPACE
When you have selected the output voltage range, you can program the VOUT1 register and VOUT2 register to
set the output voltage:
• When RANGE = 0, VO = (VOUT[6:0] × 0.025) + 1.8 V
• When RANGE = 1, VO = (VOUT[6:0] × 0.025) + 2.025 V
VOUT[6:0] is the 7-bit value in the VOUT1 register or VOUT2 register, whichever is active.
WHITESPACE
The VSEL pin selects which VOUT register is active:
• When VSEL = low, the VOUT1 register sets the output voltage.
• When VSEL = high, the VOUT2 register sets the output voltage.
WHITESPACE
14
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NOTE
To prevent output voltage transients, TI recommends that you do not change the output
voltage range while the converter is in operation. Instead, clear the ENABLE bit in the
Control register to 0 to disable the DC/DC converter before you change the RANGE bit.
8.3.9.1 Dynamic Voltage Scaling
The device has a dynamic voltage scaling (DVS) function which lets you change the output voltage in a
controlled way during operation. Figure 16 shows a simplified block diagram of the DVS function. The VSEL pin
controls a multiplexer which selects either the VOUT1 register or the VOUT2 register to control the set voltage.
The ramp control block detects when the target output voltage is different from the actual output voltage and
ramps the output voltage to the target voltage in 25-mV steps. You can use the 2-bit SLEW parameter in the
Control register to select one of four slew rates from 0.5 V/ms to 10 V/ms.
The device starts a DVS ramp when you change the logic level on the VSEL pin or program to a new value in
the active VOUT register.
WHITESPACE
0
VOUT1[6:0]
MUX
VOUT[6:0]
Ramp
Control
VSET[6:0]
To rest of
converter
1
VOUT2[6:0]
VSEL
SLEW[1:0]
Figure 16. Dynamic Voltage Scaling Block Diagram
Note that if you change the contents of the active VOUT register or change the state of the VSEL pin during
start-up (that is, before the end of the soft start), the converter uses the new value immediately and does not
ramp gradually to the final value.
Figure 17 shows the timing diagram when you use the VSEL pin to change between the output voltage values in
the VOUT1 and VOUT2 registers.
WHITESPACE
td(VSEL)
td(VSEL)
VSEL
tr
tf
VO(2)
VO
VO(1)
tr = tf =
+VO(1) ± VO(2) +
SR
Where
ƒ
VO(1) is the output voltage set by the VOUT1 register
ƒ
VO(2) is the output voltage set by the VOUT2 register
ƒ
SR is the slew rate set by the SLEW bits in the CONTROL register
Figure 17. DVS Timing Diagram Using the VSEL Pin
WHITESPACE
Figure 18 shows the timing diagram when you use the I2C interface to change the output voltage value in one of
the VOUT registers.
WHITESPACE
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VSEL
low
Write 30h
to VOUT1
I 2C
Write 20h
to VOUT1
tr
tf
3.0 V
VO
2.6 V
tr = tf =
3.0 ± 2.6
SR
Where SR is the slew rate set by the SLEW bits in the CONTROL register.
Figure 18. DVS Timing Using the I2C Interface
8.3.10 Protection Functions
8.3.10.1 Input Voltage Protection (IVP)
Under certain operating conditions, current can flow from the output of the device to the input. For example, this
can occur during dynamic voltage scaling when the output ramps down to a lower voltage and the VOUT pin
sinks current from the output capacitor. Under such conditions, if the voltage source supplying the device cannot
sink current, the voltage on the VIN pin can rise uncontrollably.
To make sure the input voltage stays within the permitted range, the device stops switching if the voltage on the
VIN pin is greater than 5.7 V. The device automatically starts to switch again when the voltage on the VIN pin is
less than 5.7 V.
The device sets the PG bit in the Status register when an input overvoltage event occurs. The device clears the
PG bit if the Status register is read when the power-not-good condition no longer exists.
8.3.10.2 Current Limit Mode and Overcurrent Protection
The device has a clamp circuit which limits the peak inductor current in the event of an overload. The exact value
of the output current during an overload changes with the operating conditions (VI and VO) and the switching
mode (buck, buck-boost, or boost) – see Figure 52.
Overloads increase the power dissipation in the device, which increases its temperature. If the device becomes
too hot, the thermal shutdown function turns off the converter. When the device cools down, the thermal
shutdown function automatically turns on the converter again. Thus, under a permanent overload condition, the
device can periodically turn on and off, as it cools down and then heats up.
8.3.10.3 Thermal Shutdown
The device has a thermal shutdown function which turns off the converter if the junction temperature is greater
than 150°C. The device automatically turns on the converter again when the junction temperature is less than
130°C. You can still use the I2C interface to read and write to the registers when the device is in an
overtemperature condition.
When the device detects an overtemperature condition, it sets the TSD bit in the Status register to 1. The device
clears the TSD bit to 0 if you read the Status register when the junction temperature of the device is less than
130°C.
8.3.11 Power Good
The device has a power-good function which indicates if the output of the DC/DC converter is in regulation or
not. The device detects a power-good condition when the output voltage is greater than 95% of its nominal value
and detects a power-not-good condition when the output voltage is less than 90% of its nominal value.
When a power-not-good condition occurs, the device sets the PG bit in the Status register to 1. The device clears
the PG bit to 0 if you read the Status register when a power-good condition exists.
16
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8.3.12 Load Disconnect
During device shutdown, the input is disconnected from the output. This prevents any current flow from the
output to the input or from the input to the output.
8.3.13 Output Discharge
The device actively discharges the output when the EN pin is low.
8.4 Device Functional Modes
The device has two functional modes: off and on. The device enters the on mode when the voltage on the VIN
pin is higher than the UVLO threshold and a high logic level is applied to the EN pin. The device enters the off
mode when the voltage on the VIN pin is lower than the UVLO threshold or a low logic level is applied to the EN
pin.
on
VI > VIT+ &&
EN pin = high
VI < VIT± ||
EN pin = low
off
Figure 19. Device Functional Modes
8.5 Programming
8.5.1 Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see NXP
Semiconductors, UM10204 – I2C-Bus Specification and User Manual ). The bus consists of a data line (SDA)
and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All
the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA, and SCL. A master device,
usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating
the SCL signal and device addresses. The master also generates specific conditions that indicate the START
and STOP of data transfer. A slave device receives and transmits data on the bus under control of the master
device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification:
• Standard-mode (100 kbps)
• Fast-mode (400 kbps)
• Fast-mode Plus (1 Mbps)
The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new
values, depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.1 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore, it is referred to as F/Smode in this document. The device supports 7-bit addressing; 10-bit addressing and general call address are not
supported. The device 7-bit address is 75h (1110101b).
To make sure that the I2C function in the device is correctly reset, it is recommended that the I2C master initiates
a STOP condition on the I2C bus after the initial power up of SDA and SCL pullup voltages.
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Programming (continued)
8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
The master initiates a data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 20. All I2C-compatible devices recognize
a start condition.
DATA
CLK
S
P
START
Condition
STOP
Condition
Figure 20. START and STOP Conditions
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit, R/W,
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 21). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 22) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data line stable;
data valid
Change of
data allowed
Figure 21. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 20). This releases the bus and stops the communication link with the
addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
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Programming (continued)
Data Output by
Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL from
Master
1
2
8
9
S
Clock pulse for
acknowledgment
START
Condition
Figure 22. Acknowledge on the I2C Bus
P
SDA
acknowledgement
signal from slave
MSB
acknowledgement
signal from receiver
Sr
SCL
S
or
Sr
1
2
START or
repeated START
condition
7
8
9
1
2
3 to 8
ACK
byte complete,
interrupt within slave
9
ACK
clock line held low while
interrupts are serviced
Sr
or
P
STOP or
repeated START
condition
Figure 23. Bus Protocol
8.5.3 I2C Update Sequence
A
•
•
•
•
single update requires the following:
A start condition
A valid I2C slave address
A register address
A data byte
To acknowledge the receipt of each byte, the device pulls the SDA line low during the high period of a single
clock pulse. The device performs an update on the falling edge of the acknowledge signal that follows the last
byte.
WHITESPACE
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Programming (continued)
1
7
1
1
8
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A/A
P
From master to slave
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
From slave to master
Figure 24. “Write” Data Transfer Format in Standard, Fast, and Fast-Plus Modes
1
7
1
1
8
1
1
8
1
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A/A
P
"0" Write
"1" Read
From master to slave
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
From slave to master
Figure 25. “Read” Data Transfer Format in Standard, Fast, and Fast-Plus Modes
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8.6 Register Map
8.6.1 Register Description
8.6.1.1 Register Map
ADDRESS
ACRONYM
REGISTER NAME
SECTION
0x01
CONTROL
Control Register
Go
0x02
STATUS
Status Register
Go
0x03
DEVID
DEVID Register
Go
0x04
VOUT1
VOUT1 Register
Go
0x05
VOUT2
VOUT2 Register
Go
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8.6.1.2 Register CONTROL (Slave address: 0b1110101; Register address: 0x01; Default: 0x00 or 0x20)
Return to Register Map.
Figure 26. Register CONTROL Format
7
RESERVED
R/W
6
RANGE
R/W
5
ENABLE
R/W
4
RESERVED
R/W
3
FPWM
R/W
2
RPWM
R/W
1
0
SLEW[1:0]
R/W
LEGEND: R/W = Read/Write; R = Read only
Table 3. Register CONTROL Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
Reserved for future use.
This bit can be written to and read from but it has no function. For compatibility with
possible future device variants, it is recommended to program this bit to 0.
6
RANGE
R/W
0
This bit selects the output voltage range.
0: Low range (1.800 V to 4.975 V)
1 : High range (2.025 V to 5.200 V)
5
ENABLE
R/W
X
This bit controls operation of the converter.
0 : Converter operation disabled (TPS63811)
1 : Converter operation enabled (TPS63810)
4
RESERVED
R/W
0
Reserved for future use.
This bit can be written to and read from but it has no function. For compatibility with
possible future device variants, it is recommended to program this bit to 0.
3
FPWM
R/W
0
This bit controls the forced-PWM function.
0: Forced-PWM operation disabled
1 : Forced-PWM operation enabled
2
RPWM
R/W
0
This bit controls the ramp-PWM function.
0: Ramp-PWM operation disabled
1 : Ramp-PWM operation enabled
1:0
SLEW[1:0]
R/W
00
These bits control the slew rate of the DVS function.
00: 1.0 V/ms
01: 2.5 V/ms
10: 5.0 V/ms
11: 10.0 V/ms
8.6.1.3 Register STATUS (Slave address: 0b1110101; Register address: 0x02; Default: 0x00)
Return to Register Map.
Figure 27. Register STATUS Format
7
6
5
4
3
2
NIL[5:0]
R
1
TSD
R
0
PGn
R
LEGEND: R/W = Read/Write; R = Read only
Table 4. Register STATUS Field Descriptions
Bit
Field
Type
Reset
Description
7:2
NIL[5:0]
R
000000
Not used.
These bits always return 0 when read.
1
TSD
R
0
This bit shows the status of the thermal shutdown function.
This bit is cleared if the STATUS register is read when the overtemperature condition
no longer exists.
0: Temperature good
1 : An overtemperature event was detected.
0
PGn
R
0
This bit shows the status of the power-good comparator.
This bit is cleared if the STATUS register is read when the power-not-good condition no
longer exists.
0: Power-good
1 : A power-not-good event was detected.
22
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8.6.1.4 Register DEVID (Slave address: 0b1110101; Register address: 0x03; Default: 0x04)
Return to Register Map.
Figure 28. Register DEVID Format
7
6
5
MANUFACTURER[3:0]
R
4
3
2
1
MAJOR[1:0]
R
0
MINOR[1:0]
R
LEGEND: R/W = Read/Write; R = Read only
Table 5. Register DEVID Field Descriptions
Bit
Field
Reset
Description
7:4
MANUFACTURER[3:0] R
Type
0000
These bits identify the device manufacturer.
0000: Texas Instruments
3:2
MAJOR[1:0]
R
01
These bits identify the major silicon revision.
00: A (initial silicon)
01: B (first major revision)
10: C (second major revision)
11: D (third major revision)
1:0
MINOR[1:0]
R
00
These bits identify the minor silicon revision.
00: 0 (initial silicon)
01: 1 (first minor revision)
10: 2 (second minor revision)
11: 3 (third minor revision)
8.6.1.5 Register VOUT1 (Slave address: 0b1110101; Register address: 0x04; Default: 0x3C)
Return to Register Map.
Figure 29. Register VOUT1 Format
7
NIL
R
6
5
4
3
VOUT1[6:0]
R/W
2
1
0
LEGEND: R/W = Read/Write; R = Read only
Table 6. Register VOUT1 Field Descriptions
Bit
Field
Type
Reset
Description
7
NIL
R
0
Not used
This bit always returns 0 when read.
6:0
VOUT1[6:0]
R/W
0111100
These bits set the output voltage when the VSEL pin is low.
Output voltage = 1.800 + (VOUT1[6 :0] × 0.025) V (low range) (default = 3.3 V)
Output voltage = 2.025 + (VOUT1[6 :0] × 0.025) V (high range) (default = 3.525 V)
8.6.1.6 Register VOUT2 (Slave address: 0b1110101; Register address: 0x05; Default: 0x42)
Back to Register Map.
Figure 30. Register VOUT2 Format
7
NIL
R
6
5
4
3
VOUT2[6:0]
R/W
2
1
0
LEGEND: R/W = Read/Write; R = Read only
Table 7. Register VOUT2 Field Descriptions
Bit
Field
Type
Reset
Description
7
NIL
R
0
Not used
This bit always returns 0 when read.
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Table 7. Register VOUT2 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6:0
VOUT2[6:0]
R/W
1000010
These bits set the output voltage when the VSEL pin is high.
Output voltage = 1.800 + (VOUT2[6 :0] × 0.025) V (low range) (default = 3.45 V)
Output voltage = 2.025 + (VOUT2[6 :0] × 0.025) V (high range) (default = 3.675 V)
24
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS63810 and TPS63811 devices are high efficiency, high current buck-boost converters, suitable for
applications where the input voltage is higher, lower, or equal to the output voltage. The maximum peak current
in the switches is limited to a typical value of 6 A.
9.2 Typical Applications
9.2.1 1.8-V to 5.2-V Output Smartphone Power Supply
L1
0.47 µH
VI
2.5 V to 4.8 V
L1
VIN
VO
1.8 V to 5.2 V
L2
VOUT
EN
3.3 V
C1
10 µF
C2
22 µF
C3
22 µF
C4
22 µF
TPS63810 /
TPS63811
3.3 NŸ 3.3 NŸ
SCL
SDA
VSEL
To system
GND
AGND
Figure 31. Typical Application Schematic
9.2.1.1 Design Requirements
This example uses the design parameters listed in Table 8.
Table 8. Design Parameters
DESIGN PARAMETER
SYMBOL
EXAMPLE VALUE
Input voltage
VI
2.5 V to 4.8 V
Output voltage
VO
1.8 V to 5.2 V
Output current
IO
2A
I2C bus voltage
VBUS
3.3 V
I2C bus capacitance
Cb
100 pF
2
I C bus speed
Fast-mode (400 kHz)
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1
Input Capacitor Selection
TI recommends a minimum input capacitance (including DC bias effects) of 5 µF. A 10-µF, 10-V ceramic
capacitor is suitable for typical applications. If the input supply is located more than a few centimeters from the
converter, you may need to add additional bulk capacitance (a 47-µF electrolytic or tantalum capacitor is a typical
choice).
The output capacitance does not have an upper limit; you can make it as big as you want.
9.2.1.2.2 Inductor Selection
TI recommends you use the TPS63810 device with 0.47-µH inductors. For high efficiencies, use an inductor with
a low DC resistance (DCR) and low core losses.
The saturation current of the inductor must be greater than the maximum inductor current in your application. To
include sufficient margin for worst-case and transient operating conditions, TI recommends you use an inductor
with saturation current that is at least 20% higher than the maximum inductor current in your application. The
maximum current in the inductor occurs when the device operates in boost mode and the following is true:
• The input voltage is at its minimum value.
• The output voltage is at its maximum value.
• The output current is at its maximum value.
To calculate the maximum inductor current, first use Equation 1 to calculate the maximum duty cycle during
boost operation (which is when the maximum inductor current occurs).
WHITESPACE
VO ± VI
D=
VO
where
•
•
•
D is the duty cycle
VI is the input voltage
VO is the output voltage
(1)
WHITESPACE
5 V ± 2.5 V
D=
= 0.5
5V
WHITESPACE
Next, use Equation 2 to calculate the maximum inductor current.
IO
DVI
ILM =
+
:1 ± D; 2fL
where
•
•
•
•
•
•
•
ILM is the peak inductor current
IO is the output current
η is the converter efficiency (use the value from the application curves or assume 90%)
D is the duty cycle (calculated with Equation 1)
VI is the input voltage
f is the switching frequency (assume 2 MHz)
L is the inductance (use 0.47 µH)
(2)
WHITESPACE
ILM =
:0.5;:2.5 V;
2A
+
= 5.1 A
:0.9;:1 ± 0.5; :2;:2 MHz;:
H;
WHITESPACE
26
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To include enough margin for transient conditions, TI recommends you use an inductor with a saturation current
rating at least 20% higher than the calculated maximum current. In this example, TI recommends an inductor
with a saturation current of at least 6.1 A.
9.2.1.2.3
Output Capacitor Selection
TI recommends a minimum output capacitance (including DC bias effects) of 16 µF. Two 22-µF, 10-V ceramic
capacitors are suitable for typical applications with VO ≤ 3.6 V. For VO > 3.6 V, three 22-µF or two 47-µF ceramic
capacitors are suitable. If you want to minimize switching noise on the output, connect a small ceramic capacitor
(100 nF is a typical value) in parallel to the two main output capacitors and place it closest to the VOUT pin.
Smaller capacitors have lower parasitic inductance and are more effective at filtering high frequencies than the
two main output capacitors.
The output capacitance does not have an upper limit, however, very large values of output capacitance make the
transient response of the converter slower.
It is important that the effective capacitance is given according to the recommended value in Recommended
Operating Conditions. In general, consider DC bias effects resulting in less effective capacitance. The choice of
the output capacitance is mainly a trade-off between size and transient behavior as higher capacitance reduces
transient response overshoot and undershoot and increases transient response time. Table 9 lists possible
output capacitors.
Table 9. List of Recommended Capacitors (1)
CAPACITOR
[µF]
VOLTAGE RATING [V]
ESR [mΩ]
22
6.3
22
10
47
47
(1)
PART NUMBER
MANUFACTURER
SIZE
(METRIC)
10
GRM187R60J226ME15
Murata
0603 (1608)
40
GRM187R61A226ME15
Murata
0603 (1608)
6.3
43
GRM188R60J476ME15
Murata
0603 (1608)
6.3
43
GRM219R60J476ME44
Murata
0805 (2012)
See Third-party Products Disclaimer.
9.2.1.2.4 I2C Pullup Resistor Selection
Refer to the NXP Semiconductors, UM10204 – I2C-Bus Specification and User Manual for the specifications
relevant to your application.
Use Equation 3 to calculate the maximum permitted pullup resistor value for the bus speed used in the
application.
WHITESPACE
RP :max; =
tr
0.8473 × Cb
where
•
•
tr is the maximum permitted rise time (300 ns for Fast-mode)
Cb is the capacitive load on each bus line
(3)
WHITESPACE
RP :max; =
300 ns
= 3.541 k
0.8473 × 100 pF
WHITESPACE
If you do not know what the bus capacitance is in your application, start with a 1-kΩ pullup resistor and measure
the rise time with an oscilloscope. Use Equation 3 to calculate the bus capacitance and thus the maximum
permitted pullup resistor.
Use Equation 4 to calculate the minimum permitted pullup resistor value for different bus speeds.
WHITESPACE
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RP :min; =
www.ti.com
VBUS ± VOL
IOL
where
•
•
•
VBUS is the I2C bus pullup voltage
VOL is the low-level output voltage (0.4 V)
IOL is the low-level output current (3 mA for Fast-mode)
(4)
WHITESPACE
RP :min; =
3.3 V ± 0.4 V
= 967
3 mA
WHITESPACE
A pullup resistor value of 3.3 kΩ meets both of these requirements.
28
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9.2.1.3 Application Curves
Table 10 lists the components that were used for the measurements contained in the following pages.
Table 10. Components for Application Characteristic Curves
REFERENCE
DESCRIPTION
PART NUMBER
MANUFACTURER
C1
Capacitor, 10 µF, 10 V, 0603, ceramic
GRM188R61A106ME69
Murata
C2, C3
Capacitor, 22 µF, 10 V, 0603, ceramic
GRM187R61A226ME15
Murata
L1
Inductor, 0.47 µH
XFL4015-471MEC
Coilcraft
U1
Integrated circuit
TPS63810YFF
Texas Instruments
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100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
WHITESPACE
70
60
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
50
40
0.01
0.1
Output Current (A)
VI = 3.6 V
1
PSM
70
60
40
2.5
2.5
TA = 25°C
0.15
0.15
0
-0.15
-0.3
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-0.6
VI = 3.6 V
1
1.5
Output Current (A)
2
FPWM
TA = 25°C
2.5
Output Voltage Regulation (%)
Output Voltage Regulation (%)
0.3
0.5
3.5
4
4.5
Input Voltage (V)
PSM
5
5.5
TA = 25°C
Figure 33. Efficiency versus Input Voltage
0.3
0
3
IO = 1 A
Figure 32. Efficiency versus Output Current
-0.45
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
50
0
-0.15
-0.3
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-0.45
-0.6
2.5
3
IO = 1 A
3.5
4
4.5
Input Voltage (V)
FPWM
Figure 34. Load Regulation
5
5.5
TA = 25°C
Figure 35. Line Regulation
tV(LX1) (2 V/div)t
tV(LX1) (2 V/div)t
tV(LX2) (2 V/div)t
tV(LX2) (2 V/div)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 2 µs/divt
tTime = 2 µs/divt
VI = 5 V
VO = 3.3 V
PSM
IO = 100 mA
TA = 25°C
Figure 36. PFM Switching Waveforms
(Buck Operation)
30
VI = 3.3 V
VO = 3.3 V
PSM
IO = 100 mA
TA = 25°C
Figure 37. PFM Switching Waveforms
(Buck-Boost Operation)
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tV(LX1) (2 V/div)t
tV(LX1) (2 V/div)t
tV(LX2) (2 V/div)t
tV(LX2) (2 V/div)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 2 µs/divt
VI = 2.5 V
VO = 3.3 V
PSM
IO = 100 mA
tTime = 400 ns/divt
TA = 25°C
VI = 5 V
VO = 3.3 V
Figure 38. PFM Switching Waveforms
(Boost Operation)
FPWM
IO = 100 mA
TA = 25°C
Figure 39. PWM Switching Waveforms
(Buck Operation)
tV(LX1) (2 V/div)t
tV(LX1) (2 V/div)t
tV(LX2) (2 V/div)t
tV(LX2) (2 V/div)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 400 ns/divt
tTime = 400 ns/divt
VI = 3.3 V
VO = 3.3 V
FPWM
IO = 100 mA
TA = 25°C
Figure 40. PWM Switching Waveforms
(Buck-Boost Operation)
VI = 2.5 V
VO = 3.3 V
FPWM
IO = 100 mA
TA = 25°C
Figure 41. PWM Switching Waveforms
(Boost Operation)
tVO (200 mV/div, ac)t
tVO (200 mV/div, ac)t
tVI (2 V/div)t
tVI (2 V/div)t
tIL (2 A/div)t
tIL (2 A/div)t
tTime = 200 µs/divt
tTime = 200 µs/divt
VI = 2.5 V to 5.5 V
VO = 3.3 V
PSM
IO = 200 mA
TA = 25°C
Figure 42. Line Transient Response
VI = 2.5 V to 5.5 V
VO = 3.3 V
PSM
IO = 2 A
TA = 25°C
Figure 43. Line Transient Response
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tVO (200 mV/div, ac)t
tVO (200 mV/div, ac)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 200 µs/divt
VI = 4.2 V
VO = 3.3 V
PSM
IO = 10 mA to 2 A
tTime = 200 µs/divt
TA = 25°C
Figure 44. Load Transient Response (Buck)
VI = 3.3 V
VO = 3.3 V
PSM
IO = 10 mA to 2 A
TA = 25°C
Figure 45. Load Transient Response (Buck-Boost)
tVI (1 V/div, ac)t
tVO (200 mV/div, ac)t
tVO (1 V/div, ac)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 200 µs/divt
VI = 2.6 V
VO = 3.3 V
PSM
IO = 10 mA to 2 A
tTime = 200 µs/divt
TA = 25°C
VI = 3.3 V ±0.9 V
VO = 3.3 V
FPWM
RL = 3 Ω
Figure 46. Load Transient Response (Boost)
Figure 47. Line Sweep (PWM)
tVI (2 V/div)t
tVI (2 V/div)t
tVO (2 V/div)t
tVO (2 V/div)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 40 µs/divt
tTime = 40 µs/divt
VI = 3.6 V
VO = 3.3 V
PSM
RL = 33 Ω
TA = 25°C
Figure 48. Start-Up Waveforms
(Light Load)
32
TA = 25°C
VI = 3.6 V
VO = 3.3 V
PSM
RL = 3.3 Ω
TA = 25°C
Figure 49. Start-Up Waveforms
(Heavy Load)
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tVO (2 V/div)t
tVO (2 V/div)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 4 ms/divt
tTime = 4 ms/divt
VI = 3.6 V
VO = 2 V to 4 V
PSM
RL = 330 Ω
TA = 25°C
VI = 3.6 V
VO = 2 V to 4 V
Figure 50. Dynamic Voltage Scaling (PFM)
PSM
RPWM
TA = 25°C
RL = 330 Ω
Figure 51. Dynamic Voltage Scaling (RPWM)
3.5
Switching Frequency (MHz)
tIL (5 A/div)t
tIO (2 A/div)t
tVO (2 V/div, ac)t
3
2.5
2
1.5
1
2.5
tTime = 40 µs/divt
VI = 3.6 V
VO = 3.3 V
PSM
TA = 25°C
3.5
4
4.5
Input Voltage (V)
FPWM
5
5.5
TA = 25°C
Figure 53. Switching Frequency versus Input Voltage
0.5
6
Maximum Output Current (A)
PFM Burst Frequency (MHz)
3
IO = 1 A
VI rising
Figure 52. Overcurrent Protection
0.1
0.01
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
0.001
0.005
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
0.01
VI = 3.6 V
0.1
Output Current (A)
PSM
1
TA = 25°C
Figure 54. Burst Switching Frequency versus Output
Current
5
4
3
2
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
1
0
2.5
3
PSM
3.5
4
4.5
Input Voltage (V)
5
5.5
TA = 25°C
Figure 55. Maximum Output Current versus Input Voltage
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10 Power Supply Recommendations
The device is designed to operate with a DC supply voltage in the range 2.2 V to 5.5 V. If the input supply is
more than a few centimeters from the device, TI recommends adding some bulk capacitance to the ceramic
bypass capacitors. A 47-µF electrolytic capacitor is a typical selection for the bulk capacitance.
11 Layout
11.1 Layout Guidelines
Correct PCB layout is necessary to obtain the full performance from the device. TI recommends to follow these
basic principles:
• Place input and output capacitors close to the device to minimize the input and output loop areas.
• If you combine different-sized capacitors to make up the total input capacitance, place the smallest capacitor
closest to the device. The same applies to the output capacitance.
• Keep PCB traces short and wide to minimize parasitic resistance and inductance.
• Use the following PCB layer stack (or something similar):
– Layer 1 (top): All components and all power traces
– Layer 2 (inner): Signals
– Layer 3 (inner): Signals
– Layer 4 (bottom): Ground plane
Figure 56 shows an example of the PCB layout used for all of the measurement data in Application Curves.
11.2 Layout Example
Input
Capacitance
Output
Capacitance
TPS63810 /
TPS63811
Figure 56. Recommended PCB Layout for the TPS63810 Device
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• NXP Semiconductors, UM10204 – I2C-Bus Specification and User Manual
• Texas Instruments, TPS63810 EVM User Guide
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 11. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS63810
Click here
Click here
Click here
Click here
Click here
TPS63811
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Glossary
SLYZ022– TI Glossary
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS63810YFFR
ACTIVE
DSBGA
YFF
15
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS63810
TPS63811YFFR
ACTIVE
DSBGA
YFF
15
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS63811
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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15-Nov-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS63810YFFR
DSBGA
YFF
15
3000
180.0
8.4
TPS63811YFFR
DSBGA
YFF
15
3000
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.5
2.42
0.75
4.0
8.0
Q1
1.5
2.42
0.75
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS63810YFFR
DSBGA
YFF
15
3000
182.0
182.0
20.0
TPS63811YFFR
DSBGA
YFF
15
3000
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0015
DSBGA - 0.625 mm max height
SCALE 6.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.30
0.12
BALL TYP
0.05 C
0.8 TYP
SYMM
E
D
1.6
TYP
D: Max = 2.285 mm, Min =2.225 mm
SYMM
C
E: Max = 1.374 mm, Min =1.314 mm
B
0.4 TYP
A
15X
0.015
0.3
0.2
C A B
1
2
3
0.4
TYP
4219378/A 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
15X ( 0.23)
2
1
3
A
(0.4) TYP
B
SYMM
C
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
( 0.23)
METAL
SOLDER MASK
OPENING
0.05 MAX
EXPOSED
METAL
0.05 MIN
METAL UNDER
SOLDER MASK
EXPOSED
METAL
( 0.23)
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219378/A 04/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YFF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
15X ( 0.25)
1
2
3
A
(0.4) TYP
B
METAL
TYP
SYMM
C
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219378/A 04/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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