Texas Instruments | LMR33640 SIMPLE SWITCHER 3.8-V to 36-V, 4-A Synchronous Step-down Converter (Rev. A) | Datasheet | Texas Instruments LMR33640 SIMPLE SWITCHER 3.8-V to 36-V, 4-A Synchronous Step-down Converter (Rev. A) Datasheet

Texas Instruments LMR33640 SIMPLE SWITCHER 3.8-V to 36-V, 4-A Synchronous Step-down Converter (Rev. A) Datasheet
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LMR33640
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LMR33640 SIMPLE SWITCHER® 3.8-V to 36-V, 4-A Synchronous Step-down Converter
1 Features
3 Description
•
The LMR33640 SIMPLE SWITCHER® regulator is an
easy-to-use,
synchronous,
step-down
DC/DC
converter that delivers best-in-class efficiency for
rugged industrial applications. The LMR33640 drives
up to 4 A of load current from an input of up to 36 V.
The LMR33640 provides high light-load efficiency and
output accuracy. Features such as a power-good flag
and precision enable provide both flexible and easyto-use solutions for a wide range of applications. The
LMR33640 automatically folds back frequency at light
load to improve efficiency. Protection features include
thermal shutdown, input undervoltage lockout, cycleby-cycle current limit, and hiccup short-circuit
protection. Integration and internal compensation
eliminates many external components and provides a
pinout designed for a simple PCB layout. The feature
set of the device is designed to simplify
implementation for a wide range of end equipment.
The LMR33640 is pin-to-pin compatible with the
LMR33610, LMR33620, LMR33630 (36 V, 1 A/2, A/3
A), LMR36510 (65 V, 1 A), and LMR36520 (65 V, 2
A), completing the family of scalable SIMPLE
SWITCHER power supplies. This minimizes the cost
and effort associated with board layout modifications.
The LMR33640 is available in an 8-pin HSOIC
package.
1
•
•
•
•
Configured for rugged industrial applications
– Input voltage range: 3.8 V to 36 V
– Output voltage range: 1 V to 24 V
– Peak-current mode control
– Junction temperature range: –40°C to +125°C
– Ease-of-use SOIC package
Well-suited for scalable industrial power supplies
– Pin compatible with:
– LMR33610, LMR33620, and LMR33630
(36 V, 1 A, 2 A, or 3 A)
– LMR36510 and LMR36520
(65 V, 1 A, or 2 A)
– 400-kHz and 1-MHz frequency
– Integrated compensation helps reduce solution
size, cost, and design complexity
High-efficiency solution
– Peak efficiency > 95%
– Low shutdown quiescent current of 5 µA
– Low operating quiescent current of 24 µA
Flexible system interface
– Power-good flag and precision enable
Create a custom design using the LMR33640 with
the WEBENCH® Power Designer
•
•
PART NUMBER
LMR33640
2 Applications
•
Device Information(1)
Motor drive systems: drones, AC inverters,
VF drives, servos
Factory and building automation systems:
PLC, HMI, HVAC systems, elevator main control
panel
Wide VIN DC/DC power supply
PACKAGE
HSOIC (8)
BODY SIZE (NOM)
5.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Efficiency vs Output Current
VOUT = 5 V, 400 kHz, HSOIC
BOOT
VIN
100
VIN
CBOOT
CIN
EN
SW
L1
95
VOUT
90
COUT
PGND
PG
RFBT
CVCC
Efficiency (%)
VCC
85
80
75
70
65
FB
RFBB
8V
12V
24V
36V
60
AGND
55
50
0.001
0.01
0.1
Output Current (A)
1
5
eff_
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR33640
SNVSB99A – OCTOBER 2019 – REVISED OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Characteristics............................................... 8
System Characteristics ............................................. 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
9.3 What to Do and What Not to Do ............................. 28
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
34
34
34
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2019) to Revision A
•
2
Page
Changed product status from Advance Information to Production Data ................................................................................ 1
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5 Device Comparison Table
DEVICE OPTION
RATED CURRENT
LMR33640ADDA
4A
SWITCHING FREQUENCY
400 kHz
LMR33640DDDA
4A
1000 kHz
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6 Pin Configuration and Functions
DDA Package
8-Pin HSOIC with PowerPAD™
Top View
PGND
1
VIN
2
EN
3
PG
4
THERMAL
PAD
8
SW
7
BOOT
6
VCC
5
FB
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
PGND
1
G
Power ground terminal. Connect to system ground and AGND. Connect to bypass capacitor
with short wide traces.
VIN
2
P
Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this
pin and PGND.
EN
3
A
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; Do not
float.
PG
4
A
Open drain power-good flag output. Connect to suitable voltage supply through a current
limiting resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can be
left open when not used.
FB
5
A
Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not float. Do
not ground.
VCC
6
P
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external
loads. Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor
from this pin to PGND.
BOOT
7
P
Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor
from this pin to the SW pin.
SW
8
P
Regulator switch node. Connect to power inductor.
G
Analog ground for regulator and system. Ground reference for internal references and logic.
All electrical parameters are measured with respect to this pin. Connect to system ground on
PCB. For the HSOIC package, the pad on the bottom of the device serves as both the AGND
connection and a thermal connection to the heat sink ground plane. This pad must be
soldered to a ground plane to achieve good electrical and thermal performance.
AGND
THERMAL
PAD
A = Analog, P = Power, G = Ground
4
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range (1)
MIN
MAX
VIN to PGND
PARAMETER
–0.3
38
EN to AGND (2)
–0.3
VIN + 0.3
FB to AGND
–0.3
5.5
0
22
PG to AGND (2)
Voltages
AGND to PGND
–0.3
0.3
SW to PGND
–0.3
VIN + 0.3
SW to PGND less than 100-ns transients
–3.5
38
BOOT to SW
–0.3
5.5
UNIT
V
V
VCC to AGND (3)
–0.3
5.5
TJ
Junction temperature (4)
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V
Under some operating conditions the VCC LDO voltage may increase beyond 5.5V.
Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
7.2 ESD Ratings
VALUE
Human-body model (HBM)
V(ESD)
(1)
(2)
Electrostatic discharge
UNIT
(1)
Charged-device model (CDM)
±2500
V
(2)
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating temperature range of –40°C to 125°C (unless otherwise noted)
VIN to PGND
Input voltage
(2)
MIN
MAX
3.8
36
UNIT
0
VIN
PG (2)
0
18
Adjustable output voltage
VOUT (3)
1
24
V
Output current
IOUT
0
4
A
(1)
(2)
(3)
EN
(1)
V
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
The maximum output voltage can be extended to 95% of VIN; contact TI for details. Under no conditions should the output voltage be
allowed to fall below zero volts.
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7.4 Thermal Information
The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design
purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application. For design information, see Absolute Maximum Ratings.
LMR33640
THERMAL METRIC
(1) (2)
DDA (HSOIC)
UNIT
8 PINS
42.9 (2)
°C/W
54
°C/W
Junction-to-board thermal resistance
13.6
°C/W
ψJT
Junction-to-top characterization parameter
4.3
°C/W
ψJB
Junction-to-board characterization parameter
13.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.3
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These
values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application. For design information see the Absolute Maximum Ratings.
7.5 Electrical Characteristics
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN
= 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VIN
Minimum operating input
voltage
IQ
Non-switching input current;
measured at VIN pin (1)
VFB = 1.2 V
ISD
Shutdown quiescent current;
measured at VIN pin
EN = 0
VEN-VCC-H
EN input level required to turn
on internal LDO
Rising threshold
VEN-VCC-L
EN input level required to turn
off internal LDO
Falling threshold
0.3
VEN-H
EN input level required to
start switching
Rising threshold
1.2
VEN-HYS
Hysteresis below VEN-H
Hysteresis below VEN-H; falling
100
mV
ILKG-EN
Enable input leakage current
VEN = 3.3 V
0.2
nA
3.8
V
24
34
µA
5
10
µA
1
V
ENABLE
V
1.231
1.26
V
INTERNAL SUPPLIES
VCC
Internal LDO output voltage
appearing at the VCC pin
VBOOT-UVLO
Bootstrap voltage
undervoltage lock-out
threshold (2)
6 V ≤ VIN ≤ 36 V
4.75
5
5.25
2.2
V
V
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage; ADJ option
IFB
Current into FB pin; ADJ
option
0.985
FB = 1 V
ISC
High-side current limit
LMR33640
ILIMIT
Low-side current limit
LMR33640
IPEAK-MIN
Minimum peak inductor
current
LMR33640
1
1.015
V
0.2
50
nA
4.8
5.5
6.2
A
3.9
4.5
5
A
CURRENT LIMITS
(1)
(2)
6
0.824
A
This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turned on to recharge CBOOT.
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Electrical Characteristics (continued)
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN
= 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
Zero current detector
threshold
IZC
TYP
MAX
-0.106
UNIT
A
SOFT START
tSS
Internal soft-start time
2.9
4
6
ms
POWER GOOD (PG PIN)
VPG-HIGH-UP
Power-good upper threshold rising
% of FB voltage
105%
107%
110%
VPG-HIGH-DN
Power-good upper threshold falling
% of FB voltage
103%
105%
108%
VPG-LOW-UP
Power-good lower threshold rising
% of FB voltage
92%
94%
97%
VPG-LOW-DN
Power-good lower threshold falling
% of FB voltage
90%
92%
95%
tPG
Power-good glitch filter
delay (3)
RPG
Power-good flag RDSON
VIN-PG
Minimum input voltage for
proper PG function
50-µA, EN = 0 V
VPG
PG logic low output
50-µA, EN = 0 V, VIN = 2V
60
170
VIN = 12 V, VEN = 4 V
76
150
VEN = 0 V
35
60
µs
Ω
2
V
0.2
V
OSCILLATOR
ƒSW
Switching frequency
860
1000
1140
kHz
ƒSW
Switching frequency
340
400
460
kHz
(3)
See Power-Good Flag Output for details.
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Electrical Characteristics (continued)
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN
= 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFETS
RDS-ON-HS
High-side MOSFET ONresistance
DDA package
95
160
mΩ
RDS-ON-LS
Low-side MOSFET ONresistance
DDA package
66
110
mΩ
7.6 Timing Characteristics
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN
= 12 V, VEN = 4 V.
NOM
MAX
UNIT
tON-MIN
Minimum switch on-time
DDA package
MIN
75
108
ns
tOFF-MIN
Minimum switch off-time
DDA package
50
85
ns
tON-MAX
Maximum switch on-time
7
9
µs
8
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7.7 System Characteristics
The following specifications apply to a typical applications circuit, with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –40°C to 125°C. These specifications are not ensured by
production testing.
PARAMETER
VIN
Operating input voltage range
Output voltage regulation for VOUT = 5
V (1)
VOUT
Output voltage regulation for VOUT = 3.3
V (1)
TEST CONDITIONS
VOUT = 3.3 V, IOUT= 0 A
MIN
TYP
MAX
3.8
36
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 0 A to 4
A
–1.6%
2.5%
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 1 A to 4
A
–1.6%
1.5%
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 0 A
to 4 A
–1.6%
2.5%
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 1 A to
4A
–1.6%
1.5%
UNIT
V
ISUPPLY
Input supply current when in regulation
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ
VDROP
Dropout voltage; (VIN – VOUT)
DMAX
Maximum switch duty cycle (2)
VHC
FB pin voltage required to trip short-circuit
hiccup mode
0.4
V
tHC
Time between current-limit hiccup burst
94
ms
tD
Switch voltage dead time
TSD
(1)
(2)
Thermal shutdown temperature
25
µA
VOUT = 5 V, IOUT = 1A
Dropout at –1% of regulation,
ƒSW = 140 kHz
150
mV
VIN = VOUT = 12 V, IOUT = 1 A
98%
2
ns
Shutdown temperature
165
°C
Recovery temperature
148
°C
Deviation is with respect to VIN = 12 V, IOUT = 1 A.
In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: ƒMIN =
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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7.8 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 12 V, ƒSW = 400 kHz
36
12
11
10
Shutdown Current (µA)
Quiescent Current (µA)
34
32
30
28
26
-40C
24
9
8
7
6
5
4
25C
22
5
10
15
20
25
30
35
Input Voltage (V)
-40C
2
25C
1
125C
20
0
3
0
0
40
125C
5
10
15
20
25
30
35
40
Input Voltage (V)
C005
C003
EN = 0 V
VFB = 1.2 V
Figure 1. Non-Switching Input Supply Current
Figure 2. Shutdown Supply Current
1.35
1
EN Threshold Voltage (V)
1.30
Output Current (A)
0.95
0.9
0.85
1.25
1.20
1.15
1.10
UP
1.05
DN
1.00
0.8
0
5
10
15
20
25
30
35
Input Voltage (V)
VOUT = 0 V
ƒS = 400 kHz
±40
40
±20
0
20
40
60
80
100
120
140
Temperature (C)
C006
C004
See Figure 39
Figure 4. Precision Enable Thresholds
Figure 3. Short-Circuit Output Current
1
DN
Peak Inductor Current (A)
OUTPUT VOLTAGE (0.8V/Div)
0.95
UP
0.9
0.85
0.8
0.75
0.7
3.3V
0.6
0
0
INPUT VOLTAGE (1V/Div)
IOUT = 1 mA
See Figure 39
5
IOUT = 0 A
ƒSW = 400 kHz
10
15
20
25
30
Input Voltage (V)
VOUT = 5 V
35
40
C003
See Figure 39
Figure 6. IPEAK-MIN
Figure 5. UVLO Thresholds
10
5V
0.65
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8 Detailed Description
8.1 Overview
The LMR33640 is a synchronous peak-current-mode buck regulator designed for a wide variety of industrial
applications. Advanced high-speed circuitry allows the device to regulate from an input voltage of 36 V, while
providing an output voltage of 3.3 V at a switching frequency of 400 kHz. The innovative architecture allows the
device to regulate a 3.3 V output from an input of only 3.8 V. The regulator automatically switches modes
between PFM and PWM, depending on the load. At heavy loads, the device operates in PWM at a constant
switching frequency. At light loads, the mode changes to PFM with diode emulation, allowing DCM. This reduces
the input supply current and keeps efficiency high. The device features internal loop compensation, which
reduces design time and requires fewer external components than externally compensated regulators.
8.2 Functional Block Diagram
VCC
Int. Reg.
Bias
Oscillator
EN
VIN
Enable
Logic
BOOT
HS Current
Sense
1V
Reference
Error
Amplifier
PWM
Comp.
+
Control Logic
Driver
SW
+
±
FB
±
LS Current
Sense
PFM Mode
Control
PG
Power
Good
Control
AGND
PGND
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8.3 Feature Description
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR33640 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. The timing parameters of the
glitch filter are found in the Electrical Characteristics table. Output voltage excursions lasting less than tPG do not
trip the power-good flag. Power-good operation can best be understood by reference to Figure 7 and Figure 8.
During initial power up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted to the time
that the power-good flag goes high. This delay only occurs during start-up and is not encountered during normal
operation of the power-good function.
The power-good output consists of an open-drain NMOS and requires an external pullup resistor to a suitable
logic supply. It can also be pulled up to either VCC or VOUT through a 100-kΩ resistor, as desired. If this function
is not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into the powergood flag pin to less than 5 mA D.C. The maximum current is internally limited to about 35 mA when the device
is enabled and approximately 65 mA when the device is disabled. The internal current limit protects the device
from any transient currents that can occur when discharging a filter capacitor connected to this output.
VOUT
VPG-HIGH_UP (107%)
VPG-HIGH-DN (105%)
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
PG
High = Power Good
Low = Fault
Figure 7. Static Power-Good Operation
Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
< tPG
PG
tPG
tPG
tPG
Figure 8. Power-Good-Timing Behavior
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Feature Description (continued)
8.3.2 Enable and Start-up
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see the External UVLO section). Applying a
voltage greater than or equal to VEN-VCC_H causes the device to enter standby mode, which powers the internal
VCC, but does not produce an output voltage. Increasing the EN voltage to VEN-H fully enables the device,
allowing it to enter start-up mode and begin the soft-start period. When the EN input is brought below VEN-H by
VEN-HYS, the regulator stops running and enters standby mode. Further decrease in the EN voltage to below VENVCC-L completely shuts down the device. Figure 9 shows this behavior. The EN input can be connected directly to
VIN if this feature is not needed. This input must not be allowed to float. The values for the various EN thresholds
can be found in the Electrical Characteristics table.
The LMR33640 uses a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up. Figure 10 shows a typical start-up waveform, indicating typical timings.
The rise time of the output voltage is about 4 ms (see the Electrical Characteristics section).
EN
VEN-H
VEN-H ± VEN-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5V
0
VOUT
VOUT
0
Figure 9. Precision Enable Behavior
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Feature Description (continued)
EN
Output
Voltage
2V/div
PG
5V/div
Inductor
Curent
2A/
2ms/div
Figure 10. Typical Start-up Behavior
VIN = 12 V, VOUT = 5 V, IOUT = 4 A
8.3.3 Current Limit and Short Circuit
The LMR33640 incorporates both peak and valley inductor current limit to provide protection to the device from
overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current
run-away during short circuits on the output, while both peak and valley limits work together to limit the maximum
output current of the converter. Cycle-by-cycle current limit is used for overloads while hiccup mode is used for
sustained short circuits. Finally, a zero current detector is used on the low-side power MOSFET to implement
DEM at light loads (see the Glossary). The typical value of this current limit is found under IZC in the Electrical
Characteristics section.
When the device is overloaded, the valley of the inductor current may not reach below ILIMIT, (see the Electrical
Characteristics table) before the next clock cycle. When this occurs, the valley current limit control skips that
cycle, causing the switching frequency to drop. Further overload causes the switching frequency to continue to
drop and the inductor ripple current to increase. When the peak of the inductor current reaches the high-side
current limit, ISC (see the Electrical Characteristics table), the switch duty cycle is reduced and the output voltage
falls out of regulation. This represents the maximum output current from the converter and is given approximately
by Equation 1.
I
I
IOUT max LIMIT SC
(1)
2
If during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
into hiccup mode. In this mode, the device stops switching for tHC (see the System Characteristics section), or
about 94 ms, and then goes through a normal re-start with soft start. If the short-circuit condition remains, the
device runs in current limit for about 20 ms (typical) and then shuts down again. This cycle repeats, as shown in
Figure 11, as long as the short-circuit condition persists. This mode of operation reduces the temperature rise of
the device during a hard short on the output. The output current is greatly reduced during hiccup mode (see the
Typical Characteristics section). Once the output short is removed and the hiccup delay is passed, the output
voltage recovers normally as shown in Figure 12.
Figure 13 shows the overall output voltage versus the output current characteristic.
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Feature Description (continued)
Short triggered
Short Released
Output
Voltage
2V/div
Inductor
Curent
2A/
Inductor
Curent
1A/
50ms/div
50ms/div
Figure 12. Short-Circuit Transient and Recovery
VIN = 12 V, VOUT = 5 V
Figure 11. Inductor Current Burst in Short-Circuit Mode
Output
Voltage
VOUT
0.4· VOUT
0.2· IOMAX
IOMAX
Output
Current
Figure 13. Output Voltage versus Output Current in Current Limit
8.3.4 Undervoltage Lockout and Thermal Shutdown
The LMR33640 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC pin).
When VCC reaches about 3.7 V, the device is ready to receive an EN signal and start up. When VCC falls below
approximately 3 V, the device shuts down, regardless of EN status. Since the LDO is in dropout during these
transitions, the above values roughly represent the input voltage levels during the transitions.
Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 165°C, the device shuts down; re-start occurs when the temperature falls to about
148°C .
8.4 Device Functional Modes
8.4.1 Auto Mode
In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM. The load current for which the device moves from
PFM to PWM can be found in the Application Curves. The output current at which the device changes modes
depends on the input voltage, inductor value, and the output voltage. For output currents above the curve, the
device is in PWM mode. For currents below the curve, the device is in PFM. The curves apply for a nominal
switching frequency of 400 kHz and the BOM shown in Table 3. For applications where the switching frequency
must be known for a given condition, the transition between PFM and PWM must be carefully tested before the
design is finalized.
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Device Functional Modes (continued)
In PWM mode, the regulator operates as a constant frequency converter using PWM to regulate the output
voltage. While operating in this mode, the output voltage is regulated by switching at a constant frequency and
modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and
low-output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The
duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The periodicity of these
bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency (see the
Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current required
to regulate the output voltage at light loads. PFM results in very good light-load efficiency, but also yields larger
output voltage ripple and variable switching frequency. Also, a small increase in output voltage occurs at light
loads. The actual switching frequency and output voltage ripple depend on the input voltage, output voltage, and
load. Figure 14 and Figure 15 show typical switching waveforms in PFM and PWM. See the Application Curves
section for output voltage variation with load in auto mode.
SW,
5V/Div
SW
5V/Div
0
VOUT,
10mV/Div
5V
VOUT
10mV/Div
Inductor
Current,
0.5A/Div
Inductor Current
2A/Div
0
2µs/Div
50µs/Div
Figure 14. Typical PFM Switching Waveforms
VIN = 12 V, VOUT = 5 V, IOUT = 10 mA
Figure 15. Typical PWM Switching Waveforms
VIN = 12 V, VOUT = 5 V, IOUT = 4 A, ƒS = 400 kHz
8.4.2 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage level
approaches the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value.
Beyond this point, the switching can become erratic, and the output voltage can fall out of regulation. To avoid
this problem, the LMR33640 automatically reduces the switching frequency to increase the effective duty cycle
and maintain regulation. In this data sheet, the dropout voltage is defined as the difference between the input
and output voltage when the output has dropped by 1% of its nominal value. Under this condition, the switching
frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V short circuit detection
threshold is not activated when in dropout mode. Typical dropout characteristics can be found in Figure 16,
Figure 17, and Figure 18.
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6
0.7
5.5
0.6
Drop-Out Voltage (V)
Output Voltage (V)
Device Functional Modes (continued)
5
4.5
4
3.5
0.5
0.4
0.3
0.2
0.1
3
0
4
4.5
5
5.5
6
6.5
Input Voltage (V)
7
0
0.5
1
1.5
Figure 16. Overall Dropout Characteristic
VOUT = 5 V, IOUT = 4 A
2
2.5
3
3.5
4
4.5
Output Current (A)
C005
5
C007
Figure 17. Typical Dropout Voltage vs Output
Current in Frequency Fold-back
ƒSW = 140 kHz
Switching Frequency (kHz)
450
400
350
300
250
200
150
100
4
4.5
5
5.5
6
Input Voltage (V)
6.5
7
C006
Figure 18. Typical Switching Frequency in Dropout Mode
VOUT = 5 V, fSW = 400 kHz
8.4.3 Minimum Switch On-Time
Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times
associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To extend the
minimum controllable duty cycle, the LMR33640 automatically reduces the switching frequency when the
minimum on-time limit is reached. This way the converter can regulate the lowest programmable output voltage
at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage before
frequency foldback occurs is found in Equation 2. The values of tON and fSW can be found in the Electrical
Characteristics table. As the input voltage is increased, the switch on-time (duty-cycle) reduces to regulate the
output voltage. When the on-time reaches the limit, the switching frequency drops while the on-time remains
fixed.
VOUT
VIN d
t ON ˜ fSW
(2)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMR33640 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 4 A. The following design procedure can be used to select components
for the LMR33640. Alternately, the WEBENCH design tool can be used to generate a complete design. This tool
uses an iterative design procedure and has access to a comprehensive database of components. This allows the
tool to create an optimized design and allows the user to experiment with various options.
NOTE
In this data sheet, the effective value of capacitance is defined as the actual capacitance
under D.C. bias and temperature; not the rated or nameplate values. Use high-quality,
low-ESR, ceramic capacitors with an X5R or better dielectric throughout. All high value
ceramic capacitors have a large voltage coefficient in addition to normal tolerances and
temperature effects. Under D.C. bias, the capacitance drops considerably. Large case
sizes and higher voltage ratings are better in this regard. To help mitigate these effects,
multiple capacitors can be used in parallel to bring the minimum effective capacitance up
to the required value. This can also ease the RMS current requirements on a single
capacitor. A careful study of bias and temperature variation of any capacitor bank must be
made to ensure that the minimum value of effective capacitance is provided.
9.2 Typical Application
Figure 19 shows a typical application circuit for the LMR33640. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick-start guide, Table 2 provides typical
component values for a range of the most common output voltages. The values given in the table are typical.
Other values can be used to enhance certain performance criterion as required by the application.
L
VIN
6 V to 36 V
CIN
10 µF
VOUT
SW
VIN
5V
4A
6.8 µH
CHF
CBOOT
220 nF
COUT
BOOT
EN
4x 22 µF
0.1 µF
RFBT
CFF
PG
100 NŸ
PG
100 NŸ
VCC
CVCC
1 µF
FB
PGND
AGND
RFBB
24.9 NŸ
Figure 19. Example Application Circuit (400 kHz)
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Typical Application (continued)
9.2.1 Design Requirements
Table 1 provides the parameters for our detailed design procedure example.
Table 1. Detailed Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V (6 V to 36 V)
Output voltage
5V
Maximum output current
0 A to 4 A
Switching frequency
400 kHz
Table 2. Typical External Component Values
ƒSW
(kHz)
VOUT (V)
L (µH)
TYPICAL COUT
MINIMUM
COUT
RFBT (Ω)
RFBB (Ω)
CIN + CHF
CBOOT
CVCC
400
3.3
6.8
4 × 22 µF
3 × 22 µF
100 k
43.2 k
10 µF + 220 nF
100 nF
1 µF
400
5
6.8
4 × 22 µF
3 × 22 µF
100 k
24.9 k
10 µF + 220 nF
100 nF
1 µF
1000
3.3
3.3
3 × 22 µF
2 × 22 µF
100 k
43.2 k
10 µF + 220 nF
100 nF
1 µF
1000
5
3.3
3 × 22 µF
2 × 22 µF
100 k
24.9 k
10 µF + 220 nF
100 nF
1 µF
9.2.2 Detailed Design Procedure
The following design procedure applies to Figure 19 and Table 1.
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR33640 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Setting the Output Voltage
The output voltage of LMR33640 is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in the table. The divider network is comprised of RFBT and RFBB and closes
the loop between the output voltage and the converter. The converter regulates the output voltage by holding the
voltage on the FB pin equal to the internal reference voltage, VREF. The resistance of the divider is a compromise
between excessive noise pickup and excessive loading of the output. Smaller values of resistance reduce noise
sensitivity and reduce the light-load efficiency. The recommended value for RFBT is 100 kΩ with a maximum
value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a feedforward capacitor must be used across this resistor to
provide adequate loop-phase margin (see the CFF Selection section). Once RFBT is selected, use Equation 3 to
select RFBB. VREF is nominally 1 V (see the Electrical Characteristics section for limits).
RFBT
RFBB
ª VOUT
º
1»
«
¬ VREF
¼
(3)
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For this 5-V example, RFBT = 100 kΩ and RFBB = 24.9 kΩ are chosen.
9.2.2.3 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum
output current. Experience shows that the best value for inductor ripple current is 30% of the maximum load
current. Note that when selecting the ripple current for applications with much smaller maximum load than the
maximum available from the device, the maximum device current must be used. Equation 4 can be used to
determine the value of inductance. The constant K is the percentage of inductor current ripple. For this example,
K = 0.3, giving a calculated inductance of 6.08 µH. The next standard value of 6.8 µH is used.
VIN VOUT
V
˜ OUT
fSW ˜ K ˜ IOUT max VIN
L
(4)
Ideally, the saturation current rating of the inductor must be at least as large as the high-side switch current limit,
ISC. This ensures that the inductor does not saturate, even during a short circuit on the output. When the inductor
core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly.
Although the valley current limit, ILIMIT, is designed to reduce the risk of current run-away, a saturated inductor
can cause the current to rise to high values very rapidly. This can lead to component damage. Do not allow the
inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually
have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some
relaxation in the current rating of the inductor. However, they have more core losses at frequencies typically
above 1 MHz. In any case, the inductor saturation current must not be less than the device low-side current limit,
ILIMIT. To avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 5. The
maximum inductance is limited by the minimum current ripple required for the current mode control to perform
correctly. As a rule-of-thumb, the minimum inductor ripple current must not be less than about 10% of the device
maximum rated current under nominal conditions.
V
L t 0.23 ˜ OUT
FSW
(5)
9.2.2.4 Output Capacitor Selection
The value of the output capacitor and its ESR determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements rather than the
output voltage ripple. Use Equation 6 to estimate a lower bound on the total output capacitance and an upper
bound on the ESR, which are required to meet a specified load transient.
º
ª
'IOUT
K2
COUT t
˜«1 D ˜ 1 K
˜ 2 D»
12
fSW ˜ 'VOUT ˜ K ¬«
¼»
ESR d
D
2 K ˜ 'VOUT
ª
K2 §
1 ·º
¸»
˜ ¨¨1
2 ˜ 'IOUT «1 K
12 © (1 D) ¸¹¼»
¬«
VOUT
VIN
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = ripple factor from Inductor Selection
(6)
Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the peak-to-peak
output voltage ripple, Vr.
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1
8 ˜ fSW ˜ COUT
2
(7)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
For this example, a ΔVOUT of ≤ 350 mV for an output current step of ΔIOUT = 4 A is required. Equation 6 gives a
minimum value of about 80 µF and a maximum ESR of 77 mΩ. Assuming a 20% tolerance and a 10% bias derating, you arrive at a minimum capacitance of about 110 µF. This can be achieved with a bank of 4 × 22-µF, 16V, ceramic capacitors in the 1210 case size or 5 × 22-µF for a worst case. More output capacitance can be used
to improve the load transient response. Ceramic capacitors can easily meet the minimum ESR requirements. In
some cases, an aluminum electrolytic capacitor can be placed in parallel with the ceramics to build up the
required value of capacitance. When using a mixture of aluminum and ceramic capacitors, use the minimum
recommended value of ceramics and add aluminum electrolytic capacitors as needed.
In general, use a capacitor of at least 10 V for output voltages of 3.3 V or less, while a capacitor of 16 V or more
must be used for output voltages of 5 V and above.
In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1
nF to 100 nF can be very helpful in reducing voltage spikes on the output caused by inductor and board
parasitics.
The maximum value of total output capacitance must be limited to about 10 times the design value, or 1000 µF,
whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of startup at full load and loop stability must be performed.
9.2.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum of 10 µF of ceramic capacitance is required
on the input of the LMR33640. This must be rated for at least the maximum input voltage that the application
requires; preferably twice the maximum input voltage. This capacitance can be increased to reduce input voltage
ripple and maintain the input voltage during load transients. In addition, a small case size 220-nF ceramic
capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency bypass
for the control circuits internal to the device. For this example, a 10-µF, 50-V, X7R (or better) ceramic capacitor is
chosen. The 220 nF must also be rated at 50 V with an X7R dielectric.
Many times, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is
especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of
this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high
impedance.
Most of the input switching current passes through the ceramic input capacitors. The approximate worst case
RMS value of this current can be calculated from Equation 8 and must be checked against the manufacturers'
maximum ratings.
I
IRMS # OUT
2
(8)
9.2.2.6 CBOOT
The LMR33640 requires a boot-strap capacitor connected between the BOOT pin and the SW pin. This capacitor
stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of
100 nF and at least 10 V is required.
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9.2.2.7 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, avoid
loading this output with any external circuitry. However, this output can be used to supply the pullup for the
power-good function. A value of 100 kΩ is a good choice in this case. The nominal output voltage on VCC is 5 V;
see the Electrical Characteristics for limits. Do not short this output to ground or any other external voltage.
9.2.2.8 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help mitigate this effect. Use Equation 9 to estimate the value of CFF. The value
found with Equation 9 is a starting point. Use lower values to determine if any advantage is gained by the use of
a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters with Feedforward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.
VOUT ˜ COUT
CFF
VREF
120 ˜ RFBT ˜
VOUT
(9)
9.2.2.9 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in Figure 20. The input voltage at which the device turns on is
designated VON while the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100
kΩ, then Equation 10 is used to calculate RENT and VOFF.
VIN
RENT
EN
RENB
Figure 20. Setup for External UVLO Application
R ENT
§ V ON
¨¨
© VEN H
·
1¸¸ ˜ R ENB
¹
V OFF
§
V ON ˜ ¨¨ 1
©
VEN HYS
VEN H
·
¸¸
¹
where
•
•
VON = VIN turnon voltage
VOFF = VIN turnoff voltage
(10)
9.2.2.10 Maximum Ambient Temperature
As with any power conversion device, the LMR33640 dissipates internal power while operating. The effect of this
power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,
RθJA, of the device and PCB combination. The maximum internal die temperature for the LMR33640 must be
limited to 125°C. This establishes a limit on the maximum device power dissipation and, therefore, the load
current. Equation 11 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The converter
efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions
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cannot be found in one of the curves, then interpolation can be used to estimate the efficiency. Alternatively, the
EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly.
The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal
Metrics Application Report, the value of RθJA given in the Thermal Information table is not valid for design
purposes and must not be used to estimate the thermal performance of the application. The values reported in
that table were measured under a specific set of conditions that are rarely obtained in an actual application.
IOUT
MAX
TJ TA
1
K
˜
˜
R TJA
1 K VOUT
where
•
η = Efficiency
(11)
The effective RθJA is a critical parameter and depends on many factors such as the following:
• Power dissipation
• Air temperature
• Air flow
• PCB area
• Copper heat-sink area
• Number of thermal vias under the package
• Adjacent component placement
The HSOIC (DDA) package uses a die attach paddle or thermal pad (PAD) to provide a place to solder down to
the PCB heat-sinking copper. This provides a good heat conduction path from the regulator junction to the heat
sink and must be properly soldered to the PCB heat sink copper. Typical examples of RθJA versus copper board
area can be found in Figure 21. The copper area given in the graph is for each layer; the top and bottom layers
are 2 oz copper each, while the inner layers are 1 oz. Figure 22 shows the typical curves of maximum output
current versus ambient temperature This data was taken with a device and PCB combination, giving an RθJA as
noted in the graph. Remember that the data given in these graphs are for illustration purposes only and the
actual performance in any given application depends on all of the previously mentioned factors.
44
42
40
R
JA
(ƒC/W)
38
36
34
32
30
28
26
24
22
DDA, 4L
20
0
10
20
30
40
50
Copper Area (cm2)
60
70
C003
Figure 21. Typical RθJA versus Copper Area for a Four-Layer Board
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5
4.5
Output Current (A)
4
3.5
3
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
Ambient Temperature (ƒC)
120
140
C010
Figure 22. Maximum Output Current versus Ambient Temperature
VIN = 12 V, VOUT = 5 V, RθJA = 30°C/W, ƒSW = 400 kHz
Use the following resources as a guide to optimal thermal PCB design and to estimate RθJA for a given
application environment:
• Thermal Design by Insight Not Hindsight Application Report
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
• Semiconductor and IC Package Thermal Metrics Application Report
• Thermal Design Made Simple with LM43604 And LM43602 Application Report
• PowerPAD Thermally Enhanced Package Application Report
• PowerPAD Made Easy Application Report
• Using New Thermal Metrics Application Report
24
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9.2.3 Application Curves
Unless otherwise specified, the following conditions apply: VIN = 12 V, TA = 25°C. Figure 39 shows the circuit
with the appropriate BOM from Table 3.
100
100
95
95
90
90
85
Efficiency (%)
Efficiency (%)
85
80
75
70
65
55
50
0.001
0.01
0.1
Output Current (A)
VOUT = 5 V
1
75
70
65
60
8V
12V
24V
36V
60
80
8V
12V
24V
36V
55
50
45
0.001
5
0.01
eff_
ƒSW = 400 kHz
VOUT = 3.3 V
100
100
95
95
90
90
85
85
80
80
75
70
65
60
50
0.1
Output Current (A)
VOUT = 5 V
eff_
ƒSW = 400 kHz
1
75
70
65
8V
12V
24V
36V
55
50
45
0.001
5
0.01
eff_
ƒSW = 1000 kHz
VOUT = 3.3 V
Figure 25. Efficiency
0.1
Output Current (A)
1
5
eff_
ƒSW = 1000 kHz
Figure 26. Efficiency
3.35
5.06
8V
12V
24V
36V
8V
12V
24V
36V
3.34
Output Voltage (V)
5.05
Output Voltage (V)
5
60
8V
12V
24V
36V
55
0.01
1
Figure 24. Efficiency
Efficiency (%)
Efficiency (%)
Figure 23. Efficiency
45
0.001
0.1
Output Current (A)
5.04
5.03
3.33
3.32
5.02
5.01
3.31
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
0
LMR3
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
VOUT = 5 V
VOUT = 3.3 V
Figure 27. Line and Load Regulation
Figure 28. Line and Load Regulation
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Output Voltage
200mV/div
Output Voltage
200mV/div
5V
3.3V
Output Current
2A/div
100µs/div
0
VIN = 12 V
ƒSW = 400 kHz
Output Current
2A/div
0
VIN = 12 V
ƒSW = 400 kHz
VOUT = 5 V
IOUT = 0 A to 4 A
Output Voltage
200mV/div
Output Voltage
200mV/div
3.3V
5V
Output Current
2A/div
Output Current
2A/div
100µs/div
0
100µs/div
0
VIN = 12 V
ƒSW = 400 kHz
VOUT = 5 V
IOUT = 1 A to 4 A
VIN = 12 V
ƒSW = 400 kHz
Figure 31. Load Transient
VOUT = 3.3 V
IOUT = 1 A to 4 A
Figure 32. Load Transient
Output Voltage
200mV/div
Output Voltage
200mV/div
3.3V
5V
Output Current
2A/div
VIN = 12 V
ƒSW = 1000 kHz
100µs/div
VOUT = 5 V
IOUT = 0 A to 4 A
Output Current
2A/div
0
VIN = 12 V
ƒSW = 1000 kHz
100µs/div
VOUT = 3.3 V
IOUT = 0 A to 4 A
Figure 34. Load Transient
Figure 33. Load Transient
26
VOUT = 3.3 V
IOUT = 0 A to 4 A
Figure 30. Load Transient
Figure 29. Load Transient
0
100µs/div
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Output Voltage
200mV/div
Output Voltage
200mV/div
3.3V
5V
Output Current
2A/div
Output Current
2A/div
100µs/div
0
0
VIN = 12 V
ƒSW = 1000 kHz
VOUT = 5 V
IOUT = 1 A to 4 A
VIN = 12 V
ƒSW = 1000 kHz
Figure 35. Load Transient
0.65
1
0.55
0.9
0.45
PWM
0.35
VOUT = 3.3 V
IOUT = 1 A to 4 A
Figure 36. Load Transient
Output Current (A)
Output Current (A)
100µs/div
0.25
0.15
0.8
0.7
PWM
0.6
0.5
0.4
PFM
0.05
PFM
0.3
6
9
12
15
18
21
24
Input Voltage (V)
ƒSW = 400 kHz
27
30
33
36
6
9
12
15
mode
VOUT = 5 V
ƒSW = 1000 kHz
Figure 37. Load Transient
18
21
24
Input Voltage (V)
27
30
33
36
mode
VOUT = 5 V
Figure 38. Load Transient
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L
VIN
VIN
VOUT
SW
U1
CBOOT
CIN
CHF
COUT
BOOT
EN
0.1 µF
RFBT
PG
100 NŸ
PG
100 NŸ
VCC
CVCC
1 µF
FB
PGND
AGND
RFBB
Figure 39. Circuit for Application Curves
Table 3. BOM for Typical Application Curves (1)
(1)
VOUT
FREQUENCY
RFBB
COUT
CIN + CHF
L
U1
3.3 V
400 kHz
43.3 kΩ
3 × 22 µF
1 × 10 µF + 1 × 220 nF
6.8 µH, 18 mΩ
LMR33640ADDA
5V
400 kHz
24.9 kΩ
3 × 22 µF
1 × 10 µF + 1 × 220 nF
6.8 µH, 18 mΩ
LMR33640ADDA
3.3 V
1000 kHz
43.3 kΩ
3 × 22 µF
1 × 10 µF + 1 × 220 nF
3.3 µH, 16 mΩ
LMR33640DDDA
5V
1000 kHz
24.9 kΩ
3 × 22 µF
1 × 10 µF + 1 × 220 nF
3.3 µH, 16 mΩ
LMR33640DDDA
The values in this table were selected to enhance certain performance criteria and may not represent typical values.
9.3 What to Do and What Not to Do
•
•
•
•
•
•
•
28
Don't: Exceed the ESD Ratings.
Don't: Exceed the Absolute Maximum Ratings.
Don't: Exceed the Recommended Operating Conditions.
Don't: Allow the EN input to float.
Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
Don't: Use the value of RθJA given in the Thermal Information table to design your application. Use the
information in the Maximum Ambient Temperature section.
Do: Follow all the guidelines and/or suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make your
project a success (see the Support Resources section).
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10 Power Supply Recommendations
The characteristics of the input supply must be compatible with the recommendations found in this data sheet. In
addition, the input supply must be capable of delivering the required input current to the loaded regulator. The
average input current can be estimated with Equation 12.
VOUT ˜ IOUT
IIN
VIN ˜ K
where
•
η is the efficiency
(12)
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an under-damped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the
regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with
the ceramics. The moderate ESR of these types of capacitors help to damp the input resonant circuit and reduce
any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DCDC Converters User Guide provides helpful suggestions when designing
an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors discharges through the internal parasitic diode found between the VIN and SW pins of
the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If
this scenario is considered likely, then use a Schottky diode between the input supply and the output is
recommended.
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter, the
most critical PCB feature is the loop formed by the input capacitors and power ground, as shown in Figure 40.
This loop carries large transient currents that can cause large transient voltages when reacting with the trace
inductance. These unwanted transient voltages disrupts the proper operation of the converter. Because of this,
the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic
inductance. Figure 40 and Figure 41 show recommended layouts for the critical components of the LMR33640.
1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are
adjacent, simplifying the input capacitor placement.
2. Place the bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device
and routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short and wide traces to the
BOOT and SW pins.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also a heat
dissipation path.
6. Connect the thermal pad to the ground plane. The SOIC package has a thermal pad (PAD) connection that
must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection and an electrical
ground connection for the regulator. The integrity of this solder connection has a direct bearing on the total
effective RθJA of the application.
7. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
8. Provide enough PCB area for proper heat sinking. As stated in the Maximum Ambient Temperature section,
enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and
ambient temperature. Make the top and bottom PCB layers with two-ounce copper and no less than one
ounce. With the SOIC package, use an array of heat-sinking vias to connect the thermal pad (PAD) to the
ground plane on the bottom PCB layer. If the PCB design uses multiple copper layers (recommended),
thermal vias can also be connected to the inner layer heat-spreading ground planes.
9. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies Application Report
• Simple Switcher PCB Layout Guidelines Application Report
• Construction Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
30
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Layout Guidelines (continued)
VIN
CIN
KEEP
CURRENT
LOOP
SMALL
SW
GND
Figure 40. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control
circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass
capacitors. PGND pins are connected directly to the source of the low-side MOSFET switch, and also connected
directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching
frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be
constrained to one side of the ground planes. The other side of the ground plane contains much less noise and
must be used for sensitive routes.
TI recommends providing adequate device heat sinking by using the thermal pad (PAD) of the device as the
primary thermal path. Use a minimum 4 × 4 array of 10 mil thermal vias to connect the PAD to the system
ground plane heat sink. The vias must be evenly distributed under the PAD. For the best heat dissipation, use as
much copper as possible for system ground plane and on the top and bottom layers. Use a four-layer board with
the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with
enough copper thickness, and proper layout, provides low-current conduction impedance, proper shielding, and
lower thermal resistance.
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11.2 Layout Example
GND
HEATSINK
INDUCTOR
VOUT
COUT
COUT
CBOOT
COUT
CHF
GND
CIN
VIN
EN
CVCC
PGOOD
RFBT
RFBB
GND
GND
HEATSINK
Top Trace
Bottom Trace
VIA
Ground Plane
VIA
Bottom
Figure 41. Example PCB Layout
32
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM33630 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Thermal Design by Insight not Hindsight Application Report
• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Thermal Design Made Simple with LM43604 And LM43602 Application Report
• Texas Instruments, PowerPAD Thermally Enhanced Package Application Report
• Texas Instruments, PowerPAD Made Easy Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
• Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report
• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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12.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMR33640ADDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
33640A
LMR33640DDDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
33640D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Nov-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMR33640ADDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
LMR33640DDDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMR33640ADDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
LMR33640DDDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.2
TYP
5.8
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
3.81
5.0
4.8
NOTE 3
4
5
B
8X
4.0
3.8
NOTE 4
0.51
0.31
0.1
C A
1.7 MAX
B
0.25
TYP
0.10
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
3.1
2.5
8
1
0 -8
0.15
0.00
1.27
0.40
DETAIL A
2.6
2.0
TYPICAL
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.6)
SOLDER MASK
OPENING
8X (1.55)
SEE DETAILS
1
8
8X (0.6)
SYMM
(1.3)
TYP
(3.1)
SOLDER MASK
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
( 0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
SYMM
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
BASED ON
0.127 THICK
STENCIL
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.150
0.175
2.91 X 3.47
2.6 X 3.1 (SHOWN)
2.37 X 2.83
2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Copyright © 2019, Texas Instruments Incorporated
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