Texas Instruments | TPS563231 4.5-V to 17-V Input, 3-A Synchronous Step-Down Voltage Regulator in SOT563 (Rev. B) | Datasheet | Texas Instruments TPS563231 4.5-V to 17-V Input, 3-A Synchronous Step-Down Voltage Regulator in SOT563 (Rev. B) Datasheet

Texas Instruments TPS563231 4.5-V to 17-V Input, 3-A Synchronous Step-Down Voltage Regulator in SOT563 (Rev. B) Datasheet
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TPS563231
SLUSD65B – JULY 2018 – REVISED OCTOBER 2019
TPS563231 4.5-V to 17-V Input, 3-A Synchronous Step-Down Voltage Regulator in SOT563
1 Features
3 Description
•
•
The TPS563231 is a simple, easy-to-use, 3-A
synchronous step-down converter in SOT563
package.
1
•
•
•
•
•
•
•
•
•
•
•
3-A Converter integrated 95-mΩ and 55-mΩ FETs
D-CAP3™ mode control with fast transient
response
Input voltage range: 4.5 V to 17 V
Output voltage range: 0.6 V to 7 V
Pulse skip mode
600-kHz switching frequency
Low shutdown current Less than 12 µA
2% Feedback voltage accuracy (25ºC)
Startup from pre-biased output voltage
Cycle-by-cycle over current limit
Hiccup-mode over current protection
Non-latch UVP and TSD protections
6-Pin SOT563 package
2 Applications
•
•
•
•
•
The device is optimized to operate with minimum
external component counts and also optimized to
achieve low standby current.
These switch mode power supply (SMPS) devices
employ D-CAP3 mode control providing a fast
transient response and supporting both lowequivalent series resistance (ESR) output capacitors
such as specialty polymer and ultra-low ESR ceramic
capacitors
with
no
external
compensation
components.
During light load operation, TPS563231 operates in
pulse skip mode (PSM), which maintains high
efficiency. The TPS563231 is available in a 6-pin 1.6mm × 1.6-mm SOT563 (DRL) package, and specified
from a –40°C to 125°C junction temperature.
Device Information(1)
Digital TV power supply
High definition Blu-ray™ disc players
Networking home terminal
Digital set top box (STB)
Surveillance
Simplified Schematic
PART NUMBER
TPS563231
BODY SIZE (NOM)
1.60 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TPS563231 Efficiency
VIN
VIN
PACKAGE
DRL (6)
100
BST
CBST
CIN
L
EN
90
VOUT
SW
RFBT
FB
80
COUT
RFBB
Efficiency(%)
GND
70
60
50
40
Vout=1.05V
Vout=1.8V
Vout=3.3V
Vout=5V
30
20
0.001
0.005
0.02
0.05 0.1 0.2
Iout(A)
0.5
1
2 3
12Vi
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS563231
SLUSD65B – JULY 2018 – REVISED OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
3
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
2
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
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4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2019) to Revision B
Page
•
Changed FB I/O Version from 'O' to 'I' ................................................................................................................................... 5
•
Changed Function Block Diagram Pin number .................................................................................................................... 10
Changes from Original (July 2018) to Revision A
•
Page
Changed marketing status from Advance Information to Final. ............................................................................................ 1
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5 Pin Configuration and Functions
DRL Package
6-Pin SOT563
Top View
VIN
1
6
FB
SW
2
5
EN
GND
3
4
BST
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BST
4
O
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
BST and SW pins.
EN
5
I
Enable input control. High = On, Low = Off. Can be connected to VIN. Do not float. Adjust
the input undervoltage lockout with EN resistor divider.
FB
6
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
GND
3
—
Power ground terminals, connected to the source of low-side FET internally. Connect to
system ground, ground side of CIN and COUT. Path to CIN must as short as possible.
SW
2
O
Switch node connection between high-side NFET and low-side NFET.
VIN
1
I
Input voltage supply pin. The drain terminal of high-side power NFET.
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
UNIT
VIN
–0.3
19
V
BST
–0.3
24.5
V
BST (10 ns transient)
–0.3
26.5
V
BST to SW
–0.3
5.5
V
FB
–0.3
5.5
V
EN
–0.3
VIN + 0.3
V
SW
–2
19
V
SW (10 ns transient)
–3.5
21
V
Operating junction
temperature
TJ
–40
150
°C
Storage temperature
Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
Operating junction
temperature
MIN
MAX
VIN
4.5
17
BST
–0.1
22
BST to SW
–0.1
5
EN
–0.1
VIN
FB
–0.1
4.5
SW
–1.8
17
TJ
–40
125
UNIT
V
V
°C
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6.4 Thermal Information
TPS56323x
THERMAL METRIC (1)
DRL
UNIT
6 PINS
θJA
Junction-to-ambient thermal resistance
135.8
°C/W
θJC(top)
Junction-to-case (top) thermal resistance
45.5
°C/W
θJB
Junction-to-board thermal resistance
23.8
°C/W
ψJT
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
24.0
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
220
300
µA
2
12
µA
4.0
4.3
POWER SUPPLY (VIN PIN)
IVIN
Operating – non-switching
supply current
VEN = 5 V, VFB = 0.7 V
IVINSDN
Shutdown supply current
VEN = 0 V
VIN_UVLO
Undervoltage lockout
thresholds
Rising threshold
Falling threshold
3.3
Hysteresis
3.6
V
0.4
ENABLE (EN PIN)
VENH
EN high-level input voltage
1.10
1.24
1.42
VENL
EN low-level input voltage
1.00
1.13
1.30
REN
EN pin resistance to GND
VEN = 12 V
1000
V
V
kΩ
VOLTAGE REFERENCE (FB PIN)
VIN = 4.5 V to 17 V, TJ = 25 °C
588
600
612
mV
VREF
Reference voltage
IFB
VFB input current
VFB = 0.6 V
RDSON_H
High-side switch resistance
TJ = 25°C, VBST – VSW = 5V
95
mΩ
RDSON_L
Low-side switch resistance
TJ = 25°C
55
mΩ
VIN = 4.5 V to 17 V, TJ = –40°C to 125°C
600
0
mV
±100
nA
MOSFET
CURRENT LIMIT
IOC_LS
Low side FET source current
limit
IZC
Zero cross current detection
3
3.9
4.8
0
A
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown
threshold (1)
Shutdown temperature
Hysteresis
160
25
°C
ON-TIME TIMER CONTROL
tON(MIN)
tOFF(MIN)
Minimum on time (1)
80
ns
VFB = 0.5 V
250
ns
Soft-start time
Internal soft-start time
1.5
ms
Switching frequency
VIN = 12 V, VOUT = 3.3 V, CCM mode
600
kHz
65
%
Minimum off time
(1)
SOFT START
Tss
FREQUENCY
Fsw
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP
Output UVP falling threshold
THICCUP_WAIT
UVP propagation delay
0.8
ms
THICCUP_RE
Hiccup time before restart
24
ms
(1)
Hiccup detect
Not production tested.
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6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
230
610
Reference Voltage VREF (V)
Quiescent Current IQ (µA)
225
220
215
210
205
200
-50
-25
0
25
50
75
Temperature (°C)
100
125
608
606
604
602
600
-50
150
-25
0
Iq-S
Figure 1. IQ vs Junction Temperature
25
50
75
Temperature (°C)
100
125
150
Vref
Figure 2. VREF Voltage vs Junction Temperature
4.3
1.3
EN Threshold VEN (V)
VIN UVLO Threshold (V)
4.2
4.1
4
Rising
Falling
3.9
3.8
1.25
1.2
Rising
Falling
1.15
3.7
3.6
-50
-25
0
25
50
75
Temperature (°C)
100
125
1.1
-50
150
3.95
3.9
120
3.85
3.8
25
50
75
Temperature (°C)
100
125
150
en-S
HS
LS
100
80
60
3.75
-25
0
25
50
75
Temperature(qC)
100
125
150
40
-50
-25
Ilim
Figure 5. Current Limit vs Junction Temperature
8
0
Figure 4. EN Pin UVLO vs Junction Temperature
140
HS and LS FET RDSON
LS FET Valley Current Limit ILS_CL(A)
Figure 3. VIN UVLO vs Junction Temperature
3.7
-50
-25
vin-
0
25
50
75
Temperature (°C)
100
125
150
rdso
Figure 6. RDS-ON vs Junction Temperature
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Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
100
100
90
90
80
80
Efficiency(%)
Efficiency(%)
70
60
50
40
70
60
50
30
40
Vin=5V
Vin=9V
Vin=12V
Vin=17V
20
10
0
0.001
0.005
0.02
0.05 0.1 0.2
Iout(A)
0.5
1
Vin=5V
Vin=9V
Vin=12V
Vin=17V
30
20
0.001
2 3
Figure 7. TPS563231 VOUT = 1.05 V Efficiency
105
90
95
Efficiency(%)
Efficiency(%)
80
70
60
50
Vin=5V
Vin=9V
Vin=12V
Vin=17V
40
0.005
0.02
0.05 0.1 0.2
Iout(A)
0.5
1
0.05 0.1 0.2
Iout(A)
0.5
1
2 3
1V8V
85
75
65
Vin=9V
Vin=12V
Vin=17V
55
45
0.001
2 3
0.005
0.02
3V3V
Figure 9. TPS563231 VOUT = 3.3 V Efficiency
0.05 0.1 0.2
Iout(A)
0.5
1
2 3
5Vo_
Figure 10. TPS563231 VOUT = 5 V Efficiency
3.36
3.36
Vin=6V
Vin=9V
Vin=12V
Vin=17V
3.35
3.34
3.34
Vout(V)
3.33
Vout(V)
0.02
Figure 8. TPS563231 VOUT = 1.8 V Efficiency
100
30
0.001
0.005
1V05
3.32
3.31
3.32
3.3
3.3
Iout=0A
Iout=1A
Iout=2A
Iout=3A
3.28
3.29
3.28
3.26
0
0.3
0.6
0.9
1.2
1.5 1.8
Iout(A)
2.1
2.4
2.7
3
6
3V3V
Figure 11. TPS563231 VOUT = 3.3V Load Regulation
8
10
12
Vin(V)
14
16
18
3V3V
Figure 12. TPS563231 VOUT = 3.3 V Line Regulation
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7 Detailed Description
7.1 Overview
The TPS563231 is 3-A synchronous step-down converter. The proprietary D-CAP3 mode control supports low
ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex
external compensation circuits. The fast transient response of D-CAP3 mode control can reduce the output
capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN 5
1 VIN
VUVP
+
UVP
Hiccup
Control Logic
VREG5
Regulator
UVLO
FB 6
Voltage
Reference
+
+
+
4 BST
PWM
SS
Soft Start
HS
+
Internal Ramp
2 SW
One-Shot
XCON
VREG5
Ripple Injection
TSD
OCL
threshold
LS
OCL
3 GND
+
+
ZC
7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS563231 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP3 mode control. The D-CAP3 mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal onshot timer expires. This one shot duration is set proportional to the converter output voltage, VOUT , and inversely
proportional to the input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage range, hence it
is called adaptive on-time control. The on-shot timer is reset and the high-side MOSFET is turned on again when
the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate
output ripple, eliminating the need for ESR induced output ripple from D-CAP3 mode control.
10
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Feature Description (continued)
7.3.2 Soft Start and Pre-Biased Soft Start
The TPS563231 has an internal 1.5-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage from 0 V to 0.6 V linearly.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.3 Over Current and Short Circuit Protection
The TPS563231 is protected from over-current conditions by cycle-by-cycle current limit on the valley of the
inductor current. Hiccup mode will be activated if a fault condition persists to prevent over-heating.
The current going through low-side (LS) MOSFET is sensed and monitored. When the LS MOSFET turns on, the
inductor current begins to ramp down. The LS MOSFET will not be turned OFF if its current is above the LS
current limit ILS_LIMIT even the feedback voltage, VFB, drops below the reference voltage VREF. The LS MOSFET is
kept ON so that inductor current keeps ramping down, until the inductor current ramps below the LS current limit
ILS_LIMIT. Then the LS MOSFET is turned OFF and the HS switch is turned on after a dead time.
As the inductor current is limited by ILS_LIMT, the output voltage tends to drop as the inductor current may be
smaller than the load current. Hiccup current protection mode is activated once the VFB drops below the UVP
threshold after a delay time (800 µs typically). In hiccup mode, the regulator is shut down and kept off for 24 ms
typically before the TPS563231 try to start again. If over-current or short-circuit fault condition still exists, hiccup
will repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe over-current
conditions, prevents over-heating and potential damage to the device.
7.3.4 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.5 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 160°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPS563231. When VEN is below its threshold (1.13 V
typically), the device is in shutdown mode. The switching regulator is turned off and the quiescent current drops
to 2.0 µA typically. The TPS563231 also employs VIN under voltage lock out protection. If VIN voltage is below its
UVLO threshold (3.6 V typically), the regulator is turned off.
7.4.2 Continuous Conduction Mode (CCM)
Continuous Conduction Mode (CCM) operation is employed when the load current is higher than half of the
peak-to-peak inductor current. In CCM operation, the frequency of operation is pseud fixed, output voltage ripple
will be at a minimum in this mode and the maximum output current of 3-A can be supplied.
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Device Functional Modes (continued)
7.4.3 Pulse Skip Mode (PSM, TPS563231)
The TPS563231 is designed with Advanced Eco-mode™ to maintain high light load efficiency. As the output
current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point
that its rippled valley touches zero level, which is the boundary between continuous conduction mode (CCM) and
discontinuous conduction mode (DCM). The low-side MOSFET is turned off when the zero inductor current is
detected. As the load current further decreases the converter runs into discontinuous conduction mode. The ontime is kept almost the same as it was in the continuous conduction mode so that it takes longer time to
discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the
switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The transition
point to the light load operation current IOUT_LL can be calculated in Equation 1.
(V
VOUT ) u VOUT
1
u IN
IOUT _ LL
2 u L u fSW
VIN
(1)
As the load current continues to decrease, the switching frequency also decreases. The on-time starts to
decrease once the switching frequency is lower than 250 kHz. The on-time can be about 22% reduced at most
for extremely light load condition. This function is employed to achieve smaller ripple at extremely light load
condition.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is typical step-down DC-DC converter. It is typically used to convert a higher dc voltage to a lower dc
voltage with a maximum available output current of 3 A. The following design procedure can be used to select
component values for the TPS563231. Alternately, the WEBENCH® software may be used to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Application
The TPS563231 only requires a few external components to convert from a higher variable voltage supply to a
fixed output voltage. Figure 13 shows a basic schematic of 3.3-V output application. This section provides the
design procedure.
VIN 12 V
BST
VIN
CIN
10 µF
CBOOT
0.1 µF
VOUT
3.3 V
L 3.3 µH
SW
EN
RFBT
45.3 NŸ
COUT
47 µF
FB
GND
RFBB
10 NŸ
Figure 13. TPS563231 3.3V/3-A Reference Design
8.2.1 Design Requirements
Table 1 shows the design parameters for this application.
Table 1. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
4.5 to 17 V
Output voltage
3.3 V
Transient response, 3-A load step
ΔVout = ±5%
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
3A
Operating frequency
600 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. 1% tolerance or better divider
resistors are recommended. Start by using Equation 2 to calculate VOUT.
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To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the FB input current will be more noticeable.
§
RFBT ·
VOUT
0.6 u ¨ 1
¸
RFBB ¹
©
(2)
Choose the value of RFBB to be 10 kΩ. With the desired output voltage set to 3.3 V and the VREF = 0.6 V, the
RFBT value can then be calculated using Equation 2. The formula yields to a value 45.3 kΩ of RFBT.
8.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP
2S L u COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP3 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of Equation 3 is located below the
high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.
Table 2. Recommended Component Values
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
MIN
TYP
MAX
C8 + C9 (µF)
1
6.65
10.0
1
1.2
4.7
20 to 68
1.05
7.5
10.0
1
1.2
4.7
20 to 68
1.2
10
10.0
1.2
1.5
4.7
20 to 68
1.5
15
10.0
1.5
1.5
4.7
20 to 68
1.8
20
10.0
1.5
2.2
4.7
20 to 68
2.5
31.6
10.0
2.2
2.2
4.7
20 to 68
3.3
45.3
10.0
2.2
3.3
4.7
20 to 68
5
73.2
10.0
3.3
4.7
4.7
20 to 68
6.5
97.6
10.0
3.3
4.7
4.7
20 to 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
VIN _ MAX VOUT
VOUT
IL _ PP
u
VIN _ MAX
L u fSW
(4)
IL _ PK
IL _ RMS
IOUT
2
IOUT
IL _ PP
2
(5)
1 2
IL _ PP
12
(6)
For this design example, the calculated peak current is 3.67 A and the calculated RMS current is 3.02 A. The
inductor used is a WE 74437349033 with a peak current rating of 12 A and an RMS current rating of 6 A.
The capacitor value and ESR determine the amount of output voltage ripple. The TPS563231 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
IC _ RMS
14
VOUT u VIN _ MAX
VOUT
12 u VIN _ MAX u L u fSW
(7)
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For this design two Murata GRM21BR61A226ME44L 22-µF/10-V output capacitors are used in parallel. The
typical ESR is 3mΩ each. The calculated RMS current is 0.39 A and each output capacitor is rated for 5 A.
8.2.2.3 Input Capacitor Selection
The TPS563231 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10-µF for the decoupling capacitor. An additional 0.1-µF
capacitor from VIN pin to GND pin is also recommended to provide additional high frequency filtering. The
capacitor voltage rating needs to be greater than the maximum input voltage, 25 V or higher voltage rating is
recommended.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BST to SW pin for proper operation. 10 V or higher
voltage rating is recommended.
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8.2.3 Application Curves
VSW [5V/div]
VSW [5V/div]
VOUT(AC) [20mV/div]
VOUT(AC) [10mV/div]
iL [1A/div]
iL [2A/div]
Time [2µs/div]
Figure 14. CCM Mode
Time [2µs/div]
Figure 15. DCM Mode
VSW [5V/div]
VIN [5V/div]
VOUT [1V/div]
VOUT(AC) [20mV/div]
iL [2A/div]
iL [1A/div]
Time [8ms/div]
Time [800µs/div]
IOUT of TPS563231: 10 mA
Figure 16. PSM Mode
Figure 17. Start-up by VIN
VEN [1V/div]
VOUT(AC) [100mV/div]
VOUT [1V/div]
iOUT [1A/div]
iL [2A/div]
Time [800µs/div]
Figure 18. Start-up by EN
16
Time [100µs/div]
Figure 19. Load Transient
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VOUT [1V/div]
VOUT [1V/div]
iL [2A/div]
iL [2A/div]
Time [20ms/div]
Figure 20. Short Protection
Time [20ms/div]
Figure 21. Short Recovery
9 Power Supply Recommendations
TPS563231 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 72%. Using that criteria, the minimum recommended input voltage is VO / 0.72.
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10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
VIN
GND
CIN
SW
RFBB
VIN
FB
SW
EN
GND
BST
RFBT
EN
Control
CBST
L
VOUT
GND
COUT
VIA (Connected to GND plane at bottom layer)
VIA (Connected to SW)
Figure 22. TPS563231 Layout
18
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS563231
Click here
Click here
Click here
Click here
Click here
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
D-CAP3, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Blu-ray is a trademark of Blu-ray Disc Association.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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19
PACKAGE OPTION ADDENDUM
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19-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS563231DRLR
ACTIVE
SOT-5X3
DRL
6
4000
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-1-260C-UNLIM
-40 to 125
3231
TPS563231DRLT
ACTIVE
SOT-5X3
DRL
6
250
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-1-260C-UNLIM
-40 to 125
3231
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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19-Nov-2019
Addendum-Page 2
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
SCALE 8.000
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
1
A
6
4X 0.5
1.7
1.5
NOTE 3
2X 1
4
3
B
1.3
1.1
6X
0.3
0.1
0.6 MAX
0.05
TYP
0.00
C
SEATING PLANE
6X
0.18
0.08
0.05 C
SYMM
SYMM
6X
6X
0.4
0.2
0.27
0.15
0.1
0.05
C A B
4223266/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4223266/A 09/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/A 09/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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