Texas Instruments | TPS3813-Q1 Processor Supervisory Circuits With Window-Watchdog (Rev. G) | Datasheet | Texas Instruments TPS3813-Q1 Processor Supervisory Circuits With Window-Watchdog (Rev. G) Datasheet

Texas Instruments TPS3813-Q1 Processor Supervisory Circuits With Window-Watchdog (Rev. G) Datasheet
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TPS3813K33-Q1, TPS3813I50-Q1
SPRS288G – MAY 2008 – REVISED OCTOBER 2019
TPS3813-Q1 Processor Supervisory Circuits With Window-Watchdog
1 Features
•
•
1
•
•
•
•
•
•
During power on, the RESET pin is asserted when
the supply voltage (VDD) becomes higher than 1.1 V.
Thereafter, the supervisory circuit monitors VDD and
keeps the RESET pin active as long as VDD remains
below the threshold voltage (VIT).
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature range
– Device HBM classification level 2
– Device CDM classification level C4B
Window-watchdog with programmable delay and
window ratio
6-Pin SOT-23 package
Supply current of 9 μA (Typ)
Power-on reset generator with a fixed delay time
of 25 ms
Precision supply-voltage monitor:
2.5 V, 3 V, 3.3 V, 5 V
Open-Drain Reset Output
An internal timer delays the return of the output to the
inactive (high) state to ensure proper system reset.
The delay time, td = 25 ms typical, begins after VDD
has risen above the threshold voltage (VIT). When the
supply voltage drops below the threshold voltage
(VIT), the output becomes active (low) again. No
external components are required. All the devices of
this family have a fixed-sense threshold voltage (VIT)
set by an internal voltage divider.
For safety-critical applications, the TPS3813-Q1
family of devices incorporate a window-watchdog with
programmable delay and window ratio. The upper
limit of the watchdog time-out can be set by either
connecting the WDT pin to GND or VDD, or by using
an external capacitor. The lower limit, and thus the
window ratio, is set by connecting the WDR pin to
GND or VDD. The RESET pin will assert a reset to the
microcontroller if the watchdog is incorrectly serviced.
2 Applications
•
•
•
•
Applications using DSPs, microcontrollers, or
microprocessors
Safety-critical systems
Automotive systems
Heating systems
The product spectrum is designed for supply voltages
of 2.5 V, 3 V, 3.3 V, and 5 V. The devices are
available in a 6-pin SOT-23 package. The devices
are characterized for operation over a temperature
range of –40°C to 125°C.
3 Description
The TPS3813-Q1 supervisory circuits provide circuit
initialization and timing supervision, primarily for
DSPs and processor-based systems.
Device Information(1)
PART NUMBER
TPS3813K33-Q1
PACKAGE
SOT-23 (6)
TPS3813I50-Q1
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Figure 1. Typical Operating Circuit
VDD
0.1 µF
0.1 µF
R
VDD
VDD
WDR
RESET
TPS3813xxx-Q1
WDT
CWP
WDI
GND
RESET
µC
I/O
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS3813K33-Q1, TPS3813I50-Q1
SPRS288G – MAY 2008 – REVISED OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 13
11 Device and Documentation Support ................. 13
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
14
14
14
14
14
14
14
12 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (December 2016) to Revision G
Page
•
Updated text for device conditions on start-up. ..................................................................................................................... 7
•
Added information to further clarify shaded areas in the Upper and Lower Boundary Visualization. .................................... 8
Changes from Revision E (October 2016) to Revision F
•
Page
Changed the part numbers in the Electrical Characteristics table and deleted references to TPS3813-Q1J25 and
TPS3813-Q1L30..................................................................................................................................................................... 5
Changes from Revision D (June 2015) to Revision E
Page
•
Added + 1 back to the twindow,typ equation in the Programming Window-Watchdog Using an External Capacitor section ... 11
•
Added the Receiving Notification of Documentation Updates section ................................................................................ 14
Changes from Revision C (September 2013) to Revision D
Page
•
Deleted the TPS38131J25-Q1 and TPS3813L30-Q1 devices from the data sheet............................................................... 1
•
Added the ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Deleted the Dissipation Ratings table ................................................................................................................................... 4
•
Changed the voltage on the VDD pin from 0.6 V to 1.1 V in the Timing Diagram figure ........................................................ 9
Changes from Revision B (May 2012) to Revision C
•
2
Page
Deleted banner stating that TPS3813K33-Q1 is Not Recommended for New Designs ........................................................ 6
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SPRS288G – MAY 2008 – REVISED OCTOBER 2019
Changes from Revision A (November 2008) to Revision B
•
Page
Changed value from 47 pF to 155 pF. ................................................................................................................................. 11
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
WDI
1
6
RESET
GND
2
5
WDR
WDT
3
4
VDD
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
2
I
Ground
RESET
6
O
Open-drain reset output
VDD
4
I
Supply voltage and supervising input
WDI
1
I
Watchdog timer input
WDR
5
I
Selectable watchdog window ratio input
WDT
3
I
Programmable watchdog delay input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD
Supply voltage (2)
VDD
IOL
Maximum low output current
IOH
IIK
IOK
RESET
–0.3
VDD + 0.3
All other pins (2)
–0.3
7
mA
Maximum high output current
–5
mA
Input clamp current (VI < 0 or VI > VDD)
±20
mA
Output clamp current (VO < 0 or VO > VDD)
±20
mA
See Thermal Information
Operating free-air temperature
–40
125
Soldering temperature
Tstg
(1)
(2)
V
5
Continuous total power dissipation
TA
UNIT
7
°C
260°C
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND. For reliable operation the device should not be operated at 7 V for more than t = 1000h
continuously.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
All pins
±500
Corner pins (1, 3, 4, and 6)
±750
Charged-device model (CDM), per AEC
Q100-011
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
at specified temperature range
MIN
MAX
UNIT
VDD
Supply voltage
2
6
V
VI
Input voltage
0
VDD + 0.3
V
VIH
High-level input voltage
VIL
Low-level input voltage
Δt/ΔV
Input transition rise and fall rate
tw
Pulse width of WDI trigger pulse
TA
Operating free-air temperature range
0.7 × VDD
V
0.3 × VDD
ns/V
125
°C
50
–40
V
100
ns
6.4 Thermal Information
TPS3813-Q1
THERMAL METRIC
(1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
202.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
164.3
°C/W
RθJB
Junction-to-board thermal resistance
54.6
°C/W
ψJT
Junction-to-top characterization parameter
44.2
°C/W
ψJB
Junction-to-board characterization parameter
54
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted).
PARAMETER
VOL
Low-level output voltage
Power up reset voltage
(1)
VIT
Negative-going input
threshold voltage (2)
Vhys
Hysteresis
IIH
High-level input current
IIL
Low-level input current
IOH
High-level output current
IDD
Supply current
Ci
Input capacitance
(1)
(2)
TEST CONDITIONS
MIN
TYP
MAX
VDD = 2 V to 6 V, IOL = 500 μA
0.2
VDD = 3.3 V IOL = 2 mA
0.4
VDD = 6 V, IOL = 4 mA
0.4
VDD ≥ 1.1 V, IOL = 50 μA
0.2
TPS3813K33-Q1
2.87
2.93
3
TPS3813I50-Q1
4.45
4.55
4.65
TPS3813K33-Q1
40
TPS3813I50-Q1
60
WDI = VDD = 6 V, WDR = VDD = 6 V
–125
125
WDT
WDT = VDD = 6 V, VDD > VIT, RESET = High
–125
125
WDI, WDR
WDI = 0 V, WDR = 0 V, VDD = 6 V
–125
125
WDT
WDT = 0 V, VDD > VIT, RESET = High
–125
125
25
VDD = 2 V output unconnected
9
13
VDD = 5 V output unconnected
20
25
VI = 0 V to VDD
V
V
V
mV
WDI, WDR
VDD = VIT + 0.2 V, VOH = VDD
UNIT
5
nA
nA
μA
pF
The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 μs/V.
To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed near to the supply terminals.
6.6 Timing Requirements
RL = 1 MΩ, CL = 50 pF, TA = –40°C to +125°C
MIN
tw
Pulse width at VDD
VDD = VIT– + 0.2 V, VDD = VIT– – 0.2 V
MAX
3
UNIT
μs
6.7 Switching Characteristics
RL = 1 MΩ, CL = 50 pF, TA = –40°C to 125°C
PARAMETER
td
Delay time
tt(out)
Watchdog time-out
TEST CONDITIONS
Upper limit
MIN
TYP
MAX
VDD ≥ VIT + 0.2 V (see Figure 8)
20
25
30
WDT = 0 V
0.2
0.25
0.3
WDT = VDD
2
2.5
3
WDT = programmable
(1)
See
WDR = 0 V, WDT = 0 V
tPHL
(1)
(2)
VDD to RESET delay
ms
1:25.8
WDR = VDD, WDT = 0 V
1:124.9
WDR = VDD, WDT = VDD
1:127.7
VIL = VIT – 0.2 V, VIH = VIT + 0.2 V
s
1:32
WDR = 0 V, WDT = programmable
WDR = VDD, WDT = programmable
Propagation (delay) time,
high-to-low-level output
ms
1:31.8
WDR = 0 V, WDT = VDD
Watchdog window ratio
(2)
UNIT
1:64.5
30
50
μs
155 pF < C(ext) < 63 nF
(C(ext) / 15.55 pF + 1) × 6.25 ms
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6.8 Typical Characteristics
20
2
18
1.75
Low-Level Output Voltage (V)
16
85°C
Supply Current (µA)
14
12
25°C
10
8
−40°C
6
0°C
4
25°C
1.25
1
0.75
85°C
0°C
0.50
−40°C
0.25
2
0
1.50
0
1
2
3
4
5
0
6
0
1
2
Supply Voltage (V)
WDI = GND
WDT = GND
WDR = GND
WDI = GND
VDD = 2 V
Figure 2. Supply Current vs Supply Voltage
5
6
7
WDT = GND
WDR = GND
1.001
600
Normalized Input Threshold Voltage (V) [25 °C]
800
25°C
400
Input Current (nA)
4
Figure 3. Low-Level Output Voltage vs Low-Level Output
Current
1000
85°C
200
0°C
0
−200
−40°C
−400
−600
−800
−1000
3
Low-Level Output Current (mA)
0
1
2
3
4
5
1.000
0.999
0.998
0.997
0.996
0.995
−40
6
−20
WDI = GND
0
20
40
60
80
Free-Air Temperature At VDD (°C)
Input Voltage at WDT (V)
WDR = GND
VDD = 6 V
WDI = Triggered
Figure 4. Input Current vs Input Voltage at WDT
WDT = GND
WDR = GND
Figure 5. Normalized Input Threshold Voltage vs Free-Air
Temperature at VDD
20
Minimum Pulse Duration at VDD (µs)
18
16
14
12
10
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Threshold Overdrive Voltage (V)
Figure 6. Minimum Pulse Duration At VDD vs VDD Threshold Overdrive Voltage
6
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7 Detailed Description
7.1 Overview
The TPS3813-Q1 devices (TPS3813K33-Q1 and TPS3813I50-Q1) are a family of supervisory circuits with
watchdog functionality. The TPS3813-Q1 family of devices is designed to assert a reset on the RESET pin when
the supply (VDD) drops below the threshold voltage (VIT) which varies depending on which device is used. When
the VDD supply rises above 1.1 V, the RESET pin output state becomes valid and is active in logic low state until
the VDD supply crosses the voltage threshold (VIT + Vhys). The watchdog window can be programmed using the
WDT and WDR pins with several different configurations, all of which are explained in the following sections.
7.2 Functional Block Diagram
RESET
Oscillator
WDT
Reset Logic
and Timer
Detection
Circuit
V DD
GND
Power to circuitry
Watchdog
Ratio
Detection
R1
+
WDR
_
R2
Bandgap
Voltage
Reference
GND
Rising Edge
Detection
WDI
GND
GND
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7.3 Feature Description
7.3.1 Implemented Window-Watchdog Settings
The watchdog window can be set up in two different ways. The first way is to use the implemented timing, which
is a default setting. The other way is to activate the default settings by wiring the WDT and WDR pin to VDD or
GND. Four different timings available with these settings which are listed in Table 1.
Table 1. Window-Watchdog Configuration Settings
SELECTED OPERATION MODE
WDR = 0 V
WDT = 0 V
WDR = VDD
WDR = 0 V
WDT = VDD
WDR = VDD
twindow
tboundary
Max = 0.3 s
Max = 9.46 ms
Typ = 0.25 s
Typ = 7.86 ms
Min = 0.2 s
Min = 6.27 ms
Max = 0.3 s
Max = 2.43 ms
Typ = 0.25 s
Typ = 2 ms
Min = 0.2 s
Min = 1.58 ms
Max = 3 s
Max = 93.8 ms
Typ = 2.5 s
Typ = 78.2 ms
Min = 2 s
Min = 62.5 ms
Max = 3 s
Max = 23.5 ms
Typ = 2.5 s
Typ = 19.6 ms
Min = 2 s
Min = 15.6 ms
See Figure 7 to visualize the values named in the table. The upper boundary of the window frame is defined by
twindow and the lower boundary of the window frame is defined by tboundary. Table 1 describes the upper and lower
boundary settings. The device must detect a rising edge at the WDI pin between tboundary,max and twindow,min to
prevent asserting a reset. The values in Table 1 are typical and worst case conditions and are valid over the
whole temperature range of –40°C to +125°C.
The shaded areas shown in Figure 7 are cases where undefined operation may happen. This device may not
detect a violation if a WDI pulse occurs within these three shaded areas. The first shaded area addresses the
situation of two consecutive rising edges occur within a quick amount of time. The typical time between rising
edges should be more than 500 µs. The second and third shaded areas are defined by the min and max
variance of the lower boundary (tboundary) and upper boundary (twindow). Set the WDI rising edge within the
tboundary,max and twindow,min for correct operation.
WDI
Detection of
Rising Edge
Window Frame to Reset the WDI
t boundary,min
t
t boundary,typ
t boundary,max
t window,min
t window,typ
t window,max
Figure 7. Upper and Lower Boundary Visualization
8
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7.3.1.1 Timing Rules of Window-Watchdog
After the reset of the supervisor is released, the lower boundary of the first WDI window is disabled. However,
after the first WDI pulse low-to-high transition is detected, the lower boundary function of the window is enabled.
All further WDI pulses must fit into the configured window frame.
The lower boundary of the watchdog window begins with the rising edge of the WDI trigger pulse. At the same
time, all internal timers are reset. If an external capacitor is used, the lower boundary is impacted because of the
different oscillator frequency. See the Programming Window-Watchdog Using an External Capacitor section for
additional details. Figure 8, especially the shaded boundary area, was prepared in a nonreal ratio scale to better
visualize the description.
VDD
VIT
1.1 V
t
td
td
td
RESET
Output Condition
Undefined
Output Condition
Undefined
t
WDI
1st Window
Without Lower
Boundary
t
2nd Window
With Lower
Boundary
3rd Window
With Lower
Boundary
Trigger Pulse
1st Window
Lower Window
Without Lower 2nd Window
1st Window
Boundary
Boundary
With Lower
Without Lower
Boundary
Boundary
3rd Window
With Lower
Boundary
Figure 8. Timing Diagram
7.3.2 Watchdog Software Considerations
To benefit from the window watchdog feature and help the watchdog timer monitor the software execution more
closely, TI recommends that the watchdog be set and reset at different points in the program rather than pulsing
the watchdog input periodically by using the prescaler of a microcontroller or DSP. Furthermore, the watchdog
trigger pulses should be set to different timings inside the window frame to release a defined reset if the program
should hang in any subroutine. This setting allows the window watchdog to detect timeouts of the trigger pulse as
well as pulses that distort the lower boundary.
7.4 Device Functional Modes
The functional mode for the TPS3813-Q1 family family of devices is either on or reset. Table 2 lists the device
truth table.
Table 2. Device States
CONDITION
VDD > VIT
VDD < VIT
Watchdog fault
STATE
RESET
On
H
Reset
L
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Lower-Boundary Calculation
The lower boundary can be calculated based on the values listed in the Switching Characteristics table.
Additionally, facts must be taken into account to verify that the lower boundary is where it is expected. Because
the internal oscillator of the window watchdog is running free, any rising edge at the WDI pin is taken into
account at the next internal clock cycle. Accounting for any rising edge at the WDI pin occurs regardless of the
external source. Because the shift between internal and external clock is not known, consider the worst-case
condition when calculating this value.
Table 3. Watchdog Lower-Boundary Calculation
SELECTED OPERATION MODE
LOWER BOUNDARY OF FRAME
tboundary,max = twindow,max / 23.5
WDR = 0 V
tboundary,typ = twindow,typ / 25.8
tboundary,min = twindow,min / 28.7
WDT = external capacitor C(ext)
tboundary,max = twindow,max / 51.6
WDR = VDD
tboundary,typ = twindow,typ / 64.5
tboundary,min = twindow,min / 92.7
8.2 Typical Application
A typical application example (see Figure 9) is used to describe the function of the watchdog in more detail.
VDD
0.1 µF
0.1 µF
VDD
R
18 kΩ
Position 1
VDD
Position 2
WDR
RESET
RESET
µC
TPS3813-Q1
Position 4
Position 5
Position 3
I/O
WDI
WDT
C(ext)
VDD
GND
GND
VDD
Figure 9. Application Example
10
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Typical Application (continued)
8.2.1 Design Requirements
Design requirements include any design parameters that are solely based on the watchdog timing desired by the
user. The Implemented Window-Watchdog Settings and Detailed Design Procedure sections describe these
timings. Select the TPS3813-Q1 device option based on desired threshold voltage of either 2.5 V, 3 V, 3.3 V, or
5 V.
8.2.2 Detailed Design Procedure
To configure the window watchdog function, two pins are provided by the TPS3813-Q1 family of devices. These
pins set the window timeout and ratio.
The window watchdog ratio is a fixed ratio, which determines the lower boundary of the window frame. This ratio
can be configured in two different frame sizes.
If the window watchdog ratio pin (WDR) is set to VDD (Position 1 in Figure 9) then the lower boundary frame is a
value based on a ratio calculation of the overall window timeout size. For the watchdog timeout pin (WDT)
connected to GND, the value is a ratio of 1:124.9, for WDT connected to VDD, the value is a ratio of 1:127.7, and
for an external capacitor connected to WDT, the value is a ratio of 1:64.5.
If the window watchdog ratio pin (WDR) is set to GND (Position 2) the lower boundary frame is a value based on
a ratio calculation of the overall window timeout size. For the watchdog timeout pin (WDT) connected to GND,
the value is a ratio of 1:31.8, for WDT connected to VDD the value is a ratio 1:32, and for an external capacitor
connected to WDT the value is a ratio of 1:25.8.
The watchdog timeout can be set in two fixed timings of 0.25 s and 2.5 s for the window or can by programmed
by connecting a external capacitor with a low leakage current at WDT.
For example, if the watchdog timeout pin (WDT) is connected to VDD, the timeout is 2.5 s. If the window
watchdog ratio pin (WDR) is set in this configuration to a ratio of 1:127.7 by connecting the pin to VDD, the lower
boundary is 19.6 ms.
8.2.2.1 Programming Window-Watchdog Using an External Capacitor
The upper boundary of the watchdog timer can be set by an external capacitor connected between the WDT pin
and GND. Common consumer electronic capacitors can be used to implement this feature. The capacitors that
are used should have low ESR and low tolerances because the tolerances must be considered to perform the
calculations. The first formula is used to calculate the upper window frame. After calculating the upper window
frame, the lower boundary can be calculated. As in the last example, the most important values are the
tboundary,max and twindow,min. The trigger pulse must fit into this window frame.
The external capacitor should have a value between a minimum of 155 pF and a maximum of 63 nF.
§ C(ext)
·
t window,typ ¨¨
1¸¸ u 6.25 ms
15.55
pF
©
¹
(1)
Table 4. Watchdog Upper-Boundary Capacitor Programming
SELECTED OPERATION MODE
WDT = external capacitor C(ext)
WDR = 0 V and WDR = VDD
WINDOW FRAME
twindow,max = 1.25 × twindow,typ
twindow,min = 0.75 × twindow,typ
Copyright © 2008–2019, Texas Instruments Incorporated
Product Folder Links: TPS3813K33-Q1 TPS3813I50-Q1
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8.2.3 Application Curve
20
18
16
85°C
Supply Current (µA)
14
12
25°C
10
8
−40°C
6
0°C
4
2
0
0
1
2
3
4
5
6
Supply Voltage (V)
WDI = GND
WDT = GND
WDR = GND
Figure 10. Supply Current vs Supply Voltage
9 Power Supply Recommendations
TPS3813-Q1 family of devices are designed to operate from an input supply with a voltage range from 2 V to
6 V. Although not required, placing a 0.1-µF ceramic capacitor close to the VDD pin is good analog design
practice.
10 Layout
10.1 Layout Guidelines
Use the following guidelines for proper layout design of the device:
• Place the VDD decoupling capacitor as close to the device as possible.
• Avoid using long traces for the VDD supply node. The VDD capacitor, along with the parasitic inductance from
the supply to the capacitor, can cause ringing if the traces are excessive.
• If using a capacitor between the WDT pin and GND pin to program the upper boundary of the windowwatchdog, the capacitor must be placed as close to the device as possible.
• Traces for WDR and WDT pins must be short and tight to avoid building up excessive parasitics.
12
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Copyright © 2008–2019, Texas Instruments Incorporated
Product Folder Links: TPS3813K33-Q1 TPS3813I50-Q1
TPS3813K33-Q1, TPS3813I50-Q1
www.ti.com
SPRS288G – MAY 2008 – REVISED OCTOBER 2019
10.2 Layout Example
Watchdog
Trigger
Input
1
RESET
Flag
6
RPU
2
5
(1)(2)
C(ext)
3
Input
Supply
4
CVDD
(1)
(1)
In this layout example, the WDR pin is tied to VDD and the WDT pin is tied to GND through an external capacitor.
(2)
The overall window timeout in this configuration is based on the external capacitor connected to the WDT pin. The
formula used to calculate this value can be found in the Detailed Design Procedure section.
NOTE: In this configuration, the ratio of the frame lower boundary is 1:64.5 (typical) of the overall window timeout size. The
maximum and minimum ratios are 1:51.6 and 1:92.7 of the overall window timeout size, respectively.
Figure 11. Device Layout
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Figure 12 shows a legend for reading the complete device name for and TPS3813-Q1 device.
TPS381
3
J
25
Q
DBV
R
Q1
Qualified for automotive applications
Reel
Package
Temperature range
Nominal supply voltage
Nominal threshold voltage
Functionality
Family
Figure 12. Device Nomenclature
Copyright © 2008–2019, Texas Instruments Incorporated
Product Folder Links: TPS3813K33-Q1 TPS3813I50-Q1
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TPS3813K33-Q1, TPS3813I50-Q1
SPRS288G – MAY 2008 – REVISED OCTOBER 2019
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• All Window–Watchdog Supervisors (SLVA365)
• Choosing an Appropriate Pull-up/Pull-down Resistor for Open Drain Outputs (SLVA485)
• Disabling the Watchdog Timer for TI’s Family of Supervisors (SLVA145)
• Window Watchdog Calculator for TPS3813 Voltage Supervisors (SPRCAG1)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS3813K33-Q1
Click here
Click here
Click here
Click here
Click here
TPS3813I50-Q1
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resource
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Copyright © 2008–2019, Texas Instruments Incorporated
Product Folder Links: TPS3813K33-Q1 TPS3813I50-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS3813I50QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PFBI
TPS3813K33QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PFBQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2019
OTHER QUALIFIED VERSIONS OF TPS3813-Q1 :
• Catalog: TPS3813
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS3813I50QDBVRQ1
SOT-23
DBV
6
3000
180.0
9.0
TPS3813K33QDBVRQ1
SOT-23
DBV
6
3000
180.0
9.0
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.15
3.2
1.4
4.0
8.0
Q3
3.15
3.2
1.4
4.0
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS3813I50QDBVRQ1
SOT-23
DBV
6
3000
182.0
182.0
20.0
TPS3813K33QDBVRQ1
SOT-23
DBV
6
3000
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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