Texas Instruments | UCCx895 BiCMOS Advanced Phase-Shift PWM Controller (Rev. Q) | Datasheet | Texas Instruments UCCx895 BiCMOS Advanced Phase-Shift PWM Controller (Rev. Q) Datasheet

Texas Instruments UCCx895 BiCMOS Advanced Phase-Shift PWM Controller (Rev. Q) Datasheet
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UCC1895, UCC2895, UCC3895
SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
UCCx895 BiCMOS Advanced Phase-Shift PWM Controller
1 Features
3 Description
•
•
•
•
The UCC3895 is a phase-shift PWM controller that
implements control of a full-bridge power stage by
phase shifting the switching of one half-bridge with
respect to the other. The device allows constant
frequency pulse-width modulation in conjunction with
resonant zero-voltage switching to provide high
efficiency at high frequencies. The part is used either
as a voltage-mode or current-mode controller.
1
•
•
•
•
•
•
Programmable-output turnon delay
Adaptive delay set
Bidirectional oscillator synchronization
Voltage-mode, peak current-mode, or average
current-mode control
Programmable soft start, soft stop, and chip
disable via a single pin
0% to 100% duty-cycle control
7-MHz error amplifier
Operation to 1 MHz
Typical 5-mA operating current at 500 kHz
Very low 150-μA current during UVLO
While the UCC3895 maintains the functionality of the
UC3875/6/7/8 family and UC3879, it improves on that
controller family with additional features such as
enhanced control logic, adaptive delay set, and
shutdown capability. Because the device is built using
the BCDMOS process, it operates with dramatically
less supply current than it’s bipolar counterparts. The
UCC3895 operates with a maximum clock frequency
of 1 MHz.
2 Applications
•
•
•
•
Phase-shifted full-bridge converters
Off-line, telecom, datacom, and servers
Distributed power architecture
High-density power modules
Device Information(1)
PART NUMBER
PACKAGE
UCCx895
BODY SIZE (NOM)
CDIP (20)
24.20 mm × 6.92 mm
LCCC (20
8.89 mm × 8.89 mm
SOIC (20)
12.80 mm × 7.50 mm
PDIP (20)
24.33 mm × 6.35 mm
TSSOP (20)
6.50 mm × 4.40 mm
PLCC (20)
8.96 mm × 8.96 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
UCC3895
1
EAN
2
EAOUT
3
Q1
EAP
20
7
SS/DISB
19
RAMP
OUTA
18
4
REF
OUTB
17
5
GND
PGND
16
6
SYNC
VDD
15
7
CT
OUTC
14
8
RT
OUTD
13
9
DELAB
CS
12
10
DELCD
ADS
11
VOUT
A
C
VIN
VBIAS
B
D
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC1895, UCC2895, UCC3895
SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Typical Characteristics ............................................ 10
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
11
11
14
17
7.5 Programming........................................................... 17
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 42
10 Layout................................................................... 42
10.1 Layout Guidelines ................................................. 42
10.2 Layout Example .................................................... 43
11 Device and Documentation Support ................. 44
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
44
44
44
44
45
45
12 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (June 2013) to Revision Q
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Changed UCC1895 VOL MAX, From 250 mV : To 300 mV in Electrical Characteristics ....................................................... 8
•
Changed UCC1895 RAMP sink current MIN, From 12 mA : To 10 mA in Electrical Characteristics .................................... 8
•
Changed the FSW note in the Detailed Design Procedure section ...................................................................................... 23
•
Changed the voltage drop across the RDS(on) from 0.5-V to 4.5-V forward voltage drop in the output rectifiers.................. 23
•
Added Output Voltage Setpoint section................................................................................................................................ 34
•
Added Setting the Switching Frequency section .................................................................................................................. 36
•
Added Soft Start section....................................................................................................................................................... 36
•
Added Setting the Switching Delays section ........................................................................................................................ 36
•
Added Setting the Slope Compensation section .................................................................................................................. 38
Changes from Revision O (April 2010) to Revision P
Page
•
Added The CS input connects to text to the beginning of the CS Detailed Pin Description. ............................................... 14
•
Added second paragraph to detailed REF Pin Description and included the UCC1895 at the end of the first
paragraph to differentiate capacitance capabilities of the devices. ...................................................................................... 16
•
Changed UCC3895 Timing Diagram in the Application Information section to reflect the maximum duty cycle conditions 19
Changes from Revision N (May 2009) to Revision O
•
2
Page
Changed REF pin description from “Do not use more than 1.0 μF of total capacitance on this pin.” to “Do not use
more than 4.7 μF of total capacitance on this pin.” .............................................................................................................. 16
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SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
5 Pin Configuration and Functions
PW AND DW PACKAGE DRAWINGS
(TOP VIEW)
N AND J PACKAGE DRAWINGS
(TOP VIEW)
PW and DW PACKAGE
(TOP VIEW)
EAN
EAOUT
RAMP
REF
GND
SYNC
CT
RT
DELAB
DELCD
1
2
3
4
5
6
7
8
9
10
EAP
SS/DISB
OUTA
OUTB
PGND
VDD
OUTC
OUTD
CS
ADS
20
19
18
17
16
15
14
13
12
11
EAN
1
20
EAP
EAOUT
2
19
SS/DISB
RAMP
3
18
OUTA
REF
4
17
OUTB
GND
5
16
PGND
SYNC
6
15
VDD
CT
7
14
OUTC
RT
8
13
OUTD
DELAB
9
12
CS
DELCD
10
11
ADS
FN AND FK PACKAGE DRAWINGS
(TOP VIEW)
EAN
EAOUT
RAMP
EAP
SS/DISB
3
2
1
20 19
REF
4
18
OUTA
GND
5
17
OUTB
SYNC
6
16
PGND
CT
7
15
VDD
RT
8
14
OUTC
9
DELAB
DELCD
10 11 12 13
OUTD
CS
ADS
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Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ADS
11
I
The adaptive-delay-set pin sets the ratio between the maximum and minimum programmed output delay
dead time.
CS
12
I
Current sense input for cycle-by-cycle current limiting and for over-current comparator.
CT
7
I
Oscillator timing capacitor for programming the switching frequency. The UCC3895 oscillator charges CT via
a programmed current.
DELAB
9
I
The delay-programming between complementary-outputs pin, DELAB, programs the dead time between
switching of output A and output B.
DELCD
10
I
The delay-programming between complementary-outputs pin, DELCD, programs the dead time between
switching of output C and output D.
EAOUT
2
I/O
EAP
20
I
Non-inverting input to the error amplifier. Keep below 3.6 V for proper operation.
EAN
1
I
Inverting input to the error amplifier. Keep below 3.6 V for proper operation.
GND
5
—
OUTA
18
O
OUTB
17
O
OUTC
14
O
OUTD
13
O
PGND
16
—
RAMP
3
I
Inverting input of the PWM comparator.
REF
4
O
5-V, ±1.2%, 5-mA voltage reference. For best performance, bypass with a 0.1-μF low ESR, low ESL
capacitor to ground. Do not use more than 4.7 μF of total capacitance on this pin.
RT
8
I
Oscillator timing resistor for programming the switching frequency.
SS/DISB
19
I
Soft-start and disable pin which combines the two independent functions.
SYNC
6
I/O
VDD
15
I
4
Error amplifier output.
Chip ground for all circuits except the output stages.
The four outputs are 100-mA complementary MOS drivers, and are optimized to drive FET driver circuits
such as UCC27714 or gate drive transformers.
Output stage ground.
The oscillator synchronization pin is bidirectional.
The power supply input pin, VDD, must be bypassed with a minimum of a 1-μF low ESR, low ESL capacitor
to ground. The addition of a 10-μF low ESR, low ESL between VDD and PGND is recommended.
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SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MAX
UNIT
Supply voltage
MIN
17
V
Output current
100
mA
Reference current
15
mA
Supply current
30
mA
Analog inputs
EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS,
SS/DISB
–0.3
REF + 0.3
V
Drive outputs
OUTA, OUTB, OUTC, OUTD
–0.3
VCC + 0.3
V
650
mW
Power dissipation at TA = 25°C
TJ
DW-20 package
N-20 package
1
W
Junction temperature
–55
150
°C
Tstg Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
NOM
10
MAX
UNIT
VDD
Supply voltage
VDD
Supply voltage bypass capacitor (2)
CREF
Reference bypass capacitor (UCC1895) (3)
0.1
1
µF
CREF
Reference bypass capacitor (UCC2895, UCC3895) (3)
0.1
4.7
µF
CT
Timing capacitor (for 500-kHz switching frequency)
RT
Timing resistor (for 500-kHz switching frequency)
RDEL_AB, RDEL_CD Delay resistor
TJ
(1)
(2)
(3)
(4)
Operating junction temperature (4)
16.5
V
10 × CREF
µF
220
pF
82
kΩ
2.5
40
kΩ
–55
125
°C
TI recommends that there be a single point grounded between GND and PGND directly under the device. There must be a separate
ground plane associated with the GND pin and all components associated with pins 1 through 12, plus 19 and 20, be located over this
ground plane. Any connections associated with these pins to ground must be connected to this ground plane.
The VDD capacitor must be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor
must be located as physically close as possible to the VDD pins.
The VREF capacitor must be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is
desired for the VREF then it must be located near the VREF cap and connected to the VREF pin with a resistor of 51 Ω or greater. The bulk
capacitor on VDD must be a factor of 10 greater than the total VREF capacitance.
TI does not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.
Copyright © 1999–2019, Texas Instruments Incorporated
Product Folder Links: UCC1895 UCC2895 UCC3895
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6.4 Thermal Information
UCC2895
UCC3895
UCC1895
THERMAL METRIC
(1)
UCC2895
UCC3895
UCC3895
J
(CDIP)
FK
(LCCC)
DW
(SOIC)
PW
(TSSOP)
FN
(PLCC)
N
(PDIP)
UNIT
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
N/A
N/A
66.4
91.0
54.8
48.6
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
34.2
31.2
31.6
26.1
32.8
35.6
°C/W
RθJB
Junction-to-board thermal resistance
48.9
30.9
34.1
42.2
19.0
29.6
°C/W
ψJT
Junction-to-top characterization
parameter
N/A
N/A
8.6
1.3
9.0
16.0
°C/W
ψJB
Junction-to-board characterization
parameter
N/A
N/A
33.7
41.6
18.7
29.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
8.9
3.3
N/A
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the
outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to 85°C for UCC2895x and TA = –55°C to 125°C for the
UCC1895x (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.2
11
11.8
V
8.2
9
9.8
V
1
2
3
V
150
250
µA
5
6
mA
UVLO (UNDERVOLTAGE LOCKOUT)
UVLO(on)
Start-up voltage threshold
UVLO(off)
Minimum operating voltage after start-up
UVLO(hys)
Hysteresis
SUPPLY
ISTART
Start-up current
IDD
Operating current
VDD_CLAMP
VDD clamp voltage
VDD = 8 V
IDD = 10 mA
16.5
17.5
18.5
TJ = 25°C
4.94
5
5.06
4.85
5
5.15
10
20
V
VOLTAGE REFERENCE
VREF
Output voltage
10 V < VDD < VDD_CLAMP,
0 mA < IREF < 5 mA,
temperature
ISC
Short circuit current
REF = 0 V, TJ = 25°C
V
mA
ERROR AMPLIFIER
–0.1
3.6
VIO
Common-mode input voltage range
Offset voltage
–7
7
mV
IBIAS
Input bias current (EAP, EAN)
–1
1
µA
EAOUT_VOH
High-level output voltage
EAP – EAN = 500 mV, IEAOUT = –0.5 mA
4
4.5
5
V
EAOUT_VOL
Low-level output voltage
EAP – EAN = –500 mV, IEAOUT = 0.5 mA
0
0.2
0.4
ISOURCE
Error amplifier output source current
EAP – EAN = 500 mV, EAOUT = 2.5 V
1
1.5
mA
ISINK
Error amplifier output sink current
EAP – EAN = –500 mV, EAOUT = 2.5 V
2.5
4.5
mA
AVOL
Open-loop dc gain
75
85
dB
GBW
Unity gain bandwidth (1)
5
7
mHz
1.5
2.2
V/µs
No-load comparator turn-off threshold
0.45
0.5
0.55
V
No-load comparator turn-on threshold
0.55
0.6
0.69
V
1 V < EAN < 0 V, EAP = 500 mV,
0.5 V < EAOUT < 3 V
Slew rate (1)
(1)
6
V
V
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the
outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to 85°C for UCC2895x and TA = –55°C to 125°C for the
UCC1895x (unless otherwise noted)
PARAMETER
TEST CONDITIONS
No-load comparator hysteresis
MIN
TYP
MAX
UNIT
0.035
0.1
0.165
V
OSCILLATOR
fOSC
Frequency
TJ = 25°C
Frequency total variation
Over line, temperature
473
VIH_SYNC
SYNC input threshold, SYNC
VOH_SYNC
High-level output voltage, SYNC
ISYNC = –400 μA, VCT = 2.6 V
VOL_SYNC
Low-level output voltage, SYNC
ISYNC = 100 μA, VCT = 0 V
Sync output pulse width
LOADSYNC = 3.9 kΩ and 30 pF in parallel
VRT
Timing resistor voltage
VCT(peak)
Timing capacitor peak voltage
VCT(valley)
Timing capacitor valley voltage
500
527
2.5%
5%
kHz
2.05
2.1
2.4
V
4.1
4.5
5
V
0
0.5
1
V
85
135
ns
2.9
3
3.1
V
2.25
2.35
2.55
V
0
0.2
0.4
V
20
µA
CURRENT SENSE
ICS(bias)
0 V < CS < 2.5 V,
0 V ADS < 2.5 V
Current sense bias current
Peak current threshold
Overcurrent threshold
Current sense to output delay
–4.5
1.9
2
2.1
V
2.4
2.5
2.6
V
75
110
ns
0 V ≤ CS ≤ 2.3 V,
DELAB = DELCD = REF
SOFT START/SHUTDOWN
ISOURCE
Soft-start source current
SS/DISB = 3.0 V,
CS = 1.9 V
–40
–35
–30
µA
ISINK
Soft-start sink current
SS/DISB = 3.0 V,
CS = 2.6 V
325
350
375
µA
0.44
0.5
0.56
V
0.45
0.5
0.55
Soft-start/disable comparator threshold
ADAPTIVE DELAY SET (ADS)
ADS = CS = 0 V
tDELAY
(2)
DELAB/DELCD output voltage
ADS = 0 V,
CS = 2 V
1.9
2
2.1
V
Output delay (1) (2)
ADS = CS = 0 V
450
560
620
ns
ADS bias current
0 V < ADS < 2.5 V,
0 V < CS < 2.5 V
–20
20
µA
Output delay is measured between OUTA and OUTB, or OUTC and OUTD. Output delay is defined as shown below where: tf(OUTA) =
falling edge of OUTA signal, tr(OUTB) = rising edge of OUTB signal (see Figure 1 and Figure 2).
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Electrical Characteristics (continued)
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the
outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to 85°C for UCC2895x and TA = –55°C to 125°C for the
UCC1895x (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
OUTPUT
VOH
High-level output voltage (all outputs)
IOUT = –10 mA, VDD to output
250
400
VOL
Low-level output voltage (all outputs)
IOUT = 10 mA
UCC1895
150
300
UCC2895, UCC3895
150
250
tR
Rise time (1)
CLOAD = 100 pF
20
35
ns
CLOAD = 100 pF
20
35
ns
0.85
1.05
V
0.0% 0.85%
1.4%
70
120
ns
5
µA
tF
Fall time
(1)
mV
PWM COMPARATOR
EAOUT to RAMP input offset voltage
RAMP = 0 V,
DELAB = DELCD = REF
Minimum phase shift (3)
(OUTA to OUTC, OUTB to OUTD)
RAMP = 0 V,
EAOUT = 650 mV
tDELAY
Delay (2)
(RAMP to OUTC, RAMP to OUTD)
0 V < RAMP < 2.5 V, EAOUT = 1.2 V,
DELAB = DELCD = REF
IR(bias)
RAMP bias current
RAMP < 5 V, CT = 2.2 V
IR(sink)
(3)
RAMP = 5 V,
CT = 2.6 V
RAMP sink current
Minimum phase shift is defined as:
F = 180 ´
(a)
(b)
(c)
(d)
(e)
t f (OUTC ) - t f (OUTA )
tPERIOD
or F = 180 ´
0.72
–5
UCC1895
10
19
UCC2895, UCC3895
12
19
mA
t f (OUTC ) - t f (OUTB )
tPERIOD
where
tf(OUTA) = falling edge of OUTA signal
tf(OUTB) = falling edge of OUTB signal
tf(OUTC) = falling edge of OUTC signal
tf(OUTD) = falling edge of OUTD signal
tPERIOD = period of OUTA or OUTB signal
tPERIOD
OUTA
tDELAY = tf(OUTA) - tf(OUTC)
OUTC
Figure 1. Same Applies to OUTB and OUTD
8
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OUTA
tDELAY = tR(OUTB) - tf(OUTA)
OUTB
Figure 2. Same Applies to OUTC and OUTD
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6.6 Typical Characteristics
2000
1600
1400
Oscillator Frequency (kHz)
Vcs = 2 V
1600
1400
1200
1000
800
600
400
1200
1000
800
600
400
200
200
0
0
0
10
20
30
40
Delay Resistance (k
100
1000
Timing Capacitance (pF)
C001
Figure 3. Output Delay (tDELAY) vs
Delay Resistance (RDEL)
Figure 4. Oscillator Frequency (fSW) vs
Timing Capacitance (CT)
1.00
100
200
80
160
60
120
40
80
0.95
Gain (dB)
EAOUT to Ramp Offset (V)
C002
0.90
0.85
20
Phase Margin (°)
Output Delay (ns)
RT = 47 k
RT = 62 k
RT = 82 k
RT = 100 k
Vcs = 0 V
1800
40
Gain (dB)
Phase Margin (°C)
0
0.80
±60
±40
0
±20
20
40
60
80
100
1
120
Temperature (ƒC)
10
10k
100k
1M
0
10M
Frequency (Hz)
C004
Figure 6. Amplifier Gain and Phase Margin vs
Frequency (fOSC)
13
Vdd = 10 V
Vdd = 12 V
Vdd = 15 V
Vdd = 17 V
8
1k
C003
Figure 5. EAOUT to Ramp Offset (VOFFSET) vs
Temperature (TA)
9
100
Vdd = 10 V
Vdd = 12 V
Vdd = 15 V
Vdd = 17 V
12
11
Idd (mA)
Idd (mA)
10
7
6
9
8
7
6
5
5
4
4
0
400
800
1200
Oscillator Frequency (kHz)
Figure 7. Input Current (IDD) vs
Oscillator Frequency (fOSC)
10
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1600
0
400
800
1200
Oscillator Frequency (kHz)
C005
1600
C006
Figure 8. Input Current (IDD) vs
Oscillator Frequency (fOSC)
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7 Detailed Description
7.1 Overview
The UCC3895 device combines all the functions necessary to control a phase-shifted full bridge power stage in a
20-pin package. It includes all the outputs needed to drive the four switches in the full-bridge circuit. The dead
times between the upper and lower switches in the full bridge may be set using the DELAB and DELCD inputs.
Further, this dead time may be dynamically adjusted according to the load level using the ADS pin allowing the
user to optimize the dead time for their particular power circuit and to achieve ZVS over the entire operating
range. At light loads a no-load comparator forces cycle skipping to maintain output voltage regulation. At higherpower levels, two or more UCC3895 devices may be easily synchronized for parallel operation. The SS/DISB
input may be used to set the length of the soft-start process and to turn the controller on and off. The controller
may be used in Voltage mode or Current mode control and cycle-by-cycle current limiting is provided in both
modes. The switching frequency may be set over a wide range making this device suited to both IGBT and
MOSFET based designs.
7.2 Functional Block Diagrams
+
VOUT
VIN
CIN
-
UCC3895
EAP 20
1
EAN
2
EAOUT SS/DISB 19
3
RAMP
OUTA 18
A
4
REF
OUTB 17
B
5
GND
PGND 16
6
SYNC
VDD 15
QC
DB
C
T1
LS
DC
CT
OUTC
14
C
8
RT
OUTD 13
D
9
DELAB
CS 12
10
DELCD
ADS 11
7
QA
A
QB
QD
D
B
VOUT
+
-
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Figure 9. Simplified Application Diagram
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Functional Block Diagrams (continued)
IRT
RT
Q
8
CT
7
Q
Q
6
PWM
COMPARATOR
RAMP
0.8 V
EAOUT
EAP
EAN
R Q
DELAY B
D S Q
DELAY C
OUTA
9
DELAB
17
OUTB
+
ERROR
AMP
20
NO LOAD
COMPARATOR
+
+
1
CURRENT SENSE
COMPARATOR
R Q
14
DELAY D
OUTC
10
DELCD
13
OUTD
16
PGND
11
ADS
4
REF
5
GND
0.5 V / 0.6 V
+
12
2.5 V
+
OVER CURRENT
COMPARATOR
ADAPTIVE DELAY SET
AMPLIFIER
+
REF
Q
S
Q
R
HI=ON
+
0.5 V
+
19
11 V / 9 V
REF
REFERENCE OK
COMPARATOR
HI=ON
10(IRT)
0.5V
UVLO COMPARATOR
DISABLE
COMPARATOR
IRT
SS
18
DELAY A
2
2V
CS
D S Q
+
3
VDD
OSC
R
SYNC
15
D S Q
8(IRT)
4V
+
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Figure 10. Block Diagram
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Functional Block Diagrams (continued)
REF
VREF
8IRT
RT
IRT
RT
CT
2.5 V
S
CLOCK
Q
+
CT
+
0.2 V
R
SYNC
CLOCK
Figure 11. Oscillator Block Diagram
REF
0.5 V
100 k:
75 k:
TO DELAY A
AND DELAY B
BLOCKS
+
DELAB
CS
+
100 k:
ADS
REF
75 k:
+
TO DELAY C
AND DELAY D
BLOCKS
DELCD
Figure 12. Adaptive Delay Set Block Diagram
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Functional Block Diagrams (continued)
REF
BUSSED CURRENT
FROM ADS CIRCUIT
3.5 V
DELAB/CD
FROM PAD
DELAYED
CLOCK
SIGNAL
2.5 V
CLOCK
Figure 13. Delay Block Diagram (One Delay Block Per Outlet)
7.3 Feature Description
7.3.1 ADS (Adaptive Delay Set)
This function sets the ratio between the maximum and minimum programmed output-delay dead time. When the
ADS pin is directly connected to the CS pin, no delay modulation occurs. The maximum delay modulation occurs
when ADS is grounded. In this case, delay time is four-times longer when CS = 0 than when CS = 2 V (the peakcurrent threshold), ADS changes the output voltage on the delay pins DELAB and DELCD by Equation 1.
VDEL = éë0.75 ´ (VCS - VADS )ùû + 0.5 V
where
•
VCS and VADS are in volts
(1)
ADS must be limited to between 0 V and 2.5 V and must be less-than or equal-to CS. DELAB and DELCD are
clamped to a minimum of 0.5 V.
7.3.2 CS (Current Sense)
The CS input connects to the inverting input of the current-sense comparator and the non-inverting input of the
overcurrent comparator and the ADS amplifier. The current sense signal is used for cycle-by-cycle current
limiting in peak current-mode control, and for overcurrent protection in all cases with a secondary threshold for
output shutdown. An output disable initiated by an overcurrent fault also results in a restart cycle, called soft stop,
with full soft start.
7.3.3 CT (Oscillator Timing Capacitor)
The UCC3895 oscillator charges CT via a programmed current. The waveform on CT is a sawtooth, with a peak
voltage of 2.35 V. The approximate oscillator period is calculated by Equation 2.
5 ´ R T ´ CT
t OSC =
+ 120 ns
48
where
•
•
•
•
14
CT is in Farads
RT is in Ohms
tOSC is in seconds
CT can range from 100 to 880 pF
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Feature Description (continued)
NOTE
A large CT and a small RT combination results in extended fall times on the CT waveform.
The increased fall time increases the SYNC pulse width, hence limiting the maximum
phase shift between OUTA, OUTB and OUTC, OUTD outputs, which limits the maximum
duty cycle of the converter (see Figure 11).
7.3.4 DELAB and DELCD (Delay Programming Between Complementary Outputs)
DELAB programs the dead time between switching of OUTA and OUTB. DELCD programs the dead time
between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the
external bridge. The UCC3895 allows the user to select the delay, in which the resonant switching of the external
power stages takes place. Separate delays are provided for the two half-bridges to accommodate differences in
resonant-capacitor charging currents. The delay in each stage is set according to Equation 3.
(25 ´ 10 )´ R
-12
DEL
tDELAY =
VDEL
+ 25 ns
where
•
•
•
VDEL is in volts
RDEL is in Ohms
tDELAY is in seconds
(3)
DELAB and DELCD source about 1-mA maximum. Choose the delay resistors so that this maximum is not
exceeded. Programmable output delay is defeated by tying DELAB and, or, DELCD to REF. For an optimum
performance keep stray capacitance on these pins at less than 10 pF.
7.3.5 EAOUT, EAP, and EAN (Error Amplifier)
EAOUT connects internally to the non-inverting input of the PWM comparator and the no-load comparator.
EAOUT is internally clamped to the soft-start voltage. The no-load comparator shuts down the output stages
when EAOUT falls below 500 mV, and allows the outputs to turn on again when EAOUT rises above 600 mV.
EAP is the non-inverting and the EAN is the inverting input to the error amplifier.
7.3.6 OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
The four outputs are 100-mA complementary MOS drivers, and are optimized to drive MOSFET driver circuits.
OUTA and OUTB are fully complementary, (assuming no programming delay) and operate near 50% duty cycle
and one-half the oscillator frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external
power stage. OUTC and OUTD drive the other half-bridge and have the same characteristics as OUTA and
OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB.
NOTE
Changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB
requires other than the nominal 50% duty ratio on OUTC and OUTD during those
transients.
7.3.7 PGND (Power Ground)
To keep output switching noise from critical analog circuits, the UCC3895 has two different ground connections.
PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically tied
together. Also, because PGND carries high current, board traces must be low impedance.
7.3.8 RAMP (Inverting Input of the PWM Comparator)
This pin receives either the CT waveform in voltage and average current-mode controls, or the current signal
(plus slope compensation) in peak current-mode control.
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Feature Description (continued)
7.3.9 REF (Voltage Reference)
The 5-V ± 1.2% reference supplies power to internal circuitry, and also supplies up to 5 mA to external loads.
The reference is shutdown during undervoltage lockout but is operational during all other disable modes. For
best performance, bypass with a 0.1-μF low-ESR low-ESL capacitor to GND. To ensure the stability of the
internal reference, do not use more than 1 μF of total capacitance on this pin for the UCC1895.
For the UCC2895 and the UCC3895, this capacitance increases as per the limits defined in the Recommended
Operating Conditions of this specification.
7.3.10 RT (Oscillator Timing Resistor)
The oscillator in the UCC3895 operates by charging an external timing capacitor, CT, with a fixed current
programmed by RT. RT current is calculated with Equation 4.
3V
IRT (A ) =
RT (W )
(4)
RT ranges from 40 kΩ to 120 kΩ. Soft-start charging and discharging currents are also programmed by IRT (Refer
to Figure 11).
7.3.11 GND (Analog Ground)
This pin is the chip ground for all internal circuits except the output stages.
7.3.12 SS/DISB (Soft Start/Disable)
This pin combines two independent functions.
Disable Mode: A rapid shutdown of the chip is accomplished by externally forcing SS/DISB below 0.5 V,
externally forcing REF below 4 V, or if VDD drops below the undervoltage lockout threshold. In the case of REF
being pulled below 4 V or an undervoltage condition, SS/DISB is actively pulled to ground via an internal
MOSFET switch.
If an overcurrent fault is sensed (CS = 2.5 V), a soft stop is initiated. In this mode, SS/DISB sinks a constant
current of (10 × IRT). The soft stop continues until SS/DISB falls below 0.5 V. When any of these faults are
detected, all outputs are forced to ground immediately.
NOTE
If SS/DISB is forced below 0.5 V, the pin starts to source current equal to IRT. The only
time the part switches into low IDD current mode, though, is when the part is in
undervoltage lockout.
Soft Start Mode: After a fault or disable condition has passed, VDD is above the start threshold, and, or,
SS/DISB falls below 0.5 V during a soft stop, SS/DISB switches to a soft-start mode. The pin then sources
current, equal to IRT. A user-selected resistor/capacitor combination on SS/DISB determines the soft-start time
constant.
NOTE
SS/DISB actively clamps the EAOUT pin voltage to approximately the SS/DISB pin
voltage during soft-start, soft-stop, and disable conditions.
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Feature Description (continued)
7.3.13 SYNC (Oscillator Synchronization)
This pin is bidirectional (refer to Figure 11). When used as an output, SYNC is used as a clock, which is the
same as the internal clock of the device. When used as an input, SYNC overrides the internal oscillator of the
chip and acts as the clock signal. This bidirectional feature allows synchronization of multiple power supplies.
Also, the SYNC signal internally discharge the CT capacitor and any filter capacitors that are present on the
RAMP pin. The internal SYNC circuitry is level sensitive, with an input-low threshold of 1.9 V, and an input-high
threshold of 2.1 V. A resistor as small as 3.9 kΩ may be tied between SYNC and GND to reduce the sync pulse
width.
7.3.14 VDD (Chip Supply)
This is the input pin to the chip. VDD must be bypassed with a minimum of 1-μF low ESR, low ESL capacitor to
ground. The addition of a 10-μF low ESR, low ESL between VDD and PGND is recommended.
7.4 Device Functional Modes
The UCC3895 has a number of operational modes. These modes are described in detail in Feature Description
section.
• Current mode - The UCC3895 device may be operated in current mode control. The CS pin is connected to
the current sense signal plus slope compensation. The RAMP pin is connected to the CS pin.
• Voltage mode - The UCC3895 may be operated in voltage mode control. The RAMP pin is connected to the
signal at CT.
• Light load mode - Under light load conditions the signal at the EAOUT pin can fall below the threshold of the
No-Load-Comparator. When this happens the UCC3895 maintains output regulation by skipping cycles.
• Synchronized mode - Multiple UC3895 devices may be synchronised to each other or to an external clock
signal.
• Disable mode - The device will stop if the EN/DISB pin is pulled below 0.5 V.
• Soft-start mode - This mode protects the power stage from excessive stresses during the start-up process.
7.5 Programming
7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
The UCC3895 allows the user to set the delay between switch commands within each leg of the full-bridge
power circuit according to Equation 5.
(25 ´ 10 )´ R
-12
DEL
tDELAY =
VDEL
+ 25 ns
(5)
From Equation 5 VDEL is determined in conjunction with the desire to use (or not) the ADS feature from
Equation 6.
VDEL = éë0.75 ´ (VCS - VADS )ùû + 0.5 V
(6)
Figure 14 illustrates the resistors needed to program the delay periods and the ADS function.
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Programming (continued)
UCC3895
9
DELAB
10
DELCD
CS
12
ADS
11
RDELAB
RDELCD
Figure 14. Programming Adaptive Delay Set
The ADS allows the user to vary the delay times between switch commands within each of the two legs of the
converter. The delay-time modulation is implemented by connecting ADS (pin 11) to CS, GND, or a resistive
divider from CS through ADS to GND to set VADS as shown in Figure 14. From Equation 6 for VDEL, if ADS is tied
to GND then VDEL rises in direct proportion to VCS, causing a decrease in tDELAY as the load increases. In this
condition, the maximum value of VDEL is 2 V.
If ADS is connected to a resistive divider between CS and GND, the term (VCS – VADS) becomes smaller,
reducing the level of VDEL. This reduction decreases the amount of delay modulation. In the limit of ADS tied to
CS, VDEL = 0.5 V and no delay modulation occurs. Figure 15 graphically shows the delay time versus load for
varying adaptive delay set feature voltages (VADS).
In the case of maximum delay modulation (ADS = GND), when the circuit goes from light load to heavy load, the
variation of VDEL is from 0.5 to 2 V. This change causes the delay times to vary by a 4:1 ratio as the load is
changed.
The ability to program an adaptive delay is a desirable feature because the optimum delay time is a function of
the current flowing in the primary winding of the transformer, and changes by a factor of 10:1 or more as circuit
loading changes. Reference 7 (see the Related Documentation section) describes the many interrelated factors
for choosing the optimum delay times for the most efficient power conversion, and illustrates an external circuit to
enable ADS using the UC3879. Implementing this adaptive feature is simplified in the UCC3895 controller, giving
the user the ability to tailor the delay times to suit a particular application with a minimum of external parts.
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Programming (continued)
DELAY TIME
vs
CURRENT SENSE VOLTAGE
A = VADS/VCS RDELAY = 10k
A=1.0
DELAY TIME (ns)
500
400
A=0.8
300
A=0.6
200
100
0
0.5
1.0
1.5
A=0.4
A=0.2
A=0.1
2.0
2.5
CURRENT SENSE VOLTAGE (V)
Figure 15. Delay Time Under Varying ADS Voltages
CLOCK
RAMP
&
COMP
PWM
SIGNAL
OUTPUT A
OUTPUT B
OUTPUT C
OUTPUT D
No Output Delay Shown, COMP to RAMP offset not included.
Figure 16. UCC3895 Timing Diagram
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A simplified electrical diagram of this converter is shown in Figure 18. The controller device is located on the
primary side of converter to allow easy bias power generation.
The power stage includes primary side MOSFETs, QA, QB, QC and QD. Diode rectification is used here for
simplicity but synchronous rectification is also possible and is described in application notes SLUU109 Using the
UCC3895 in a Direct Control Driven Synchronous Rectifier Applications and SLUA287 Control Driven
Synchronous Rectifiers In Phase Shifted Full Bridge Converters. The centre-tapped rectifier scheme with L-C
output filter is a popular choice for the 12-V output converters in server power supplies.
The major waveforms of the phase-shifted converter during normal operation are shown in Figure 17. The upper
four waveforms show the output drive signals of the controller. Current, IPR, is the current flowing through the
primary winding of the power transformer. The bottom two waveforms show the voltage at the output inductor,
VLOUT, and the current through the output inductor, ILOUT. ZVS is an important feature for high input voltage
converters in reducing switching losses associated with the internal parasitic capacitances of power switches and
transformers. The controller ensures ZVS conditions over the entire load current range by adjusting the delay
time between the primary MOSFETs switching in the same leg in accordance to the load variation. At light loads
the output of the error amplifier (EAOUT) will drop below the threshold of the No-Load Comparator and the
controller will enter a pulse skipping mode.
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Application Information (continued)
TSW(nom)
TABSET2
OUTA
TABSET1
TCDSET2
OUTB
TSW(osc)
OUTC
TCDSET1
OUTD
IPR
VOUTx(1-D) /D
VLOUT
VOUT
ILOUT
IOUT
Figure 17. Major Waveforms of Phase-Shifted Converter
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8.2 Typical Application
A typical application for the UCC3895 device is a controller for a phase-shifted full-bridge converter that converts
a 390-VDC input to a regulated 12-V output.
+
RG
CT
VOUT
VIN
CIN
50
UCC3895
RR
1
-
DA
RCS
RH
RLF
EAN
EAP 20
CF
2
EAOUT SS/DISB 19
3
RAMP
OUTA 18
A
4
REF
OUTB 17
B
RF
RA
½ UCC27714
GND
PGND 16
6
SYNC
VDD 15
7
CT
Q1
QC
HO
CT
RSLC
OUTC 14
8
RT
OUTD 13
½ UCC27714
D
RAB
9
DELAB
CS 12
RCD
10
DELCD
ADS 11
HI
QB
QD
½ UCC27714
LOUT
LI
CE
RADSH
CRAMP
HO
DC
C
B
RT
C
T1
LS
CVDD
RJ
½ UCC27714
DB
HI
RD
5
QA
A
CREF
CLF
RLOOP
U2
CSS
D
LO
LO
U1
LI
VOUT
TL431
D1
+
D2
RB
COUT
RADSL
-
Figure 18. UCC3895 Typical Application
8.2.1 Design Requirements
Table 1 lists the requirements for this application.
Table 1. UCC3895 Typical Application Design Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
370
390
410
V
2
A
12.6
V
INPUT CHARACTERISTICS
VIN
DC input voltage range
IIN(max)
Maximum input current
VIN= 370 VDC to 410 VDC
OUTPUT CHARACTERISTICS
VOUT
Output voltage
VIN= 370 VDC to 410 VDC
IOUT
Output current
VIN= 370 VDC to 410 VDC
Output voltage transient
90% load step
Continuous output power
VIN= 370 VDC to 410 VDC
600
W
Load regulation
VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A
140
mV
Line regulation
VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A
140
mV
Output ripple voltage
VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A
200
mV
POUT
11.4
12
50
600
A
mV
SYSTEM
FSW
Switching frequency
Full-load efficiency
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100
VIN= 370 VDC to 410 VDC, POUT= 500 W
92%
kHz
93%
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8.2.2 Detailed Design Procedure
The phase-shifted full-bridge converter topology is well suited to high-power server applications. This is because
the phase-shifted, full-bridge converter can obtain zero-voltage switching on the primary side of the converter,
reducing switching losses and EMI and increasing overall efficiency. This is a review of the design of a 600-W,
phase-shifted, full-bridge converter for one of these power systems using TI's UCC3895 device. The review is
based on typical values. In a production design, the values may need to be modified for worst-case conditions.
NOTE
FSW refers to the switching frequency applied to the power transformer. The oscillator on
the UCC2895 is set to 2 × FSW. The output inductor also experiences a switching
frequency which is 2 × FSW.
8.2.2.1 Power Loss Budget
To meet the efficiency goal a power loss budget needs to be set.
æ 1- h ö
PBUDGET = POUT ´ ç
÷ » 52W
è h ø
(7)
8.2.2.2 Preliminary Transformer Calculations (T1)
Transformer turns ratio (a1):
a1 =
NP
NS
(8)
The voltage drop across the RDS(on) of the primary side FETs is negligible. We assume a 0.5-V forward voltage
drop in the output rectifiers.
Vf = 0.45V
(9)
Select transformer turns based on 70% duty cycle (DMAX) at minimum specified input voltage. This will give some
room for dropout if a PFC front end is used.
a1 =
NP
NS
(10)
´ DMAX
V
» 21
a1 = INMIN
VOUT - Vf
(11)
Turns ratio rounded to the nearest whole turn.
a1 = 21
(12)
Calculated typical duty cycle (DTYP) based on average input voltage.
(V + Vf )´ a1
» 0.66
DTYP = OUT
VIN
(13)
Output inductor peak-to-peak ripple current is set to 20% of the output current.
DILOUT =
POUT ´ 0.2
= 10 A
VOUT
(14)
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Care must be taken in selecting the correct amount of magnetizing inductance (LMAG). The following equations
calculate the minimum magnetizing inductance of the primary of the transformer (T1) to ensure the converter
operates in current-mode control. As LMAG reduces, the increasing magnetizing current becomes an increasing
proportion of the signal at the CS pin. If the magnetizing current increases enough it can swamp out the current
sense signal across RCS and the converter will operate increasingly as if it were in voltage mode control rather
than current mode.
LMAG ³
VIN ´ (1 - DTYP )
» 2.78mH
DILOUT ´ 0.5
´ 2 ´ FSW
a1
(15)
Figure 19 shows the transformer primary and secondary currents during normal operation.
IPP
IMP2
IMP
IMP2 C /PP - 4ILOUT/(2 a1)
0A
IPS
IMS2
IMS
IMS C /PS + 4ILOUT/2
0A
4ILOUT/2
0A
TON
TOFF
Figure 19. T1 Primary and Secondary Currents
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Calculate T1 secondary RMS current (ISRMS):
IPS =
POUT DILOUT
+
» 55 A
VOUT
2
(16)
POUT DILOUT
» 45 A
VOUT
2
(17)
ΔI
- LOUT » 50 A
2
(18)
IMS =
IMS2 = IPS
Secondary RMS current (ISRMS1) when energy is being delivered to the secondary: (OUTA = OUTD = HI or
OUTB = OUTC = HI).
(I - I )
æD
öé
ISRMS1 = ç MAX ÷ êIPS ´ IMS + PS MS
3
è 2 ø êë
2
ù
ú » 29.6 A
úû
(19)
Secondary RMS current (ISRMS2) during freewheeling period: (OUTA = OUTC = HI or OUTB = OUTD = HI).
(I - I )
æ 1 - DMAX ö é
êIPS ´ IMS2 + PS MS2
= ç
÷
2
3
è
ø êë
2
ISRMS2
ù
ú » 20.3 A
úû
(20)
Secondary RMS current (ISRMS3) caused by the negative current in the opposing winding during freewheeling
period, please refer to Figure 19.
ISRMS3 =
DILOUT æ 1 - DMAX ö
ç 2 ´ 3 ÷ » 1.1A
2
è
ø
(21)
Total secondary RMS current (ISRMS):
ISRMS = ISRMS12 + ISRMS22 + ISRMS3 2 » 36.0 A
(22)
Calculate T1 Primary RMS Current (IPRMS):
D ILMAG =
VINMIN ´ DMAX
» 0.47 A
LMAG ´ 2 ´ FSW
(23)
æ P
DI
IPP = ç OUT + LOUT
2
è VOUT ´ h
ö1
÷ + DILMAG » 3.3 A
ø a1
(24)
æ P
DI
IMP = ç OUT - LOUT
2
è VOUT ´ h
ö1
÷ + DILMAG » 2.8A
ø a1
(25)
é
(IPP - IMP )2 ùú
ê
IPRMS1 = (DMAX ) IPP ´ IMP +
» 2.5 A
ê
ú
3
ë
û
(26)
æ DI
ö1
IMP2 = IPP - ç LOUT ÷ » 3.0 A
è 2 ø a1
(27)
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T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary.
é
(IPP - IMP )2 ùú
ê
IPRMS1 = (DMAX ) IPP ´ IMP +
» 2.5 A
ê
ú
3
ë
û
(28)
T1 Primary RMS (IPRMS2) current when the converter is free wheeling.
IPRMS2
2
é
IPP - IMP2 ) ù
(
ú » 1.7 A
= (1 - DMAX )êIPP ´ IMP2 +
3
êë
úû
(29)
Total T1 primary RMS current (IPRMS):
IPRMS = IPRMS12 + IPRMS22 » 3.1A
(30)
We select a transformer with the following specifications:
a1= 21
LMAG = 2.8mH
(31)
(32)
Transformer Primary DC resistance:
DCRP = 0.215 W
(33)
Transformer Secondary DC resistance:
DCRS = 0.58 W
(34)
Estimated transformer core losses (PT1) are twice the copper loss.
NOTE
This is just an estimate and the total losses may vary based on magnetic design.
(
)
PT1 » 2 ´ IPRMS 2 ´ DCRP + 2 ´ ISRMS 2 ´ DCRS » 7.0 W
(35)
Calculate remaining power budget:
PBUDGET = PBUDGET - PT1 » 45W
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8.2.2.3 QA, QB, QC, QD FET Selection
In this design to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineon are chosen
for QA..QD.
FET drain to source on resistance:
Rds(on)QA = 0.220 W
(37)
FET Specified COSS:
COSS _ QA _ SPEC = 780pF
(38)
Voltage across drain-to-source (VdsQA) where COSS was measured, data sheet parameter:
VdsQA = 25 V
(39)
Calculate average Coss [2]:
COSS _ QA _ AVG = COSS _ QA _ SPEC
VdsQA
» 193pF
VINMAX
(40)
QA FET gate charge:
QA g = 15nC
(41)
Voltage applied to FET gate to activate FET:
Vg = 12 V
(42)
Calculate QA losses (PQA) based on Rds(on)QA and gate charge (QAg):
PQA
IPRMS2 u RDS(on)QA
2 u QAg u Vg u fSW | 2.1W
(43)
Recalculate power budget:
PBUDGET = PBUDGET - 4 ´ PQA » 36.6W
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8.2.2.4 Selecting LS
Calculating the value of the shim inductor (LS) is based on the amount of energy required to achieve zero voltage
switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch node.
The following equation selects LS to achieve ZVS at 100% load down to 50% load based on the primary FET’s
average total COSS at the switch node.
NOTE
The actual parasitic capacitance at the switched node may differ from the estimate and LS
may have to be adjusted accordingly.
VINMAX 2
- LLK » 26 mH
LS ³ (2 ´ COSS _ QA _ AVG )
2
æ IPP DILOUT ö
ç 2 - 2 ´ a1 ÷
è
ø
(45)
LS = 26 mH
(46)
Typical shim inductor DC resistance:
DCRLS = 27mW
(47)
Estimate LS power loss (PLS) and readjust remaining power budget:
PLS = 2 ´ IPRMS 2 ´ DCRLS » 0.5 W
(48)
PBUDGET = PBUDGET - PLS » 36.1W
(49)
8.2.2.5 Selecting Diodes DB and DC
There is a potential for high voltage ringing on the secondary rectifiers, caused by the difference in current
between the transformer and the shim inductor when the transformer comes out of freewheeling. Diodes DB and
DC provide a path for this current and prevent any ringing by clamping the transformer primary to the primary
side power rails. Normally these diodes do not dissipate much power but they should be sized to carry the full
primary current. The worse case power dissipated in these diodes is:
P = 0.5 ´ LS ´ I2PRMS ´ FSW
(50)
The diodes should be ultra-fast types and rated for the input voltage of the converter – VIN (410 VDC in this
case).
A MURS360 part is suitable at this power level.
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8.2.2.6 Output Inductor Selection (LOUT)
Inductor LOUT is designed for 20% inductor ripple current (∆ILOUT):
DILOUT =
LOUT
POUT ´ 0.2 600 W ´ 0.2
=
» 10 A
VOUT
12 V
(51)
VOUT u (1 DTYP )
| 2 PH
'ILOUT u 2 u fSW
(52)
Calculate output inductor RMS current (ILOUT_RMS):
2
ILOUT _ RMS
2
æ P ö æ DI
ö
= ç OUT ÷ + ç LOUT ÷ = 50.3 A
è VOUT ø è 3 ø
(53)
LOUT = 2 mH
(54)
Typical output inductor DC resistance:
DCRLOUT = 750 mW
(55)
Estimate output inductor losses (PLOUT) and recalculate power budget. Note PLOUT is an estimate of inductor
losses that is twice the copper loss. Note this may vary based on magnetic manufactures. It is advisable to
double check the magnetic loss with the magnetic manufacture.
PLOUT = 2 ´ ILOUT _ RMS 2 ´ DCRLOUT » 3.8 W
(56)
PBUDGET = PBUDGET - PLOUT » 32.8W
(57)
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8.2.2.7 Output Capacitance (COUT)
The output capacitor is selected based on holdup and transient (VTRAN) load requirements.
Time it takes LOUT to change 90% of its full load current:
tHU
LOUT ´ POUT ´ 0.9
VOUT
=
= 7.5 ms
VOUT
(58)
During load transients most of the current will immediately go through the capacitors equivalent series resistance
(ESRCOUT). The following equations are used to select ESRCOUT and COUT based on a 90% load step in current.
The ESR is selected for 90% of the allowable transient voltage (VTRAN), while the output capacitance (COUT) is
selected for 10% of VTRAN.
ESRCOUT £
COUT
VTRAN ´ 0.9
= 12mW
POUT ´ 0.9
VOUT
(59)
POUT ´ 0.9 ´ tHU
VOUT
³
» 5.6mF
VTRAN ´ 0.1
(60)
Before selecting the output capacitor, the output capacitor RMS current (ICOUT_RMS) must be calculated.
ICOUT _ RMS =
DILOUT
3
» 5.8 A
(61)
To meet the design requirements five 1500-µF, aluminum electrolytic capacitors are chosen for the design from
United Chemi-Con™, part number EKY-160ELL152MJ30S. These capacitors have an ESR of 31 mΩ.
Number of output capacitors:
n=5
(62)
Total output capacitance:
COUT = 1500 mF ´ n » 7500 mF
(63)
Effective output capacitance ESR:
ESRCOUT =
31mW
= 6.2mW
n
(64)
Calculate output capacitor loss (PCOUT):
PCOUT = ICOUT _ RMS 2 ´ ESRCOUT » 0.21W
(65)
Recalculate remaining Power Budget:
PBUDGET = PBUDGET - PCOUT » 32.6W
(66)
8.2.2.8 Select Rectifier Diodes
Selecting the rectifier diodes begins with determining the voltage and current ratings necessary. In this case the
peak diode reverse voltage is given by:
Vr =2×
VINMAX
a1
» 38V
(67)
The average output diode current is given by:
If =
30
IOUT _ avg
2
» 30A
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For this design we select dual 40-A, 45-V Schottky diodes type STPS40L45CT. This is a dual diode and we
connect both of the diodes in parallel for current sharing. Each diode in the package will carry approximately half
of the If calculated above, or about 15 A. The forward voltage drop of these diodes at maximum output current
will be typically 0.45 V.
The power loss in the output rectifiers is dominated by the VfIf product.
The loss in each dual diode package is given by:
PDiode =Vf ×If » 13.5W
(69)
The device will require a heatsink to keep its junction temperature at a reasonable level.
The heatsink thermal resistance will have to be less than:
R TH_HSK_D =
TJ_max - TA
PDiode
- R THJC » 4.5 o CW -1
(70)
where Tj_max = 125°C, TA = 50°C, and RTH_jc = 0.8°CW–1.
A typical heatsink with this thermal resistance would have dimensions 63.5 mm × 42 mm × 25 mm.
Recalculate the power budget.
PBUDGET = PBUDGET - 2 ´ PDiode » 5.6W
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8.2.2.9 Input Capacitance (CIN)
The input voltage in this design is 390 VDC, which is generally fed by the output of a PFC boost pre-regulator.
The input capacitance is generally selected based on holdup and ripple requirements.
NOTE
The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).
Calculate tank frequency:
fR =
1
2p LS ´ (2 ´ COSS _ QA _ AVG )
(72)
Estimated delay time:
tDELAY =
2
» 314ns
f R ´4
(73)
Effective duty cycle clamp (DCLAMP):
DCLAMP
§ 1
¨
© 2 u fSW
·
tDELAY ¸ u 2 u fSW
¹
94%
(74)
VDROP is the minimum input voltage where the converter can still maintain output regulation. The converter’s input
voltage would only drop down this low during a brownout or line-drop condition if this converter was following a
PFC pre-regulator.
a1´ (VOUT + Vf )
» 278V
VDROP =
DCLAMP
(75)
CIN was calculated based on one line cycle of holdup:
2 ´ POUT ´
CIN ³
(V
2
IN
1
60Hz
- VDROP 2
)
» 364 mF
(76)
Calculate high frequency input capacitor RMS current (ICINRMS).
2
ICINRMS = I
2
PRMS1
æ POUT ö
-ç
÷ = 1.8 A
V
a1
´
è INMIN
ø
(77)
To meet the input capacitance and RMS current requirements for this design a 330-µF capacitor was chosen
from Panasonic part number EETHC2W331EA.
CIN = 330 mF
(78)
This capacitor has a high frequency (ESRCIN) of 150 mΩ, measured with an impedance analyzer at 200 kHz.
ESRCIN = 0.150 W
(79)
Estimate CIN power dissipation (PCIN):
PCIN = ICINRMS 2 ´ ESRCIN = 0.5 W
(80)
Recalculate remaining power budget:
PBUDGET = PBUDGET - PCIN » 5.0 W
(81)
There is roughly 5.0 W left in the power budget left for the current sensing network, and biasing the control
device and all resistors supporting the control device.
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8.2.2.10 Current Sense Network (CT, RCS, RR, DA)
The CT chosen for this design has a turns ratio (CTRAT) of 100:1.
CTRAT =
IP
= 100
IS
(82)
Calculate nominal peak current (IP1) at VINMIN:
Peak primary current:
æ P
DI
IP1 = ç OUT + LOUT
2
è VOUT ´ h
ö1
VINMIN ´ DMAX
» 3.3 A
÷ +
ø a1 LMAG ´ 2 ´ FSW
(83)
The CS pin voltage where peak current limit will trip.
VP = 2 V
(84)
Calculate current sense resistor (RCS) and leave 300 mV for slope compensation. Include a 1.1 factor for margin:
RCS =
VP - 0.3 V
» 47 W
IP1
´ 1.1
CTRAT
(85)
Select a standard resistor for RCS:
RCS = 47 W
(86)
Estimate power loss for RCS:
2
PRCS
æI
ö
= ç PRMS1 ÷ ´ RCS » 0.03 W
è CTRAT ø
(87)
Calculate maximum reverse voltage (VDA) on DA:
VDA = VP
DCLAMP
» 29.8 V
1 - DCLAMP
(88)
Estimate DA power loss (PDA):
PDA =
POUT ´ 0.6 V
» 0.01W
VINMIN ´ h ´ CTRAT
(89)
Calculate reset resistor RR:
Resistor RR is used to reset the current sense transformer CT.
RR = 100 ´ RCS = 4.7kW
(90)
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Resistor RLF and capacitor CLF form a low pass filter for the current sense signal (Pin 15). For this design we
chose the following values. This filter has a low frequency pole (fLFP) at 482 kHz. This should work for most
applications but may be adjusted to suit individual layouts and EMI present in the design.
RLF = 1kW
(91)
CLF = 330pF
(92)
fLFP =
1
= 482kHz
2pf ´ RLF ´ CLF
(93)
The UCC3895 REF output (Pin 4) needs a high frequency bypass capacitor to filter out high frequency noise.
The maximum amount of capacitance allowed is given in the Recommended Operating Conditions.
CREF = 1 mF
(94)
The voltage amplifier reference voltage (Pin 2, EA+) can be set with a voltage divider (R1, R2), for this design
example, the error amplifier reference voltage (V1) will be set to 2.5 V. Select a standard resistor value for R1
and then calculate resistor value R2.
UCC3895 reference voltage:
VREF = 5 V
(95)
Set voltage amplifier reference voltage:
V1 = 2.5 V
R1 = 2.37kW
R1´ (VREF - V1)
R2 =
= 2.37kW
V1
(96)
(97)
(98)
Voltage divider formed by resistor R3 and R4 are chosen to set the DC output voltage (VOUT) at Pin 3 (EA–).
Select a standard resistor for R3:
R3 = 2.37kW
(99)
Calculate R4:
R4 =
R3 ´ (VOUT - V1)
V1
» 9kW
(100)
Then choose a standard resistor for R4:
R4 =
R3 ´ (VOUT - V1)
V1
» 9.09kW
(101)
8.2.2.10.1 Output Voltage Setpoint
Peak current mode control is chosen for this design and a TL431 (U1) acts as the output voltage error amplifier.
It has a 2.5-V internal reference and we want to regulate VOUT to 12 V. We set RB, the lower resistor of the
output voltage divider chain to 10 kΩ. RA the upper resistor is given by:
RA
§V
·
RB ¨ OUT 1¸
© VREF ¹
38 k :
(102)
It is possible, but not necessary, to add a small resistor, RLOOP, in series with the feedback network as a signal
injection point for loop stability tests, RLOOP.
The output of U1 is transferred across the isolation barrier by the optocoupler U2 and fed into the EAP pin of the
UCC3895 as a current demand signal. The UCC2895 internal error amplifier is configured as a voltage follower
by connecting EAN to EAOUT.
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8.2.2.10.2 Voltage Loop Compensation
We choose a standard configuration for a TL431 / optocoupler based feedback network. Type 2 loop
compensation is appropriate for a design using peak current mode control. First we set the DC operating points
for the TL431 (U1) and the optocoupler (U2).
We assume that the optocoupler (U2) has a current transfer ratio (CTR) of 1 and choose to operate it at a
maximum LED current, IF of 10 mA. RD is then given by:
VOUT VF Vk _ MIN
RD
| 820 :
IF
(103)
We set the parallel combination of RG and RF to 2.4 kΩ for a nominal 10-dB gain for output perturbations via the
direct path from RD to the optocoupler diode. This path exists in parallel with the path through RA and the TL431.
The direct path is important at frequencies where the gain of the TL431 integrator has fallen to 0 dB.
RG and RF form a potential divider whose function is to keep the EAP pin within the upper limit of its common
mode input range (VCM_MAX = 3.6 V) when there is no current in the photo-transistor. RG is connected to VREF
and this constraint on the voltage at the EAP pin gives:
VREF
RG RF
1 0.39 RF
VCM _ MAX
(104)
Since we know the parallel value of RF and RG and their ratio (RF/RG), we calculate RF as follows:
1.39
RF RF || RG
| 8.6k :
0.39
(105)
and
RG 0.39 RF
3.3 k :
(106)
At low frequencies the gain is dominated by the response of the TL431 error amplifier which is configured as a
pure integrator. The TL431 has a typical open loop gain of about 60 dB at DC, which decreases at the normal
–20 dB per decade. Its gain will be 0 dB when the impedance of CE falls to that of RA. Even though the TL431
gain has fallen to 0 dB, the system still has 10-dB gain due to the direct path through RD.
We put the zero due to capacitor CE and resistor RA at the desired 0-dB gain frequency of 2 kHz. Since RA is
already selected from VOUT setpoint considerations we calculate CE as follows:
1
CE
| 22 nF
2Π2000+]38N :
(107)
The optocoupler has a 10-dB response through the direct path, to perturbations on VOUT. At higher frequencies
the capacitance at the collector of the optocoupler (CF) forms a pole with the resistor in series with the
optocoupler LED. The gain then rolls off in half a decade to reach 0 dB. With CF = 68 nF this pole is at about 2.8
kHz.
Having chosen the component values in the feedback path around the TL431 we can draw a Bode Plot of the
VOUT to EAP transfer function GC(f).
The control to output transfer function of the power train is approximated by:
GCO
f
û9OUT
5
| a1u CTRAT u LOAD
û9C
5CS
§ 1 V (65COUT u &OUT
u¨
© 1 V 5LOAD u &OUT
·
¸u
¹
1
1
s
sPP
§ s ·
¨
¸
© sPP ¹
2
where
•
•
•
s = 2πjf is the complex frequency
sPP is FSW / 2 = 50 kHz in this case
The overall loop response is then given by GC(f). GC(o).
(108)
This loop response has a crossover frequency of 7.5 kHz. TI recommends that you check the loop stability of the
final design with load transient tests and by checking that the gain and phase margins are sufficient. RLOOP
provides a convenient point to inject signals for loop gain and phase measurements. The feedback network may
need to be adjusted to achieve satisfactory performance.
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8.2.2.10.3 Setting the Switching Frequency
In this design we set the UCC2895 oscillator frequency to 200 kHz to give a switching frequency (FSW) of 100
kHz at the transformer primary. We set RT = 82 kΩ, within the limits given in the RT (Oscillator Timing Resistor)
section and rearrange Equation 2 to find the needed value of CT.
48 u ª¬tOSC 120ns º¼
CT
| 560 pF
5 u RT
(109)
This value is within the limits for CT in the CT (Oscillator Timing Capacitor) section.
8.2.2.10.4 Soft Start
IRT
3V
| 36 A
RT
(110)
The UCC3895 has a soft-start function to reduce component stresses during the start-up phase. For this design
we set the soft-start time to 50 ms. This time is controlled by the value of the capacitor CSS at the SS/DISB pin
and the charging current set by RT (Equation 4).
t
t
3V
CSS IRT u SS
u SS | 470 nF
RT 3.6 V
3.6 V
(111)
8.2.2.10.5 Setting the Switching Delays
Higher power designs will benefit from the adaptive delays provided by the ADS pin but that feature is not used
in this example. Setting RADSH = 0 Ω defeats the adaptive delay and a fixed value for tDELAB and tDELCD is used.
If it is planned to use the adaptive delay feature then the resistor RADSL should be included in the layout but not
populated until delay optimisation is being done on actual hardware.
RAHI
UCC3895
CS 15
ADEL 14
RAEFHI
ADELEF 13
RA
RAEF
Figure 20. UCC3895 Adaptive Delays
We set the delay times as follows. The resonant frequency of the shim inductor LS with the stray capacitance at
the switched node is given by:
1
fR
| 1.6 MHz
2Π/S u2 u &OSS _ AVG
(112)
Set the initial tABSET and tCDSET values to half the resonant period
tDELAY 314 ns
(113)
The resistors RAB and RCD are given by a modified version of Equation 5 and Equation 6.
tDELAY 25 ns u 0.5 V
| 5.6 k :
RAB RCD
25 u10 12
(114)
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It is important to recognise that the delay times set by RAB and RCD are those measured at the device pins.
Propagation delays mean that the delay times seen at the primary of the transformer will be different and this is
the reason why the delays have to be optimised on actual hardware. Once the prototype is up and running it is
recommended that you fine tune tABSET and tCDSET at light load. Refer to Figure 21 and Figure 22. It is easier to
achieve ZVS at the drain of QD than at the drain of QA because the output inductor current reflected in the
transformer primary is greater at QD and QC turn-off than it is at QA and QB turn-off.
Set t
ABSET
at resonant tank Peak and Valley
t ABSET = t 1 - t 0
t ABSET = t 4 - t 3
QB d
QA g
Miller Plateau
tMILLER = t
QB
2
- t1
Miller Plateau
g
t MILLER = t 5 - t 4
t0 t1 t2
t3 t4 t5
Figure 21. tABSET to Achieve Valley Switching at Light Loads
Copyright © 1999–2019, Texas Instruments Incorporated
Product Folder Links: UCC1895 UCC2895 UCC3895
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UCC1895, UCC2895, UCC3895
SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
Set t
t CDSET
QD
QC
=t
CDSET
at resonant tank Peak and Valley
t CDSET
- t0
1
=t
4
- t3
d
g
Miller Plateau
t MILLER
QD
www.ti.com
=t
2
-t1
Miller Plateau
g
t MILLER
t 0 t1 t 2
=t
5
-t4
t 3 t4 t 5
Figure 22. tCDSET to Achieve Valley Switching at Light Loads
8.2.2.10.6 Setting the Slope Compensation
Slope compensation is necessary to stabilise a converter operating in peak current mode at duty cycles greater
than 50%. The optimum slope compensation ramp should be half the inductor current ramp downslope during
the off time. This slope is calculated as follows:
VOUT u RCS
me 0.5
67 mv V 1
LOUT ua1u CTRAT
(115)
The magnetizing current of the power transformer provides part of the compensating ramp and is calculated as
follows. The VIN x DTYP factor takes account of the fact that the slope of the magnetizing current is less at lower
input voltages.
VIN u DTYP u RCS
| 43 mv V 1
mMAG
LMAG u CTRAT
(116)
The added slope compensation ramp is then:
mSUM
me
mMAG | 24 mv V
1
(117)
The resistor RSC sets the added slope compensation ramp, mSUM and is chosen as follows:
8 u IRT
RSC = RLF u
=21 k:
mMAG u CT
(118)
A small AC coupling capacitor is used in the emitter of Q1 to eliminate the need for offset biasing circuitry. CC = 1
nF.
The resistor REL is a DC load resistor for the emitter of Q1. It should have the same value as RSC.
38
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SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
A small capacitor at the RAMP pin input helps suppress high frequency noise, we set CRAMP = 56 pF. Transistor
Q1 is a small signal NPN type.
In peak current mode control the RAMP pin receives the current sense signal, plus the slope compensation
ramp, through the 510-Ω resistor RRCS. The 10-kΩ resistor RRB provides approximately 250-mV offset bias. The
value of this resistor may be adjusted up or down to alter the point at which the internal no load comparator trips.
Copyright © 2017, Texas Instruments Incorporated
Figure 23. Daughter Board Schematic
Copyright © 1999–2019, Texas Instruments Incorporated
Product Folder Links: UCC1895 UCC2895 UCC3895
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39
FC1
390V/2A
VIN-
J3
VIN+
J1
FC2
U2
UCC27714D
TP5
PGND
C2
0.47µF
C1
330µF
PGND
C18
1µF
VBIAS
R20
2.20
PGND
MURS360T3G
C14
0.1µF
D12
R5
1.0Meg
R2
1.0Meg
R1
1.0Meg
SW
i
PGND
R16
10.0k
R9
10.0k
UCC27714D
U3
D9
BAT54-7-F
3.01
R15
D4
BAT54-7-F
3.01
R6
HS1
MURS360T3G
C15
0.1µF
D13
PGND
Q3,Q4
Q4
SPP20N60C3
HS2
PGND
Q1, Q2
Q1
SPP20N60C3
10
F1
Fuse, 2A, 250V, TH
13
HB
LI
14
NC
HI
1
OUTA
2
OUTB
3
10
HO
VSS
12
HS
NC/EN
4
9
NC
COM
8
NC
LO
5
11
NC
VDD
6
7
13
HB
LI
14
NC
HI
1
OUTC
2
OUTD
12
3
HO
VSS
9
HS
8
NC
11
NC
NC/EN
PGND
4
NC
COM
5
LO
6
VDD
7
TP1
VBULK
PGND
C20
1µF
VBIAS
R22
2.20
D5
BAT54-7-F
SW
i
7
6
5
4
8
Q3
SPP20N60C3
3
60PR964
R17
10.0k
R8
10.0k
Q2
SPP20N60C3
2
1
L2
D10
BAT54-7-F
3.01
R14
3.01
R7
Product Folder Links: UCC1895 UCC2895 UCC3895
PGND
R23
21.0k
C24
1000pF
R26
21.0k
9
7
12
10
C13
REF
0.1uF
C17
56pF
C19
R19
10k
R28
82.0k
1000pF
Q5
3.3k
R21
PGND
75PR8107
T2
D11
MURS360T3G
1
3
3
5
PE-63587
T1
D3
MURS360T3G
1
2
2
2
R30
10.0M
0
R32
R18
510
STPS40L45CT
D8
ES3BB-13-F
D7
DELCD
DELAB
OUTD
OUTC
OUTB
OUTA
C4
1500µF
CS
C27
0.1uF
PGND
GND
REF
SS/DISB
VBIAS
UCC1895J
VDD
CT
RT
SYNC
ADS
CS
RAMP
EAOUT
EAN
EAP
U4
C26
1.0uF
15
7
8
6
11
12
3
2
1
20
R3
47
75PR8108
L1
ES3BB-13-F
D2
STPS40L45CT
D6
C22
560pF
3
1
3
1
R4
4.70k
D1
1N4148W-7-F
16
5
4
19
10
9
13
14
17
18
R13
100k
R31
20.0
C28
1µF
C9
1µF
REF
C3
0.22µF
C25
330pF
1.00k
R29
OUTD
OUTC
OUTB
OUTA
C5
1500µF
CS
0.047µF
C21
R11
1.00k
R33
4.48k
C10
1µF
R12
1.00k
R35
4.48k
C6
1500µF
R25
8.56k
GND
C11
1µF
C16
0.068µF
C7
1500µF
U1
VOUT
VOUT
TP2
C12
1µF
LOOP+
TP3
LOOP-
TP4
VOUT+
R10
49.9
J4
12V/50A
CXS70-14-C
J2
R24
820
U5A
0.022µF
C23
GND
R34
10.0k
R27
37.9k
CXS70-14-C
TP6
VOUT-
C8
1500µF
1
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8
40
2
3
6
7
HV i
UCC1895, UCC2895, UCC3895
SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
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Copyright © 2017, Texas Instruments Incorporated
Figure 24. Power Stage Schematic
Copyright © 1999–2019, Texas Instruments Incorporated
UCC1895, UCC2895, UCC3895
www.ti.com
SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
8.2.3 Application Curves
OUTA
OUTA
OUTB
Transformer Primary
Typical
OUTD
OUTC
OUTD
Operating at Dmax
VIN = 390 V
IOUT = 5 A
VIN = 390 V
IOUT = 5 A
Figure 25. Full Bridge Gate Drives and Primary Switched
Nodes
Figure 26. Gate Drive Signals at DMAX
OUTA
OUTB
VOUT
OUTD
OUTC
D = 72%
VIN = 390 V
IOUT = 10 A
VIN = 390 V
IOUT = 10 A
Figure 27. Gate Drive Signals D = 72%
Figure 28. Typical Start-up (Into 50% Full Load)
Copyright © 1999–2019, Texas Instruments Incorporated
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UCC1895, UCC2895, UCC3895
SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
www.ti.com
9 Power Supply Recommendations
The UCC3895 device should be operated from a VDD rail within the limits given in the Recommended Operating
Conditions of this data sheet. To avoid the possibility that the device might stop switching, VDD must not be
allowed to fall into the UVLO(off) range. In order to minimize power dissipation in the device, VDD should not be
unnecessarily high. Keeping VDD at 12 V is a good compromise between these competing constraints. The gate
drive outputs from the UCC3895 device deliver large-current pulses into their loads. This indicates the need for a
low-ESR decoupling capacitor to be connected as directly as possible between the VDD and PGND terminals.
TI recommends ceramic capacitors with stable dielectric characteristics over temperature, such as X7R. Avoid
capacitors which have a large drop in capacitance with applied DC voltage bias. For example, use a part that has
a low-voltage co-efficient of capacitance. The recommended decoupling capacitance is 1 μF, X7R, with at least a
25-V rating with a 0.1-µF NPO capacitor in parallel.
10 Layout
10.1 Layout Guidelines
In order to increase the reliability and robustness of the design, it is recommended that the following layout
guidelines are followed.
• EAN pin - This is the inverting input to the error amplifier. It is a high impedance pin and is susceptible to
noise pickup. Keep tracks from this pin as short as possible.
• EAP pin - This is the non-inverting input to the error amplifier. It is a high impedance pin and is susceptible to
noise pickup. Keep tracks from this pin as short as possible.
• EAOUT - pin Keep tracks from this pin as short as possible.
• RAMP,CT, RT, DELAB, DELCD and ADS pins - The components connected to these pins are used to set
important operating parameters. Keep these components close to the IC and provide short, low impedance
return connections to the GND pin.
• REF pin - Decouple this pin to GND with a good quality ceramic capacitor. A 1-µF, X7R, 25-V capacitor is
recommended. Keep REF PCB tracks as far away as possible from sources of switching noise.
• SYNC pin - This pin is essentially a digital I/O port. If it is unused, then it may be left open circuit. If
Synchronisation is used, then route the incoming Synchronisation signal as far away from noise sensitive
input pins as possible.
• CS pin - This connection is arguably the most important single connection in the entire PSU system. Avoid
running the CS signal traces near to sources of high dv/dt. Provide a simple RC filter as close as possible to
the pin to help filter out leading edge noise spikes which will occur at the beginning of each switching cycle.
• SS/DISB pin - Keep tracks from this pin as short as possible. If the Enable signal is coming from a remote
source then avoid running it close to any source of high dv/dt (MOSFET Drain connections for example) and
add a simple RC filter at the SS/DISB pin.
• OUTA, OUTB, OUTC, and OUTD pins - These are the gate drive output pins and will have a high dv/dt rate
associated with their rising and falling edges. Keep the tracks from these pins as far away from noise
sensitive input pins as possible. Ensure that the return currents from these outputs do not cause voltage
changes in the analog ground connections to noise sensitive input pins.
• VDD pin - This pin must be decoupled to PGND using ceramic capacitors as detailed in the Power Supply
Recommendations section. Keep this capacitor as close to the VDD and PGND pins as possible.
• GND pin - This pin provides the analog ground reference to the controller. Use this pin to provide a return
path for the components at the RAMP, REF, CT, RT, DELAB, DELCD, ADS, CS, and SS/DISB pins. Use a
Ground Plane to minimise the impedance of the ground connection and to reduce noise pickup. It is important
to have a low impedance connection from GND to PGND.
• PGND pin - This pin provides the ground reference to the controller. This pin should be used to return the
currents from the OUTX and SYNC pins. Use a Ground Plane to minimise the impedance of the ground
connection and to reduce noise pickup.
An ideal ground plane provides an equipotential surface to which the controller ground pins can be connected.
However, real ground planes have a non-zero impedance and having separate ground planes for analog and
driver circuits is an easy way to prevent the analog ground from being disturbed by driver return currents. A
single ground plane may be used if care is taken to ensure that the driver return currents are kept away from the
part of the ground plane used for analog connections.
42
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SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
10.2 Layout Example
Further layout information for this device is given in application report SLUA501.
Figure 29. Suggested PCB Layout
Copyright © 1999–2019, Texas Instruments Incorporated
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UCC1895, UCC2895, UCC3895
SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
See the following for related documentation:
1. UCC2895 Layout and Grounding Recommendations, (SLUA501).
2. Using the UCC3895 in a Direct Control Driven Synchronous Rectifier Applications, (SLUU109).
3. M. Dennis, A Comparison Between the BiCMOS UCC3895 Phase Shift Controller and the UC3875,
Application Note (SLUA246).
4. L. Balogh, The Current-Doubler Rectifier: An Alternative Rectification Technique for Push-Pull and Bridge
Converters, Application Note (SLUA121).
5. W. Andreycak, Phase Shifted, Zero Voltage Transition Design Considerations, Application Note (SLUA107).
6. L. Balogh, The New UC3879 Phase Shifted PWM Controller Simplifies the Design of Zero Voltage Transition
Full-Bridge Converters, Application Note (SLUA122).
7. L. Balogh, Design Review: 100 W, 400 kHz, dc-to-dc Converter With Current Doubler Synchronous
Rectification Achieves 92% Efficiency, Unitrode Power Supply Design Seminar Manual, SEM-1100, 1996,
Topic 2.
8. UC3875 Phase Shift Resonant Controller, Data Sheet (SLUS229).
9. UC3879 Phase Shift Resonant Controller, Data Sheet (SLUS230).
10. UCC3895EVM-1, Using the UCC3895 in a Direct Control Driven Synchronous Rectifier Applications, User's
Guide (SLUU109).
11. UCC3895,OUTC/OUTD Asymmetric Duty Cycle Operation, Application Report (SLUA275).
12. Current Doubler Rectifier Offers Ripple Current Cancellation, Application Note (SLUA323).
13. Control Driven Synchronous Rectifiers In Phase Shifted Full Bridge Converters, Application Note
(SLUA287).
11.1.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC1895
Click here
Click here
Click here
Click here
Click here
UCC2895
Click here
Click here
Click here
Click here
Click here
UCC3895
Click here
Click here
Click here
Click here
Click here
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resource
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
44
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UCC1895, UCC2895, UCC3895
www.ti.com
SLUS157Q – DECEMBER 1999 – REVISED OCTOBER 2019
11.4 Trademarks (continued)
United Chemi-Con is a trademark of United Chemi-Con.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1999–2019, Texas Instruments Incorporated
Product Folder Links: UCC1895 UCC2895 UCC3895
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PACKAGE OPTION ADDENDUM
www.ti.com
15-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC1895J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
UCC1895J
UCC1895L
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
UCC1895L
UCC2895DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCC2895DW
UCC2895DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCC2895DW
UCC2895DWTR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCC2895DW
UCC2895DWTRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCC2895DW
UCC2895N
ACTIVE
PDIP
N
20
18
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
UCC2895N
UCC2895PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCC2895
UCC2895PWTR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCC2895
UCC3895DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UCC3895DW
UCC3895DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UCC3895DW
UCC3895DWTR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UCC3895DW
UCC3895DWTRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UCC3895DW
UCC3895N
ACTIVE
PDIP
N
20
18
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
UCC3895N
UCC3895NG4
ACTIVE
PDIP
N
20
18
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
UCC3895N
UCC3895PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UCC3895
UCC3895PWTR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UCC3895
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
15-May-2019
Status
(1)
UCC3895PWTRG4
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
20
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
0 to 70
UCC3895
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC1895, UCC2895, UCC3895 :
• Catalog: UCC3895
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-May-2019
• Automotive: UCC2895-Q1
• Enhanced Product: UCC2895-EP
• Military: UCC1895
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCC2895PWTR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
UCC3895DWTR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC2895PWTR
UCC3895DWTR
TSSOP
PW
20
2000
367.0
367.0
38.0
SOIC
DW
20
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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