Texas Instruments | TPS241x N 1 and ORing Power Rail Controller (Rev. D) | Datasheet | Texas Instruments TPS241x N 1 and ORing Power Rail Controller (Rev. D) Datasheet

Texas Instruments TPS241x N 1 and ORing Power Rail Controller (Rev. D) Datasheet
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TPS2412, TPS2413
SLVS728D – JANUARY 2007 – REVISED OCTOBER 2019
TPS241x N+1 and ORing Power Rail Controller
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The TPS2412/13 controller, in conjunction with an
external N-channel MOSFET, emulates the function
of a low forward voltage diode. The TPS2412/13 can
be used to combine multiple power supplies to a
common bus in an N+1 configuration, or to combine
redundant input power buses. The TPS2412 provides
a linear turnon control while the TPS2413 has an
on/off control method.
1
Control External FET for N+1 and ORing
Wide Supply Voltage Range of 3 V to 16.5 V
Controls Buses From 0.8 V to 16.5 V
Linear or On/Off Control Method
Internal Charge Pump for N-Channel MOSFET
Rapid Device Turnoff Protects Bus Integrity
Positive Gate Control on Hot Insertion
Soft Turnon Reduces Bus Transients
Industrial Temperature Range: –40°C to 85°C
8-Pin TSSOP and SOIC Packages
Applications for the TPS2412/13 include a wide range
of systems including servers and telecom. These
applications often have either N+1 redundant power
supplies, redundant power buses, or both. Redundant
power sources must have the equivalent of a diode
OR to prevent reverse current during faults and
hotplug. A TPS2412/13 and N-channel MOSFET
provide this function with less power loss than a
schottky diode.
2 Applications
•
•
•
•
•
Rack Server (Rackmount)
Rack Server (Blade)
Merchant network & server PSU
Battery Backup Unit
Telecom systems
Accurate voltage sensing and a programmable turnoff
threshold allows operation to be tailored for a wide
range of implementations and bus characteristics.
The TPS2412/13 are lower pin count, reduced feature
versions of the TPS2410/11.
Device Information(1)
PART NUMBER
TPS2412,
TPS2413
PACKAGE
BODY SIZE (NOM)
TSSOP (8)
4.40 mm × 3.00 mm
SOIC (8)
3.91 mm × 4.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
A
C
VDD
C
GATE
BYP
RSVD
GND
RSET
Common Voltage Rail
C(BYP)
A
Voltage Source
TPS2412 /13
R(SET)
NOTE: R(SET) is Optional
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2412, TPS2413
SLVS728D – JANUARY 2007 – REVISED OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 16
10.1 Recommended Operating Range ......................... 16
10.2 VDD, BYP, and Powering Options ......................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Revision C (November 2015) to Revision D
•
Page
Changed Gate positve drive MAX voltage from 11.5 to 12.5 in the Electrical Characteristics table...................................... 5
Changes from Revision B (September 2008) to Revision C
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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5 Device Comparison Table
TPS2410
TPS2411
TPS2412
√
Linear gate control
TPS2413
√
√
ON/OFF gate control
Adjustable turnoff threshold
√
√
Fast comparator filtering
√
√
Voltage monitoring
√
√
Enable control
√
√
Mosfet fault monitoring
√
√
Status pin
√
√
√
√
√
6 Pin Configuration and Functions
PW and D Packages
8-Pins TSSOP and SOIC
Top View
1
VDD
4
RSET
RSVD
GND
BYP
A
C
GATE
8
5
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VDD
1
PWR
Input power for the gate drive charge pump and internal controls. VDD must be connected to a supply voltage
≥ 3 V.
RSET
2
I
Connect a resistor to ground to program the turnoff threshold. Leaving RSET open results in a slightly positive
V(A-C) turnoff threshold.
RSVD
3
PWR
This pin must be connected to GND.
GND
4
PWR
Device ground.
GATE
5
O
Connect to the gate of the external MOSFET. Controls the MOSFET to emulate a low forward-voltage diode.
C
6
I
Voltage sense input that connects to the simulated diode cathode. Connect to the MOSFET drain in the
typical configuration.
A
7
I
Voltage sense input that connects to the simulated diode anode. A also serves as the reference for the
charge-pump bias supply on BYP. Connect to the MOSFET source in the typical configuration.
BYP
8
I/O
Connect a storage capacitor from BYP to A to filter the gate drive supply voltage.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
18
V
A above C voltage
7.5
V
C above A voltage
18
V
30
V
A, C, FLTR, VDD, voltage
GATE (2), BYP voltage
–0.3
BYP to A voltage
–0.3
GATE above BYP (2) voltage
RSET (2) voltage
TJ
(1)
(2)
13
V
0.3
V
7
V
–0.3
GATE short to A or C or GND
Indefinite
Maximum junction temperature
Internally limited
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage should not be applied to these pins.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
voltages are referenced to GND (unless otherwise noted)
MIN
A, C
Input voltage range TPS2412
A to C
Operational voltage
3 ≤ VDD ≤ 16.5 V
(2)
R(RSET)
Resistance range
C(BYP)
Capacitance Range (2)
TJ
Operating junction temperature
TA
Operating free-air temperature
(1)
(2)
(3)
VDD = V(C)
(1)
NOM
3
16.5
0.8
16.5
UNIT
V
5
V
∞
kΩ
10k
pF
–40
125
°C
–40
85
°C
1.5
(3)
MAX
800
2200
VDD must exceed 3 V to meet gate drive specification
Voltage should not be applied to these pins.
Capacitors should be X7R, 20% or better
7.4 Thermal Information
TPS241x
THERMAL METRIC
(1)
PW (TSSOP)
D (SOIC)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
110.3
110.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.7
54.7
°C/W
RθJB
Junction-to-board thermal resistance
50.9
50.9
°C/W
ψJT
Junction-to-top characterization parameter
9.2
9.2
°C/W
ψJB
Junction-to-board characterization parameter
50.4
50.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
(1) (2) (3) (4) (5) (6)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(A), V©), VDD
VDD rising
VDD UVLO
A current
2.25
2.5
Hysteresis
0.25
| I(A) |, Gate in active region
0.66
| I(A) |, Gate saturated high
0.1
1
| I©) |, V(AC) ≤ 0.1 V
C current
10
Worst case, gate in active region
VDD current
4.25
Gate saturated high
6
1.2
V
mA
μA
mA
TURNON
TPS2412 forward turnon and regulation
voltage
TPS2412 forward turnon / turnoff difference
7
10
7
10
13
1
3
5
V(A-C) falling, R(RSET) = 28.7 kΩ
–17
–13.25
–10
V(A-C) falling, R(RSET) = 3.24 kΩ
–170
–142
–114
R(RSET) = open
13
7
TPS2413 forward turnon voltage
mV
mV
mV
TURNOFF
Gate sinks > 10 mA at V(GATE-A) = 2 V
Fast turnoff threshold voltage
V(A-C) falling, R(RSET) = open
Turnoff delay
V(A) = 12 V, V(A-C): 20 mV → –20 mV,
V(GATE-A) begins to decrease
Turnoff time
V(A) = 12 V, C(GATE-GND) = 0.01 μF, V(A-C):
20 mV → –20 mV, measure the period to
V(GATE) = V(A)
mV
70
ns
130
ns
GATE
Gate positive drive voltage, V(GATE-A)
VDD = 3 V, V(A-C) = 20 mV
6
7
8
5 V ≤ VDD ≤ 18 V, V(A-C) = 20 mV
9
10.2
12.5
250
290
350
2
5
V(GATE) = 8 V
1.75
2.35
V(GATE) = 5 V
1.25
1.75
Period
7.5
12.5
μs
V(A-C) = –0.1 V, V©) ≤ VDD, 3 V ≤ VDD ≤ 18 V,
2 V ≤ V(GATE) ≤ 18 V
15
19.5
mA
135
°C
10
°C
Gate source current
V(A-C) = 50 mV, V(GATE-A) = 4 V
Soft turnoff sink current (TPS2412)
V(A-C) = 4 mV, V(GATE-A) = 2 V
V
μA
mA
V(A-C) = –0.1 V
Fast turnoff pulsed current, I(GATE)
Sustain turnoff current, I(GATE)
A
MISCELLANEOUS
Thermal shutdown temperature
Temperature rising, TJ
Thermal hysteresis
(1)
(2)
(3)
(4)
(5)
(6)
[3 V ≤ V(A) ≤ 18 V and V©) = VDD] or [0.8 V ≤ V(A) ≤ 3 V and 3 V ≤ V DD ≤ 18 V]
C(BYP) = 2200 pF, R(RSET) = open
–40°C ≤ TJ ≤ 125°C
Positive currents are into pins
Typical values are at 25°C
All voltages are with respect to GND.
7.6 Dissipation Ratings
PACKAGE
θJA – Low k °C/W
θJA – High k °C/W
POWER RATING
High k
TA = 85°C (mW)
PW (TSSOP)
258
159
250
D (SO)
176
97.5
410
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7.7 Typical Characteristics
12.0
5.0
11.5
4.5
11.0
4.0
10.5
3.5
V(AC) − mV
V(AC) − mV
R(RSET) = Open
10.0
3.0
9.5
2.5
9.0
2.0
8.5
1.5
8.0
−40
−20
0
20
40
60
80
100
1.0
−40
120
−20
0
20
40
60
80
100
120
o
o
TJ − Junction Temperature − C
TJ − Junction Temperature − C
Figure 1. TPS2412 V(AC) Regulation Voltage vs Temperature
Figure 2. Fast Turnoff Threshold vs Temperature
3.0
60
o
TJ = -40 C
2.5
50
o
TJ = -40 C
o
TJ = 25 C
40
TJ = 85oC
Delay − ms
I(GATE) − A
2.0
1.5
o
TJ = 25 C
30
o
TJ = 125 C
1.0
20
o
0.5
TJ = 125 C
10
0.0
0
2
4
6
8
0
10
2
4
6
8
V(GATE - GND) − V
10
12
14
16
18
VDD − V
Figure 3. Pulsed Gate Sinking Current vs Gate Voltage
Figure 4. Turnon Delay vs VDD (Power Applied Until Gate is
Active)
3.0
2.5
2.0
I(VDD) − mA
o
TJ = 125 C
o
TJ = 25 C
1.5
1.0
TJ = -40oC
0.5
0.0
2
4
6
8
10
12
14
16
18
VDD − V
Figure 5. VDD Current vs VDD Voltage (Gate Saturated High)
6
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Typical Characteristics (continued)
V(AC)
V(AC)
at 20 mV/div
V(GATE)
at 5 V/div
I(GATE)
at 2 A/div
I(GATE
V(AC)
V(GATE)
at 2 V/div
V(AC)
at 20 mV/div
I(GATE)
at 2A/div
I(GATE
GATE
GATE
Delay = 68 ns, V(GATE) = 12 V at 103 ns
20 ns/div
Figure 6. Turnoff Time With
C(GATE) = 10 nF and V(AC) = -20 mV (VDD = VA = 12 V)
Delay = 70 ns, V(GATE) = 1 V at 113 ns
20 ns/div
Figure 7. Turnoff Time With
C(GATE) = 10 nF and V(AC) = -20 mV (VDD = 5, VA = 1 V)
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8 Detailed Description
8.1 Overview
The TPS2412/13 is designed to allow an output ORing in N+1 power supply applications (see Figure 9), and an
input-power bus ORing in redundant source applications (see Figure 10). The TPS2412/13 and external
MOSFET emulate a discrete diode to perform this unidirectional power combining function. The advantage to this
emulation is lower forward voltage drop and the ability to tune the operation.
The TPS2412 turns the MOSFET on with a linear control loop that regulates V(AC) to 10 mV as shown in
Figure 8. With the gate low, and V(AC) increasing to 10 mV, the amplifier drives GATE high with all available
output current until regulation is reached. The regulator controls V(GATE) to maintain V(AC) at 10 mV as long as the
MOSFET rDS(on) × I(DRAIN) is less than this the regulated voltage. The regulator drives GATE high, turning the
MOSFET fully ON when the rDS(on) × I(DRAIN) exceeds 10 mV; otherwise, V(GATE) will be near V(A) plus the
MOSFET gate threshold voltage. If the external circuits force V(AC) below 10 mV and above the programmed fast
turnoff, GATE is slowly turned off. GATE is rapidly pulled to ground if V(AC) falls to the RSET programmed fast
turnoff threshold.
The TPS2413 turns the MOSFET on and off like a comparator with hysteresis as shown in Figure 8. GATE is
driven high when V(AC) exceeds 10 mV, and rapidly turned off if V(AC) falls to the RSET programmed fast turnoff
threshold.
System designs should account for the inherent delay between a TPS2412/13 circuit becoming forward biased,
and the MOSFET actually turning ON. The delay is the result of the MOSFET gate capacitance charge from
ground to its threshold voltage by the 290 μA gate current. If there are no additional sources holding the ORed
rail voltage up, the MOSFET internal diode will conduct and maintain voltage on the ORed output, but there will
be some voltage droop. This condition is analogous to the power source being ORed in this case. The DC-DC
converter output voltage droops when its load increases from zero to a high value. Load sharing techniques that
keep all ORed sources active solve this condition.
V(GATE)
V(GATE)
V(A) + 10 V
Active
Regulation
Gnd
Gate
ON
Gate
OFF
3 mV
V(AC)
10 mV
3 mV
V(A) + V(T)
Programmable
Fast Turn-off
Threshold
TPS2413
(See Text)
Slow Turn-off
Range
Programmable
Fast Turn-off
Threshold
10 mV
TPS2412
(See Text)
V(AC)
Figure 8. TPS241x Operation
The operation of the two parts is summarized in Table 1.
Table 1. Operation as a Function of VAC
PART
V(AC) ≤ TURNOFF
THRESHOLD (1)
TURNOFF THRESHOLD (1) ≤ VAC ≤ 10 mV
V(AC) FORCED < 10 mV
(MOSFET
rDS(on) × ILOAD) ≤ 10 mV
TPS2412 Strong GATE pulldown (OFF)
Weak GATE pulldown (OFF)
TPS2413 Strong GATE pulldown (OFF)
Depends on previous state (Hysteresis region)
(1)
8
V(AC) regulated to 10 mV
V(AC) > 10 mV
GATE pulled high (ON)
GATE pulled high (ON)
Turnoff threshold is established by the value of RSET.
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8.2 Functional Block Diagram
10 V
A
V(DD)
Charge Pump
and Bias Supply
HVUV
BYP
+
A
‘12: AMP
‘13: COMP
10 mV
0.5 V
3 mV
RSET
-
GATE
-
C
FAST
COMP.
EN
+
A
EN
C
T >135°C
RSVD
BIAS
and
Control
V(DD)
GND
HVUV
V(BIAS)
EN
8.3 Feature Description
8.3.1 Definitions
The following descriptions refer to the pinout and the functional block diagram.
A, C: The A pin serves as the simulated diode anode and the C as the cathode. GATE is driven high when V(AC)
exceeds 10 mV. Both devices provide a strong GATE pulldown when V(AC) is less than the programmable fast
turnoff threshold. The TPS2412 has a soft pulldown when V(AC) is less than 10 mV but above the fast turnoff
threshold.
Several internal comparator and amplifier circuits monitor these two pins. The inputs are protected from excess
differential voltage by a clamp diode and series resistance. If C falls below A by more than about 0.7 V, a small
current flows out of C. Protect the internal circuits with an external clamp if C can be more than 6 V lower than A.
The internal charge pump output, which provides bias power to the comparators and voltage to drive GATE, is
referenced to A. Some charge pump current appears on A due to this topology. The A and C pins should be
Kelvin connected to the MOSFET source and drain. A and C connections should also be short and low
impedance, with special attention to the A connection. Residual noise from the charge pump can be reduced with
a bypass capacitor at A if the application permits.
BYP: BYP is the internal charge pump output, and the positive supply voltage for internal comparator circuits and
GATE driver. A capacitor must be connected from BYP to A. While the capacitor value is not critical, a 2200-pF
ceramic is recommended. Traces to this part must be kept short and low impedance to provide adequate filtering.
CAUTION
Shorting this pin to a voltage below A damages the TPS241x.
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Feature Description (continued)
GATE: Gate controls the external N channel MOSFET gate. GATE is driven positive with respect to A by a driver
operating from the voltage on BYP. A time-limited high current discharge source pulls GATE to GND when the
fast turnoff comparator is activated. The high-current discharge is followed by a sustaining pulldown. The turnoff
circuits are disabled by the thermal shutdown, leaving a resistive pulldown to keep the gate from floating. The
gate connection should be kept low impedance to maximize turnoff current.
GND: This is the input supply reference. GND should have a low impedance connection to the ground plane. It
carries several Amperes of rapid-rising discharge current when the external MOSFET is turned off, and also
carries significant charge pump currents.
RSET: A resistor connected from this pin to GND sets the fast V(A-C) comparator turnoff threshold. The threshold
is slightly positive when the RSET pin is left open. Current drawn by the resistor programs the turnoff voltage to
increasing negative values. The TPS2413 must have a negative threshold programmed to avoid an unstable
condition at light load. The expression for R(RSET) in terms of the trip voltage, V(OFF), follows.
æ
ö
-470.02
÷
R(RSET) = ç
ç V(OFF) - 0.00314 ÷
è
ø
(1)
The units of the numerator are (V × V/A). V(OFF) is positive for V(A) greater than V(C), V(OFF) is less than 3 mV, and
R(RSET) is in ohms.
RSVD: Connect to ground.
VDD: VDD is the primary supply for the gate drive charge pump and other internal circuits. This pin must be
connected a source that is 3 V or greater when the external MOSFET is to be turned on. VDD may be greater or
lower than the controlled bus voltage.
A 0.01-μF bypass capacitor, or 10-Ω and a 0.01-μF filter, is recommended because charge pump currents are
drawn through VDD.
8.3.2 TPS2412 vs TPS2413 – MOSFET Control Methods
The TPS2412 control method yields several benefits. First, the low-current GATE driver provides a gentle turnon
and turnoff for slowly rising and falling input voltage. Second, it reduces the tendency for on/off cycling of a
comparator based solution at light loads. Third, it avoids reverse currents if the fast turnoff threshold is left
positive. The drawback to this method is that the MOSFET appears to have a high resistance at light load when
the regulation is active. A momentary output voltage droop occurs when a large step load is applied from a lightload condition. The TPS2412 is a better solution for a mid-rail bus that is re-regulated.
The TPS2413 turns the MOSFET on if V(AC) is greater than 10 mV, and the rapid turnoff is activated at the
programmed negative threshold. There is no linear control range and slow turnoff. The disadvantage is that the
turnoff threshold must be negative (unless a minimum load is always present) permitting a continuous reverse
current. Under a dynamic reverse voltage fault, the lower threshold voltage may permit a higher peak reverse
current. There are a number of advantages to this control method. Step loads from a light load condition are
handled without a voltage droop beyond I × R. If the redundant converter fails, applications with redundant
synchronous converters may permit a small amount of reverse current at light load to assure that the MOSFET is
all ready on. The TPS2413 is a better solution for low-voltage buses that are not re-regulated, and that may see
large load steps transients.
These applications recommendations are meant as a starting point, with the needs of specific implementations
overriding them.
8.3.3 N+1 Power Supply – Typical Connection
The N+1 power supply configuration shown in Figure 9 is used where multiple power supplies are paralleled for
either higher capacity, redundancy or both. If it takes N supplies to power the load, adding an extra, identical unit
in parallel permits the load to continue operation in the event that any one of the N supplies fails. The supplies
are ORed together, rather than directly connected to the bus, to isolate the converter output from the bus when it
is plugged-in or fails short. The TPS2412/13 with an external MOSFET emulates the function of the ORing diode.
10
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Feature Description (continued)
It is possible for a malfunctioning converter in an ORed topology to create a bus overvoltage if the loading is less
than the converter's capacity (for example, N = 1). The ORed topology shown cannot protect the bus from this
condition, even if the ORing MOSFET can be turned off. One common solution is to use two MOSFETs in a
back-to-back configuration to provide bidirectional blocking. The TPS2412/13 does not have a provision for
forcing the gate off when the overvoltage condition occurs, use of the TPS2410/11 is recommended.
ORed supplies are usually designed to share power by various means, although the desired operation could
implement an active and standby concept. Sharing approaches include both passive, or voltage droop, and
active methods. Not all of the output ORing devices may be ON depending on the sharing control method, bus
loading, distribution resistances, and TPS2412/13 settings.
Implementation
Power
Bus
Concept
C(BYP)
V DD
C
GATE
BYP
GND
DC/DC
Converter
A
Input
Voltage
Power Conversion Block
CommonBus
DC/DC
Converter
Figure 9. N+1 Power Supply Example
8.3.4 Input ORing – Typical Connection
Figure 10 shows how redundant buses may be ORed to a common point to achieve higher reliability. It is
possible to have both MOSFETs ON at once if the bus voltages are matched, or the combination of tolerance
and regulation causes both TPS2412/13 circuits to see a forward voltage. The ORing MOSFET disconnects the
lower-voltage bus, protecting the remaining bus from potential overload by a fault.
Backplane
Power Buses
Concept
Implementation
Common
Buses
C(BYP)
BYP
VDD
C
GATE
A
VDD
C
GATE
BYP
A
DC/DC
Converter
C(BYP)
BUS2
BUS1
Hotswap
LOAD
GND
GND
Plug-In Unit
Figure 10. Example ORing of Input Power Buses
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Feature Description (continued)
8.3.5 System Design and Behavior With Transients
The power system, perhaps consisting of multiple supplies, interconnections, and loads, is unique for every
product. A power distribution has low impedance, and low loss, which yields high Q by its nature. While the
addition of lossy capacitors helps at low frequencies, their benefit at high frequencies is compromised by
parasitics. Transient events with rise times in the 10 ns range may be caused by inserting or removing units, load
fluctuations, switched loads, supply fluctuations, power supply ripple, and shorts. These transients cause the
distribution to ring, creating a situation where ORing controllers may trip off unnecessarily. In particular, when an
ORing device turns off due to a reverse current fault, there is an abrupt interruption of the current, causing a fast
ringing event. Because this ringing occurs at the same point in the topology as the other ORing controllers, they
are the most likely to be effected.
The ability to operate in the presence of noise and transients is in direct conflict with the goal of precise ORing
with rapid response to actual faults. A fast response reduces peak stress on devices, reduces transients, and
promotes un-interrupted system operation. However, a control with small thresholds and high speed is most
likely to be falsely tripped by transients that are not the result of a fault. The power distribution system should be
designed to control the transient voltages seen by fast-responding devices such as ORing and hotswap devices.
While some applications may find it possible to use RSET to avoid false tripping, the TPS2410/11 provides
features beyond the TPS2412/13 including fast-comparator input filtering and STAT to dynamically shift the
turnoff threshold.
8.3.6 TPS2412 Regulation-Loop Stability
The TPS2412 uses an internal linear error amplifier to keep the external MOSFET from saturating at light load.
This feature has the benefits of setting a turnoff above 0 V, providing a soft turnoff for slowly decaying input
voltages, and helps droop-sharing redundancy at light load.
Although the control loop has been designed to accommodate a wide range of applications, there are a few
guidelines to be followed to assure stability.
• Select a MOSFET C(ISS) of 1 nF or greater
• Use low ESR bulk capacitors on the output C terminal, typically greater than 100μF with less than 50 mΩ
ESR
• Maintain some minimum operational load (for example, 10 mA or more)
Symptoms of stability issues include V(AC) undershoot and possible fast turnoff on large-transient recovery, and a
worst-case situation where the gate continually cycles on and off. These conditions are solved by following the
previous rules. Loop stability should not be confused with tripping the fast comparator due to V(AC) tripping the
gate off.
Although not common, a condition may arise where the DC-DC converter transient response may cause the
GATE to cycle on and off at light load. The converter experiences a load spike when GATE transitions from OFF
to ON because the ORed bus capacitor voltage charges abruptly by as much as a diode drop. The load spike
may cause the supply output to droop and overshoot, which can result in the ORed capacitor peak charging to
the overshoot voltage. When the supply output settles to its regulated value, the ORed bus may be higher than
the source, causing the TPS2412/13 to turn the GATE off. While this may not actually cause a problem, its
occurrence may be mitigated by control of the power supply transient characteristic and increasing its output
capacitance while increasing the ORed load to capacitance ratio. Adjusting the TPS2412/13 turnoff threshold to
desensitize the redundant ORing device may help as well. Careful attention to layout and charge-pump noise
around the TPS2412/13 helps with noise margin.
The linear gate driver has a pullup current of 290 μA and pulldown current of 3 mA typical.
8.3.7 MOSFET Selection and R(RSET)
MOSFET selection criteria include voltage rating, voltage drop, power dissipation, size, and cost. The voltage
rating consists of both the ability to withstand the rail voltage with expected transients, and the gate breakdown
voltage. The MOSFET gate rating should be the minimum of 12 V, or the controlled rail voltage. Typically this
requires a ±20-V GATE voltage rating.
12
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Feature Description (continued)
While rDS(on) is often chosen with the power dissipation, voltage drop, size and cost in mind, there are several
other factors to be concerned with in ORing applications. When using the TPS2412, the minimum voltage across
the device is 10 mV. A device that would have a lower voltage drop at full-load would be overspecified. When
using a TPS2413 or TPS2412 with RSET programmed to a negative voltage, the permitted static reverse current
is equal to the turnoff threshold divided by the rDS(on). While this current may actually be desirable in some
systems, the amount may be controlled by selection of rDS(on) and RSET. The practical range of rDS(on) for a
single MOSFET runs from the low milliohms to 40 mΩ for a single MOSFET.
MOSFETs may be paralleled for lower voltage drop (power loss) at high current. For TPS2412 operation, one
should plan for only one of the MOSFETs to carry current until the 10 mV regulation point is exceeded and the
loop forces GATE fully ON. TPS2413 operation does not rely on linear range operation, so the MOSFETs are all
ON or OFF together except for short transitional times. Beyond the control issues, current sharing depends on
the resistance match including both the rDS(on) and the connection resistance.
The TPS2412 may be used without a resistor on RSET. In this case, the turnoff V(AC) threshold is about 3 mV.
The TPS2413 may only be operated without an RSET programming resistor if the loading provides a higher
V(AC). A larger negative turnoff threshold reduces sensitivity to false tripping due to noise on the bus, but permits
larger static reverse current. Installing a resistor from RSET to ground creates a negative shift in the fast turnoff
threshold per Equation 2.
æ
ö
-470.02
÷
R(RSET) = ç
ç V(OFF) - 0.00314 ÷
è
ø
(2)
To obtain a –10 mV fast turnoff ( V(A) is less than V(C) by 10 mV ), R(RSET) = (–470.02/ ( –0.01–0.00314) ) ≈
35,700Ω. If a 10 mΩ rDS(on) MOSFET was used, the reverse turnoff current would be calculated using Equation 3.
V(THRESHOLD)
I(TURN_OFF) =
r DS(on)
I(TURN_OFF) = -10 mV
10 mW
I(TURN_OFF) = - 1 A
(3)
The sign indicates that the current is reverse, or flows from the MOSFET drain to source ( C to A ).
The turnoff speed of a MOSFET is influenced by the effective gate-source and gate-drain capacitance CISS).
Because these capacitances vary a great deal between different vendor parts and technologies, they should be
considered when selecting a MOSFET where the fastest turnoff is desired.
8.3.8 Gate Drive, Charge Pump and C(BYP)
Gate drive of 270 μA typical is generated by an internal charge pump and current limiter. A separate supply, VDD,
is provided to avoid having the large charge pump currents interfere with voltage sensing by the A and C pins.
The GATE drive voltage is referenced to V(A) as GATE will only be driven high when V(A) > V(C). The
recommended capacitor on BYP (bypass) must be used to form a quiet supply for the internal high-speed
comparator. V(GATE) must not exceed V(BYP).
8.4 Device Functional Modes
TPS2412 regulates MOSFET V(AC) to 10 mV linearly while TPS2413 operates in a comparator like manner. Both
devices have a programmable ON/OFF threshold.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS2412 and TPS2413 are designed to allow output ORing in N+1 power supply applications and inputpower bus ORing in redundant source applications. The external MOSFET in conjunction with the TPS2412/13
emulate a discrete diode to perform this unidirectional power combining function.
9.2 Typical Application
Applications with the TPS2412/13 are not limited to ORing of identical sections. The TPS2412/13 and external
MOSFET form a general purpose function block. Figure 11 shows a circuit with ORing between a discrete diode
and a TPS2412/MOSFET section. This circuit can be used to combine two different voltages in cases where the
output is regulated, and the additional voltage drop in the Input 1 path is not a concern. An example is ORing of
an AC adapter on Input 1 with a lower voltage on Input 2.
Input 1
Input 2
Output
2200 pF
VDD
C
GATE
BYP
A
GND
Figure 11. ORing Circuit
The TPS2412 may be a better choice in applications where inputs may be removed, causing an open-circuit
input. If the MOSFET was ON when the input is removed, VAC will be virtually zero. If the reverse turnoff
threshold is programmed negative, the TPS2412/13 will not pull GATE low. A system interruption could then be
created if a short is applied to the floating input. For example, if an AC adapter is first connected to the unit, and
then connected to the AC mains, the adapter's output capacitors will look like a momentary short to the unit. A
TPS2412 with RSET open will turn the MOSFET OFF when the input goes open circuit.
14
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V
Output voltage
12 V
Load current
5A
9.2.2 Detailed Design Procedure
The following is a summarized design procedure:
1. Choose between the TPS2412 or 2413, see TPS2412 vs TPS2413 – MOSFET Control Methods.
2. Choose the VDD source. Table 3 provides a guide for where to connect VDD that covers most cases. VDD may
be directly connected to the supply, but an R(VDD) and C(VDD) of 10 Ω and 0.01 μF is recommended.
Table 3. VDD Connection Guide
3 V ≤ VA ≤ 3.6 V
VA < 3 V
Bias Supply > 3 V
VA > 3.6 V
VA or Bias Supply > 3 V. VC if always > 3 V
VC, VA, or Bias for special configurations
3. Noise voltage and impedance at the A pin should be kept low. C(A) may be required if there is noise on the
bus, or A is not low impedance. If either of these is a concern, a C(A) of 0.01 μF or more may be required.
4. Select C(BYP) as 2200 pF, X7R, 25-V or 50-V ceramic capacitor.
5. Select the MOSFET based on considerations of voltage drop, power dissipated, voltage ratings, and gate
capacitance. See sections: MOSFET Selection and RSET and TPS2412 Regulation-Loop Stability.
6. Select R(RSET) based on which MOSFET was chosen and reverse current considerations – see MOSFET
Selection and RSET. If the noise and transient environment is not well known, make provision for R(RSET)
even when using the TPS2412.
7. Make sure to connect RSVD to ground.
9.2.3 Application Curves
V(AC) (Left)
at 20 mV/div
V(AC) (Left)
at 10 mV/div
V(GATE) (Right)
at 5 V/div
V(IN)
V(AC)
V(AC)
V(GATE) (Left)
at 5 V/div
V(IN) (Right)
at 20 mVac/div
V(GATE) (Right)
at 10 V/div
GATE
GATE
50 ns/div
V(GATE) (Left)
at 10 V/div
500 μs/div
Figure 12. Typical Turnoff With Two ORED Devices Active
(VDD = 12 V, I(LOAD) = 5 A, IRL3713,
Transient Applied to Left Side)
Figure 13. Typical Turnoff And Recovery
With Two ORED Devices Active
(VDD = 3 V, VA = 18 V, I(LOAD) = 5 A, IRL3713,
Transient Applied to Left Side)
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10 Power Supply Recommendations
10.1 Recommended Operating Range
The maximum recommended bus voltage is lower than the absolute maximum voltage ratings on A, C, and VDD
solely to provide some margin for transients on the bus. Most power systems experience transient voltages
above the normal operating level. Short transients, or voltage spikes, may be clamped by the ORing MOSFET to
an output capacitor and/or voltage rail depending on the system design. Transient protection, for example, a TVS
diode (transient voltage suppressor, a type of Zener diode), may be required on the input or output if the system
design does not inherently limit transient voltages below the TPS2412/13 absolute maximum ratings. If a TVS is
required, it must protect to the absolute maximum ratings at the worst case clamping current. The TPS2412/13
will operate properly up to the absolute maximum voltage ratings on A, C, and VDD.
10.2 VDD, BYP, and Powering Options
The separate VDD pin provides flexibility for operational power and controlled rail voltage. While the internal
UVLO has been set to 2.5 V, the TPS2412/13 requires at least 3 V to generate the specified GATE drive voltage.
Sufficient BYP voltage to run internal circuits occurs at VDD voltages from 2.5 V to 3 V. There are three choices
for power, A, C, or a separate supply, two of which are demonstrated in Figure 14. One choice for voltage rails
over 3.3 V is to power from C, because it is typically the source of reliable power. Voltage rails below 3.3 V
nominal, for example, 2.5 V and below, should use a separate supply such as 5 V. A separate VDD supply can be
used to control voltages above it, for example 5 V powering VDD to control a 12-V bus.
VDD is the main source of power for the internal control circuits. The charge pump that powers BYP draws most
of its power from VDD. The input should be low impedance, making a bypass capacitor a preferred solution. A 10Ω series resistor may be used to limit inrush current into the bypass capacitor, and to provide noise filtering for
the supply.
BYP is the interconnection point between a charge pump, V(AC) monitor amplifiers and comparators, and the gate
driver. C(BYP) must be used to filter the charge pump. A 2200 pF is recommended, but the value is not critical.
Common
Bus
Common Bus Powering
Common
Bus
Separate Bus Powering
5V
2200pF
10*
Input
* Optional Filtering
0.01 mF
Voltage
0.8 V - 18 V
10*
V DD
C
GATE GND
BYP
A
0.01 mF
V DD
C
GATE GND
BYP
A
3.3 V - 18 V
2200pF
Input
Voltage
* Optional Filtering
Figure 14. VDD Powering Examples
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11 Layout
11.1 Layout Guidelines
1.
2.
3.
4.
5.
6.
7.
8.
The TPS2412/13, MOSFET, and associated components should be used over a ground plane.
The GND connection should be short, with multiple vias to ground.
C(VDD) should be adjacent to the VDD pin with a minimal ground connection length to the plane.
The GATE connection should be short and wide (for example, 0.025" minimum).
The C pin should be Kelvin connected to the MOSFET.
The A pin should be a short, wide, Kelvin connection to the MOSFET.
R(SET) should be kept immediately adjacent to the TPS2412/13 with short leads.
C(BYP) should be kept immediately adjacent to the TPS2412/13 with short leads.
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11.2 Layout Example
POWER FLOW
S
S
S
D
D
MOSFET
D
G
D
B
Y
P
A
C
8
7
6
G
A
T
E
5
TPS2412/13
Top Trace
Bottom Trace
VIA
1
V
D
D
2
R
S
E
T
3
R
S
V
D
4
G
N
D
Figure 15. Layout Recommendation
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS2412
Click here
Click here
Click here
Click here
Click here
TPS2413
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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19
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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