Texas Instruments | UCC23513, 4-A Source, 5-A Sink, 5.7-kVRMS Opto-Compatible Single-Channel Isolated Gate Driver (Rev. D) | Datasheet | Texas Instruments UCC23513, 4-A Source, 5-A Sink, 5.7-kVRMS Opto-Compatible Single-Channel Isolated Gate Driver (Rev. D) Datasheet

Texas Instruments UCC23513, 4-A Source, 5-A Sink, 5.7-kVRMS Opto-Compatible Single-Channel Isolated Gate Driver (Rev. D) Datasheet
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UCC23513
SLUSD31D – OCTOBER 2018 – REVISED OCTOBER 2019
UCC23513, 4-A Source, 5-A Sink, 5.7-kVRMS Opto-Compatible
Single-Channel Isolated Gate Driver
1 Features
3 Description
•
The UCC23513 is an opto-compatible, singlechannel, isolated gate driver for IGBTs, MOSFETs
and SiC MOSFETs, with 4.5-A source and 5.3-A sink
peak output current and 5.7-KVRMS reinforced
isolation rating. The high supply voltage range of 33V allows the use of bipolar supplies to effectively
drive IGBTs and SiC power FETs. UCC23513 can
drive both low side and high side power FETs. Key
features and characteristics bring significant
performance and reliability upgrades over standard
opto-coupler based gate drivers while maintaining
pin-to-pin compatibility in both schematic and layout
design. Performance highlights include high common
mode transient immunity (CMTI), low propagation
delay, and small pulse width distortion. Tight process
control results in small part-to-part skew. The input
stage is an emulated diode (e-diode) which means
long
term
reliability
and
excellent
aging
characteristics compared to traditional LEDs. It is
offered in a stretched SO6 package with >8.5mm
creepage and clearance, and a mold compound from
material group I which has a comparative tracking
index (CTI) >600V. UCC23513's high performance
and reliability makes it ideal for use in all types of
motor drives, solar inverters, industrial power
supplies, and appliances. The higher operating
temperature opens up opportunities for applications
not previously able to be supported by traditional
optocouplers.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
5.7-kVRMS single channel isolated gate driver with
opto-compatible input
Pin-to-pin, drop in upgrade for opto isolated gate
drivers
4.5-A source / 5.3-A sink, peak output current
14-V to 33-V output driver supply voltage
Rail-to-rail output
105-ns (maximum) propagation delay
25-ns (maximum) part-to-part delay matching
35-ns (maximum) pulse width distortion
150-kV/μs (minimum) common-mode transient
immunity (CMTI)
Isolation barrier life >50 Years
13-V reverse polarity voltage handling capability
on input stage
Stretched SO-6 package with >8.5-mm creepage
and clearance
Operating junction temperature, TJ: –40°C to
+150°C
Safety-related certifications (Planned):
– 8000-VPKreinforced isolation per DIN V VDE
V0884-11: 2017-01
– 5.7-KVRMS isolation for 1 minute per UL 1577
– CQC certification per GB4943.1-2011
2 Applications
•
•
•
•
Industrial motor-control drives
Industrial power supplies, UPS
Solar inverters
Induction heating
Device Information(1)
PART NUMBER
UCC23513
PACKAGE
BODY SIZE (NOM)
Stretched SO-6
7.5 mm x 4.68 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram of UCC23513 (SO6)
NC 2
ISOLATION
ANODE 1
e
6 VCC
UVLO
5 VOUT
BARRIER
CATHODE 3
4 VEE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC23513
SLUSD31D – OCTOBER 2018 – REVISED OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Function ...........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ........................................ 8
Insulation Characteristics Curves ........................... 9
Typical Characteristics .......................................... 10
7
Parameter Measurement Information ................ 13
7.1 Propagation Delay, rise time and fall time .............. 13
7.2 IOH and IOL testing................................................... 13
7.3 CMTI Testing........................................................... 13
8
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 21
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
11.3 PCB Material ......................................................... 31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2019) to Revision D
•
Changed Minimum internal gap unit from mm to µm. ........................................................................................................... 6
Changes from Revision B (June 2019) to Revision C
•
2
Page
Page
Changed marketing status from Advance Information to initial release. ............................................................................... 1
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5 Pin Configuration and Function
UCC23513 Package
SO-6
Top View
1
6
ANODE
VCC
5
2
VOUT
NC
3
4
CATHODE
VEE
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
UCC23513
ANODE
1
I
Anode
CATHODE
3
I
Cathode
NC
2
-
No Connection
VCC
6
P
Positive output supply rail
VEE
4
P
Negative output supply rail
VOUT
5
O
Gate-drive output
(1)
P = Power, G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free air temperature range (unless otherwise noted) (1)
Average Input Current
IF(AVG)
Peak Transient Input Current
IF(TRAN) <1us pulse, 300pps
Reverse Input Voltage
VR(MAX)
Output supply voltage
VCC – VEE
Output signal voltage
VOUT – VCC
Output signal voltage
VOUT – VEE
MIN
MAX
-
25
UNIT
mA
1
A
14
V
35
V
0.3
V
-0.3
-0.3
V
Junction temperature
TJ (2)
-40
150
°C
Storage temperature
Tstg
-65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS–001 (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Output Supply Voltage(VCC – VEE)
IF (ON)
Input Diode Forward Current (Diode "ON")
VF (OFF)
NOM
MAX
UNIT
14
33
V
7
16
mA
Anode voltage - Cathode voltage (Diode "OFF")
-13
0.9
V
TJ
Junction temperature
-40
150
°C
TA
Ambient temperature
-40
125
°C
6.4 Thermal Information
UCC23513
THERMAL METRIC (1)
SO6
UNIT
6 Pins
RqJA
Junction-to-ambient thermal resistance
126
°C/W
RqJC(top)
Junction-to-case (top) thermal resistance
66.1
°C/W
RqJB
Junction-to-board thermal resistance
62.8
°C/W
YJT
Junction-to-top characterization parameter
29.6
°C/W
YJB
Junction-to-board characterization parameter
60.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the http://www.ti.com/lit/SPRA953 application report.
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6.5 Power Ratings
PARAMETER
PD
PD1
PD2
(1)
(2)
TEST CONDITIONS
Maximum power dissipation on input and
VCC = 20 V, IF= 10mA 10-kHz, 50% duty
output (1)
cycle, square wave,180-nF load,
Maximum input power dissipation (2)
TA=25oC
Maximum output power dissipation
MIN
TYP
MAX
UNIT
750
mW
10
mW
740
mW
Derate at 6 mW/°C beyond 25°C ambient temperature
Recommended maximum PD1 = 40mW. Absolute maximum PD1 = 55mW
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6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
SPECIFIC
ATION
UNIT
(1)
Shortest terminal-to-terminal distance through air
>8.5
mm
CPG
External Creepage (1)
Shortest terminal-to-terminal distance across the
package surface
>8.5
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>17
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
>600
V
Material Group
According to IEC 60664-1
I
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1500
Maximum isolation working voltage
AC voltage (sine wave); time-dependent dielectric
1060
breakdown (TDDB) test; see Figure 1
VRMS
DC voltage
1500
VDC
8000
VPK
8000
VPK
CLR
External clearance
Overvoltage category per IEC 60664-1
DIN V VDE 0884-11 (VDE V 0884-11)
VIORM
VIOWM
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
VIOSM
Maximum surge isolation voltage (2)
Test method per IEC 62368, 1.2/50 ms
waveform,
VTEST = 1.6 x VIOSM = 12800 VPK (qualification)
VPK
Method a: After I/O safety test subgroup 2/3,Vini =
VIOTM,
≤5
tini = 60 s; Vpd(m) = 1.2 x VIORM = 1800 VPK, tm =
10 s
Apparent charge (3)
qpd
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 x VIORM =
2400 VPK, tm = 10 s
≤5
pC
Method b1: At routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s; ≤5
Vpd(m) = 1.875 x VIORM = 2813 VPK, tm = 1 s
Barrier capacitance, input to output (4)
CIO
Insulation resistance, input to output (4)
RIO
VIO = 0.4 x sin (2πft), f = 1 MHz
0.5
VIO = 500 V, TA = 25°C
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
VIO = 500 V at TS = 150°C
>109
Pollution degree
2
Climatic category
40/125/21
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
6
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 s
(qualification),
VTEST = 1.2 x VISO = 6840 VRMS, t = 1 s (100%
production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
CQC
Plan to certify according to DIN V VDE V
0884-11: 2017-01
Plan to certify according to UL 1577
Component Recognition Program
Plan to certify according to GB4943.1-2011
Reinforced insulation Maximum transient
isolation voltage, 8000 VPK;
Maximum repetitive peak isolation voltage,
1500 VPK;
Maximum surge isolation voltage, 8000 VPK
Single protection, 5700 VRMS
Reinforced insulation, Altitude ≤ 5000 m,
Tropical Climate
Certificate planned
Certificate planned
Certificate planned
6.8 Safety Limiting Values
PARAMETER
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature (1)
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RqJA = 126°C/W, VI = 15 V, TJ = 150°C,
TA = 25°C
50
RqJA = 126°C/W, VI = 30 V, TJ = 150°C,
TA = 25°C
25
RqJA = 126°C/W, TJ = 150°C, TA = 25°C
750
mW
150
°C
mA
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ , specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RqJA, in the Thermal Information
table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value
for each parameter: TJ = TA + RqJA ´ P, where P is the power dissipated in the device. TJ(max) = TS = TA + RqJA ´ PS, where TJ(max) is the
maximum allowed junction temperature. PS = IS ´ VI , where VI is the maximum supply voltage.
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6.9 Electrical Characteristics
Unless otherwise noted, all typical values are at TA = 25°C, VCC–VEE= 15V, VEE= GND. All min and max specifications are at
recommended operating conditions (TJ = -40C to 150°C, IF(on)= 7 mA to 16 mA, VEE= GND, VCC= 15 V to 30 V, VF(off)= –5V to
0.8V)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT > 5 V, Cg = 1 nF
1.5
2.8
4
1.8
2.1
2.4
V
1
1.35
mV/ºC
INPUT
IFLH
Input Forward Threshold Current Low to High
VF
Input Forward Voltage
VF_HL
Threshold Input Voltage High to Low
ΔVF/ΔT
Temp Coefficient of Input Forward Voltage
VR
Input Reverse Breakdown Voltage
IR= 10 uA
CIN
Input Capacitance
F = 0.5 MHz
High Level Peak Output Current
IF = 10 mA, VCC =15V,
CLOAD=0.18uF,
CVDD=10uF, pulse
width <10us
IOL
Low Level Peak Output Current
VF= 0 V, VCC =15V,
CLOAD=0.18uF,
CVDD=10uF, pulse
width <10us
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VF = 0 V, IO= 20 mA
25
mV
ICC_H
Output Supply Current (Diode On)
IF = 10 mA, IO= 0 mA
2.2
mA
ICC_L
Output Supply Current (Diode Off)
VF = 0 V, IO= 0 mA
2
mA
IF =10 mA
V < 5 V, Cg = 1 nF
mA
0.9
IF =10 mA
V
15
V
15
pF
3
4.5
A
3.5
5.3
A
0.07
0.18
OUTPUT
IOH
IF = 10 mA, IO= -20mA
(with respect to VCC)
IF = 10 mA, IO= 0 mA
0.36
V
VCC
V
UNDER VOLTAGE LOCKOUT
UVLOR
Under Voltage Lockout VCC rising
VCC_Rising, IF=10 mA
11
12.5
13.5
V
UVLOF
Under Voltage Lockout VCC falling
VCC_Falling, IF=10 mA
10
11.5
12.5
V
UVLOHYS
UVLO Hysteresis
1.0
V
6.10 Switching Characteristics
Unless otherwise noted, all typical values are at TA = 25°C, VCC-VEE= 30 V, VEE= GND. All min and max specifications are at
recommended operating conditions (TJ = -40 to 150°C, IF(ON)= 7 mA to 16 mA, VEE= GND, VCC= 15 V to 30 V, VF(OFF)= –5V to
0.8V)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr
Output-signal Rise Time
28
ns
tf
Output-signal Fall Time
25
ns
tPLH
Propagation Delay, Low to High
70
105
ns
tPHL
Propagation Delay, High to Low
70
105
ns
tPWD
Pulse Width Distortion |tPHL –
tPLH|
35
ns
tsk(pp)
Part-to-Part Skew in Propagation
Delay Between any Two Parts (1)
Cg = 1nF
FSW = 20 kHz, (50% Duty Cycle)
VCC=15V, IF=10mA
25
ns
tUVLO_rec
UVLO Recovery Delay
VCC Rising from 0V to 15V
30
µs
CMTIH
Common-mode Transient
Immunity (Output High)
IF = 10 mA, VCM = 1500 V, VCC= 30 V,
TA= 25ºC
150
kV/µs
CMTIL
Common-mode Transient
Immunity (Output Low)
VF = 0 V, VCM = 1500 V, VCC= 30 V,
TA= 25ºC
150
kV/µs
(1)
8
Cg = 1nF
FSW = 20 kHz, (50% Duty Cycle)
VCC=15V
20
tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads ensured by characterization.
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6.11 Insulation Characteristics Curves
60
800
VCC=15V
VCC=30V
Gate Driver Power Dissipation PD (mW)
Safety Limiting Current (mA)
50
40
30
20
10
0
600
400
200
0
0
25
50
75
100
TA (°C)
125
150
0
25
50
75
TA (°C)
D015
Figure 1. Thermal Derating Curve for Limiting Current per
VDE
100
125
150
D014
Figure 2. Thermal Derating Curve for Limiting Power per
VDE
1.E+12
Safety Margin Zone: 1275 VRMS, 412 Years
Operating Zone: 1060 VRMS, 220 Years
1.E+11
87.5%
TDDB Line (<1 PPM Fail Rate)
412 Yrs
1.E+10
220 Yrs
1.E+09
Time to Fail (sec)
1.E+08
1.E+07
VDE Safety Margin Zone
1.E+06
1.E+05
Operating Zone
1.E+04
20%
1.E+03
1.E+02
1060 VRMS
1275 VRMS
1.E+01
200
1200
2200
3200
4200
5200
6200
Applied Voltage (VRMS)
Figure 3. Reinforced Isolation Capacitor Life Time Projection
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6.12 Typical Characteristics
VCC= 15 V, 1-µF capacitor from VCC to VEE, CLOAD = 1 nF for timing tests and 180nF for IOH and IOL tests, TJ = –40°C to
+150°C, (unless otherwise noted)
6.6
1.5
IOH
IOL
ICC H
ICC L
1.45
6
1.4
5.7
1.35
5.4
Current (mA)
Peak Current (A)
6.3
5.1
4.8
4.5
1.3
1.25
1.2
1.15
4.2
1.1
3.9
1.05
3.6
1
3.3
-40
-20
0
20
40
60
80
Temp (qC)
100
120
140
0.95
-40
160
-20
0
20
D001
40
60
80
Temp (qC)
100
120
140
160
D002
CLOAD = 180-nF
Figure 4. Output Drive currents versus Temperature
Figure 5. Supply currents versus Temperature
1.4
3.5
ICC H
ICC L
3.4
3.3
3.2
IFLH (mA)
Current (mA)
1.3
1.2
3.1
3
2.9
1.1
2.8
2.7
1
13
15.5
18
20.5
23
25.5
VCC (V)
28
30.5
33
2.6
-40
35
Figure 6. Supply current versus Supply Voltage
0
20
40
60
80
Temp (qC)
100
120
140
160
D004
Figure 7. Forward threshold current versus Temperature
66
84
82
-20
D003
tPDLH
tPDHL
64
80
Delay (ns)
Delay (ns)
78
76
74
72
62
tPDLH
tPDHL
60
70
58
68
66
64
-40
56
-20
0
20
40
60
80
Temp (qC)
100
120
140
160
7
9
D005
13
15
17
IF (mA)
19
21
23
25
D006
CLOAD = 1-nF
CLOAD = 1-nF
Figure 8. Propagation delay versus Temperature
10
11
Figure 9. Propagation delay versus Forward current
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Typical Characteristics (continued)
0.9
300
0.85
280
Voltage Drop (VCC-VOUT) (mV)
Voltage Drop (VCC-VOUT) (mV)
VCC= 15 V, 1-µF capacitor from VCC to VEE, CLOAD = 1 nF for timing tests and 180nF for IOH and IOL tests, TJ = –40°C to
+150°C, (unless otherwise noted)
0.8
0.75
0.7
0.65
0.6
0.55
0.5
260
240
220
200
180
160
140
0.45
-40
-20
0
20
40
60
80
Temp (qC)
100
120
140
120
-40
160
-20
0
20
D007
IOUT = 0mA
40
60
80
Temp (qC)
100
120
140
160
D008
IOUT = 20mA
(sourcing)
Figure 10. VOH (No Load) versus Temperature
Figure 11. VOH (20mA Load) versus Temperature
20
71
19
18
70
16
Delay (ns)
VOUT (mV)
17
15
14
69
tPLH
tPHL
13
68
12
11
10
-40
-20
0
20
40
60
80
Temp (qC)
100
120
140
67
10
160
15
20
25
30
35
VCC (V)
D009
D010
IOUT = 20mA
(sinking)
Figure 13. Propagation delay versus Supply voltage
Figure 12. VOL versus Temperature
3
2.2
2.8
2.1
2.6
2
2.2
VF (V)
ICC (mA)
2.4
2
1.9
1.8
1.8
1.6
1.4
1.7
1.2
1
1.6
0
20
40
60
80 100 120
Freq (KHz)
140
160
180
200
4
6
D011
8
10
12
14 16
IF (mA)
18
20
22
24 25
D012
TA = 25°C
Figure 14. Supply current versus Frequency
Figure 15. Forward current versus Forward voltage drop
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Typical Characteristics (continued)
VCC= 15 V, 1-µF capacitor from VCC to VEE, CLOAD = 1 nF for timing tests and 180nF for IOH and IOL tests, TJ = –40°C to
+150°C, (unless otherwise noted)
2.3
2.28
2.26
2.24
VF (V)
2.22
2.2
2.18
2.16
2.14
2.12
2.1
2.08
-40
-20
0
20
40
60
80
Temp (qC)
100
120
140
160
D013
IF = 10mA
Figure 16. Forward voltage drop versus Temperature
12
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7 Parameter Measurement Information
7.1 Propagation Delay, rise time and fall time
Figure 17 shows the propagation delay from the input forward current IF, to VOUT. This figures also shows the
circuit used to measure the rise (tr) and fall (tf) times and the propagation delays tPDLH and tPDHL.
ANODE
1
IF
VCC
ISOLATION
270Q
+
VOUT
NC
5
0
IF
6
2
e
BARRIER
3
tPD_HL
-
1nF
CATHODE
tPD_LH
15V
5
80%
50%
20%
VOUT
VEE
4
tf
tr
Figure 17. IF to VOUT Propagation Delay, Rise Time and Fall Time
7.2 IOH and IOL testing
Figure 18 shows the circuit used to measure the output drive currents IOH and IOL. A load capacitance of 180nF is
used at the output. The peak dv/dt of the capacitor voltage is measured in order to determine the peak source
and sink currents of the gate driver.
ANODE
1
IF
VCC
ISOLATION
270Q
6
+
VOUT
NC
5
0
e
2
IOH
15V
5
IOL
180nF
BARRIER
CATHODE
3
-
VEE
4
Figure 18. IOH and IOL
7.3 CMTI Testing
Figure 19 is the simplified diagram of the CMTI testing. Common mode voltage is set to 1500V. The test is
performed with IF = 6mA (VOUT= High) and IF = 0mA (VOUT = LOW). The diagram also shows the fail criteria for
both cases. During the application on the CMTI pulse with IF = 6mA, if VOUT drops from VCC to ½VCC it is
considered as a failure. With IF= 0mA, if VOUT rises above 1V, it is considered as a failure.
e-diode off
e-diode on
ANODE
150Q
ISOLATION
1
IF
+
VCC
1500V
2
e
15V
5
1nF
CATHODE
3
BARRIER
150Q
VCM
1500V
+
VOUT
NC
5V
6
VCM
0V
30V
0V
VOUT
VEE
4
15V
Fail Threshold
0V
VCM =1500V
t
1V
0V
Fail Threshold
VOUT
t
Figure 19. CMTI Test Circuit for UCC23513
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8 Detailed Description
8.1 Overview
UCC23513 is a single channel isolated gate driver, with an opto-compatible input stage, that can drive IGBTs,
MOSFETs and SiC FETs. It has 4A peak output current capability with max output driver supply voltage of 33V.
The inputs and the outputs are galvanically isolated. UCC23513 is offered in an industry standard 6 pin (SO6)
package with >8.5mm creepage and clearance. It has a working voltage of 1060-VRMS, reinforced isolation rating
of 5.7-KVRMS for 60s and a surge rating of 8-kVPK. It is pin-to-pin compatible with standard opto isolated gate
drivers. While standard opto isolated gate drivers use an LED as the input stage, UCC23513 uses an emulated
diode (or "e-diode") as the input stage which does not use light emission to transmit signals across the isolation
barrier. The input stage is isolated from the driver stage by dual, series HV SiO2 capacitors in full differential
configuration that not only provides reinforced isolation but also offers best-in-class common mode transient
immunity of >150kV/us. The e-diode input stage along with capacitive isolation technology gives UCC23513
several performance advantages over standard opto isolated gate drivers. They are as follows:
1. Since the e-diode does not use light emission for its operation, the reliability and aging characteristics of
UCC23513 are naturally superior to those of standard opto isolated gate drivers.
2. Higher ambient operating temperature range of 125°C, compared to only 105°C for most opto isolated gate
drivers
3. The e-diode forward voltage drop has less part-to-part variation and smaller variation across temperature.
Hence, the operating point of the input stage is more stable and predictable across different parts and
operating temperature.
4. Higher common mode transient immunity than opto isolated gate drivers
5. Smaller propagation delay than opto isolated gate drivers
6. Due to superior process controls achievable in capacitive isolation compared to opto isolation, there is less
part-to-part skew in the prop delay, making the system design simpler and more robust
7. Smaller pulse width distortion than opto isolated gate drivers
The signal across the isolation has an on-off keying (OOK) modulation scheme to transmit the digital data across
a silicon dioxide based isolation barrier (see Figure 20). The transmitter sends a high-frequency carrier across
the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver
demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. The
UCC23513 also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the
radiated emissions from the high frequency carrier and IO buffer switching. Figure 21 shows conceptual detail of
how the OOK scheme works.
8.2 Functional Block Diagram
Receiver
NC
IF
VBIAS
Vclamp
Cathode
RNMOS
VEE
Amplifier
Oscillator
VCC
UVLO
ISOLATION
Anode
BARRIER
Transmitter
Demodulator
ROH
Level
Shift /
Pre
driver
VOUT
ROL
VEE
Figure 20. Conceptual Block Diagram of a Isolated Gate Driver with an Opto Emulated Input Stage (SO6
pkg)
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Functional Block Diagram (continued)
IF IN
Carrier signal
through isolation
barrier
RX OUT
Figure 21. On-Off Keying (OOK) Based Modulation Scheme
8.3 Feature Description
8.3.1 Power Supply
Since the input stage is an emulated diode, no power supply is needed at the input.
The output supply, VCC, supports a voltage range from 14V to 33V. For operation with bipolar supplies, the power
device is turned off with a negative voltage on the gate with respect to the emitter or source. This configuration
prevents the power device from unintentionally turning on because of current induced from the Miller effect. The
typical values of the VCC and VEE output supplies for bipolar operation are 15V and -8V with respect to GND for
IGBTs, and 20V and -5V for SiC MOSFETs.
For operation with unipolar supply, the VCC supply is connected to 15V with respect to GND for IGBTs, and 20V
for SiC MOSFETs. The VEE supply is connected to 0V.
8.3.2 Input Stage
The input stage of UCC23513 is simply the e-diode and therefore has an Anode (Pin 1) and a Cathode (Pin 3).
Pin 2 has no internal connection and can be left open or connected to ground. The input stage does not have a
power and ground pin. When the e-diode is forward biased by applying a positive voltage to the Anode with
respect to the Cathode, a forward current IF flows into the e-diode. The forward voltage drop across the e-diode
is 2.1V (typ). An external resistor should be used to limit the forward current. The recommended range for the
forward current is 7mA to 16mA. When IF exceeds the threshold current IFLH(2.8mA typ.) a high frequency signal
is transmitted across the isolation barrier through the high voltage SiO2 capacitors. The HF signal is detected by
the receiver and VOUT is driven high. See Selecting the Input Resistor for information on selecting the input
resistor. The dynamic impedance of the e-diode is very small(<1.0Ω) and the temperature coefficient of the ediode forward voltage drop is <1.35mV/°C. This leads to excellent stability of the forward current IF across all
operating conditions. If the Anode voltage drops below VF_HL (0.9V), or reverse biased, the gate driver output is
driven low. The reverse breakdown voltage of the e-diode is >15V. So for normal operation, a reverse bias of up
to 13V is allowed. The large reverse breakdown voltage of the e-diode enables UCC23513 to be operated in
interlock architecture (see example in Figure 22) where VSUP can be as high as 12V. The system designer has
the flexibility to choose a 3.3V, 5.0V or up to 12V PWM signal source to drive the input stage of UCC23513 using
an appropriate input resistor. The example shows two gate drivers driving a set of IGBTs. The inputs of the gate
drivers are connected as shown and driven by two buffers that are controlled by the MCU. Interlock architecture
prevents both the e-diodes from being "ON" at the same time, preventing shoot through in the IGBTs. It also
ensures that if both PWM signals are erroneously stuck high (or low) simultaneously, both gate driver outputs will
be driven low.
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Feature Description (continued)
VSUP
ANODE
ISOLATION
R1
HSON from MCU
1
GND
NC
UVLO
VOUT
To High Side
Gate
5
BARRIER
VSUP
CATHODE
R2
6
e
2
LSON from MCU
VCC
3
VEE
4
GND
ANODE
ISOLATION
1
NC
2
VCC
6
UVLO
VOUT
e
3
5
BARRIER
CATHODE
To Low Side
Gate
VEE
4
Figure 22. Interlock
8.3.3 Output Stage
The output stages of the UCC23513 family feature a pullup structure that delivers the highest peak-source
current when it is most needed which is during the Miller plateau region of the power-switch turnon transition
(when the power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure features
a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel
MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turnon. Fast turnon is
accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing
states from low to high. The on-resistance of this N-channel MOSFET (RNMOS) is approximately 5.1 Ω when
activated.
Table 1. UCC23513 On-Resistance
RNMOS
ROH
ROL
UNIT
5.1
9.5
0.40
Ω
The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device
only. This parameter is only for the P-channel device because the pullup N-channel device is held in the OFF
state in DC condition and is turned on only for a brief instant when the output is changing states from low to high.
Therefore, the effective resistance of the UCC23513 pullup stage during this brief turnon phase is much lower
than what is represented by the ROH parameter, yielding a faster turn on. The turnon-phase output resistance is
the parallel combination ROH || RNMOS.
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The pulldown structure in the UCC23513 is simply composed of an N-channel MOSFET. The output voltage
swing between VCC and VEE provides rail-to-rail operation because of the MOS-out stage which delivers very low
dropout.
VCC
UVLO
RNMOS
VEE
Demodulator
ROH
VOUT
Level
Shift /
Pre
driver
ROL
VEE
Figure 23. Output Stage
8.3.4 Protection Features
8.3.4.1 Undervoltage Lockout (UVLO)
UVLO function is implemented for VCC and VEE pins to prevent an under-driven condition on IGBTs and
MOSFETs. When VCC is lower than UVLOR at device start-up or lower than UVLOF after start-up, the voltagesupply UVLO feature holds the effected output low, regardless of the input forward current as shown in Table 2.
The VCC UVLO protection has a hysteresis feature (UVLOhys). This hysteresis prevents chatter when the power
supply produces ground noise which allows the device to permit small drops in bias voltage, which occurs when
the device starts switching and operating current consumption increases suddenly.
When VCC drops below UVLOF, a delay, tUVLO_rec occurs on the output when the supply voltage rises above
UVLOR again.
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10mA
VCC
UVLOR
UVLOF
VCC
VOUT
tUVLO_rec
t
Figure 24. UVLO functionality
8.3.4.2 Active Pulldown
The active pull-down function is used to pull the IGBT or MOSFET gate to the low state when no power is
connected to the VCC supply. This feature prevents false IGBT and MOSFET turn-on by clamping VOUT pin to
approximately 2V.
When the output stage of the driver is in an unbiased condition (VCC floating), the driver outputs (see Figure 23)
are held low by an active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the
upper PMOS & NMOS are held off while the lower NMOS gate is tied to the driver output through an internal
500-kΩ resistor. In this configuration, the lower NMOS device effectively clamps the output (VOUT) to less than
2V.
8.3.4.3 Short-Circuit Clamping
The short-circuit clamping function is used to clamp voltages at the driver output and pull the output pin VOUT
slightly higher than the VCC voltage during short-circuit conditions. The short-circuit clamping function helps
protect the IGBT or MOSFET gate from overvoltage breakdown or degradation. The short-circuit clamping
function is implemented by adding a diode connection between the dedicated pins and the VCC pin inside the
driver. The internal diodes can conduct up to 500-mA current for a duration of 10 µs and a continuous current of
20 mA. Use external Schottky diodes to improve current conduction capability as needed.
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8.4 Device Functional Modes
Table 2 lists the functional modes for UCC23513
Table 2. Function Table for UCC23513 with VCC Rising
e-diode
VCC
VOUT
OFF (IF< IFLH)
0V - 33V
Low
ON (IF> IFLH)
0V - UVLOR
Low
ON ( (IF> IFLH)
UVLOR - 33V
High
Table 3. Function Table for UCC23513 with VCC Falling
e-diode
VCC
VOUT
OFF (IF< IFLH)
0V - 33V
Low
ON (IF> IFLH)
UVLOF- 0V
Low
ON ( (IF> IFLH)
33V - UVLOF
High
8.4.1 ESD Structure
Figure 25 shows the multiple diodes involved in the ESD protection components of the UCC23513 device . This
provides pictorial representation of the absolute maximum rating for the device.
VCC
Anode
40V
20V
VOUT
40V
2.5V
36V
Cathode
VEE
Figure 25. ESD Structure
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
UCC23513 is a single channel, isolated gate driver with opto-compatible input for power semiconductor devices,
such as MOSFETs, IGBTs, or SiC MOSFETs. It is intended for use in applications such as motor control,
industrial inverters, and switched-mode power supplies. It differs from standard opto isolated gate drivers as it
does not have an LED input stage. Instead of an LED, it has an emulated diode (e-diode). To turn the e-diode
"ON", a forward current in the range of 7mA to 16mA should be driven into the Anode. This will drive the gate
driver output High and turn on the power FET. Typically, MCU's are not capable of providing the required forward
current. Hence a buffer has to be used between the MCU and the input stage of UCC23513. Typical buffer
power supplies are either 5V or 3.3V. A resistor is needed between the buffer and the input stage of the
UCC23513 to limit the current. It is simple, but important to choose the right value of resistance. The resistor
tolerance, buffer supply voltage tolerance and output impedance of the buffer, have to be considered in the
resistor selection. This will ensure that the e-diode forward current stays within the recommended range of 7mA
to 16mA. Detailed design recommendations are given in the Application Information. The current driven input
stage offers excellent noise immunity that is need in high power motor drive systems, especially in cases where
the MCU cannot be located close to the isolated gate driver. UCC23513 offers best in class CMTI performance
of >150kV/us at 1500V common mode voltages.
The e-diode is capable of 25mA continuous in the forward direction. The forward voltage drop of the e-diode has
a very tight part to part variation (1.8V min to 2.4V max). The temperature coefficient of the forward drop is
<1.35mV/°C. The dynamic impedance of the e-diode in the forward biased region is ~1Ω. All of these factors
contribute in excellent stability of the e-diode forward current. To turn the e-diode "OFF", the Anode - Cathode
voltage should be <0.8V, or IF should be <IFLH. The e-diode can also be reverse biased up to 13V (14V abs max)
in order to turn it off and bring the gate driver output low. The large reverse breakdown voltage of the input stage
provides system designers the flexibility to drive the input stage with 12V PWM signals without the need for an
additional clamping circuit on the Anode and Cathode pin.
The output power supply for UCC23513 can be as high as 33V (35V abs max). The output power supply can be
configured externally as a single isolated supply up to 33V or isolated bipolar supply such that VCC-VEE does not
exceed 33V, or it can be bootstrapped (with external diode & capacitor) if the system uses a single power supply
with respect to the power ground. Typical quiescent power supply current from VCC is 1.2mA (max 2.2mA).
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9.2 Typical Application
The circuit in Figure 26, shows a typical application for driving IGBTs.
VSUP
REXT/2
ISOLATION
ANODE
1
IF
+
NC
VF
2
VCC
6
15V
VOUT
e
5
BARRIER
CATHODE
3
+
VEE
-
RGON
RG_int
RGOFF
4
REXT/2
PWM
M1
GND
Figure 26. Typical Application Circuit for UCC23513 to Drive IGBT
9.2.1 Design Requirements
Table 4 lists the recommended conditions to observe the input and output of the UCC23513 gate driver.
Table 4. UCC23513 Design Requirements
PARAMETER
VALUE
UNIT
VCC
15
V
IF
10
mA
Switching frequency
8
kHz
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9.2.2 Detailed Design Procedure
9.2.2.1 Selecting the Input Resistor
The input resistor limits the current that flows into the e-diode when it is forward biased. The threshold current
IFLH is 2.5mA typ. The recommended operating range for the forward current is 7mA to 16mA (e-diode ON). All
the electrical specifications are guaranteed in this range. The resistor should be selected such that for typical
operating conditions, IF is 10mA. Following are the list of factors that will affect the exact value of this current:
1. Supply Voltage VSUP variation
2. Manufacturer's tolerance for the resistor and variation due to temperature
3. e-diode forward voltage drop variation (at IF=10mA, VF= typ 2.1V, min 1.8V, max 2.4V, with a temperature
coefficient <1.35mV/°C and dynamic impedance <1Ω)
See Figure 27 for the schematic using a single NMOS and split resistor combination to drive the input stage of
UCC23513. The input resistor can be selected using the equation shown.
VSUP
REXT/2
1
IF
+
6
VOUT
NC
VF
VCC
ISOLATION
ANODE
e
2
5
BARRIER
CATHODE
3
VEE
4
REXT/2
PWM
M1
GND
R EXT =
VSUP F VF
F R M1
IF
Figure 27. Configuration 1: Driving the input stage of UCC23513 with a single NMOS and split resistors
Driving the input stage of UCC23513 using a single buffer is shown in Figure 28 and using 2 buffers is shown in
Figure 29
VSUP
ANODE
ISOLATION
IF
REXT/2
PWM (From MCU)
1
GND
+
NC
VF
2
e
GND
CATHODE
3
R EXT =
5
BARRIER
-
REXT/2
VCC
6
VEE
4
VSUP F VF
F R OH_buf
IF
Figure 28. Configuration 2: Driving the input stage of UCC23513 with one Buffer and split resistors
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VSUP
IF
ANODE
ISOLATION
REXT/2
PWM (From MCU)
1
GND
+
NC
VF
2
VSUP
CATHODE
3
R EXT =
5
BARRIER
-
REXT/2
PWM (From MCU)
e
VCC
6
VEE
4
VSUP F VF
F (R OH_buf + R OL_buf)
IF
Figure 29. Configuration 3: Driving the input stage of UCC23513 with 2 buffers and split resistors
Table 5 shows the range of values for REXT for the 3 different configurations shown in Figure 27, Figure 28 and
Figure 29.The assumptions used in deriving the range for REXT are as follows:
1. Target forward current IF is 7mA min, 10mA typ and 16mA max
2. e-diode forward voltage drop is 1.8V to 2.4V
3. VSUP (Buffer supply voltage) is 5V with ±5% tolerance
4. Manufacturer's tolerance for REXT is 1%
5. NMOS resistance is 0.25Ω to 1.0Ω (for configuration 1)
6. ROH(buffer output impedance in output "High" state) is 13Ω min, 18Ω typ and 22Ω max
7. ROL(buffer output impedance in "Low" state) is 10Ω min, 14Ω typ and 17Ω max
Table 5. REXT Values to Drive The Input Stage
REXT Ω
Min
Typ
Max
Single NMOS and
REXT
218
290
331
Single Buffer and
REXT
204
272
311
Two Buffers and REXT
194
259
294
Configuration
9.2.2.2 Gate-Driver Output Resistor
The external gate-driver resistors, RG(ON) and RG(OFF) are used to:
1. Limit ringing caused by parasitic inductances and capacitances
2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
4. Reduce electromagnetic interference (EMI)
The output stage has a pull up structure consisting of a P-channel MOSFET and an N-channel MOSFET in
parallel. The combined peak source current is 4.6 A Use Equation 1 to estimate the peak source current as an
example.
(1)
IOH = min H4.5A,
VCC
(R NMOS ||R OH + R GON + R GFETINT )
I
where
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•
•
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RGON is the external turnon resistance.
RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will
assume 0Ω for our example
IOH is the peak source current which is the minimum value between 4.6A, the gate-driver peak source current,
and the calculated value based on the gate-drive loop resistance.
(2)
•
In this example, the peak source current is approximately 1.8A as calculated in Equation 3.
IOH = min H4.5A,
15
(5.sÀ||9.wÀ + wÀ + rÀ)
I = 1.8A
(3)
Similarly, use Equation 4 to calculate the peak sink current.
IOL = min H5.3A,
VCC
(R OL + R GOFF + R GFETINT )
I
where
•
•
RGOFF is the external turnoff resistance.
IOL is the peak sink current which is the minimum value between 5.7A, the gate-driver peak sink current, and
the calculated value based on the gate-drive loop resistance.
(4)
In this example, the peak sink current is the minimum of Equation 5 and 5.7A.
IOL = min H5.3A,
15
(0.vÀ + srÀ + rÀ)
I = 1.44A
(5)
NOTE
The estimated peak current is also influenced by PCB layout and load capacitance.
Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and
introduce overshoot and undershoot. Therefore, TI strongly recommends that the gatedriver loop should be minimized. Conversely, the peak source and sink current is
dominated by loop parasitics when the load capacitance (CISS) of the power transistor is
very small (typically less than 1 nF) because the rising and falling time is too small and
close to the parasitic ringing period.
9.2.2.3 Estimate Gate-Driver Power Loss
The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC23513 device and
the power losses in the peripheral circuitry, such as the external gate-drive resistor.
The PGD value is the key power loss which determines the thermal safety-related limits of the UCC23513 device,
and it can be estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes power dissipated in the input stage (PGDQ_IN)
as well as the quiescent power dissipated in the output stage (PGDQ_OUT) when operating with a certain switching
frequency under no load. PGDQ_IN is determined by IF and VF and is given by Equation 6. The PGDQ_OUT
parameter is measured on the bench with no load connected to VOUT pin at a given VCC, switching frequency,
and ambient temperature. In this example, VCC is 15 V. The current on the power supply, with PWM switching at
10 kHz, is measured to be ICC = 1.33 mA . Therefore, use Equation 7 to calculate PGDQ_OUT.
1
PGDQ _IN = 2 Û VF * IF
(6)
PGDQ _OUT = VCC * ICC
(7)
The total quiescent power (without any load capacitance) dissipated in the gate driver is given by the sum of
Equation 6 and Equation 7 as shown in Equation 8
24
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PGDQ = PGDQ _IN + PGDQ _OUT = 10 mW + 20mW = 30mW
(8)
The second component is the switching operation loss, PGDSW, with a given load capacitance which the driver
charges and discharges the load during each switching cycle. Use Equation 9 to calculate the total dynamic loss
from load switching, PGSW.
PGSW VCC2 u QG u fSW
where
•
QG is the gate charge of the power transistor at VCC.
(9)
So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated
in Equation 10.
PGSW 15 V u 120 nC u 10 kHz 18 mW
(10)
QG represents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change
with different testing conditions. The UCC23513 gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO
is equal to PGSW if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the
gate driver-loss will be dissipated inside the UCC23513. If an external turn-on and turn-off resistance exists, the
total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and powertransistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the
source/sink current is not saturated to 4.6A/5.7A, however, it will be non-linear if the source/sink current is
saturated. Therefore, PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
PGDO =
PGSW
ROH ||RNMOS
ROL
H
+
I
2
ROH ||RNMOS + RGON + RGFET_int ROL + RGOFF + RGFET_int
(11)
In this design example, all the predicted source and sink currents are less than 4.6 A and 5.7 A, therefore, use
Equation 11 to estimate the UCC23513 gate-driver loss.
PGDO =
18 mW
9.5À||5.1À
0.4À
H
+
I = 3.9 mW
2
9.5À||5.1À + 5.1À + 0À 0.4À + 10À + 0À
(12)
Case 2 - Nonlinear Pull-Up/Down Resistor:
PGDO = fsw x f4.5A x ± (VCC F VOUT (t))dt + 5.3A x ± VOUT (t) dtj
T R _Sys
0
T F_Sys
0
where
•
VOUT(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is
saturated for some time, this value can be simplified as a constant-current source (4.6 A at turnon and 5.7 A at
turnoff) charging or discharging a load capacitor. Then, the VOUT(t) waveform will be linear and the TR_Sys and
TF_Sys can be easily predicted.
(13)
For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO is
a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based
on this discussion.
Use Equation 14 to calculate the total gate-driver loss dissipated in the UCC23513 gate driver, PGD.
PGD = PGDQ + PGDO = 30mW + 3.9mW = 33.9mW
(14)
9.2.2.4 Estimating Junction Temperature
Use Equation 15 to estimate the junction temperature (TJ) of UCC23513.
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TJ
TC
www.ti.com
< JT u PGD
where
•
•
TC is the UCC23513 case-top temperature measured with a thermocouple or some other instrument.
ΨJT is the junction-to-top characterization parameter from the table.
(15)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RθJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
The RθJC resistance can only be used effectively when most of the thermal energy is released through the case,
such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of RθJC will
inaccurately estimate the true junction temperature. The ΨJT parameter is experimentally derived by assuming
that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the
application environment. As long as the recommended layout guidelines are observed, junction temperature
estimations can be made accurately to within a few degrees Celsius.
9.2.2.5 Selecting VCC Capacitor
Bypass capacitors for VCC is essential for achieving reliable performance. TI recommends choosing low-ESR and
low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with sufficient voltage ratings, temperature
coefficients, and capacitance tolerances. A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the
CVCC capacitor. If the bias power supply output is located a relatively long distance from the VCC pin, a tantalum
or electrolytic capacitor with a value greater than 10 μF should be used in parallel with CVCC.
NOTE
DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V,
1-μF X7R capacitor is measured to be only 500 nF when a DC bias of 15-VDC is applied.
10 Power Supply Recommendations
The recommended input supply voltage (VCC) for the UCC23513 device is from 14V to 33V. The lower limit of the
range of output bias-supply voltage (VCC) is determined by the internal UVLO protection feature of the device.
VCC voltage should not fall below the UVLO threshold for normal operation, or else the gate-driver outputs can
become clamped low for more than 20 μs by the UVLO protection feature. The higher limit of the VCC range
depends on the maximum gate voltage of the power device that is driven by the UCC23513 device, and should
not exceed the recommended maximum VCC of 33 V. A local bypass capacitor should be placed between the
VCC and VEE pins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing an additional 100nF capacitor in parallel with the device biasing capacitor for high frequency filtering. Both capacitors should be
positioned as close to the device as possible. Low-ESR, ceramic surface-mount capacitors are recommended.
If only a single, primary-side power supply is available in an application, isolated power can be generated for the
secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501
Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for
Isolated Power Supplies data sheet.
26
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11 Layout
11.1 Layout Guidelines
Designers must pay close attention to PCB layout to achieve optimum performance for the UCC23513. Some
key guidelines are:
• Component placement:
– Low-ESR and low-ESL capacitors must be connected close to the device between the VCC and VEE pins to
bypass noise and to support high peak currents when turning on the external power transistor.
– To avoid large negative transients on the VEE pins connected to the switch node, the parasitic inductances
between the source of the top transistor and the source of the bottom transistor must be minimized.
• Grounding considerations:
– Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area
is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of
the transistors. The gate driver must be placed as close as possible to the transistors.
• High-voltage considerations:
– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces
or copper below the driver device. A PCB cutout or groove is recommended in order to prevent
contamination that may compromise the isolation performance.
• Thermal considerations:
– A large amount of power may be dissipated by the UCC23513 if the driving voltage is high, the load is
heavy, or the switching frequency is high. Proper PCB layout can help dissipate heat from the device to
the PCB and minimize junction-to-board thermal impedance (θJB).
– Increasing the PCB copper connecting to the VCC and VEE pins is recommended, with priority on
maximizing the connection to VEE. However, the previously mentioned high-voltage PCB considerations
must be maintained.
– If the system has multiple layers, TI also recommends connecting the VCC and VEE pins to internal ground
or power planes through multiple vias of adequate size. These vias should be located close to the IC pins
to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high
voltage planes are overlapping.
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11.2 Layout Example
Figure 30 shows a PCB layout example with the signals and key components labeled.
(1)
No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.
Figure 30. Layout Example
28
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Layout Example (continued)
Figure 31 and Figure 32 show the top and bottom layer traces and copper.
Figure 31. Top-Layer Traces and Copper
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Layout Example (continued)
Figure 32. Bottom-Layer Traces and Copper (Flipped)
30
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Layout Example (continued)
Figure 33 shows the 3D layout of the top view of the PCB.
(1)
The location of the PCB cutout between primary side and secondary sides ensures isolation performance.
Figure 33. 3-D PCB View
11.3 PCB Material
Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of
lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the selfextinguishing flammability-characteristics.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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UCC23513
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www.ti.com
PACKAGE OUTLINE
SOIC -3.55 mm max height
DWY0006A
SOIC
C
11.75
11.25
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
6
1
SYMM
4.78
4.58
2X
2.54
3
4
SYMM
B
6X
0.51
0.28
0.25
C A
B
3.55 MAX
7.60
7.40
0.304
0.204
SEE DETAIL A
(3.18)
GAGE PLANE 0.25
0.30
0.10
1.00
0.50
DETAIL A
TYPICAL
4223977/A 01/2018
NOTES:
1.
2.
3.
4.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
This dimension does not include interlead flash. Interlead flash shall not exceed 0.70 per side.
www.ti.com
32
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EXAMPLE BOARD LAYOUT
SOIC - 3.55 mm max height
DWY0006A
SOIC
SYMM
6X(1.905)
SEE DETAILS
SYMM
6X(0.76)
6X(1.27)
(10.75)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
0.07 MAX
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAAILS
4223977/A 01/2018
NOTES: (continued)
5.
6.
Publication IPC-7351 may have alternate designs.
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
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UCC23513
SLUSD31D – OCTOBER 2018 – REVISED OCTOBER 2019
www.ti.com
EXAMPLE STENCIL DESIGN
SOIC - 3.55 mm max height
DWY0006A
SOIC
6X(1.905)
SYMM
SEE DETAILS
SYMM
6X(0.76)
6X(1.27)
(10.75)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 6X
4223977/A 01/2018
NOTES: (continued)
7.
8.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
Board assembly site may have different recommendations for stencil design.
www.ti.com
34
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC23513DWY
ACTIVE
SOIC
DWY
6
100
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC23513
UCC23513DWYR
ACTIVE
SOIC
DWY
6
850
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC23513
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC23513DWYR
Package Package Pins
Type Drawing
SOIC
DWY
6
SPQ
850
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
12.05
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
5.08
4.0
16.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC23513DWYR
SOIC
DWY
6
850
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
SOIC -3.55 mm max height
DWY0006A
SOIC
C
11.75
11.25
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
6
1
SYMM
4.78
4.58
2X
2.54
3
4
SYMM
B
6X
0.51
0.28
0.25
C A
B
3.55 MAX
7.60
7.40
0.304
0.204
SEE DETAIL A
(3.18)
GAGE PLANE 0.25
0.30
0.10
1.00
0.50
DETAIL A
TYPICAL
4223977/A 01/2018
NOTES:
1.
2.
3.
4.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
This dimension does not include interlead flash. Interlead flash shall not exceed 0.70 per side.
www.ti.com
EXAMPLE BOARD LAYOUT
SOIC - 3.55 mm max height
DWY0006A
SOIC
SYMM
6X(1.905)
SEE DETAILS
SYMM
6X(0.76)
6X(1.27)
(10.75)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
0.07 MAX
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAAILS
4223977/A 01/2018
NOTES: (continued)
5.
6.
Publication IPC-7351 may have alternate designs.
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOIC - 3.55 mm max height
DWY0006A
SOIC
6X(1.905)
SYMM
SEE DETAILS
SYMM
6X(0.76)
6X(1.27)
(10.75)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 6X
4223977/A 01/2018
NOTES: (continued)
7.
8.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
Board assembly site may have different recommendations for stencil design.
www.ti.com
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