Texas Instruments | UCC28064A Natural Interleaving™ Transition-Mode PFC Controller with High Light-Load Efficiency (Rev. B) | Datasheet | Texas Instruments UCC28064A Natural Interleaving™ Transition-Mode PFC Controller with High Light-Load Efficiency (Rev. B) Datasheet

Texas Instruments UCC28064A Natural Interleaving™ Transition-Mode PFC Controller with High Light-Load Efficiency (Rev. B) Datasheet
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UCC28064A
SLUSC60B – DECEMBER 2017 – REVISED OCTOBER 2019
UCC28064A Natural Interleaving™ Transition-Mode PFC Controller
with High Light-Load Efficiency
1 Features
3 Description
•
The UCC28064A interleaved PFC controller has
higher power ratings than previously possible. The
device uses a Natural Interleaving™ technique. Both
channels operate as masters (there is no slave
channel) synchronized to the same frequency. This
approach enables faster response time, excellent
phase-to-phase on-time matching, and transition
mode operation for each channel. The device has a
burst mode function to get high light-load efficiency.
Burst mode eliminates the need to turn off the PFC
during light load operation to meet standby power
targets. Burst mode eliminates the need for an
auxiliary flyback converter when paired with
UCC25630x LLC controller and the UCC24624
synchronous rectifier controller.
•
•
•
•
•
•
Input filter and output capacitor ripple-current
reduction
– Reduced current ripple for higher system
reliability and smaller bulk capacitor
– Reduced EMI filter size
High light-load efficiency
– User adjustable phase management with input
voltage compensation
– Burst mode operation with adjustable burst
threshold
– Helps enable compliance to EUP Lot6 Tier II,
CoC Tier II and DOE Level VI standards
Sensorless current-shaping simplifies board layout
and improves efficiency
Input line feed-forward for fast line transient
response
Inrush-safe current limiting:
– Prevents MOSFET conduction during inrush
– Eliminates CCM operation and reverse
recovery events in output rectifier
Operating temperature range –40°C to +125°C in
a 16-pin SOIC package
Create a Custom Design Using the UCC28064A
With the WEBENCH® Power Designer
Device Information(1)
PART NUMBER
UCC28064A
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
5
POUT = 600 W
VOUT = 40 V
Capacitor Ripple Current (A)
1
2 Applications
4
1-phase TM
1-phase CCM
3
2
2-phase TM Interleaved
•
•
•
•
•
HD, U-HD, and LED TVs
All-in-one PC
Gaming
Adapters
Home audio systems
1
70
120
170
Input Voltage (V)
220
270
Simplified Application
UCC28064A
RZCDB
ZCD_B
LB
L
VSENSE
VSENSE
TSET
N
PHB Threshold
PHB
CS
COMP
VINAC
VRECT
HVSEN
HVSEN
AGND
RZCDA
ZCD_A
VOUT
LA
VREF
+
GDA
PGND
VCC
GDB
VSENSE
VCC
HVSEN
CS RCS
±
CS
BRST
Burst Threshold
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28064A
SLUSC60B – DECEMBER 2017 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
5
5
5
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
14
15
36
9
Application and Implementation ........................ 37
9.1 Application Information............................................ 37
9.2 Typical Application .................................................. 37
10 Power Supply Recommendations ..................... 45
11 Layout................................................................... 46
11.1 Layout Guidelines ................................................. 46
11.2 Layout Example .................................................... 47
11.3 Package Option Addendum .................................. 48
12 Device and Documentation Support ................. 49
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
49
49
49
49
49
49
50
13 Mechanical, Packaging, and Orderable
Information ........................................................... 51
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2018) to Revision B
•
2
Page
Changed Simplified Application diagram. .............................................................................................................................. 1
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5 Description (Continued)
Expanded system level protections features include input brownout and dropout recovery, output over-voltage,
open-loop, overload, soft-start, phase-fail detection, and thermal shutdown. The additional fail-safe over-voltage
protection (OVP) feature protects against shorts to an intermediate voltage that, if undetected, could lead to
catastrophic device failure. Advanced non-linear gain results in rapid, yet smooth response to line and load
transient events. Special line-dropout handling avoids significant current disruption. Strong reduction of bias
current when not switching during burst mode operation, improves stand-by performance.
6 Pin Configuration and Functions
D Package
16-Pin SOIC
Top View
ZCD_B
1
16
ZCD_A
VSENSE
2
15
VREF
TSET
3
14
GDA
PHB
4
13
PGND
COMP
5
12
VCC
AGND
6
11
GDB
VINAC
7
10
CS
HVSEN
8
9
BRST
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
6
-
Analog ground
BRST
9
I
Burst mode threshold input
COMP
5
O
Error amplifier output
CS
10
I
Current sense input
GDA
14
O
Phase A gate driver output
GDB
11
O
Phase B gate driver output
HVSEN
8
I
High voltage output sense
PGND
13
-
Power ground
PHB
4
I
Phase B enable disable threshold input
TSET
3
I
Timing set
VCC
12
-
Bias supply input
VINAC
7
I
Input AC voltage sense
VSENSE
2
I
Error amplifier input
VREF
15
O
Voltage reference output
ZCDA
16
I
Phase A zero current detection input
ZCDB
1
I
Phase B zero current detection input
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7 Specifications
7.1 Absolute Maximum Ratings
All voltages are with respect to GND, −40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified
terminal, unless otherwise noted.
Continuous input voltage
MIN
MAX
VCC (1)
−0.5
21
COMP (2), PHB, HVSEN (3), VINAC (3), VSENSE (3), TSET, BRST
–0.5
7
ZCDA, ZCDB
–0.5
4
CS (4)
–0.5
3
GDA, GDB (5)
–0.5
VCC + 0.3
VCC
±5
GDA, GDB (5)
–25
VREF
Peak input current
TJ
Operating junction temperature
TSOL
Soldering 10 s
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
V
20
ZCDA, ZCDB
Continuous input current
UNIT
25
mA
–2
CS
–30
mA
–40
–65
125
°C
260
°C
150
°C
Voltage on VCC is internally clamped. VCC may exceed the continuous absolute maximum input voltage rating if the source is current
limited below the absolute maximum continuous VCC input current level.
In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.
In normal use, VINAC, VSENSE, and HVSEN are connected to high-value resistors and are internally limited in negative-voltage swing.
Although not recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as -10mA from negative
voltage sources, and input currents as high as +0.5mA from positive voltage sources.
In normal use, CS is connected to a series resistor to limit peak input current during brief system line-inrush conditions. In these
situations, negative voltage on CS may exceed the continuous absolute maximum rating.
No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to
damp resonant ringing due to stray inductance.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
4
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±2000
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
All voltages are with respect to GND, −40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified
terminal, unless otherwise noted.
MIN
MAX
VCC input voltage from a low-impedance source
14
21
V
VCC input current from a high-impedance source
8
18
mA
VINAC input voltage
0
6
V
VREF load current
0
–2
mA
20
80
kΩ
66.5
400
kΩ
0.8
4.5
V
PHB Phase management threshold voltage
0
2
V
BRST Burst mode threshold voltage
0 VPHB - 0.6 V
V
ZCDA, ZCDB series resistor
TSET resistor to program PWM on-time
HVSEN input voltage
UNIT
7.4 Thermal Information
UCC28064A
THERMAL METRIC
SOIC (D)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance (1)
(2)
91.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.1
°C/W
RθJB
Junction-to-board thermal resistance (3)
48.6
°C/W
ψJT
Junction-to-top characterization parameter (4)
14.9
°C/W
48.3
°C/W
Junction-to-board characterization parameter
ψJB
(1)
(2)
(3)
(4)
(5)
(5)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
7.5 Electrical Characteristics
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R TSET = 133 kΩ,
all voltages are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and
negative out of the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC BIAS SUPPLY
VCCSHUNT
VCC shunt voltage (1)
IVCC = 10 mA
24
26
V
IVCC(UVLO)
VCC current, UVLO
VCC = 9.3 V prior to turn on
125
200
µA
IVCC(stby)
VCC current, disabled
VSENSE = 0 V
150
210
µA
IVCC(on)
VCC current, enabled
VSENSE = 2 V
5
8
mA
IVCC(BURST)
VCC current burst mode no
switching
VCOMP < VBURST
650
850
µA
22
UNDERVOLTAGE LOCKOUT (UVLO)
VCCON
VCC turnon threshold
VCC rising
9.45
10.35
11.1
V
VCCOFF
VCC turnoff threshold
VCC falling
8.8
9.6
10.7
V
ΔVCCUVLO
UVLO Hysteresis
VCCON - VCCOFF
0.68
0.8
0.9
V
REFERENCE
(1)
Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply.
If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended.
See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.
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Electrical Characteristics (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R TSET = 133 kΩ,
all voltages are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and
negative out of the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VREF
VREF output voltage, no load
IVREF = 0 mA
ΔVREF_LOAD
VREF change with load
0 mA ≤ IVREF ≤ −2 mA
ΔVREF_VCC
VREF change with VCC
12 V ≤ VCC ≤ 20 V
MIN
TYP
MAX
5.82
6.00
6.18
-6
-1
UNIT
V
mV
2
10
mV
5.85
6
6.15
V
5.82
6
6.18
V
50
100
150
nA
ERROR AMPLIFIER
VSENSEreg25
VSENSE input regulation
voltage
VSENSEreg
VSENSE input regulation
voltage
IVSENSE
VSENSE input bias current
VENAB
VSENSE enable threshold,
rising
1.15
1.25
1.35
V
VSENSE enable hysteresis
0.02
0.07
0.15
V
4.70
4.95
5.10
V
0.03
0.125
V
40
55
70
µS
TA = 25°C
In regulation
VCOMP_CLMP
COMP high voltage, clamped
VSENSE = VSENSEreg – 0.3 V
VCOMP_SAT
COMP low voltage, saturated
VSENSE = VSENSEreg + 0.3 V
gM1
VSENSE to COMP
transconductance, small signal
0.99(VSENSEreg) < VSENSE <
1.01(VSENSEreg), COMP = 3 V
VSENSE_gM2_SIN
VSENSE high-going threshold
to enable COMP large signal
gain, percent
Relative to VSENSEreg, COMP = 3 V
3.25
5
6.75
%
VSENSE low-going threshold to
enable COMP large signal gain, Relative to VSENSEreg, COMP = 3 V
percent
–6.75
−5
−3.25
%
K
VSENSE_gM2_SO
URCE
gM2_SOURCE
VSENSE to COMP
transconductance, large signal
VSENSE = VSENSEreg – 0.4 V , COMP =
3V
210
290
370
µS
gM2_SINK
VSENSE to COMP
transconductance, large signal
VSENSE = VSENSEreg + 0.4 V, COMP =
3V
210
290
370
µS
ICOMP_SOURCE_
COMP maximum source current VSENSE = 5 V, COMP = 3 V
-170
-125
-80
µA
MAX
RCOMPDCHG
COMP discharge resistance
HVSEN = 5.2 V, COMP = 3 V
1.6
2
2.4
kΩ
IDODCHG
COMP discharge current during
Dropout
VSENSE = 5 V, VINAC = 0.3 V, COMP =
1V
3.2
4
4.8
µA
VLOW_OV
VSENSE overvoltage threshold,
Relative to VSENSEreg
rising
6.5
8
9.5
%
-3
-2
-1.5
%
ΔVLOW_OV_HYS
T
VSENSE overvoltage hysteresis Relative to VLOW_OV
VSENSE 2nd overvoltage
threshold, rising
Relative to VSENSEreg
9.3
11
12.7
%
VSSTHR
COMP Soft-Start threshold,
falling
VSENSE = 1.5 V
10
23
35
mV
ISS,FAST
COMP Soft-Start current, fast
SS-state, VENAB < VSENSE < VREF/2
-170
-125
-80
µA
ISS,SLOW
COMP Soft-Start current, slow
SS-state, VREF/2 < VSENSE < 0.88VREF
-20
-16
-11.5
µA
KEOSS
VSENSE End-of-Soft-Start
threshold factor
Percent of VSENSEreg
96.5%
98.3%
99.8%
VHIGH_OV
SOFT START
OUTPUT MONITORING
VHV_OV_FLT
HVSEN threshold to
overvoltage fault
HVSEN rising
4.64
4.87
5.1
V
VHV_OV_CLR
HVSEN threshold to
overvoltage clear
HVSEN falling
4.45
4.67
4.8
V
GATE DRIVE
6
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Electrical Characteristics (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R TSET = 133 kΩ,
all voltages are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and
negative out of the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10.7
12.4
15
V
IGDA, IGDB = −100 mA
8.8
16.7
Ω
GDA, GDB output voltage, low
IGDA, IGDB = 100 mA
0.18
0.32
V
GDA, GDB on-resistance, low
IGDA, IGDB = 100 mA
2
3.2
Ω
VGDx_H_VCCH
GDA, GDB output voltage high,
clamped
VCC = 20 V, IGDA, IGDB = −5 mA
11.8
13.5
15
V
VGDx_H_VCCL
GDA, GDB output voltage high,
low VCC
VCC = 12 V, IGDA, IGDB = −5 mA
10
10.5
11.5
V
VGDx_L_UVLO
GDA, GDB output voltage,
UVLO
VCC = 3.0 V, IGDA, IGDB = 2.5 mA
100
200
mV
tGDx_RISE
Rise time
1 V to 9 V, CLOAD = 1 nF
18
30
ns
tGDx_FALL
Fall time
9 V to 1 V, CLOAD = 1 nF
12
25
ns
VGDx_H
GDA, GDB output voltage, high
IGDA, IGDB = −100 mA
RGDx_H
GDA, GDB on-resistance, high
VGDx_L
RGDx_L
UNIT
ZERO CURRENT DETECTOR
VZCDx_TRIG
ZCDA, ZCDB voltage threshold,
falling
0.8
1
1.2
V
VZCDx_ARM
ZCDA, ZCDB voltage threshold,
rising
1.5
1.7
1.9
V
VZCDx_CLMP_H
ZCDA, ZCDB clamp, high
IZCDA = +2 mA, IZCDB = +2 mA
2.6
3
3.4
V
VZCDx_CLMP_L
ZCDA, ZCDB clamp, low
IZCDA = −2 mA, IZCDB = −2 mA
-0.40
−0.2
0
V
IZCDx
ZCDA, ZCDB input bias current
ZCDA = 1.4 V, ZCDB = 1.4 V
-0.5
0
0.5
µA
tZCDx_DEL
ZCDA, ZCDB delay to GDA,
GDB outputs
From ZCDx input falling to 1 V to
respective gate drive output rising 10%
50
100
ns
tZCDx_BLNK
ZCDA, ZCDB blanking time
From GDx rising to GDx falling
100
ns
CURRENT SENSE
ICS
CS input bias current, dualphase
VCS_DPh
CS current-limit rising threshold,
dual-phase
VCS_SPh
At rising threshold
-200
-166
-120
µA
-0.22
-0.2
-0.18
V
CS current-limit rising threshold,
PHB = 6 V
single-phase
-0.183
-0.166
-0.149
V
VCS_RST
CS current-limit reset falling
threshold
-0.025
–0.015
-0.002
V
tCS_DEL
CS current-limit response time
From CS exceeding threshold−0.05 V to
GDx dropping 10%
60
100
ns
tCS_BLNK
CS blanking time
From GDx rising and falling edges
IVINAC
VINAC input bias current,
above brownout
VINAC = 2 V
VBOTHR
VINAC brownout threshold
100
ns
VINAC INPUT
-0.5
0
0.5
µA
1.33
1.45
1.6
V
500
640
810
ms
tBODLY
VINAC brownout filter time
VINAC below the brownout threshold for
the brownout filter time
tBORST
VINAC brownout reset time
VINAC above the brownout threshold for
the brownout reset time after Brown out
event
300
450
600
ms
IBOHYS
VINAC brownout hysteresis
current
VINAC = 1 V for > tBODLY
1.6
1.95
2.25
µA
VDODET
VINAC dropout detection
threshold
VINAC falling
0.310
0.35
0.38
V
tDODLY
VINAC dropout filter time
VINAC below the dropout detection
threshold for the dropout filter time
3.5
5
7
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Electrical Characteristics (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R TSET = 133 kΩ,
all voltages are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and
negative out of the specified terminal, unless otherwise noted.
PARAMETER
VDOCLR
VINAC dropout clear threshold
TEST CONDITIONS
VINAC rising
MIN
TYP
MAX
UNIT
0.67
0.71
0.75
V
PULSE-WIDTH MODULATOR
KTL
On-time factor, two phases
operating, low VINAC_PK
VINAC=1.6V, VCOMP=4V (2)
3.0
4.15
5.3
µs/V
KTH
On-time factor, two phases
operating, high VINAC_PK
VINAC= 5V, VCOMP = 4V (2)
0.36
0.43
0.5
µs/V
KTSL
On-time factor, single-phase
operating, low VINAC_PK
VINAC=1.6V, VCOMP = 1.5V, PHB = 2V (2)
6.1
8.3
10.5
µs/V
KTSH
On-time factor, single-phase
operating, high VINAC_PK
VINAC= 5V, VCOMP = 1.5V, PHB=2V (2)
0.73
0.87
1.01
µs/V
tZCC_I
Zero-crossing distortion
correction additional on time
COMP = 0.5 V, VINAC = 0.1 V
15
23.6
32.2
µs
tZCC_II
Zero-crossing distortion
correction additional on time
COMP = 0.5 V, VINAC = 1.6 V
0.7
1.1
1.5
µs
tMIN
Minimum Switching period
RTSET = 133 kΩ, VCOMP = 0.3, VINAC = 3
V (2)
1.9
2.7
3.5
µs
tSTART
PWM restart time
ZCDA = ZCDB = 2 V (3)
160
210
265
µs
tONMAX_L
Maximum FET on time at low
VINAC
VSENSE = 5.8 V, VINAC=1.6V
15.1
20.4
26.2
µs
tONMAX_H
Maximum FET on time at High
VINAC
VSENSE = 5.8 V, VINAC= 5V
1.5
2
2.4
µs
tONMAX_SL
Maximum FET on time at low
VSENSE = 5.8V, VINAC=1.6V, PHB = 6V
VINAC, Single Phase operation.
11.8
16
20.2
µs
tONMAX_SH
Maximum FET on time at hgih
VINAC, single phase operation
VSENSE = 5.8V, VINAC=5 V, PHB = 6V
1.37
1.66
1.95
µs
ΔtONMAX_AB_L
Phase B to phase A on-time
matching error
VSENSE = 5.8 V, VINAC=1.6V
–6
6
%
ΔtONMAX_AB_H
Phase B to phase A on-time
matching error
VSENSE = 5.8 V, VINAC= 5V
-6
6
%
ΔVBRST_HYST
BRST Hysteresis, COMP
voltage rising
BRST = 1V, VINAC = 1.5 V
30
50
70
mV
ΔVPHB_HYST
PHB Hysteresis COMP voltage
rising
PHB = 3V, VINAC = 2.5 V
80
150
210
mV
IPHB_RANGE
PHB pin sourced current when
high input voltage
VINAC = 3.75V, PHB = 2V
2
3
4.1
µA
IBRST_RANGE
BRST pin sourced current when
VINAC = 3.75V, BRST = 2V
high input voltage
2
3
4.1
µA
VVINAC _
VINAC range falling threshold
PHB = 2V, BRST = 2V
2.95
3.15
3.3
V
VINAC range Hysteresis at
rising edge
PHB = 2V, BRST=2V
300
350
400
mV
RANGE_THF
ΔVINAC_RANGE
THERMAL SHUTDOWN
TJ
Thermal shutdown temperature
Temperature rising (4)
160
°C
TJ
Thermal restart temperature
Temperature falling (4)
140
°C
(2)
(3)
(4)
8
Gate drive on-time is proportional to (VCOMP – 0.125 V). The on-time proportionality factor, KT, scales linearly with the value of RTSET
and is different in two-phase and single-phase modes. The minimum switching period is proportional to RTSET.
An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart
time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.
Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating
temperature is not specified or assured.
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7.6 Typical Characteristics
VVCC = 16 V, VAGND = VPGND = 0 V, VVINAC = 3 V, VVSENSE = 6 V, VHVSEN = 3 V, VPHB = 0 V, RTSET = 133 kΩ; all voltages are
with respect to GND, all outputs unloaded, TJ = 25°C, and currents are positive into and negative out of the specified terminal,
unless otherwise noted.
30
1.5
66.5k:
130k:
266k:
27
24
1.49
1.48
1.47
VBODET (V)
tZCC (µs)
21
18
15
12
9
1.46
1.45
1.44
1.43
1.42
6
1.41
3
1.4
0
0
0.3
0.6
0.9
1.2 1.5 1.8
VINAC (V)
2.1
2.4
2.7
1.39
-40
3
Figure 1. RTSET Resistance and Zero-Crossing Distortion
Correction Additional On Time
1.9375
6.03
Reference Voltage (V)
6.04
1.9325
1.9275
1.9225
1.9175
1.9125
1.9075
100
120
140
D101
VREF (V)
VREF_LOAD (V)
6.02
6.01
6
5.99
5.98
5.97
1.9025
5.96
1.8975
-40
-20
0
20
40
60
80
Tj-Temperature (°C)
100
120
5.95
-40
140
D102
-20
Figure 3. VINAC Brownout Hysteresis Current
0
20
40
60
80
Tj-Temperature (°C)
100
120
140
D103
Figure 4. VREF Output Voltage
0.85
11
VCCON (V)
VCCOFF (V)
10.8
0.84
0.83
10.6
UVLO Hysteresis (V)
UnderVoltage Lockout Thresholds (V)
20
40
60
80
Tj-Temperature (°C)
6.05
1.9425
10.4
10.2
10
9.8
9.6
0.82
0.81
0.8
0.79
0.78
0.77
9.4
0.76
9.2
9
-40
0
Figure 2. VINAC Brownout Detection Threshold
1.9475
IBOHYS (µA)
-20
D100
-20
0
20
40
60
80
Tj-Temperature (°C)
100
120
140
0.75
-40
-20
D104
Figure 5. UVLO On Off Thresholds
0
20
40
60
80
Tj-Temperature (°C)
100
120
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D105
Figure 6. UVLO Hysteresis
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Typical Characteristics (continued)
VVCC = 16 V, VAGND = VPGND = 0 V, VVINAC = 3 V, VVSENSE = 6 V, VHVSEN = 3 V, VPHB = 0 V, RTSET = 133 kΩ; all voltages are
with respect to GND, all outputs unloaded, TJ = 25°C, and currents are positive into and negative out of the specified terminal,
unless otherwise noted.
150
COMP Output Current (µA)
IVCC-Bias Supply Current (mA)
10
1
0.1
IVCC (ON)
IVCC (BURST)
IVCC (UVLO)
0.01
-40
-20
0
20
40
60
80
Tj-Temperature(°C)
100
120
Low OV
Clear
100
50
Transconduction
55 S
Low OV
Trigger
5.4
6.6
0
±50
±100
140
±150
5.0
5.2
D106
5.6 6.8 6.0 6.2 6.4
VSENSE Input Voltage (V)
6.8
7.0
Soft-start period completed
Figure 7. VCC Bias Supply Current
Figure 8. Error Amplifier Output Current vs Input Voltage
300
60
5.9 V < VVSENSE < 6.1 V
58
56
gM − Transconductance (µS)
gM − Transconductance (µS)
250
200
150
100
54
52
50
48
46
44
50
42
0
5.0
5.2
5.4
5.6 5.8 6.0 6.2 6.4
VVSENSE − Input Voltage (V)
6.6
6.8
7.0
40
−40
G005
Figure 9. Error Amplifier Transconductance vs VSENSE
10
−20
0
20
40
60
80
TJ − Temperature (°C)
100
120
G006
Figure 10. Error Amplifier Transconductance vs
Temperature
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Typical Characteristics (continued)
VVCC = 16 V, VAGND = VPGND = 0 V, VVINAC = 3 V, VVSENSE = 6 V, VHVSEN = 3 V, VPHB = 0 V, RTSET = 133 kΩ; all voltages are
with respect to GND, all outputs unloaded, TJ = 25°C, and currents are positive into and negative out of the specified terminal,
unless otherwise noted.
20
15
14
3.0
12
2.5
10
Gate Drive Output (V)
ICOMP − Output Current (µA)
10
VVSENSE = 6.1 V
5
0
VVSENSE = 5.9 V
−5
VVSENSE = 5.8 V
−10
−15
−20
0
1
2
3
VCOMP − Output Voltage (V)
4
2.0
8
GD Voltage:
VCC = 20 V
VCC = 12 V
GD Source Current:
VCC = 20 V
VCC = 12 V
6
1.0
4
0.5
2
0
0
-0.5
-2
5
1.5
Gate Drive Source Current (A)
VVSENSE = 6.2 V
-1.0
0
50
100
150
200
250
300
350
Time (ns)
G007
CLOAD = 4.7 nF
Figure 11. Error Amplifier Output Current vs Output Voltage
7
14
12
2.5
6
12
1.5
6
1.0
4
0.5
2
0
GD Voltage:
VCC = 20 V
VCC = 12 V
0
-0.5
-1.0
20
40
4
8
3
6
2
4
1
2
0
0
ZCD Input Voltage
-2
0
10
GD Output:
TJ = –40°C
TJ = +25°C
TJ = +125°C
Gate Drive Output (V)
8
5
ZCD Input (V)
2.0
GD Sink Current:
VCC = 20 V
VCC = 12 V
Gate Drive Source Current (A)
3.0
10
Gate Drive Output (V)
Figure 12. Gate Drive Rising vs Time
14
60
80
100
120
140
-2
-1
-25 0
50
100
150
200
250
300
Time (ns)
Time (ns)
CLOAD = 4.7 nF
CLOAD = 4.7 nF
Figure 13. Gate Drive Falling vs Time
Figure 14. Gate Drive Rising and Delay From ZCD Input vs
Time
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Typical Characteristics (continued)
500
14
400
12
300
10
200
8
100
CS Input
Voltage
6
GD Output:
TJ = -40°C
TJ = +25°C
TJ = +125°C
0
4
-100
2
-200
0
Gate Drive Output - V
Current Sense Input (mV)
VVCC = 16 V, VAGND = VPGND = 0 V, VVINAC = 3 V, VVSENSE = 6 V, VHVSEN = 3 V, VPHB = 0 V, RTSET = 133 kΩ; all voltages are
with respect to GND, all outputs unloaded, TJ = 25°C, and currents are positive into and negative out of the specified terminal,
unless otherwise noted.
-2
-300
-25 0
50
100
150
200
250
300
Time (ns)
CLOAD = 4.7 nF
Figure 15. Gate Drive Falling and Delay From CS Input vs Time
12
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8 Detailed Description
8.1 Overview
Transition mode (TM) control is a popular choice for the boost power factor correction topology at lower power
levels. Some advantages of this control method are its lower complexity in achieving high power factor and
because lower cost boost diode with higher reverse recovery current specification may be used. In TM control
MOSFET is turned on always when no current is flowing into diode. Interleaved Transition Mode Control retains
this benefit and generally extends the applicability up to much higher power levels while simultaneously
conferring the interleaving benefits of reduced input and output ripple current and system thermal optimization.
In UCC28064A, burst mode was introduced respect its predecessor (UCC28063) to achieve higher efficiency in
light load conditions. Input voltage feed-forward and threshold adjustment is also available to ensure the user can
optimize performance across line and load conditions. When operating single phase on time of the switching
phase is doubled with the purpose of compensating the missing power from the not switching phase. In this way
for the same COMP value the converter should provide the same output power regardless if operating single
phase mode or dual phase mode. Unfortunately this is not always the case. Component variations and
MOSFETs turn-off delay can lead to big differences (for the same COMP voltage) in the output power delivery.
The Phase Management and Light-Load Operation section will discuss some ways to deal with the variations.
Line voltage feed-forward compensation provides several benefits: it maintains constant bandwidth of the control
loop versus line voltage variation, avoids high current in the MOSFETs, inductors, and line filter when line
transitions from low to high happens, and helps to keep simple Phase Management control because the COMP
pin voltage is almost proportional to Load. Burst Mode enables high efficiency at light load and soft-on and softoff in burst mode reduces risk of audible noise. The optimal load current at which the converter should enter
burst mode can be different for different input voltages. These thresholds can be customized by the user.
Interleaving control and phase management facilitates high efficiency 80+ and Energy Star designs with reduced
input and output ripple. The Natural Interleaving method allows TM operation and achieves 180 degrees between
the phases by On-time management. Moreover Natural interleaving method does not rely on tight tolerance
requirements on the inductors. Negative current sensing is implemented on the total input current instead of just
the MOSFET current which prevents MOSFET switching during inrush surges or in any mode where the inductor
current may enter in continuous conduction mode (CCM). This prevents reverse recovery conduction events
between the MOSFET and output rectifier.
Independent output voltage sense circuits with their separate fault management behaviors provide a high degree
of redundancy against PFC stage over-voltage. Brownout, over voltage protection on HVSEN pin (HVSENSE
OV), under voltage lockout (UVLO), and device over-temperature faults will all cause a complete Soft-Start cycle.
Other faults such as short duration AC Drop-Out, minor over-voltage or cycle-by-cycle over-current cause a live
recovery process to initiate by pulling down the COMP pin or by terminating the pulses early.
The error amplifier transconductance is designed to allow smaller compensation components and optimum
transient response for large changes in line or load. The Soft-Start process is carefully optimized. A complete
Soft-Start is implemented. It is dependent on the output voltage sense to speed up start-up from low AC line and
to minimize the effect of excessive capacitance on the COMP pin during start-up into no-load. If some faults
events are triggered COMP pin is fast pulled down to zero. This complete discharge of COMP aids with
preventing excessive currents on recovery from an AC Brown-Out event.
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8.2 Functional Block Diagram
CS_OPEN
100ns
Blanking
TSD
CS_OPEN
TSET_FAULT
EN
UVLO
HVSEN_OV
BROWNOUT
PHB_OFF
S
Q
R Q
5ms
Delay
0.7V /
0.35V
2 A
DROPOU
T
15
VREF
14
GDA
11
GDB
13
PGND
9
BRST
8
HVSEN
BROWNOUT
tBODLY
VAC_PK
tBORST
PHB_OFF
COMP_DSCHG
PEAK
DETECT
BROWN OUT
VCC
Brownout
VBOTHR
VINAC
12
24
V
COMP_DSCHG
DISCH_RST
7
6V
200mV
Hyst. 15mV
OC
12.4V Max
167mV
Hyst. 15mV
6V
Reg.
10
VCCON /
VCCOFF
UVLO
VGD
Reg.
CS
Overcurrent
CS
OPEN
6V
STOP_GDB
HIGH_OV
OC
VAC_PK
STOP_GDA
TSET
VFF
VFF_ITSET
VCOMP_II
Clamping
100ns
Blankin
g
16
1.7V /
1V
100ns
Blanking
Clamping
1
PGND
Interleaving
Control
TRIGGE
R
ZCB
VCOMP_II
VFF_ITSET
tON Modulation
Phase B
On Time Control
20mV /
40mV
DISCH_RST
SW_EN
Crossove
r
Notch
Reductio
n
VINAC
ZCDB
tON
Modulation
TRIGGE
R
ZCA
STOP_GDA
Phase A
On Time Control
PWMA
VFF_ITSET
PWMB
TSET_FAULT
1.7V /
1V
ZCDA
12.4V
Max
PHB_OFF
tON
Basis
3
tON
Basis
TSET
SW_E
N
STOP_GDB
3 A
VAC_PK
HLN
3.15V
2.8V
HIGH_OV
12.4V Max
4
A
HLN
VCOMP_II
PHB_OFF_F
2kW
6.67V
Burst Mode
Managment
VCOMP
SW_EN
DROPOUT
LOW_OV
6.48V
VCOMP
LOW_OV
COMP_DISCH
HVSEN_OV
1.25V
4.87V /
4.67V
EN
EA gain control for
Soft Start
And Dropout
DIS_HIGH_GAIN
DIS_EA
COMP_DISC
H
VREF
PHB_OFF_F
VCOMP
VSENSE 2
100nA
14
3 A
HLN
Double Gain
Error Amplifier
VCOMP
6
5
4
AGND
COMP
PHB
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Managment
PHB_OFF
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8.3 Feature Description
8.3.1 Principles of Operation
The UCC28064A device contains the control circuits for two parallel-connected boost pulse-width modulated
(PWM) power converters. The boost PWM power converters ramp current in the boost inductors for a time period
proportional to the voltage on the error amplifier output (COMP pin). Each power converter then turns off the
power MOSFET until current in the boost inductor decays to zero (as sensed on the zero current detection
inputs, ZCDA and ZCDB). After the inductor demagnetizes, the power converter starts another cycle. This cycle
process produces a triangular waveform of current, with peak current set by the on-time and the instantaneous
power mains input voltage, VIN(t) value, as shown in Equation 1.
IPEAK =
VIN × t ON
L
(1)
The average line current is exactly equal to half of the peak line current, as shown in Equation 2.
IPEAK =
VIN × t ON
2×L
(2)
When the tON and L values are essentially constant during an AC-line period, the resulting triangular current
waveform during each switching cycle has an average value proportional to the instantaneous value of the
rectified AC-line voltage. This architecture results in a resistive input impedance characteristic at the line
frequency and a near-unity power factor.
8.3.2 Natural Interleaving
Under normal operating conditions, the UCC28064A device regulates the relative phasing of the channel A and
channel B inductor currents to be approximately 180°. This greatly reduces the switching-frequency ripple
currents seen at the line-filter and output capacitors, compared to the ripple current of each individual converter.
This design allows a reduction in the size and cost of input and output filtering. The phase-control function
differentially modulates the on-times of the A and B channels based on their phase and frequency relationship.
The Natural Interleaving method allows the converter to achieve 180° phase-shift and transition-mode operation
for both phases without tight requirements on boost inductor tolerance.
Ideally, the best current-sharing is achieved when both inductors are exactly the same value. Typically the
inductances are not the same, so the current-sharing of the A and B channels is proportional to the inductor
tolerance. Also, switching delays and resonances of each channel typically differ slightly, and the controller
allows some necessary phase-error deviation from 180° to maintain equal switching frequencies. Optimal phase
balance occurs if the individual power stages and the on-times are well matched. Mismatches in inductor values
do not affect the phase relationship.
Interleaving may not be ideal under all conditions. In particular a loss of interleaving may be experienced at light
loads near the zero crossings. In some cases there may be insufficient current to trigger a large enough signal to
trip the zero crossing detectors. In addition the turn off delay in the MOSFET may dominate the overall on-time at
very light loads. This creates a very limited ability for the controller to correct for phase errors in the system.
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Feature Description (continued)
8.3.3 On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward
compensation
Gate-drive on-time varies proportionately with the error-amplifier output voltage (VCOMP) and inversely
proportional to the squared value of the peak of the rectified input voltage sensed through VINAC pin as stated
by equation (3). In equation (3) it is shown that the on-time is inversely proportionally to the value of resistor
RTSET connected between pin TSET and pin AGND. In order to calculate on-time, Equation (4) can be used.
Parameter KT is function of the rectified peak input voltage sensed by pin VINAC as reported in graph of
Figure 16. In this graph 3 curves are reported for three different values of RTSET. Two values of parameter KT are
reported in the electrical specs table for two values of VINAC: KTL and KTH corresponding at the VINAC = 1.6V
and VINAC = 5V and RTSET = 133kΩ. Because voltage on VINAC is proportional to the line rectified voltage, for
tON calculation purposes we refer to the peak value of this voltage that is obtained through an internal peak
detect. KT is inversely proportional to the squared value of VINAC peak value so it is the tON time realizing the so
called voltage feed-forward compensation. The Voltage Feed-forward function modifies the MOSFET on time
according to line voltage so, ideally output power delivered does not change if line voltage changes. When
operating in single phase mode KT is called KTS and its value is doubled.
t ON =ß
:VCOMP F 125 mV;
VINAC PK 2 × R TSET
(3)
The COMP pin voltage value is clamped at 4.95 V, so the maximum on time can be calculated by Equation 4.
t ON = :VCOMP F 125 mV; × K T :VINAC ;
(4)
Figure 16 shows the values of KT versus the peak voltage value on VINAC pin.
The maximum switching frequency of each phase is limited by minimum-period timers. If the inductor current
decays to zero before the minimum-period timer elapses, the next turn on will be delayed, resulting in
discontinuous phase current.
A restart timer ensures starting under all circumstances by restarting both phases if the ZCD input of either
phase has not transitioned from high-to-low within approximately 210 µs.
The minimum switching period, T(MIN), is inversely proportional to the time-setting resistor RTSET (the resistor from
the TSET pin to ground).
KT vs VINAC, PK
10
7
5
RTSET
66 k:
133 k:
266 k:
3
KT (Ps/V)
2
1
0.7
0.5
0.3
0.2
0.1
1.5
2
2.5
3
3.5
4
VINAC,PK(V)
4.5
5
5.5
6
D012
Figure 16. KT vs Peak Voltage
16
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Feature Description (continued)
8.3.4 Distortion Reduction
Due to the parasitic resonance between the drain-source capacitance of the switching MOSFET and the boost
inductor, conventional transition-mode PFC circuits may not be able to absorb power from the input line when the
input voltage is near zero. This limitation increases total harmonic distortion as a result of ac-line current
waveform distortion in the form of flat spots. To help reduce line-current distortion, the UCC28064A increases
switching MOSFET on-time when the input voltage is near 0 V to improve the power absorption capability and
compensate for this effect.
Figure 1 in the Typical Characteristics section shows the increase in on-time with respect to VINAC voltage.
Excessive filtering of the VINAC signal will nullify this function. In cases where small inductances are used (< 250
µH) the increased MOSFET on time can be excessive, increasing distortion instead of decreasing. If this is the
case the external circuit shown in Figure 17 can help limit this effect.
VREF
100NŸ
1N4148
VINAC
RU
1N4148
L
1N4148
N
AGND
RD
RS
Figure 17. External Circuit to improve THD in case of Low inductance
8.3.5 Zero-Current Detection and Valley Switching
In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current reaches zero. Because of
the resonance between the boost inductor and the parasitic capacitance at the MOSFET drain node, part of the
energy stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore,
when the rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET
junction capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate
delay, the MOSFET can be turned on at the valley of its resonating drain voltage (valley-switching). In this way,
the energy recovery can be maximized and switching loss is minimized.
The optimal time delay is generally derived empirically, but a good starting point is a value equal to 25% of the
resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 18, but
the delay time increases slightly as the input voltage nears the output voltage. Because the ZCD pin is internally
clamped, a more accurate delay can also be realized by using the circuit shown in Figure 19.
ZCD
R
CT
C
Figure 18. Simple RC Delay Circuit
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Feature Description (continued)
R1
D1
ZCD
CT
C1
R2
Figure 19. More Accurate Time Delay Circuit
18
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Feature Description (continued)
8.3.6 Phase Management and Light-Load Operation
It is challenging to maintain high efficiency under all loading conditions. When operating in light-load, switching
losses may dominate over conduction losses and the efficiency may be improved if one phase is turned off.
Turning off a phase at light load is especially valuable for meeting light-load efficiency standards. This is a major
benefit of interleaved PFC and it is especially valuable for meeting 80+ design requirements.
In order to ensure smooth operation when removing or adding a phase, some additional considerations are
required. When the number of phases operating is changed from 2 to 1 the overall switching frequency is
reduced by a factor of 2. If everything else is held constant this will also reduce the energy delivered to the load
by a factor of 2. In order to maintain the same power delivery to the output, it is necessary to increase the ontime when performing such a transition. A similar situation exists when a phase is added. In other words, when
going from 1 phase to 2 phases, the on-time should decrease in order to have smooth continuous power
delivery. If everything is ideal, the amount by which the system has to increase/decrease the on-time is a factor
of 2. Since 1 phase needs to deliver twice the energy as each phase when both phases are operating, doubling
the on-time would seem to make the most sense (or cutting it in half if going from 1 phase to 2 phases). While
this works well in many cases there are real world examples where this fails to provide a sufficiently smooth
phase shedding/adding operation. In order to resolve this conflict the circuit in Figure 20 can be utilized to
program a custom on-time for both 1 phase and 2 phase operation. The circuit operates by monitoring the gate
drive of phase 2 (GDB). When this signal is active the resistor RTSET configures the on-time. When the gate drive
is absent the on-time is configured by the parallel combination of RTSET and RTSET_II. The capacitors CFIL and
CHOLD can be adjusted to set up custom delays in the phase shedding/adding process.
TSET
VREF
RTSET_II
900 lQ
GDB
RPULL_UP
100 lQ
330 Q
M1
D1
1N4148
RTSET
160 lQ
M2
CFIL
1 nF
RDISCH
120 lQ
CHOLD
4.7 nF
Figure 20. External circuit for Enhanced Phase Shedding
In the case where the 2x factor is sufficient, the UCC28064A can manage this phase shedding/adding process
without the need of the circuit in Figure 20.The PHB input can be used to set the load value when the
UCC28064A has to operate in single-phase mode. The UCC28064A internally compares the voltage fed to PHB
pin with the COMP pin voltage. If COMP is below PHB channel B will stop switching and the channel A on-time
will automatically double to compensate the missing power from channel B. When operating in single phase
mode in order to avoid risk of inductor saturation an internal clamp ensures the on time never can exceed the
maximum on-time you will have when operating in dual phase mode. The device will resume dual-phase mode
when the COMP pin voltage exceeds PHB voltage plus the PHB hysteresis. In order to avoid voltage ripple on
the COMP pin causing the system to oscillate between one and two phases a time delay filter is present. In order
to change from normal operation to single phase mode the COMP voltage should stay below PHB pin voltage for
14 line half cycles. The filter does not apply for the opposite transition. When the COMP pin voltage exceeds
PHB pin voltage plus the hysteresis, channel B is immediately turned on and the channel A on-time is halved.
At start up, the output voltage can be very close to the peak line voltage. The inductor current value during the
off time will decrease very slowly and it is possible systems will operate in CCM for a few switching cycles. In
order to avoid high current, during soft start, the system is forced to work with both phases on even if the COMP
pin voltage is below PHB pin voltage. In two phase mode the on-time of each phase is one half of the on time of
phase A when Phase B is off so this mitigates the risk of high CCM currents.
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Feature Description (continued)
Figure 21. Phase Management Block Diagram
Figure 22. Phase Management Time Diagram
20
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Feature Description (continued)
The voltage on the PHB pin can be set using a simple resistor divider connected to the VREF pin. Another
important feature, that allows optimization of phase management is that it is possible to set different thresholds
wether the PFC input voltage is in the range of 90 to 132 VRMS (US mains) or in the range of 180 to 265 VRMS
(European mains). If the peak voltage sensed by the VINAC pin exceeds 3.5V the converter assumes that the
input voltage is in the range of 180 to 265 VRMS and starts sourcing from PHB a small current (3µA typically) that
increases the voltage on PHB pin.
Figure 23. Change Phase Management Thresholds
Use Equation 5 and Equation 6 to calculate PHB thresholds.
VPHB _LR =
RD
× VREF
RU + RD
(5)
VPHB _HR =
RD
RD × RU
× VREF +
× IPHB _RANGE
RU + RD
RU + RD
(6)
The load value at which the system moves between single phase and dual phase modes of operation is part of
the system specification. The formulas to calculate resistor divider resistance values that allows us to get the
desired thresholds are reported below.
RU =
¿VPHB × VREF
VPHB _LR × IPHB _RANGE
(7)
RD =
(VREF
¿VPHB × VREF
F VPHB _LR ) × IPHB _RANGE
where
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Feature Description (continued)
•
•
RD is the lower resistor of the resistor divider that provides voltage to PHB pin that is supplied by VREF
RU is the upper resistor of the resistor divider.
(8)
¿VPHB = VPHB _HR F VPHB _LR
(9)
PHB thresholds are selected by the user according to the load value where they want to turn off Phase B. So
assuming we want to turn off Phase B when the load goes below POUT_PHB we can calculate the threshold using
equation (10). We can use the same equation in order to calculate the two thresholds VPHB_HR and VPHB_LR once
provided the two different load values, for US range and EU range where Phase B has to be turned off. Of
course main EU range PHB_OFF load value has to be greater than main US range PHB_OFF load value. A
reasonable range of load values is from 20% to 30% of converter rated power.
VPHB =
:4.825 V; POUT (PHB )
×
+ 125 mV
POUT (MAX )
VREF
(10)
When the COMP voltage goes below the burst mode threshold the device is forced to work in single phase mode
so if the COMP pin voltage drops below the burst threshold it is possible that the time delay filtering is not
respected. Moreover it is recommended that PHB pin voltage is at least 600mV higher than BRST pin voltage.
22
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Feature Description (continued)
8.3.7 Burst Mode Operation
To further improve light load efficiency burst mode operation can be used. In this case the burst mode threshold
is fed to BRST pin by an external source that could be a simple resistor divider connected to the VREF pin. If
COMP pin voltage goes below the BRST pin voltage the converter stops switching. When the COMP voltage
exceeds BRST pin voltage plus hysteresis, the converter restarts switching.
In order to have a smooth transition between switching and not switching and vice-versa burst soft-on and burst
soft-off features are added. So when the COMP voltage goes below BRST voltage switching is not stopped
immediately, but there will be eight additional switching cycles where FET on time is decreased gradually. In
similar way when COMP voltage exceeds BRST voltage plus hysteresis a soft-on period occurs where the on
time is increased gradually to a value that corresponds to the present COMP voltage in eight switching cycles.
When the load decreases the device is intended to operate in single phase mode starting from 35% to 15% of
rated load and goes to burst mode at lower load values when single phase operation is activated. If the PHB
threshold is lower than the Burst mode threshold, single phase operation is forced during soft-on and soft-off
periods of burst mode.
Similar to the PHB feature the burst mode threshold has two different levels depending if the PFC input voltage is
in the range of 90 to 132 VRMS (US main) or in the range of 180 to 265 VRMS (European main). If the peak
voltage on VINAC pin peak voltage exceeds 3.5 V (typ.) a small current (3 µA typically) is provided from BRST
pin. If a resistor divider is used to set the BRST pin voltage this current will raise the voltage.
Use Equation 11 and Equation 12 to calculate the resistor divider that sets the Burst Mode thresholds. These
equations are identical to the equations used to calculate the PHB resistor divider.
RU and RD are the upper and the lower resistence of the resistor divider connected to VREF pin.
RU =
¿VPHB × VREF
VPHB _LR × IPHB _RANGE
(11)
RD =
(VREF
¿VBRST × VREF
F VBRST (LR ) ) × IBRST (RANGE )
(12)
8.3.8 External Disable
The UCC28064A can be externally disabled by pulling the VSENSE pin to ground with an open-drain or opencollector driver. When disabled, the device supply current drops significantly and COMP is actively pulled low.
This disable method forces the device into standby mode and minimizes its power consumption. When VSENSE
is released, the device enters soft-start mode.
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Feature Description (continued)
8.3.9 Improved Error Amplifier
The voltage error amplifier is a transconductance amplifier. Voltage-loop compensation is connected from the
error amplifier output, COMP, to analog ground, AGND. The recommended Type-II compensation network is
shown in Figure 24. For loop-stability purposes, the compensation network values are calculated based on smallsignal perturbations of the output voltage using the nominal transconductance (gain) of 55 µS.
VREF
+
COMP
gM
VSENSE
CZ
CP
4.95V
RZ
Figure 24. Transconductance Error Amplifier With Typical Compensation Network
To improve the transient response to large perturbations, the error amplifier gain increases by a factor of around
5X when the error amplifier input deviates more than ±5% from the nominal regulation voltage, VSENSEreg. This
increase allows faster charging and discharging of the compensation components following sudden load-current
increases or decreases.
IEA
VSENSE
VREF
Basic voltage error amplifier transconductance curve showing small-signal and large-signal gain sections, with
maximum current limitations.
Figure 25. Basic Voltage-Error Amplifier Transconductance Curve
24
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Feature Description (continued)
8.3.10 Soft Start
Soft-start is a process for boosting the output voltage of the PFC converter from the peak of the ac-line input
voltage to the desired regulation voltage under controlled conditions. Instead of a dedicated soft-start pin, the
UCC28064A uses the voltage error amplifier as a controlled current source to increase the PWM duty-cycle by
way of increasing the COMP voltage. To avoid excessive start-up time-delay when the ac-line voltage is low, a
higher current is applied until VSENSE exceeds 3 V at which point the current is reduced to minimize the
tendency for excess COMP voltage at no-load start-up.
The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to
AGND charges from zero to near its final value. This process implements a soft-start, with timing set by the
output current of the error amplifier and the value of the compensation capacitors. Soft-start ends when VSENSE
pin voltage exceeds 95% of VSENSEreg. During soft-start the device will operate with both phases on and even
if the COMP voltage is below the BRST pin voltage the device will not stop switching. In the event of a HVSEN
failsafe OVP, brownout, external-disable, UVLO fault, or other protection faults, COMP is actively discharged and
the UCC28064A will soft-start after the triggering event is cleared. Even if a fault event happens very briefly, the
fault is latched into the soft-start state and soft-start is delayed until COMP is fully discharged to 20 mV and the
fault is cleared. See Figure 26 for details on the COMP current. See Figure 27 which illustrates an example of
typical system behavior during soft-start.
ICOMP
OVP1 trigger. 2k pull -down
applied to COMP .
+63μA
+15μA
OVP1 reset. 2k pull -down
removed from COMP .
1.0
2.0
3.0
4.0
5.0
6.0
-15μA
7.0
VSENSE
COMP current limit
during Soft -Start only
(high-gain disabled )
-111 μA
Expanded COMP output current curve including voltage error amplifier transconductance and modifications applicable
to soft-start and overvoltage conditions.
Figure 26. Expanded COMP pin Output Current Curve
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Feature Description (continued)
OVERSHOOT
V
VSENSEREG
VENDofSS
VSENSE
VCOMPCLMP
COMP
VSSTHR
t
I AC-LINE
ICOMP
ISS,SLOW
ISS,FAST
HIGH GAIN ENABLED
SOFTSTART
Figure 27. Soft-Start Timing with System Behavior
26
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Feature Description (continued)
8.3.11 Brownout Protection
As the power line RMS voltage decreases, RMS input current must increase to maintain a constant output
voltage for a specific load. Brownout protection helps prevent excess system thermal stress (due to the higher
RMS input current) from exceeding a safe operating level. Power-line voltage is sensed at VINAC pin. When the
VINAC fails to exceed the brownout threshold for the brownout filter time (tBODLY), a brownout condition is
detected and both gate drive outputs are turned off. During brownout, COMP is actively pulled low and soft-start
condition is initiated. When VINAC rises above the brownout threshold, the power stage soft-starts as COMP
rises with controlled current.
The brownout threshold and its hysteresis are set by the voltage-divider ratio and resistor values. Brownout
protection is based on VINAC peak voltage; the threshold and hysteresis are also based on the line peak
voltage. Hysteresis is provided by a 2-μA current-sink (IBOHYS) enabled whenever Brownout protection is
activated. As soon as the Brownout protection is activated an additional timer is started that counts the tBORST
time. During this time the device is forced to stay in a Brownout condition. So, during tBORST time, the device is
not allowed to switch, COMP is pulled low and the 2-uA current sink (IBOHYS) is active regardless of the voltage
on VINAC pin. After tBORST is elapsed the device can exit from Brownout condition only if VINAC pin exceeds
VBOTHR threshold. When the device operates in burst mode, several blocks inside the IC are turned off to reduce
IC current consumption. The Brownout management block is also turned off. Each time the system stops
switching, because of burst mode, the Brownout filter timer is reset. So if the system is operating in burst mode,
the Brownout protection, generally is not triggered. The main purpose of Brownout is to avoid excess system
thermal stress. When the system is operating in burst-mode the load is low enough to avoid thermal stress. The
peak VINAC voltage can be easily translated into an RMS value. Example resistor values for the voltage divider
are 8.61 MΩ ±1% from the rectified input voltage to VINAC and 133 kΩ ±1% from VINAC to ground. These
resistors set the typical thresholds for RMS line voltages, as shown in Table 1.
Table 1. Brownout Thresholds (For Conditions Stated in the Text)
THRESHOLD
AC-LINE VOLTAGE (RMS)
Falling
67 V
Rising
81 V
Equation 13 and Equation 14 can be used to calculate the VINAC divider-resistors values based on desired
brownout and brown-in voltage levels. VAC_OK is the desired RMS turnon voltage, VAC_BO is the desired RMS
turnoff brownout voltage, and VLOSS is total series voltage drop due to wiring, EMI-filter, and bridge-rectifier
impedances at VAC_BO. VBOTHR, and IBOHYS are found in the data-tables of this datasheet.
¾2 × kVAC OK F VAC BO o
I
IBOHYS
RA
RB =
¾2 × VAC BO F VLOSS
F
F 1G
VBOTHR
RA = H
(13)
(14)
When standard values for the VINAC divider-resistors RA and RB are selected, the actual turn-on and brownout
threshold RMS voltages for the ac-line can be back-calculated with Equation 15 and Equation 16:
1
VAC BO =
VAC OK
× dl1 +
RA
p × VBOTHR + VLOSS h
RB
¾2
RB + RA
1
×d
× VBOTHR + R A × IBOHYS h
=
RB
¾2
(15)
(16)
An example of the timing for the brownout function is illustrated in Figure 28.
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8.3.12 Line Dropout Detection
It is often the case that the AC-line voltage momentarily drops to zero or nearly zero, due to transient abnormal
events affecting the local AC-power distribution network. Referred to as AC-line dropouts (or sometimes as linedips) the duration of such events usually extends to only 1 or 2 line cycles. During a dropout, the down-stream
power conversion stages depend on sufficient energy storage in the PFC output capacitance, which is sized to
provide the ride-through energy for a specified hold-up time. Typically while the PFC output voltage is falling, the
voltage-loop error amplifier output rises in an attempt to maintain regulation. As a consequence, excess dutycycle is commanded when the AC-line voltage returns and high peak current surges may saturate the boost
inductors with possible overstress and audible noise.
The UCC28064A incorporates a dropout detection feature which suspends the action of the error amplifier for the
duration of the dropout. If the VINAC voltage falls below 0.35 V for longer than 5 ms, a dropout condition is
detected and the error amplifier output is turned off. In addition, a 4-μA pull down current is applied to COMP to
gently discharge the compensation network capacitors. In this way, when the AC-line voltage returns, the COMP
voltage (and corresponding duty-cycle setting) remains very near or even slightly below the level it was before
the dropout occurred. Current surges due to excess duty-cycle, and their undesired attendant effects, are
avoided. The dropout condition is cancelled and the error amplifier resumes normal operation when VINAC rises
above 0.71 V.
Based on the VINAC divider-resistor values calculated for Brownout in the previous section, the input RMS
voltage thresholds for dropout detection VAC_DO and dropout clearing VDO_CLR can be determined using
Equation 17 and Equation 18, below.
æR
ö
VDODET ç A + 1÷ + VLOSS
è RB
ø
VAC _ DO =
2
(17)
æR
ö
VDOCLR ç A + 1÷ + VLOSS
R
è B
ø
VDO _ CLR =
2
28
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Avoid excessive filtering of the VINAC signal, or dropout detection may be delayed or defeated. An RC timeconstant of ≤ 100 s. should provide good performance. Figure 29 shows an example of the timing for the dropout
function.
6V
VSENSE
3V
COMP
xxxxxxxxxxxxxx
xxxxxxxxxxxxxx
switching
no switching
Brownout
xxxxxx
xxxxxx
switching
Brownout
Detect
VINACPK
VBOTHR
VINAC
tBODLY
tBODLY
tBORST
Figure 28. AC-Line Brownout Timing and System Behavior
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VSENSE
VINAC
COMP
VDOCLR
VDODET
0V
t
DROPOUT
tDODLY
Figure 29. AC-Line Dropout Timing With Illustrative System Behavior
30
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8.3.13 VREF
VREF is an output which supplies a well-regulated reference voltage to circuits within the device as well as
serving as a limited source for external circuits. This output must be bypassed to GND with a low-impedance 0.1μF or larger capacitor placed as close to the VREF and GND pins as possible. Current draw by external circuits
should not exceed 2mA and should not be pulsing.
The VREF output is disabled under the following conditions: when VCC is in UVLO, or when VSENSE is below
the Enable threshold. This output can only source current and is unable to accept current into the pin.
8.3.14 VCC
VCC is usually connected to a bias supply of between 14 V and 21 V. To minimize switching ripple voltage on
VCC, it should be bypassed with a low-impedance capacitor as close to the VCC and GND pins as possible. The
capacitance should be sized to adequately decouple the peak currents due to gate-drive switching at the highest
operating frequency. When powered from a poorly-regulated low-impedance supply, an external zener diode is
recommended to prevent excessive current into VCC.
The undervoltage-lockout (UVLO) condition is when VCC voltage has not yet reached the turn-on threshold or
has fallen below the turn-off threshold, having already been turned on. While in UVLO, the VREF output and
most circuits within the device are disabled and VCC current falls significantly below the normal operating level.
The same situation applies when VSENSE is below its Enable threshold. This helps minimize power loss during
pre-power up and standby conditions.
8.3.15
System Level Protections
8.3.15.1 Failsafe OVP - Output Over-voltage Protection
Failsafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths
for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is
implemented through two independent paths: VSENSE and HVSEN.
VSENSE pin voltage is compared with two levels of over-voltage. If the lower one, VLOW_OV,is exceeded the
COMP pin is discharged by an internal 2-kΩ resistance until the output voltage falls below VLOW_OV reduced of
2% to provide hysteresis (ΔVLOW_OV_HYST). If also the higher over-voltage threshold is exceeded in addition to
activate the 2-kΩ pull down switching is soon disabled. In order to re-enable the switching the sensed voltage
has to fall below VLOW_OV reduced of 2%. Additional over-voltage protection can be implemented on HVSEN pin
through a separate resistor divider to monitor output voltage. An over-voltage is detected if HVSEN pin voltage
exceeds VHV_OV_FLT an as consequence device stops switching and the 2-kΩ pull down is activated. The pull
down 2-kΩ pull down is removed only if HVSEN pin goes below VHV_OV_CLR threshold and the COMP pin is fully
discharged to 20 mV. Both conditions needs to be true before the soft-start can begin.
The converter shuts down if either input senses a severe over-voltage condition. The output voltage can still
remain below a safe limit if either sense path fails. The device is re-enabled when both sense inputs fall back into
their normal ranges. At that time, the gate drive outputs will resume switching under PWM control. A low-level
over-voltage on VSENSE does not trigger soft-start, an higher-level over voltage on VSENSE additionally shuts
off the gate-drive outputs until the OV clears, but still does not trigger a soft-start. However, an over-voltage
detected on HVSEN does trigger a full soft-start and the COMP pin is fully discharged to 20 mV before the softstart can begin.
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8.3.15.2 Overcurrent Protection
Under certain conditions (such as inrush, brownout-recovery, and output over-load) the PFC power stage sees
large currents. It is critical that the power devices be protected from switching during these conditions.
The conventional current-sensing method uses a shunt resistor in series with each MOSFET source leg to sense
the converter currents, resulting in multiple ground points and high power dissipation. Furthermore, since no
current information is available when the MOSFETs are off, the source-resistor current-sensing method results in
repeated turn-on of the MOSFETs during overcurrent (OC) conditions. Consequently, the converter may
temporarily operate in continuous conduction mode (CCM) and may experience failures induced by excessive
reverse-recovery currents in the boost diodes or other abnormal stresses.
The UCC28064A uses a single resistor to continuously sense the combined total inductor (input) current. This
way, turn-on of the MOSFETs is completely avoided when the inductor currents are excessive. The gate drive to
the MOSFETs is inhibited until total inductor current drops to near zero, precluding reverse-recovery-induced
failures (these failures are most likely to occur when the AC-line recovers from a brownout condition).
The nominal OC threshold voltage during two-phase operation is -200 mV, which helps minimize losses. This
threshold is automatically reduced to -166 mV during single-phase operation, either by detection of a phase
failure or because COMP is below PHB.
An OC condition immediately turns off both gate-drive outputs, but does not trigger a soft-start and does not
modify the error amplifier operation. The overcurrent condition is cleared when the total inductor current-sense
voltage falls below the OC-clear threshold (–15 mV).
Following an overcurrent condition, both MOSFETs are turned on simultaneously once the input current drops to
near zero. Because the two phase currents are temporarily operating in-phase, the current-sense resistance
should be chosen so that OC protection is not triggered with twice the maximum current peak value of either
phase to allow quick return to normal operation after an overcurrent event. Automatic phase-shift control will reestablish interleaving within a few switching cycles.
8.3.15.3 Open-Loop Protection
If the feedback loop is disconnected from the device, a 100-nA current source internal to the UCC28064A pulls
the VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device becomes disabled.
When disabled, the bias supply current decreases, both gate-drive outputs and COMP are actively pulled low,
and a soft-start condition is initiated. The device is re-enabled when VSENSE rises above 1.25 V. At that time,
the gate drive outputs will begin switching under soft-start PWM control.
If the resistor connected from AGND pin and VSENSE pin (Low resistor of the resistor divider used to sense
output voltage from VSENSE pin) opens, the VSENSE voltage will be pulled high. When VSENSE rises above
the 2nd-level over-voltage protection threshold, both gate drive outputs are shut off and COMP is actively pulled
low. The device is re-enabled when VSENSE falls below the OV-clear threshold. The VSENSE input can tolerate
a limited amount of current into the device under abnormally high input voltage conditions. Refer to the Absolute
Maximum Ratings table near the beginning of this datasheet for details.
32
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8.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection
VCC must rise above the turn-on threshold for the controller to begin functioning. If VCC drops below the UVLO
threshold during operation, both gate-drive outputs are actively pulled low, COMP is actively pulled low, and a
soft-start condition is triggered. VCC must again rise above the turn-on threshold for the PWM function to restart
in soft-start mode.
8.3.15.5 Phase-Fail Protection
The UCC28064A detects failure of either of the phases by monitoring the sequence of ZCD pulses. During
normal two-phase operation, if one ZCD input remains idle for longer than approximately 400 µs while the other
ZCD input switches normally, the over-current threshold is reduced to the value used for single phase operation
(VCS_SPh). During normal single-phase operation, phase failure is not monitored. Phase failure is also not
monitored when COMP is below approximately 250 mV.
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8.3.15.6 CS - Open, TSET - Open and Short Protection
In the event that CS input becomes open-circuited, the UCC28064A detects this condition and will shutdown the
outputs and trigger a full soft start condition. In the event that TSET input becomes either open-circuited or shortcircuited to GND, the UCC28064A detects these conditions and will shutdown the outputs and trigger a full-softstart condition. Normal operation will resume (with a soft start) when the fault clears.
8.3.15.7 Thermal Shutdown Protection
Overloading of the gate-drive outputs, VREF, or both can dissipate excess power within the device which may
raise the internal temperature of the circuits beyond a safe level. Even normal power dissipation can generate
excess heat if the thermal impedance is too high or the ambient temperature is too high. When the UCC28064A
detects an internal over-temperature condition it will shutdown the outputs and trigger a full soft-start condition.
When the internal device junction temperature has cooled below the thermal hysteresis temperature, operation
will resume under soft-start control.
34
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8.3.15.8 Fault Logic Diagram
Figure 30 depicts the fault-handling logic involving VSENSE, COMP, and several internal states. It should be
noted that recovery from any fault except OC if the soft start is not triggered, will result in single phase soft-on
operation (8 switching cycles).
Figure 30. Fault Logic With VSENSE Detections and Error Amplifier Control
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8.4 Device Functional Modes
The controller is primarily intended for set up as a dual phase interleaved PFC which utilizes inductor
demagnetization information based on inductor sense winding voltages which are routed to ZCDA and ZCDB to
trigger the start of a switching cycle.
The functionality may be extended in a couple of ways:
Phase-B Enable and Disable: When the voltage on COMP is below the voltage on the PHB pin, Phase B and
the Phase Fail Detector will be disabled. The on-time for Phase-A will be doubled to compensate
the Phase-B missing power. When the voltage on COMP is greater than the PHB pin voltage, two
phase mode is enabled. Connect PHB to a resistor divider sourced by VREF to set a threshold for
COMP pin and obtain an automatic light load efficiency management feature. Because when PHB
voltage is higher then COMP voltage, the on-time is doubled, in order to avoid risk of inductor
saturation an internal clamp ensures the on-time never can exceed dual phase mode maximum ontime.
PFC Stage Enable and Disable Control: Controller operation is enabled when VSENSE voltage exceeds the
1.25-V enable threshold. The primary disable method should be by pulling VSENSE low by an open
drain or open collector logic output. This will disable the outputs and significantly reduce VCC
current. Releasing VSENSE will initiate a soft-start. Avoid any PCB traces which would couple any
noise into this node.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This control device is generally applicable to the control of AC-DC power supplies which require Active Power
Factor Correction off Universal AC line. Applications using this device generally meet the Class-D equipment
input current harmonics standards per EN61000-3-2. This standard applies to equipment with rated Powers
higher than 75W. The device brings two phase interleaved control capability to the Transition Mode Boost and
hence will be generally a very good choice for cost optimized applications in the 150W to 800W space, or to
even lower powers that wish to leverage on the interleaving benefits of reduced filtering component size, lower
profile solutions and distributed thermal management.
9.2 Typical Application
Figure 31 shows an example of the UCC28064A PFC controller in a two-phase interleaved, transition-mode PFC
pre-regulator.
LA
L
LB
CZA
N
+
CB
220nF
PHB THRESHOLD
COUT
ZCD_B
VSENSE
ZCD_A
VSENSE
VREF
TSET
GDA
PHB
PGND
HVSEN
PHB THRESHOLD
VSENSE
CZ
RZ
HVSEN
COMP
VCC
AGND
GDB
VINAC
CS
HVSEN
BRST
-
Figure 31. Typical Interleaved Transition-Mode PFC Preregulator
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Typical Application (continued)
9.2.1 Design Requirements
The specifications for this design were chosen based on the power requirements of a typical 300-W LCD TV.
Table 2 lists these specifications.
Table 2. Design Specifications
DESIGN PARAMETER
MIN
VIN
RMS input voltage
VOUT
Output voltage
fLINE
AC-line frequency
PF
Power factor at maximum load
TYP
85
(VIN_MIN)
MAX
UNIT
265
(VIN_MAX)
VRMS
390
47
Full-load efficiency
fMIN
Minimum switching frequency
Hz
300
W
0.90
POUT
η
V
63
92%
45
kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC28064A device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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9.2.2.2 Inductor Selection
The boost inductor is selected based on the minimum switching requirements. Operating at the boundary
between DCM and CCM the minimum switching frequency will be at maximum power and at the peak of the line.
It is possible that the minimum switching frequency can occur at minimum line or at maximum line. Equation 20.
LH
K u VIN _ MAX 2 u (VOUT
f MIN u VOUT u POUT _ MAX
2
LL
2 u VIN _ MAX )
K u VIN _ MIN u (VOUT
2 u VIN _ MIN )
f MIN u VOUT u POUT _ MAX
0.92 u (264V ) 2 u (390
2 u 264V )
27 kHz u 390V u 300W
338P H
(19)
2
0.92 u (85V ) u (390
2 u 85V )
27 kHz u 390V u 300W
568P H
(20)
In order to be sure that converters operates always above the desired (fMIN) we will select the minimum value
between LH that would be the value we have if we consider the minimum occurs at maximum input voltage and
LL that would be the value we have if we consider that minimum switching frequency occurs at minimum Line
voltage. For this design example, fMIN is set to 27 kHz in order to be always above the audible range. For a 2phase interleaved design, L1 and L2 are determined by minimum between LH and LLas stated in formula (19)
here belowEquation 21.
L1 L2 min( LH , LL ) # 340P H
(21)
The inductor for this design would have a peak current (ILPEAK) of 5.4 A, as shown in Equation 22, and an RMS
current (ILRMS) of 2.2 A, as shown in Equation 23.
ILPEAK =
ILRMS =
POUT 2
300 W 2
=
» 5.4 Apk
VIN _ MIN ´ h 85 V ´ 0.92
ILPEAK
6
5.4 A
=
6
(22)
» 2.2 Arms
(23)
This converter uses constant on time (TON) and zero-current detection (ZCD) to set up the converter timing.
Auxiliary windings on L1 and L2 detect when the inductor currents are zero. Selecting the turns ratio using
Equation 24 ensures that there will be at least 2 V at the peak of high line to reset the ZCD comparator after
every switching cycle.
The turns-ratio of each auxiliary winding is:
NP VOUT - VIN_MAX 2 390 V - 265 V 2
=
=
»8
Ns
2V
2V
(24)
9.2.2.3 ZCD Resistor Selection RZA, RZB
The minimum value of the ZCD resistors is selected based on the internal clamps maximum current ratings of 3
mA, as shown in Equation 25.
V
N
390 V
R ZA = R ZB ³ OUT S =
» 16.3kW
NP ´ 3mA 8 ´ 3mA
(25)
In this design the ZCD resistors are set to 20 kΩ, as shown in Equation 26.
R ZA = R ZB = 20kW
(26)
9.2.2.4 HVSEN
According to RE and RF resistor values, the Failsafe OVP threshold will be set according to Equation 27
VOV _ FAILSAFE =
4.87 V (RE + RF ) 4.87 V (8.22MW + 82.5kW )
=
» 490 V
RF
82.5kW
(27)
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9.2.2.5
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Output Capacitor Selection
The output capacitor ( COUT ) is selected based on holdup requirements, as shown in Equation 28.
POUT 1
300 W 1
2
h fLINE
0.92 47Hz
³
=
» 156 mF
2
2
VOUT - (VOUT _ MIN )
390 V 2 - (252 V)2
2
COUT
(28)
Two 100-μF capacitors were used in parallel for the output capacitor.
COUT = 200 mF
(29)
For this size capacitor, the low-frequency peak-to-peak output voltage ripple (VRIPPLE) is approximately 14 V, as
shown in Equation 30:
2 ´ POUT
1
2 ´ 300 W
VRIPPLE =
=
» 14 Vppk
VOUT ´ 4p ´ fLINE ´ COUT 0.92 ´ 390 V ´ 4p ´ 47Hz ´ 200 mF
h
(30)
In addition to holdup requirements, a capacitor must be selected so that it can withstand the low-frequency RMS
current (ICOUT_100Hz) and the high-frequency RMS current (ICOUT_HF); see Equation 31 to Equation 33. Highvoltage electrolytic capacitors generally have both a low- and a high-frequency RMS current ratings on the
product data sheets.
POUT
300 W
ICOUT _100Hz =
=
= 0.591 Arms
VOUT ´ h ´ 2 390 V ´ 0.92 ´ 2
(31)
ICOUT _ HF
æ
POUT 2 2
= ç
çç 2 ´ h ´ VIN _ MIN
è
æ 300 W ´ 2 2
ICOUT _ HF = ç
ç 2 ´ 0.92 ´ 85 V
è
40
2
4 2VIN _ MIN ö
÷ - I
COUT _100Hz
9pVOUT ÷÷
ø
(
)
2
(32)
2
4 2 ´ 85 V ö
÷ - (0.591A )2 » 0.966 Arms
9p ´ 390 V ÷
ø
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9.2.2.6 Selecting RS For Peak Current Limiting
The UCC28064A peak limit comparator senses the total input current and is used to protect the MOSFETs
during inrush and over-load conditions. For reliability, the peak current limit (IPEAK) threshold in this design is set
for 120% of the nominal maximum current that will be observed during power up, as shown in Equation 34.
IPEAK =
2POUT 2(1.2) 2 ´ 300 W 2 ´ 1.2
=
» 13 A
h ´ VIN _ MIN
0.92 ´ 85 V
(34)
A standard 15-mΩ metal-film current-sense resistor will be used for current sensing, as shown in Equation 35.
The estimated power loss of the current-sense resistor (PRS) is less than 0.25 W during normal operation, as
shown in Figure 8.
RS =
200mV 200mV
=
» 15mΩ
IPEAK
13 A
2
(35)
2
æ POUT ö
æ 300 W ö
PRS = ç
RS = ç
÷
÷ ´ 15mW » 0.22 W
çV
÷
´
h
85
V
´
0.92
è
ø
IN_MIN
è
ø
(36)
The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to
withstand a short-circuit current larger than the current required to open the fuse (F1). I2t (ampere-squaredseconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I2t is equal
to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I2t of 14 A2s was
chosen to protect the design from a short-circuit condition. To ensure the current-sense resistor has high-enough
surge protection, a 15-mΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a 2.5-W
surge rating for 5 seconds. This result translates into 833 A2s and has a high-enough I2t rating to survive a shortcircuit before the fuse opens, as described in Equation 37.
2.5 W
I2 t =
´ 5s = 833 A 2 s
0.015 W
(37)
9.2.2.7 Power Semiconductor Selection (Q1, Q2, D1, D2)
The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. For an explanation of
how to select power semiconductor components for transition-mode PFC preregulators, refer to UCC38050 100W Critical Conduction Power Factor Corrected (PFC) Pre-regulator.
The MOSFET (Q1, Q2) pulsed-drain maximum current is shown in Equation 38:
IDM ³ IPEAK = 13 A
(38)
The MOSFET (Q1, Q2) RMS current calculation is shown in Equation 39:
IDS =
IPEAK
2
1 4 2 VIN _ MIN 13 A
=
6
9p ´ VOUT
2
1 4 2 ´ 85 V
» 2.3 A
6 9p ´ 390 V
(39)
To meet the power requirements of the design, IRFB11N50A 500-V MOSFETs were chosen for Q1 and Q2.
The boost diode (D1, D2) RMS current is shown in Equation 40:
I
ID = PEAK
2
4 2 ´ VIN _ MIN
9p ´ VOUT
=
13 A
2
4 2 ´ 85 V
» 1.4 A
9p ´ 390 V
(40)
To meet the power requirements of the design, MURS360T3, 600-V diodes were chosen for D1 and D2.
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9.2.2.8 Brownout Protection
Resistor RA and RB are selected to activate brownout protection at ~75% of the specified minimum-operating
input voltage. Resistor RA programs the brownout hysteresis comparator, which is selected to provide 17 V (~12
VRMS) of hysteresis. Calculations for RA and RB are shown in Equation 41 through Equation 44.
Hysteresis 17 V
RA =
=
= 8.5MW
2 mA
2 mA
(41)
To meet voltage requirements, three 2.87-MΩ resistors were used in series for RA.
R A = 3 ´ 2.87MW = 8.61MW
RB =
1.4 V ´ R A
VIN _ MIN ´ 0.75 2 - 1.4 V
=
1.4 V ´ 8.61MW
85 V ´ 0.75 2 - 1.4 V
(42)
= 135.8kW
(43)
Select a standard value for RB.
RB = 133kW
(44)
In this design example, brownout becomes active (shuts down PFC) when the input drops below 67 VRMS for
longer than 680 ms and deactivates (restarts with a full soft start) if, after that the tBORST time is elapsed, the input
reaches 81 VRMS.
9.2.2.9 Converter Timing
The MOSFET on-time TON depends on value of the selected inductance on load value, represented by COMP
pin voltage and by the converter AC input voltage Equation 45. To ensure proper operation, the timing must be
set based on the highest boost inductance (L1MAX) and output power (POUT) at minimum operating AC input
Voltage. Because the input voltage is sensed by VINAC pin the on time setting needs to take into account of the
selected resistor divider that provide voltage at VINAC pin. In this design example, the boost inductor could be as
high as 390 µH.
Let's call KBO the ratio:Equation 49.
K BO
RA
RB
RB
8.61M : 133k :
133k :
65.74
(45)
the Maximum on time at full load (POUT = 300W) and minimum input voltage (85VAC) is given by formula;
P10_/#: =
2176 × .
2
ß × k8+0_/+0 o
=
:3009 ; × :340ä*;
= 15.34äO
0.92 × :858 ;2
(46)
The value of the resistor RT connected to TSET pin to set the on time timers is the minimum of RTH and RTL
provided by formulas (46) and (47)
RT
RTH
RTL
min( RTL , RTH )
(47)
KTH _ MIN u (5V ) 2 u (133k :) u (4.825V )
2
§ 2 u VIN _ MIN ·
¨
¸ u tON _ MAX
¨
¸
K
BO
©
¹
2
KTL _ MIN u (1.6V ) u (133k :) u (4.825V )
§ 2 u VIN _ MIN
¨
¨
K BO
©
(48)
2
·
¸ u tON _ MAX
¸
¹
(49)
Where the values of KTL_min and KTH_min are the minimum values of KTL and KTH parameters reported on the
electrical characteristic table at page 7 of this datasheet.
The selected value for RT is 115 kΩ.
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9.2.2.10 Programming VOUT
Resistor RC is selected to minimize loading on the power line when the PFC is disabled. Construct resistor RC
from two or more resistors in series to meet high-voltage requirements. Resistor RD is then calculated based on
RC, the reference voltage, VREF, and the required output voltage, VOUT. Based on the values shown in
Equation 50 to Equation 53, the primary output overvoltage protection threshold should be as shown in
Equation 54:
RC = 2.74MW + 2.74MW + 3.01MW = 8.49MW
(50)
VREF = 6 V
(51)
VREF ´ RC
6 V ´ 8.49MW
RD =
=
= 132.7kW
VOUT - VREF
390 V - 6 V
(52)
Select a standard value for RD.
RD = 133kW
(53)
R + RD
8.49MW + 133kW
VOVP = 6.48 V C
= 6.48 V
= 420.1V
RD
133kW
(54)
9.2.2.11 Voltage Loop Compensation
Resistor RZ is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This
value ensures good power factor and low harmonic distortion on the input current. The voltage on the COMP pin
needs to stay above 250 mV to maintain normal operation. If COMP falls below this threshold switching will stop.
The transconductance amplifier small-signal gain is shown in Equation 55:
gm = 50 mS
(55)
The voltage-divider feedback gain is shown in Equation 56:
V
6V
H = REF =
» 0.015
VOUT 390 V
(56)
The value of RZ is calculated as shown in Equation 57:
100mV
100mV
RZ =
=
= 9.52 kW
VRIPPLE ´ H ´ gm 14 V ´ 0.015 ´ 50 mS
(57)
CZ is then set to add 45° phase margin at 1/5th of the line frequency, as shown in Equation 58:
1
1
CZ =
=
= 1.78 mF
fLINE
47Hz
´ 9.52kW
2p ´
´ R Z 2p ´
5
5
(58)
CP is sized to attenuate high-frequency switching noise, as shown in Equation 59:
1
1
Cp =
=
= 770pF
f
45kHz
´ 9.52kW
2p ´ MIN ´ R Z 2p ´
2
2
(59)
Standard values should be chosen for RZ, CZ and CP, as shown in Equation 60 to Equation 62.
R Z = 9.53kW
(60)
CZ = 2.2 mF
(61)
CP = 820pF
(62)
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9.2.3 Application Curves
9.2.3.1 Input Ripple Current Cancellation with Natural Interleaving
Figure 32 through Figure 34 show the input current (CH2), Inductor Ripple Currents (CH3, CH4) versus rectified
line voltage. From these graphs, it can be observed that natural interleaving reduces the overall magnitude of
input (and output) ripple current caused by the individual inductor current ripples.
CH2 = Input Current
CH3 = Phase A Inductor
Current
CH4 = Phase B Inductor
Current
CH2 = Input Current
CH3 = Phase A Inductor
Current
CH4 = Phase B Inductor
Current
Figure 32. Inductor and Input Ripple Current at 85 VRMS at
Peak of Line Voltage
Figure 33. Inductor and Input Ripple Current at 265 VRMS
Input at Peak Line Voltage
CH2 = Input Current
CH4 = Phase B Inductor Current
CH3 = Phase A Inductor Current
Figure 34. Inductor and Input Ripple Current at VIN = 85 VRMS, POUT = 300 W
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9.2.3.2 Brownout Protection
The UCC28064A has a brownout protection that shuts down both gate drives (GDA and GDB) when the VINAC
pin detects that the RMS input voltage is too low. Figure 35.
CH1 = VGDA
CH2 = VGDB
CH3 = VOUT
CH3 = VIN
Figure 35. UCC28064A Response to a Line Brownout Event at 115 VRMS
10 Power Supply Recommendations
The device receives all of its power through the VCC pin. This voltage should be as well regulated as possible
through all of the operating conditions of the PFC stage. Consider creating the steady state bias for this stage
from a downstream DC:DC stage which will in general be able to provide a bias winding with very well regulated
voltage. This strategy will enhance the overall efficiency of the bias generation. A lower efficiency alternative will
be to consider a series-connected fixed positive-voltage regulator such as the UA78L15A.
For all normal and abnormal operating conditions it is critically important that VCC remains within the
recommended operating range for both Voltage and Input Current. VCC overvoltage may cause excessive power
dissipation in the internal voltage clamp and undervoltage may cause inadequate drive levels for power
MOSFETs, UVLO events (causing interrupted PFC operation) or inadequate headroom for the various on-chip
linear regulators and references.
Note also that the high RMS and peak currents required for the MOSFET gate drives are provided through the
device 13.5-V linear regulator, which does not have provision for the addition of external decoupling capacitance.
For higher Powers, very high QG power MOSFETs or high switching frequencies, consider using external driver
transistors, local to the power MOSFETs. These will reduce the device operating temperature and ensure that
the VCC maximum input current rating is not exceeded.
Use decoupling capacitances between VREF and AGND and between VCC and PGND which are as local as
possible to the device. These should have some ceramic capacitance which will provide very low ESR. PGND
and AGND should ideally be star connected at the control device so that there is negligible DC or high frequency
AC voltage difference between PGND and AGND. Use values for decoupling capacitors similar to or a little larger
than those used in the EVM.
Pay close attention to start-up and shutdown VCC bias bootstrap arrangements so that these provide adequate
regulated bias power as early as possible during power application and as late as possible during power
removal. Ensure that these start-up bias bootstrap circuits do not cause unnecessary steady-state power drain.
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11 Layout
11.1 Layout Guidelines
Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,
allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input
and output filter capacitors should be located after the two phase currents are combined together. Similar to
other power management devices, when laying out the printed circuit board (PCB) it is important to use star
grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the
interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in
(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath
magnetic elements. Because of the precise timing requirement, timing-setting resistor RT should be placed as
close as possible to the TSET pin and returned to the analog ground pin with the shortest possible path.
Figure 36 shows a recommended component placement and layout.
46
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11.2 Layout Example
Dotted line could be or a wire mounted on the top of the board or Top layer traces, assuming device and other traces
are in the bottom layer.
Figure 36. Recommended PCB Layout
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11.3 Package Option Addendum
11.3.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package Type
Package
Drawing
Pins
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
Device
Marking (5) (6)
UCC28064ADT
ACTIVE
SOIC
D
16
250
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28064A
UCC28064ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28064A
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
48
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Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: UCC28064A
UCC28064A
www.ti.com
SLUSC60B – DECEMBER 2017 – REVISED OCTOBER 2019
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC28064 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• UCC28064AEVM 300W Interleaved PFC Pre-regulator
• UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: UCC28064A
49
UCC28064A
SLUSC60B – DECEMBER 2017 – REVISED OCTOBER 2019
www.ti.com
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
50
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Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: UCC28064A
UCC28064A
www.ti.com
SLUSC60B – DECEMBER 2017 – REVISED OCTOBER 2019
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: UCC28064A
51
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC28064ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28064A
UCC28064ADT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28064A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCC28064ADR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
UCC28064ADT
SOIC
D
16
250
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28064ADR
SOIC
D
16
2500
333.2
345.9
28.6
UCC28064ADT
SOIC
D
16
250
333.2
345.9
28.6
Pack Materials-Page 2
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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