Texas Instruments | TPS6380x High-efficient, Low IQ Buck-boost Converter with Small Solution Size (Rev. C) | Datasheet | Texas Instruments TPS6380x High-efficient, Low IQ Buck-boost Converter with Small Solution Size (Rev. C) Datasheet

Texas Instruments TPS6380x High-efficient, Low IQ Buck-boost Converter with Small Solution Size (Rev. C) Datasheet
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TPS63805, TPS63806
SLVSDS9C – JULY 2018 – REVISED OCTOBER 2019
TPS6380x High-efficient, Low IQ Buck-boost Converter with Small Solution Size
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
Two pin-2-pin device options, TPS63805 and
TPS63806 with specific application focus
Input voltage range: 1.3 V to 5.5 V
– Device input voltage > 1.8 V for start-up
Output voltage range: 1.8 V to 5.2 V (adjustable)
High efficiency over the entire load range
– Low operating quiescent current
– Power save mode and mode selection for
forced PWM-mode
Peak current buck-boost mode architecture
– Defined transition points between buck, buckboost, and boost operation modes
– Forward and reverse current operation
– Start-up into pre-biased outputs
Safety and robust operation features
– Integrated soft start
– Overtemperature- and overvoltage-protection
– True shutdown function with load disconnect
– Forward and backward current limit
TPS63805
– Optimized for smallest solution size of
18.5 mm2 (works with a 22-µF minimum output
capacitor)
– 2-A Output current for VI ≥ 2.3 V, VO = 3.3 V
– 11-µA Operating quiescent current
TPS63806
– Optimized for best load step response (180mV load-step response at a 2 A current step)
– Up to 2.5 A transient output current
– 13-µA Operating quiescent current
•
TPS63805
– System pre-regulator (smartphone, tablet, left
terminal, and telematics)
– Point-of-load regulation (wired sensor,
port/cable adapter, and dongle)
TPS63806
– Time-of-Flight camera sensor (smartphone,
electronic smart lock, and ip network camera)
– Broadband network radio or SoC supply (IoT,
tracking, home automation, and EPOS)
– Thermoelectric device supply (TEC, optical
modules)
– General purpose voltage stabilizer
3 Description
The TPS63805 and TPS63806 are high efficiency,
high output current buck-boost converters. Depending
on the input voltage, they automatically operate in
boost, buck, or in a novel 4-cycle buck-boost mode
when the input voltage is approximately equal to the
output voltage. The transitions between modes
happen at defined thresholds and avoid unwanted
toggling within the modes to reduce output voltage
ripple. The device output voltages are individually set
by a resistive divider within a wide output voltage
range.The TPS63805 achieves the lowest solution
size with a tiny bill of materials. An 11-μA quiescent
current enables the highest efficiency for little to noload conditions.
Device Information(1)
PART NUMBER
TPS63805
PACKAGE
3x5 Balls WCSP
(0.4 mm pitch)
TPS63806
BODY SIZE (NOM)
2.3 mm x 1.4 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
Efficiency vs Output Current (VO = 3.3 V)
0.47µH
100
90
80
L2
VIN
VOUT
3.3V
VOUT
22 …F
10 …F
EN
PG
MODE
FB
70
Efficiency (%)
L1
VIN
1.3V t 5.5V
60
50
40
30
VIN = 3.0 V
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
20
GND
AGND
TPS63805
10
0
100P
1m
10m
100m
Output Current (A)
1
2
D001
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS63805, TPS63806
SLVSDS9C – JULY 2018 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
4
5
8.1
8.2
8.3
8.4
8.5
8.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics .............................................
Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 17
10.1 Application Information.......................................... 17
10.2 Typical Application ............................................... 17
11 Power Supply Recommendations ..................... 34
12 Layout................................................................... 34
12.1 Layout Guidelines ................................................. 34
12.2 Layout Example .................................................... 34
13 Device and Documentation Support ................. 35
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
36
36
14 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
Changes from Revision B (August 2019) to Revision C
Page
•
Changed Features list to address both pin to pin devices TPS63805 and TPS63806 ......................................................... 1
•
Deleted 2A from the data sheet title ....................................................................................................................................... 1
•
Removed RF Amplifier supply from the Applications ............................................................................................................. 1
•
Added time-of flight camera sensor, broadband network radio or SoC supply, and general purpose voltage stabilizer
to the Applications ................................................................................................................................................................. 1
•
Changed Description .............................................................................................................................................................. 1
•
Changed application information in Table 2 from ≥ 100 µF to 100 µF to be aligned with Table 3 ..................................... 18
•
Added 0.8 mm component height capacitors to Table 5 ..................................................................................................... 19
•
Added comment column for VO condition of application characteristics ............................................................................. 20
•
Changed Figure 17 image data ............................................................................................................................................ 24
Changes from Revision A (October 2018) to Revision B
Page
•
Changed the Features list ..................................................................................................................................................... 1
•
Added the TPS63086 to the data sheet ................................................................................................................................ 1
•
Changed the adjustable output voltage range from 5.0 V to 5.2 V ....................................................................................... 1
•
Deleted Operates with low and high output capacitance valuesfrom features list ................................................................. 1
•
Deleted package size parameters for features list ................................................................................................................ 1
•
Changed the textDescription to address TPS63805 and TPS63806 ..................................................................................... 1
•
Changed Efficiency vs. Output current curve ........................................................................................................................ 1
•
Added If not used can be left floating for PG-pin ................................................................................................................... 4
•
Added VIN = 3.6 V for typical value in condition text ............................................................................................................. 5
•
Changed VOUT from 5 V to 5.2 V condition text ...................................................................................................................... 5
•
Added PG Pin ......................................................................................................................................................................... 5
•
Changed PFM/PWM pin name to Mode................................................................................................................................. 5
•
Changed VO from 5 V to 5.2 V ............................................................................................................................................... 5
2
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•
Changed typical effective output capacitance from 10 uF to 8.2 uF ...................................................................................... 5
•
Added Vo conditions for CO range ........................................................................................................................................ 5
•
Changed Soft-start Current limit ramp time test conditions.................................................................................................... 6
•
Changed typical Soft-start Current limit ramp time from 0.6 ms to 224 us ........................................................................... 6
•
Changed Delay from EN-edge until rising VOUT test conditions ............................................................................................. 6
•
Changed typical Delay from EN-edge until rising VOUT from 100 us to 321 us ...................................................................... 6
•
Changed typical Overvoltage Protection Threshold from 5.66 V to 5.7 V.............................................................................. 6
•
Changed maximum Overvoltage Protection Threshold from 5.8 V to 5.9 V .......................................................................... 6
•
Changd Peak Inductor Current to enter PFM-Mode to 1.06 A typical only ............................................................................ 6
•
Changed minimum Peak Current Limit Boost Mode from 3.5 A to 4 A.................................................................................. 6
•
Changed typical Peak Current Limit Boost Mode from 4.8 A to 5 A ..................................................................................... 6
•
Changed maximum Peak Current Limit Boost Mode from 5.8 A to 5.75 A............................................................................ 6
•
Changed Peak Current Limit for Reverse Operation to 0.9 A typical only ............................................................................ 6
•
Changed Inductor Switching Frequency, Buck Mode from 2.7 MHz to 1.6 MHz ................................................................... 7
•
Changed typical Line regulation from 0.5% to 0.3 % ............................................................................................................. 7
•
Changed typical Load regulation from 0.5% to 0.1% ............................................................................................................. 7
•
Changed Quiescent Current vs. Temperature Curve for TPS63805 in Typical Characteristics ........................................... 8
•
Changed Typical Characteristics shutdown current vs. temperature curve for TPS63805 ................................................... 8
Changes from Original (July 2018) to Revision A
•
Page
Changed the document status from Advanced Information to Production Data for the TPS63805....................................... 1
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5 Description (continued)
The TPS63806 is optimized for applications where the load-step response under a heavy load profile is a
concern.
The TPS63805 and TPS63806 come in a 1.4 mm x 2.3 mm package. The device works with tiny passive
components to keep the overall solution size small.
6 Device Comparison Table
PART
NUMBER
OUTPUT VOLTAGE
(VO)
I(Q;VIN) (TYP.)
C(O,EFF) (MIN.)
VPP LOAD TRANSIENT
RESPONDS (TYP.)
TPS63805
Adjustable
11 µA
7 µF
320 mV
TPS63806
Adjustable
13 µA
21 µF
180 mV
7 Pin Configuration and Functions
WCSP Package
Top View
Pin Functions Table
PIN
NO
A2, A3
VIN
Supply voltage
B2, B3
L1
Connection for inductor
A1
EN
Device Enable input. Set HIGH to enable and LOW to disable. It must not be left floating.
C2, C3
4
DESCRIPTION
NAME
GND
Power ground
B1
MODE
PFM/PWM mode selection. Set LOW for power safe mode, set HIGH for forced PWM mode. It must not be
left floating.
C1
AGND
Analog ground
D2, D3
L2
Connection for inductor
E2, E3
VOUT
Power stage output
D1
FB
Voltage feedback sensing pin
E1
PG
Power good indicator, open drain output. If not used can be left floating.
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8 Specifications
8.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted) (1)
VIN, L1, L2, EN, MODE, VOUT, FB, PG
Voltage (2)
MAX
6
UNIT
V
–3
9
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
L1, L2 (AC, less than 10 ns)
MIN
–0.3
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
VI
Input voltage
1.3
VO
Output voltage
CI
Effective capacitance connected to VIN
L
Effective inductance
CO
TPS63805 Effective capacitance connected to VOUT
1.8
CO
TPS63806; Effective capacitance connected to VOUT
TJ
Operating junction temperature
(1)
(2)
NOM
(1)
1.8 V ≤ VO ≤ 2.3 V
VO > 2.3 V
4
5
0.47
V
(2)
V
μF
0.57
10
VO > 2.3 V
21
μH
μF
7
30
UNIT
5.5
5.2
0.37
1.8 V ≤ VO < 2.3 V
Operating junction
temperature
MAX
8.2
µF
27
µF
μF
–40
125
°C
Minimum startup voltage of VI > 1.8 V until power good
VO margin for accuracy and load steps is considerd in absolut maximum ratings
8.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
TPS63805, TPS63806
THERMAL METRIC (1)
3x5 Ball WCSP
UNIT
15 PINS
RΘJA
Junction-to-ambient thermal resistance
78.8
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
0.6
°C/W
RΘJB
Junction-to-board thermal resistance
19.5
°C/W
ΨJT
Junction-to-top characterization parameter
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
19.5
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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8.5 Electrical Characteristics
VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5.2 V , TJ= –40°C to +125°C, typical values are at VIN= 3.6 V, VOUT = 3.3 V and TJ=
25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN;LOAD
Minimum input voltage for full
load, once started
IOUT = 2 A, VOUT = 3.3 V, TJ = 25°C
2.3
V
IQ;VIN
Quiescent current into VIN
TPS63805; TJ = 25°C, EN = VIN = 3.6 V, VOUT = 3.3 V, not
switching
11
μA
IQ;VIN
Quiescent current into VIN
TPS63806; TJ = 25°C, EN = VIN = 3.6 V, VOUT = 3.3 V, not
switching
13
μA
ISD
Shutdown current into VIN
EN = low, -40°C ≤ TJ ≤ 85°C, VIN = 3.6 V, VOUT = 0 V
45
600
nA
Undervoltage lockout threshold
VIN falling, VOUT ≥ 1.8 V, once started
1.2
1.25
1.29
V
Undervoltage lockout threshold
VIN rising
1.6
1.7
1.79
TSD
Thermal shutdown
Temperature rising
TSD;HYST
Thermal shutdown hysteresis
UVLO
V
150
°C
20
°C
SOFT-START, POWER GOOD
Tramp
Soft-start, Current limit ramp time
TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V, IO = 3.5 A, time from
first switching to power good
224
µs
Tdelay
Delay from EN-edge until rising
VOUT
TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V, Delay from EN-edge
until rising
first switching
321
µs
LOGIC SIGNALS EN, MODE
VTHR;EN
Threshold Voltage rising for ENPin
1.07
1.1
1.13
V
VTHF;EN
Threshold Voltage falling for ENPin
0.97
1
1.03
V
VIH
High-level input voltage
VIL
Low-level input voltage
VPG;rising
Power Good threshold voltage
VPG;falling
1.2
V
0.4
V
VOUT rising, referenced to VOUT nominal
95
%
VOUT falling, referenced to VOUT nominal
90
%
VPG;Low
Power Good low-level output
voltage
ISINK = 1 mA
tPG;delay
Power Good delay time
VFB falling
Ilkg
Input leakage current
0.4
V
0.01
0.2
µA
±0.5
±600
14
µs
OUTPUT
ISD
Shutdown current into VOUT
VFB
Feedback Regulation Voltage
VFB
Feedback Voltage accuracy
Overvoltage Protection Threshold
EN = low, -40°C ≤ TJ ≤ 85°C, VIN = 3.6 V, VOUT = 3.3 V
500
PWM mode
–1
1
%
VOUT rising
5.5
5.7
5.9
V
VIN rising
5.5
5.7
5.9
V
IPWM/PFM
Peak Inductor Current to enter
PFM-Mode
VIN = 3.6 V; VOUT = 3.3 V
IFB
Feedback Input Bias Current
VFB = 500 mV
1.06
Peak Current Limit, Boost Mode
Peak Current Limit, Buck-Boost
Mode
IPK
4
TPS63805; VIN ≥ 2.5 V
4.4
TPS63806; VIN ≥ 2.5V
Peak Current Limit, Buck Mode
IPK;Reverse
Buck
RDS;ON
6
5
100
nA
5
5.75
A
A
3.8
Peak Current Limit, Boost Mode
IPK
A
5
Peak Current Limit, Buck Mode
Peak Current Limit, Buck-Boost
Mode
nA
mV
5.5
A
6.25
A
5.5
A
4
A
–0.9
A
Peak Current Limit for Reverse
Operation
VI = 5 V, VO = 3.3 V
High-side FET on-resistance
VIN = 3 V, VOUT = 3.3 V; I(L2) =
0.19 A
VIN = 3 V, VOUT = 3.3
V; IO = 0.5 A
47
mΩ
Low-side FET on-resistance
VIN = 3 V, VOUT = 3.3 V; I(L2) =
0.19 A
VIN = 3 V, VOUT = 3.3
V; IO = 0.5 A
30
mΩ
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Electrical Characteristics (continued)
VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5.2 V , TJ= –40°C to +125°C, typical values are at VIN= 3.6 V, VOUT = 3.3 V and TJ=
25°C (unless otherwise noted)
PARAMETER
Boost
RDS;ON
fSW
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-side FET on-resistance
VIN = 3 V, VOUT = 3.3 V; I(L1) =
0.19 A
VIN = 3 V, VOUT = 3.3
V; IO = 0.5 A
43
mΩ
Low-side FET on-resistance
VIN = 3 V, VOUT = 3.3 V; I(L1) =
0.19 A
VIN = 3 V, VOUT = 3.3
V; IO = 0.5 A
18
mΩ
Inductor Switching Frequency,
Boost Mode
VIN = 2.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ =
25°C
2.1
MHz
Inductor Switching Frequency,
Buck-Boost Mode
VIN = 3.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ =
25°C
1.4
MHz
Inductor Switching Frequency,
Buck Mode
VIN = 4.3, VOUT = 3.3V, no Load, MODE = HIGH, TJ =
25°C
1.6
MHz
Line regulation
VIN = 2.4 V to 5.5 V, VOUT = 3.3V, IOUT = 2 A
0.3
%
Load regulation
VIN= 3.6 V, VOUT = 3.3V, IOUT = 0 A to 2 A, forced-PWM
mode
0.1
%
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8.6 Typical Characteristics
20
16
Unit ID#
VI =319112
1.8 V
VI = 3.6 V
VI = 5.5 V
16
12
Quiescent Current (PA)
Quiescent Current (PA)
VI = 1.8 V
VI = 3.6 V
VI = 5.5 V
8
4
12
8
4
0
-40
-20
MODE = LOW
0
20
40
60
80
Temperature (qC)
100
120
0
-40
140
-20
0
20
D006
VO = 3.3 V
IO = 0 mA, not
switching
MODE = LOW
Figure 1. TPS63805 Quiescent Current vs. Temperature
40
60
80
Temperature (qC)
VO = 3.3 V
100
120
140
D005
IO = 0 mA, not
switching
Figure 2. Quiescent Current vs. Temperature
1.4
VI = 1.8 V
VI = 3.6 V
VI = 5.5 V
Shutdown Current (PA)
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D004
EN = LOW
Figure 3. Shutdown Current vs. Temperature
8
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9 Detailed Description
9.1 Overview
The TPS63805 and TPS63806 buck-boost converter use four internal switches to maintain synchronous power
conversion at all possible operating conditions. This enables the device to keep high efficiency over a wide input
voltage and output load range. To regulate the output voltage at all possible input voltage conditions, the device
automatically transitions between buck, buck-boost, and boost operation as required by the operating conditions.
Therefore, it operates as a buck converter when the input voltage is higher than the output voltage, and as a
boost converter when the input voltage is lower than the output voltage. When the input voltage is close to the
output voltage, it operates in a 3-cycle buck-boost operation. In this mode, all four switches are active (see BuckBoost Operation). The RMS current through the switches and the inductor is kept at a minimum to minimize
switching and conduction losses. Controlling the switches this way allows the converter to always keep high
efficiency over the complete input voltage range. The device provides a seamless transition between all modes.
9.2 Functional Block Diagram
L
L1
L2
VOUT
VIN
CIN
COUT
Gate
Driver
Gate
Driver
Current
Sensor
Device
Control
Device
Control
VIN
VMAX Switch
VOUT
PG
Device
Control
EN
+
Ref
1.1V
Device Control
FB
+
±
VIN
MODE
VOUT
GND
+
Power Safe Mode
Protection
Current Limit
Buck/Boost Control
Off-time calculation
Soft-Start
±
±
Gate
Driver
Ref
500mV
Power
Good
AGND
L1, L2
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9.3 Feature Description
9.3.1 Control Loop Description
The TPS63805 and TPS63806 use a peak current mode control architecture. It has an inner current loop where
it measures the peak current of the boost high-side MOSFET and compares it to a reference current. This
current is the output of the outer voltage loop. It measures the output voltage via the FB-pin and compares it with
the internal voltage reference. That means, the outer voltage loop measures the voltage error (VREF-VFB), and
transforms it into the system current demand (IREF) for the inner current loop.
Figure 4 shows the simplified schematic of the control loop. The error amplifier and the type-2 compensation
represent the voltage loop. The voltage output is converted into the reference current IREF and fed into the
current comparator.
The scheme shows the skip-comparator handling the power-save mode (PFM) to achieve high efficiency at light
loads. See Power Save Mode Operation for further details.
VIN
L1
IPK
±
IREF
+
FB
VEA
+
Ref
500mV
Gate
Driver
±
+
ISKIP
±
Figure 4. Control Loop Architecture Scheme
9.3.2 Precise Device Enable: Threshold- or Delayed Enable
The enable-pin is a digital input to enable or disable the device by applying a high or low level. The device enters
shutdown when EN is set low. In addition, this input features a precise threshold and can be used as a
comparator that enables and disables the part at a defined threshold. This allows you to drive the state by a
slowly changing voltage and enables the use of an external RC network to achieve a precise power-up delay.
The enable pin can also be used with an external voltage divider to set a user-defined minimum supply voltage.
For proper operation, the EN pin must be terminated and must not be left floating.
VTHRESHOLD
VDELAY
R4
R4
EN
R5
EN
C5
Figure 5. Circuit Example for How to Use the Precise Device Enable Feature
10
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Feature Description (continued)
9.3.3 Mode Selection (PFM/PWM)
The mode-pin is a digital input to enable the automatic PWM/PFM mode that features the highest efficiency by
allowing pulse-frequency-modulation for lower output currents. This mode is enabled by applying a low level. The
device can be forced in PWM operation regardless of the output current to achieve minimum output ripple by
applying a high level. This pin must not be left floating.
9.3.4 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. It activates the
device once the input voltage (VI) has increased the UVLOrising value. Once active, the device allows operation
down to even smaller input voltages, which is determined by the UVLOfalling. This behavior requires VO to be
higher than the minimum value of 1.8 V.
UVLOrising
UVLOfalling
VIN
Device
active
Figure 6. Rising and Falling Undervoltage Lockout Behavior
9.3.5 Soft-start
To minimize inrush current and output voltage overshoot during start-up, the device features a controlled soft
start-up. After the device is enabled, the device starts all internal reference and control circuits within the enable
delay time, Tdelay. After that, the maximum switch current limit rises monotonically from 0 mA to the current limit.
The loop stops switching once VO is reached. This allows a quick output voltage raise for small capacitors at the
output. The bigger the output capacitor, the longer it takes to settle Vo. A potential load during start is lengthening
the ramp as well. The raise of the current limit allows the smallest inrush current for no-load conditions, as well
as the possibility to start into high loads at start-up.
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Feature Description (continued)
VIN
EN
Current Limit
Inductor
Current
0.95 x VOUT
VOUT
Power Good
Tdelay
Tramp
TStart-up
Figure 7. Device Start-up Scheme
9.3.6 Adjustable Output Voltage
The output voltage of the device is adjusted by applying an external resistive divider between VO, the FB-pin, and
GND. This allows you to program the output voltage in the recommended range. The divider must provide a lowside resistor of less than 100 kΩ. The high-side resistor is chosen accordingly.
9.3.7 Overtemperature Protection - Thermal Shutdown
The device has a built-in temperature sensor which monitors the junction temperature. If the temperature
exceeds the threshold, the device stops operating. As soon as the IC temperature has decreased below the
programmed threshold, it starts operating again. There is a built-in hysteresis to avoid unstable operation at
junction temperatures at the overtemperature threshold.
9.3.8 Input Overvoltage - Reverse-Boost Protection (IVP)
The TPS63805 and TPS63806 can operate in reverse mode where the device transfers energy from the output
back to the input. If the source is not able to sink the revers current, the negative current builds up a charge to
the input capacitance and VIN rises. To protect the device and other components from that scenario, the device
features an input voltage protection (IVP) for reverse boost operation. Once the input voltage is above the
threshold, the converter forces PFM mode and the negative current operation is interrupted.
The PG signal goes low to indicate that behavior.
9.3.9 Output Overvoltage Protection (OVP)
In case of a broken feedback-path connection, the device can loose VO information and is not able to regulate.
To avoid an uncontrolled boosting of VO, the TPS63805 and TPS63806 feature output overvoltage protection. It
measures the voltage on the VOUT pin and stops switching when VO is greater than the threshold to avoid harm
to the converter and other components.
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Feature Description (continued)
9.3.10 Power-Good Indicator
The power good goes high-impedance once the output is above 95% of the nominal voltage, and is driven low
once the output voltage falls below typically 90% of the nominal voltage. This feature also indicates overvoltage
and device shutdown cases as shown in Table 1. The PG pin is an open-drain output and is specified to sink up
to 1 mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 5.5 V. The PG
signal can be used to sequence multiple rails by connecting it to the EN pin of other converters. Leave the PG
pin unconnected when not used.
Table 1. Power-Good Indicator Truth Table
LOGIC SIGNALS
EN
VO
VI
OVP
IVP
PG LOGIC STATUS
X
< 1.8 V
< UVLO_R
X
X
Undefined
LOW
X
> UVLO_F
X
X
LOW
HIGH
VO < 0.9 × target-VO
> 1.3V
X
X
LOW
HIGH
X
> UVLO_F
HIGH
X
LOW
HIGH
X
> UVLO_F
X
HIGH
LOW
HIGH
VO > 0.95 × target-VO
> UVLO_F
LOW
LOW
HIGH Z
9.4 Device Functional Modes
9.4.1 Peak-Current Mode Architecture
The TPS63805 and TPS63806 are based on a peak-current mode architecture. The error amplifier provides a
peak-current target (voltage that is translated into an equivalent current, see Figure 4), based on the current
demand from the voltage loop. This target is compared to the actual inductor current during the ON-time. The
ON-time is ended once the inductor current is equal to the current target and OFF-time is initiated. The OFF-time
is calculated by the control and a function of VI and VO.
IPEAK
VEAmp
IPK-PK
TON
IIND
TOFF
0
time
Figure 8. Peak-Current Architecture Operation
9.4.1.1 Reverse Current Operation, Negative Current
When the TPS63805 and TPS63806 are forced to PWM operation (MODE = HIGH), the device current can flow
in reverse direction. This happens by the negative current capability of the TPS63805 and TPS63806. The error
amplifier provides a peak-current target (voltage that is translated into an equivalent current, see Figure 4), even
if the target has a negative value. The maximum average current is even more negative than the peak current.
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Device Functional Modes (continued)
time
0
IPEAK
VEAmp
IIND
IAVG
IPK-PK
Figure 9. Peak-Current Operation, Reverse Current
9.4.1.2 Boost Operation
When VI is smaller than VO (and the voltages are not close enough to trigger buck-boost operation), the
TPS63805 and TPS63806 operate in boost mode where the boost high-side and low-side switches are active.
The buck high-side switch is always turned on and the buck low-side switch is always turned off. This lets the
TPS63805 and TPS63806 operate as a classical boost converter.
IPEAK
VEAmp
IIND
TON
TOFF
Figure 10. Peak-Current Boost Operation
9.4.1.3 Buck-Boost Operation
When VI is close to VO, the TPS63805 and TPS63806 operate in buck-boost mode where all switches are active
and the device repeats 3-cycles:
• TON: Boost-charge phase where boost low-side and buck high-side are closed and the inductor current is built
up
• TOFF: Buck discharge phase where boost high-side and buck low-side are closed and the inductor is
discharged
• TCOM: VI connected to VO where all high-side switches are closed and the input is connected to the output
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Device Functional Modes (continued)
IPEAK
VEAmp
IIND
TON
TCOM
TOFF
TCOM
Figure 11. Peak-Current Buck-Boost Operation
9.4.1.4 Buck Operation
When VI is greater than VO (and the voltages are not close enough to trigger buck-boost operation), the
TPS63805 and TPS63806 operate in buck mode where the buck high-side and low-side switches are active. The
boost high-side switch is always turned on and the boost low-side switch is always turned off. This lets the
TPS63805 and TPS63806 operate as a classical buck converter.
IPEAK
VEAmp
IIND
TON
TOFF
Figure 12. Peak-Current Buck Operation
9.4.2 Power Save Mode Operation
Besides continuos conduction mode (PWM), the TPS63805 and TPS63806 feature power safe mode (PFM)
operation to achieve high efficiency at light load currents. This is implemented by pausing the switching
operation, depending on the load current.
The skip comparator manages the switching or pause operation. It compares the current demand signal from the
voltage loop, IREF, with the skip threshold, ISKIP, as shown in Figure 4. If the current demand is lower than the
skip value, the comparator pauses switching operation. If the current demand goes higher (due to falling VO), the
comparator activates the current loop and allows switching according to the loop behavior. Whenever the current
loop has risen VO by bringing charge to the output, the voltage loop output, IREF (respectively VEA), decreases.
When IREF falls below ISKIP-hysteresis, it automatically pauses again.
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Device Functional Modes (continued)
ICOIL
VO
ISKIP
VEA
/ IREF
Hysteresis
SKIP
Yes/No
Switching
Pause
t
Figure 13. Power Safe Mode Operation Curves
9.4.2.1 Current Limit Operation
To limit current and protect the device and application, the maximum peak inductor current is limited internally on
the IC. It is measured at the buck high-side switch which turns into an input current detection. To provide a
certain load current across all operation modes, the boost and buck-boost peak current limit is higher than in
buck mode. It limits the input current and allows no further increase of the delivered current. When using the
device in this mode, it behaves similar to a current source.
The current limit depends on the operation mode (buck, buck-boost, or boost mode).
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS63805 and TPS63806 are high efficiency, low quiescent current, non-inverting buck-boost converters,
suitable for applications that need a regulated output voltage from an input supply that can be higher or lower
than the output voltage.
10.2 Typical Application
L1
0.47µH
L1
VIN
1.3V t 5.5V
VIN
L2
VOUT = 3.3V
VIN
VOUT
R3
100kQ
C1
10 …F
EN
PG
MODE
FB
C2
22 …F
R1
511kQ
R2
91kQ
GND
AGND
TPS63805
Figure 14. TPS63805 3.3 VOUT Typical Application
L1
0.47µH
L1
VIN
1.3V t 5.5V
VIN
L2
VOUT = 3.3V
VOUT
VIN
R3
100lQ
C1
10 …F
EN
PG
MODE
FB
C2
47 …F
R1
511lQ
C2
47 …F
R2
91lQ
GND
AGND
TPS63806
Figure 15. TPS63806 3.3 VOUT Typical Application
10.2.1 Design Requirements
The design guideline provides a component selection to operate the device within the Table 2.
Table 2 shows the list of components for the application characteristic curves.
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Typical Application (continued)
Table 2. Matrix of Output Capacitor and Inductor Combinations for the TPS63805
NOMINAL OUTPUT CAPACITOR VALUE [µF] (2)
NOMINAL
INDUCTOR VALUE
[µH] (1)
10
0.47
-
(1)
(2)
(3)
22
+
(3)
47
66
100
+
+
+
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
Capacitance tolerance and DC bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
TPS63805 typical application. Other check marks indicate possible filter combinations.
Table 3. Matrix of Output Capacitor and Inductor Combinations for TPS63806
NOMINAL
INDUCTOR VALUE
[µH] (1)
0.47
(1)
(2)
(3)
NOMINAL OUTPUT CAPACITOR VALUE [µF] (2)
10
22
-
47
-
+
(3)
66
100
+
+
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
Capacitance tolerance and DC bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
TPS63806 typical application. Other check marks indicate possible filter combinations.
10.2.2 Detailed Design Procedure
The first step is the selection of the output filter components. To simplify this process, the Absolute Maximum
Ratings outlines minimum and maximum values for inductance and capacitance. Take tolerance and derating
into account when selecting nominal inductance and capacitance.
10.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63805 device with the WEBENCH® Power Designer. Click
here to create a custom design using the TPS63806 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2.2.2 Inductor Selection
The inductor selection is affected by several parameters such as the following:
• Inductor ripple current
• Output voltage ripple
• Transition point into power save mode
• Efficiency
See Table 4 for typical inductors.
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For high efficiencies, the inductor must have a low DC resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a high impact on efficiency. When using small chip inductors,
the efficiency is reduced, mainly due to higher inductor core losses. This needs to be considered when selecting
the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value,
the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for
the inductor in steady-state operation is calculated using Equation 2. Only the equation which defines the switch
current in boost mode is shown because this provides the highest value of current and represents the critical
current value for selecting the right inductor.
Duty Cycle Boost
IPEAK
D=
V
-V
IN
OUT
V
OUT
(1)
Iout
Vin ´ D
=
+
η ´ (1 - D)
2 ´ f ´ L
where
•
•
•
•
D = Duty Cycle in Boost mode
f = Converter switching frequency
L = Inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.9 as an assumption)
(2)
NOTE
The calculation must be done for the minimum input voltage in boost mode.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It is recommended to choose an inductor with a saturation current 20% higher
than the value calculated using Equation 2. Table 4 lists the possible inductors.
Table 4. List of Recommended Inductors
(1)
INDUCTOR
VALUE [µH]
SATURATION CURRENT
[A]
DCR [mΩ]
PART NUMBER
MANUFACTURER
0.47
5.4
7.6
XFL4015-471ME
Coilcraft
4x4x2
0.47
5.5
26
DFE201612E
Toko
2.0 x 1.6 x 1.2
(1)
SIZE (LxWxH mm)
See Third-party Products Disclaimer.
10.2.2.3
Output Capacitor Selection
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and PGND pins of the IC. The recommended nominal output capacitor value is a single 22 µF for the
TPS63805 and 2x47 µF for the TPS63806 for all programmed output voltages ≤ 3.6 V. Above that voltage, 2x22
µF for the TPS63805 and 3x47 µF for the TPS63806 capacitors are recommended.
It is important that the effective capacitance is given according to the recommended value in Recommended
Operating Conditions. In general, consider DC bias effects resulting in less effective capacitance. The choice of
the output capacitance is mainly a trade-off between size and transient behavior since higher capacitance
reduces transient response overshoot and undershoot and increases transient response time. Table 5 lists
possible output capacitors.
There is no upper limit for the output capacitance value.
Table 5. List of Recommended Capacitors (1)
CAPACITOR
[µF]
VOLTAGE RATING [V]
ESR [mΩ]
22
6.3
22
6.3
22
10
(1)
PART NUMBER
MANUFACTURER
SIZE
(METRIC)
10
GRM188R60J226MEA0
Murata
0603 (1608)
10
GRM187R61A226ME15
Murata
0603 (1608)
40
GRM188R61A226ME15
Murata
0603 (1608)
See Third-party Products Disclaimer.
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Table 5. List of Recommended Capacitors() (continued)
CAPACITOR
[µF]
VOLTAGE RATING [V]
ESR [mΩ]
PART NUMBER
MANUFACTURER
SIZE
(METRIC)
22
10
10
GRM187R60J226ME15
Murata
0603 (1608)
47
6.3
43
GRM188R60J476ME15
Murata
0603 (1608)
47
6.3
43
GRM219R60J476ME44
Murata
0805 (2012)
10.2.2.4
Input Capacitor Selection
A 10 µF input capacitor is recommended to improve line transient behavior of the regulator and EMI behavior of
the total power supply circuit. An X5R or X7R ceramic capacitor placed as close as possible to the VIN and
PGND pins of the IC is recommended. This capacitance can be increased without limit. If the input supply is
located more than a few inches from the TPS63805 and TPS63806 converter, additional bulk capacitance can be
required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 µF
is a typical choice.
Table 6. List of Recommended Capacitors (1)
CAPACITOR
[µF]
VOLTAGE RATING [V]
ESR [mΩ]
10
6.3
10
10
22
6.3
(1)
PART NUMBER
MANUFACTURER
SIZE
(METRIC)
10
GRM188R60J106ME84
Murata
0603 (1608)
40
GRM188R61A106ME69
Murata
0603 (1608)
10
GRM188R60J226MEA0
Murata
0603 (1608)
See Third-party Products Disclaimer.
10.2.2.5 Setting The Output Voltage
The output voltage is set by an external resistor divider. The resistor divider must be connected between VOUT,
FB, and GND. The feedback voltage is 500 mV nominal. The low-side resistor R2 (between FB and GND) must
not exceed 100 kΩ. The high-side resistor (between FB and VOUT) R1 is calculated by Equation 3.
æV
ö
R1 = R2 × ç OUT - 1÷
è VFB
ø
where
•
VFB = 500 mV
(3)
Table 7. Resistor Selection for Typ. Voltages
VO [V]
R1 [kΩ]
R2 [kΩ]
2.5
365
91
3.3
511
91
3.6
562
91
5
806
91
10.2.3 Application Curves
Table 8. Components for Application Characteristic Curves
(1)
REFERENCE
DESCRIPTION
PART NUMBER
MANUFACTURER
L1
0.47µH, 4 mm x 4 mm x 1.5 mm, 5.4 A,
7.6 mΩ
XFL4015-471ME
Coilcraft
C1
10 µF, 0603, Ceramic Capacitor, ±20%,
6.3 V
GRM188R60J106ME84
Murata
C2
TPS63805 1x 22 µF, 0603, Ceramic
Capacitor, ±20%, 10 V
GRM188R61A226ME15
Murata
TPS63805, VO ≤ 3.6 V
C2
TPS63806 2x 47 µF, 0603, Ceramic
Capacitor, ±20%, 6.3 V
GRM188R60J476ME15
Murata
TPS63806, VO ≤ 3.6 V
(1)
See Third-party Products Disclaimer.
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Table 8. Components for Application Characteristic Curves
()
(continued)
REFERENCE
DESCRIPTION
PART NUMBER
MANUFACTURER
COMMENT
C2
TPS63805 2x 22 µF, 0603, Ceramic
Capacitor, ±20%, 10 V
GRM188R61A226ME15
Murata
TPS63805, VO > 3.6 V
C2
TPS63806 3x 47 µF, 0603, Ceramic
Capacitor, ±20%, 6.3 V
GRM188R60J476ME15
Murata
TPS63806, VO > 3.6 V
R1
511 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
VO = 3.3 V
R1
562 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
VO = 3.6 V
R1
806 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
VO = 5 V
R2
91 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
R3
100 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
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Table 9. Typical Characteristics Curves
PARAMETER
CONDITIONS
FIGURE
Output Current Capability
Typical Output Current Capability versus Input Voltage
VO = 3.3 V, TPS63805
Figure 16
Typical Output Current Capability versus Input Voltage
VO = 3.3 V, TPS63806
Figure 17
Typical Inductor Switching Frequency versus Input
Voltage
IO = 0 A, MODE = High
Figure 18
Typical Inductor Burst Frequency versus Output Current
VO = 3.3 V
Figure 19
Efficiency versus Output Current (PFM/PWM)
VI = 2.5 V to 4.2 V, VO = 3.3 V, MODE =
Low
Figure 20
Efficiency versus Output Current (PWM only)
VI = 2.5 V to 4.2 V, VO = 3.3 V, MODE =
High
Figure 21
Efficiency versus Output Current (PFM/PWM)
VI = 1.8 V to 5 V, VO = 3.3 V, MODE = Low
Figure 22
Efficiency versus Output Current (PWM only)
VI = 1.8 V to 5 V, VO = 3.3 V, MODE = High
Figure 23
Efficiency versus. Input Voltage (PFM/PWM)
VO = 3.3 V, MODE = Low
Figure 24
Efficiency versus Input Voltage (PWM only)
IO = 1 A, MODE = High
Figure 25
Efficiency versus Output Current (PFM/PWM)
VI = 2.5 V to 4.2, VO = 3.3 V, MODE = Low
Figure 26
Efficiency versus Output Current (PWM only)
VI = 2.5 V to 4.2 , VO = 3.3 V, MODE = High
Figure 27
Efficiency versus Output Current (PFM/PWM)
VI = 1.8 V to 5, VO = 3.3 V, MODE = Low
Figure 28
Efficiency versus Output Current (PWM only)
VI = 2.5 V to 5, VO = 3.3 V, MODE = High
Figure 31
Efficiency versus Input Voltage (PFM/PWM)
VO = 3.3 V, MODE = Low
Figure 30
Efficiency versus Input Voltage (PWM only)
IO = 1 A, MODE = High
Figure 31
Load Regulation, PWM Operation
VO = 3.3 V, MODE = High
Figure 32
Load Regulation, PFM/PWM Operation
VO = 3.3 V, MODE = Low
Figure 33
Line Regulation, PWM Operation
IO = 1 A, MODE = High
Figure 34
Line Regulation, PFM/PWM Operation
IO = 1 A, MODE = Low
Figure 35
Load Regulation, PWM Operation
VO = 3.3 V, MODE = High
Figure 36
Load Regulation, PFM/PWM Operation
VO = 3.3 V, MODE = Low
Figure 37
Line Regulation, PWM Operation
IO = 1 A, MODE = High
Figure 38
Line Regulation, PFM/PWM Operation
IO = 1 A, MODE = Low
Figure 39
Switching Waveforms, PFM Boost Operation
VI = 2.3 V, VO = 3.3 V, MODE = Low
Figure 40
Switching Waveforms, PFM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, MODE = Low
Figure 41
Switching Waveforms, PFM Buck Operation
VI = 4.3 V, VO = 3.3 V, MODE = Low
Figure 42
Switching Waveforms, PWM Boost Operation
VI = 2.3 V, VO = 3.3 V, MODE = High
Figure 43
Switching Waveforms, PWM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, MODE = High
Figure 44
Switching Waveforms, PWM Buck Operation
VI = 4.3 V, VO = 3.3 V, MODE = High
Figure 45
Load Transient, PFM/PWM Boost Operation
VI = 2.5 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = Low
Figure 46
Load Transient, PFM/PWM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = Low
Figure 47
Load Transient, PFM/PWM Buck Operation
VI = 4.2 V, VO = 3.3V, Load = 100 mA to 1A,
MODE = Low
Figure 48
Load Transient, PWM Boost Operation
VI = 2.5 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = High
Figure 49
Switching Frequency (TPS63805, TPS63806)
Efficiency (TPS63805)
Efficiency (TPS63806)
Regulation Accuracy (TPS63805)
Regulation Accuracy (TPS63806)
Switching Waveforms (TPS63805, TPS63806)
Transient Performance (TPS63805)
22
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Table 9. Typical Characteristics Curves (continued)
PARAMETER
CONDITIONS
FIGURE
Load Transient, PWM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = High
Figure 50
Load Transient, PWM Buck Operation
VI = 4.2 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = High
Figure 51
Line Transient, PWM Operation
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 0.5
A , MODE = Low
Figure 52
Line Transient, PWM Operation
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 1 A ,
MODE = Low
Figure 53
Line Transient, PWM Operation
VI = 3 V to 3.6 V, VO = 3.3 V, Load = 0.5 A ,
MODE = Low
Figure 54
Load Transient, PFM/PWM Boost Operation
VI = 2.3 V, VO = 3.3 V, Load = 25% to 75%,
MODE = Low
Figure 55
Load Transient, PFM/PWM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, Load = 25% to 75%,
MODE = Low
Figure 56
Load Transient, PFM/PWM Buck Operation
VI = 4.3 V, VO = 3.3 V, Load = 25% to 75%,
MODE = Low
Figure 57
Load Transient, PWM Boost Operation
VI = 2.3 V, VO = 3.3 V, Load = 25% to 75%,
MODE = High
Figure 58
Load Transient, PWM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, Load = 25% to 75%,
MODE = High
Figure 59
Load Transient, PWM Buck Operation
VI = 4.3 V, VO = 3.3 V, Load = 25% to 75%,
MODE = High
Figure 60
Line Transient, PWM Operation
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 0.5
A , MODE = Low
Figure 61
Line Transient, PWM Operation
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 1 A ,
MODE = Low
Figure 62
Line Transient, PWM Operation
VI = 3 V to 3.6 V, VO = 3.3 V, Load = 0.5 A ,
MODE = Low
Figure 63
Pulsed load, PWM Operation
VI = 2.8 V, VO = 3.3 V, Load = 50 mA to 5 A,
with 1 MHz and 50% duty cycle, tr = 120 ns,
tf = 60 ns, MODE = High
Figure 64
Pulsed load, PWM Operation
VI = 3.3 V, VO = 3.3 V, Load = 50 mA to 5 A,
with 1 MHz and 50% duty cycle, tr = 120 ns,
tf = 60 ns, MODE = High
Figure 65
Pulsed load, PWM Operation
VI = 4.2 V, VO = 3.3 V, Load = 50 mA to 5 A,
with 1 MHz and 50% duty cycle, tr = 120 ns
tf = 60 ns, MODE = High
Figure 66
Start-up Behavior from Rising Enable, PFM Operation
VI = 2.2 V, VO = 3.3 V, Load = 10 mA,
MODE = Low
Figure 67
Start-up Behavior from Rising Enable, PWM Operation
VI = 2.2 V, VO = 3.3 V, Load = 10 mA,
MODE = High
Figure 68
Transient Performance (TPS63806)
Start-up (TPS63805, TPS63806)
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4.5
4.5
4.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
VO = 3.3 V
VO = 3.6 V
VO = 5 V
0.5
0.0
1.3
1.8
2.3
2.8
3.3
3.8
Input Voltage (V)
MODE = High
4.3
4.8
3.5
3.0
2.5
2.0
1.5
1.0
VO = 3.3 V
VO = 3.6 V
VO = 5 V
0.5
0.0
1.3
5.3
1.8
2.3
2.8
3.3
3.8
Input Voltage (V)
D002
TPS63805
MODE = High
4.3
4.8
5.3
D003
TPS63806
Figure 16. Typical Output Current Capability versus Input
Voltage
Figure 17. Typical Output Current Capability versus Input
Voltage
3.0
1M
2.5
PFM Burst Frequency (Hz)
Switching Frequency (MHz)
Maximum Output Current (A)
Maximum Output Current (A)
SLVSDS9C – JULY 2018 – REVISED OCTOBER 2019
2.0
1.5
1.0
0.5
2.5
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
2.7
2.9
IO=0A
3.1
3.3
3.5
3.7
Input Voltage (V)
3.9
4.1
100k
10k
VI = 2.5 V
VI = 3.6 V
VI = 4.8 V
1k
1m
4.3
10m
100m
Output Current (A)
D007
MODE = High
VI rising
VO = 3.6 V
Figure 18. Typical Inductor Switching Frequency versus
Input Voltage
D018
MODE = Low
Figure 19. Typical Inductor Burst Frequency versus
Output Current
100
100
90
80
90
Efficiency (%)
Efficiency (%)
70
80
60
50
40
30
70
20
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
60
100P
VO = 3.3 V
1m
10m
100m
Output Current (A)
MODE = High
1
2
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0
1m
10m
D019
TPS63805
Figure 20. Efficiency versus Output Current (PFM/PWM)
24
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
10
VO = 3.3 V
100m
Output Current (A)
MODE = Low
1
2
D020
TPS63805
Figure 21. Efficiency versus Output Current (PWM Only)
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100
100
90
80
70
Efficiency (%)
Efficiency (%)
90
80
60
50
40
30
70
20
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
60
100P
1m
VO = 3.3 V
10m
100m
Output Current (A)
MODE = High
1
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
10
0
1m
2
10m
D021
TPS63805
VO = 3.3 V
Figure 22. Efficiency versus Output Current (PFM/PWM)
100m
Output Current (A)
MODE = Low
1
2
D022
TPS63805
Figure 23. Efficiency versus Input Voltage (PWM Only)
100
100
90
Efficiency (%)
Efficiency (%)
90
80
70
IO = 100 PA
IO = 10 mA
IO = 100 mA
IO = 1 A
IO = 1.5 A
60
50
2.5
2.9
VO = 3.3 V
3.3
Input Voltage (V)
3.7
80
70
60
1.8
4.1
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
2.3
2.8
3.3
3.8
4.3
Input Voltage (V)
D023
MODE = High
TPS63805
IO = 1 A
Figure 24. Efficiency versus Input Voltage (PFM/PWM)
MODE = Low
4.8
5.3
D024
TPS63805
Figure 25. Efficiency versus Input Voltage (PWM Only)
100
100
90
80
90
Efficiency (%)
Efficiency (%)
70
80
60
50
40
30
70
20
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
60
100P
VO = 3.3 V
1m
10m
100m
Output Current (A)
MODE = High
1
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
10
2.5
0
1m
D008
TPS63806
Figure 26. Efficiency versus Output Current (PFM/PWM)
VO = 3.3 V
10m
100m
Output Current (A)
MODE = Low
1
2.5
D013
TPS63806
Figure 27. Efficiency versus Output Current (PWM Only)
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100
100
90
80
90
Efficiency (%)
Efficiency (%)
70
80
60
50
40
30
70
20
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
60
100P
1m
VO = 3.3 V
10m
100m
Output Current (A)
1
0
1m
2.5
MODE = High
TPS63806
VO = 3.3 V
MODE = Low
1
2.5
D010
TPS63806
100
90
90
Efficiency (%)
Efficiency (%)
100m
Output Current (A)
Figure 29. Efficiency versus Input Voltage (PWM Only)
100
80
70
IO = 100 PA
IO = 10 mA
IO = 100 mA
IO = 1 A
IO = 2 A
60
50
2.5
2.9
VO = 3.3 V
3.3
Input Voltage (V)
MODE = High
3.7
80
70
60
1.8
4.1
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
2.3
2.8
D011
TPS63806
IO = 1 A
Figure 30. Efficiency versus Input Voltage (PFM/PWM)
3.3
3.8
4.3
Input Voltage (V)
MODE = Low
4.8
5.3
D012
TPS63806
Figure 31. Efficiency versus Input Voltage (PWM Only)
0.2
1.5
Output Voltage Regulation (%)
Output Voltage Regulation (%)
10m
D009
Figure 28. Efficiency versus Output Current (PFM/PWM)
0.1
0.0
-0.1
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
-0.2
-0.3
1.0
0.5
0.0
-0.5
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
-1.0
-1.5
0
0.5
VO = 3.3 V
1.0
Output Current (A)
MODE = High
1.5
2.0
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0.5
D026
TPS63805
Figure 32. Load Regulation (PWM Only)
26
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
10
VO = 3.3 V
1.0
Output Current (A)
MODE = Low
1.5
2.0
D027
TPS63805
Figure 33. Load Regulation (PFM/PWM)
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0.2
0.2
Output Voltage Regulation (%)
Output Voltage Regulation (%)
0.3
0.1
0.0
-0.1
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-0.2
-0.3
2.5
2.7
2.9
3.1
IO = 1 A
3.3
3.5
3.7
Input Voltage (V)
3.9
4.1
0.1
0.0
-0.1
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-0.2
2.5
4.3
MODE = Low
TPS63805
3.1
0.2
0.2
0.1
0.1
0.0
-0.1
-0.2
VI = 2.8 V
VI = 3.6 V
VI = 4.2 V
-0.3
3.3
3.5
3.7
Input Voltage (V)
3.9
4.1
4.3
D029
MODE = High
TPS63805
Figure 35. Line Regulation (PFM/PWM)
Output Voltage Regulation (%)
Output Voltage Regulation (%)
2.9
IO = 1 A
Figure 34. Line Regulation (PWM Only)
-0.4
0.0
-0.1
-0.2
VI = 2.8 V
VI = 3.6 V
VI = 4.2 V
-0.3
-0.4
0
0.5
1.0
1.5
Output Current (A)
VO = 3.3 V
2.0
2.5
0
MODE = High
TPS63806
1.0
1.5
Output Current (A)
VO = 3.3 V
2.0
2.5
D015
MODE = Low
TPS63806
Figure 37. Load Regulation (PFM/PWM)
0.2
0.2
Output Voltage Regulation (%)
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
0.1
0.0
-0.1
-0.2
2.5
0.5
D014
Figure 36. Load Regulation (PWM Only)
Output Voltage Regulation (%)
2.7
D028
2.7
IO = 1 A
2.9
3.1
3.3
3.5
3.7
Input Voltage (V)
3.9
4.1
4.3
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
0.1
0.0
-0.1
-0.2
2.5
2.7
2.9
D016
MODE = Low
TPS63806
Figure 38. Line Regulation (PWM Only)
IO = 1 A
3.1
3.3
3.5
3.7
Input Voltage (V)
MODE = High
3.9
4.1
4.3
D017
TPS63806
Figure 39. Line Regulation (PFM/PWM)
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VI = 2.3 V,
VO = 3.3 V
MODE = Low
www.ti.com
IO = 40 mA
Figure 40. Switching Waveforms, PFM Boost Operation
VI = 4.2 V,
VO = 3.3 V
MODE = Low
IO = 40 mA
Figure 42. Switching Waveforms, PFM Buck Operation
VI = 3.3 V,
VO = 3.3 V
MODE = Low
IO = 2 A
Figure 44. Switching Waveforms, PWM Buck-Boost
Operation
28
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VI = 3.3 V,
VO = 3.3 V
MODE = Low
IO = 40 mA
Figure 41. Switching Waveforms, PFM Buck-Boost
Operation
VI = 2.3 V,
VO = 3.3 V
MODE = Low
IO = 2 A
Figure 43. Switching Waveforms, PWM Boost Operation
VI = 4.2 V,
VO = 3.3 V
MODE = Low
IO = 2 A
Figure 45. Switching Waveforms, PWM Buck Operation
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VI = 2.5 V,
VO = 3.3 V
SLVSDS9C – JULY 2018 – REVISED OCTOBER 2019
IO from 100 mA to
1A
tr = 1 µs, tf = 1 µs
TPS63805
MODE = Low
VI = 3.3 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
TPS63805
MODE = Low
Figure 46. Load Transient, PFM/PWM Boost Operation
Figure 47. Load Transient, PFM/PWM Buck-Boost
Operation
VI = 5 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
TPS63805
MODE = Low
Figure 48. Load Transient, PFM/PWM Buck Operation
VI = 3.3 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
TPS63805
MODE = High
Figure 50. Load Transient, PWM Buck-Boost Operation
VI = 2.5 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
TPS63805
MODE = High
Figure 49. Load Transient, PWM Boost Operation
VI = 5 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
TPS63805
MODE = High
Figure 51. Load Transient, PWM Buck Operation
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IO = 0.5 A
VI from 2.2
V to 4.2 V
tr =1 µs, tf =
1 µs
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TPS63805
MODE =
High
Figure 52. Line Transient, PWM Operation
IO = 0.5 A
VI from 3 V to
3.6 V
tr = 1 µs, tf = 1
µs
TPS63805
MODE = High
Figure 54. Line Transient, PWM Operation
VI = 3.3 V,
VO = 3.3 V
IO from 100 mA
to 2 A
tr = 1 µs, tf = 1
µs
TPS63806
MODE = Low
Figure 56. Load Transient, PFM/PWM Buck-Boost
Operation
30
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VI from 2.2 V to
4.2 V
tr = 1 µs, tf = 1
µs
IO = 1 A
TPS63805
MODE = High
Figure 53. Line Transient, PWM Operation
IO from 100 mA
to 2 A
tr = 1 µs, tf = 1
µs
VI = 2.8 V,
VO = 3.3 V
TPS63806
MODE = Low
Figure 55. Load Transient, PFM/PWM Boost Operation
VI = 4.2 V,
VO = 3.3 V
IO from 100 mA
to 2 A
tr = 1 µs, tf = 1
µs
TPS63806
MODE = Low
Figure 57. Load Transient, PFM/PWM Buck Operation
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VI = 2.8 V,
VO = 3.3 V
IO from 100 mA
to 2 A
tr = 1 µs, tf = 1
µs
TPS63806
MODE = High
VI = 3.3 V,
VO = 3.3 V
IO 100 mA to 2 A
tr = tf = 1 µs
TPS63806
MODE = High
Figure 59. Load Transient, PWM Buck-Boost Operation
Figure 58. Load Transient, PWM Boost Operation
VI = 4.2 V,
VO = 3.3 V
IO 100 mA to 2
A
tr = tf = 1 µs
TPS63806
MODE = High
IO = 1 A
VI 2.2 V to 4.2 V
tr = tf = 1 µs
TPS63806
MODE = High
Figure 61. Line Transient, PWM Operation
Figure 60. Load Transient, PWM Buck Operation
IO = 2 A
VI 2.2 V to 4.2 V
tr = tf = 1 µs
TPS63806
MODE = High
Figure 62. Line Transient, PWM Operation
IO = 1 A
VI 3.0 V to 3.6 V
tr = tf = 1 µs
TPS63806
MODE = High
Figure 63. Line Transient, PWM Operation
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VI = 2.8 V,
VO = 3.3 V
IO 50 mA to 5 A
with 1 MHz and
50% duty cycle tr
= 120 ns, tf = 60
ns
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TPS63806
MODE = High
Figure 64. Pulsed Load, PWM Operation
VI = 4.2 V,
VO = 3.3 V
IO 50 mA to 5 A
with 1 MHz and
50% duty cycle tr
= 120 ns, tf = 60
ns
TPS63806
MODE = High
VI = 3.3 V,
VO = 3.3 V
IO 50 mA to 5 A
with 1 MHz and
50% duty cycle tr
= 120 ns, tf = 60
ns
TPS63806
MODE = High
Figure 65. Pulsed Load, PWM Operation
VI = 4.2 V,
VO = 3.3 V
MODE = Low
100 mΩ resistive
load
Figure 67. Start-up Behavior from Rising Enable, PFM
Operation
Figure 66. Pulsed Load, PWM Operation
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VI = 4.2 V,
VO = 3.3 V
MODE = High
100 mΩ resistive load
Figure 68. Start-up Behavior from Rising Enable, PWM Operation
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11 Power Supply Recommendations
The TPS63805 and TPS63806 device families have no special requirements for its input power supply. The input
power supply output current needs to be rated according to the supply voltage, output voltage, and output current
of the TPS63805 and TPS63806.
12 Layout
12.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TPS63805 and TPS63806 device.
1. Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Route wide
and direct traces to the input and output capacitor results in low trace resistance and low parasitic
inductance.
2. Separate AGND and PGND. Do not connect AGND and PGND directly at the IC. See Figure 69 as an
example.
3. Use a common-power GND, but connect AGND and PGND through a via at a different layer.
4. Use separate traces for the supply voltage of the power stage and the supply voltage of the analog stage.
5. The sense trace connected to FB is signal trace. Keep these traces away from L1 and L2 nodes.
12.2 Layout Example
Figure 69. TPS63805 and TPS63806 Layout
34
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SLVSDS9C – JULY 2018 – REVISED OCTOBER 2019
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.1.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63805 device with the WEBENCH® Power Designer. Click
here to create a custom design using the TPS63806 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.1.3 Development Support
QFN/SON Package FAQs
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 10. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS63805
Click here
Click here
Click here
Click here
Click here
TPS63806
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
Copyright © 2018–2019, Texas Instruments Incorporated
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TPS63805, TPS63806
SLVSDS9C – JULY 2018 – REVISED OCTOBER 2019
www.ti.com
13.5 Trademarks (continued)
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63805 TPS63806
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS63805YFFR
ACTIVE
DSBGA
YFF
15
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TPS63805
TPS63805YFFT
ACTIVE
DSBGA
YFF
15
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TPS63805
TPS63806YFFR
ACTIVE
DSBGA
YFF
15
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TPS63806
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS63805YFFR
DSBGA
YFF
15
3000
180.0
8.4
TPS63805YFFT
DSBGA
YFF
15
250
180.0
TPS63806YFFR
DSBGA
YFF
15
3000
180.0
1.5
2.42
0.75
4.0
8.0
Q1
8.4
1.5
2.42
0.75
4.0
8.0
Q1
8.4
1.5
2.42
0.75
4.0
8.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS63805YFFR
DSBGA
YFF
15
3000
182.0
182.0
20.0
TPS63805YFFT
DSBGA
YFF
15
250
182.0
182.0
20.0
TPS63806YFFR
DSBGA
YFF
15
3000
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0015
DSBGA - 0.625 mm max height
SCALE 6.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.30
0.12
BALL TYP
0.05 C
0.8 TYP
SYMM
E
D
1.6
TYP
D: Max = 2.285 mm, Min =2.225 mm
SYMM
C
E: Max = 1.374 mm, Min =1.314 mm
B
0.4 TYP
A
15X
0.015
0.3
0.2
C A B
1
2
3
0.4
TYP
4219378/A 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
15X ( 0.23)
2
1
3
A
(0.4) TYP
B
SYMM
C
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
( 0.23)
METAL
SOLDER MASK
OPENING
0.05 MAX
EXPOSED
METAL
0.05 MIN
METAL UNDER
SOLDER MASK
EXPOSED
METAL
( 0.23)
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219378/A 04/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
15X ( 0.25)
1
2
3
A
(0.4) TYP
B
METAL
TYP
SYMM
C
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219378/A 04/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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