Texas Instruments | TPS737-Q1 1-A Low-Dropout Regulator With Reverse Current Protection (Rev. B) | Datasheet | Texas Instruments TPS737-Q1 1-A Low-Dropout Regulator With Reverse Current Protection (Rev. B) Datasheet

Texas Instruments TPS737-Q1 1-A Low-Dropout Regulator With Reverse Current Protection (Rev. B) Datasheet
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TPS737-Q1
SBVS123B – DECEMBER 2008 – REVISED SEPTEMBER 2019
TPS737-Q1 1-A Low-Dropout Regulator With Reverse Current Protection
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4A
Stable with 1-µF or larger ceramic output
capacitor
Input voltage range: 2.2 V to 5.5 V
Ultra-low dropout voltage: 130 mV (typical) at 1 A
Excellent load transient response, even with only
1-µF output capacitor
NMOS topology delivers low reverse leakage
current
1% initial accuracy
3% overall accuracy over line, load, and
temperature
Less than 20-nA (typical) quiescent current in
shutdown mode
Thermal shutdown and current limit for fault
protection
Available in multiple output voltage versions
Point of load regulation for DSPs, FPGAs, ASICs,
and microprocessors
Post-regulation for switching supplies
Portable and battery-powered equipment
•
•
3 Description
The TPS737xx-Q1 family of linear low-dropout (LDO)
voltage regulators uses an NMOS pass element in a
voltage-follower configuration. This topology is
relatively insensitive to output capacitor value and
ESR, allowing a wide variety of load configurations.
Load transient response is excellent, even with a
small 1-µF ceramic output capacitor. The NMOS
topology also allows very low dropout.
The TPS737xx-Q1 family uses an advanced BiCMOS
process to yield high precision while delivering very
low dropout voltages and low ground pin current.
Current consumption, when not enabled, is under
20 nA and ideal for portable applications. These
devices are protected by thermal shutdown and
foldback current limit.
Device Information(1)
PART NUMBER
TPS737-Q1
PACKAGE
VSON (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
VIN
IN
OUT
VOUT
TPS737xx
EN
GND
ON
OFF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS737-Q1
SBVS123B – DECEMBER 2008 – REVISED SEPTEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
12.1 Package Mounting ................................................ 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2016) to Revision B
Page
•
Changed device temperature grade AEC-Q100 Features bullet............................................................................................ 1
•
Deleted sub-bullets from Features output voltage version bullet .......................................................................................... 1
Changes from Original (December 2008) to Revision A
Page
•
Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table,
Recommended Operating Conditions table, Thermal Information table, Detailed Description section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Deleted Ordering Information Table; see POA at the end of the datasheet .......................................................................... 1
2
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SBVS123B – DECEMBER 2008 – REVISED SEPTEMBER 2019
5 Pin Configuration and Functions
DRB Package
8-Pin VSON
Top View
OUT
1
8
IN
NC
2
7
NC
FB,NR
3
6
NC
GND
4
5
EN
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
5
I
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. See Enable Pin and Shutdown for more details. EN must not be left floating and can be
connected to IN if not used.
FB
3
I
Adjustable voltage version only. This is the input to the control loop error amplifier, and it is used to set
the output voltage of the device.
GND
4, Pad
G
Ground
IN
8
I
Unregulated input supply
NR
3
—
Fixed voltage versions only. Connecting an external capacitor to this pin bypasses noise generated by
the internal bandgap, reducing output noise to very low levels.
OUT
1
O
Regulator output. A 1-µF or larger capacitor of any type is required for stability.
2, 6, 7
—
No internal connection
NC
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input supply voltage
–0.3
6
V
Enable voltage
–0.3
6
V
Output voltage
–0.3
5.5
V
–0.3
6
V
Input voltage
NR or FB pin
Peak output current
Internally limited
Output short-circuit duration
Indefinite
Junction temperature range, TJ
–55
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
±2000
Charged-device model (CDM), per AEC Q100-011
UNIT
V
±500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
Input supply voltage
IOUT
Output current
TJ
Operating junction temperature
MIN
MAX
2.2
5.5
UNIT
V
0
1
A
–40
125
°C
6.4 Thermal Information
TPS737xx-Q1
THERMAL METRIC (1)
DRB (VSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
52.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
59.4
°C/W
RθJB
Junction-to-board thermal resistance
19.3
°C/W
ψJT
Junction-to-top characterization parameter
2
°C/W
ψJB
Junction-to-board characterization parameter
19.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
11.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating temperature range (TJ = –40°C to 125°C), VIN = ( VOUT(nom) + 1 V ) (1), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF
(unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range (1) (2)
VFB
Internal reference (TPS73701)
VOUT
Accuracy
(1) (4)
TJ = 25°C
Line regulation (1)
ΔVOUT% / ΔIOUT Load regulation
1.192
V
V
TJ = 25°C
–1
1
5.36 V < VIN < 5.5 V, VOUT = 5.08 V,
10 mA < IOUT < 800 mA,
–40°C < TJ < 85°C, TPS73701
–2
2
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V
±0.5
0.002
10 mA ≤ IOUT ≤ 1 A
0.0005
IOUT = 1 A
130
ZO(DO)
Output impedance in dropout
2.2 V ≤ VIN ≤ VOUT + VDO
0.25
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
ISC
Short-circuit current
VOUT = 0 V
IREV
Reverse leakage current (6)(–IIN)
mV
Ω
2.2
A
0.1
µA
IOUT = 10 mA (IQ)
400
Shutdown current (IGND)
IFB
FB pin current (TPS73701)
PSRR
Power-supply rejection ratio
(ripple rejection)
VN
Output noise voltage
BW = 10 Hz to 100 kHz
COUT = 10 µF
tSTR
Startup time
VOUT = 3 V, RL = 30 Ω, COUT = 1 µF
VEN(HI)
EN pin high (enabled)
VEN(LO)
EN pin low (shutdown)
IEN(HI)
EN pin current (enabled)
(3)
(4)
(5)
(6)
500
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
ISHDN
(1)
(2)
%/mA
mA
GND pin current
Operating junction temperature
1.6
%/V
450
IGND
TJ
1.05
%
3
0.01
1 mA ≤ IOUT ≤ 1 A
Dropout voltage (5)
(VIN = VOUT(nom) – 0.1 V)
Thermal shutdown temperature
V
1.216
VDO
TSD
UNIT
5.5
5.5 – VDO
–3
1.2
MAX
VFB
Over VIN, IOUT, and VOUT + 0.5 V ≤ VIN ≤ 5.5 V,
temperature
10 mA ≤ IOUT ≤ 1 A
ΔVOUT% / ΔVIN
TYP
2.2
Output voltage range (TPS73701) (3)
Nominal
MIN
IOUT = 1 A
µA
1300
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5 V
20
0.1
f = 100 Hz, IOUT = 1 A
58
f = 10 kHz, IOUT = 1 A
37
nA
0.6
µA
dB
27 × VOUT
µVRMS
600
µs
1.7
VIN
V
0
0.5
V
VEN = 5.5 V
20
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
–40
nA
°C
125
°C
Minimum VIN = VOUT + VDO or 2.2 V, whichever is greater.
For VOUT(nom) < 1.6 V, when VIN ≤ 1.6 V, the output locks to VIN and may result in an overvoltage condition on the output. To avoid this
situation, disable the device before powering down VIN.
TPS73701 is tested at VOUT = 1.2 V.
Tolerance of external resistors not included in this specification.
VDO is not measured for fixed output versions with VOUT(nom) < 2.3 V, because minimum VIN = 2.2 V.
Fixed-voltage versions only; see the Reverse Current section for more information.
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6.6 Typical Characteristics
TJ = 25°C, VIN = ( VOUT(nom) + 1 V ), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
0.5
Referred to VIN = VOUT + 1.0V at IOUT = 10mA
-40°C
+25°C
+125°C
0.2
0.1
0
-0.1
-0.2
Change in VOUT (%)
0.15
0.3
Change in VOUT (%)
0.20
Referred to IOUT = 10mA
0.4
-0.3
0.10
0
-0.05
-40°C
-0.10
-0.15
-0.4
-0.5
-0.20
0
100 200
300 400
500 600 700
800 900 1000
0
0.5
1.0
IOUT (mA)
2.0
2.5
3.0
3.5
4.0
4.5
Figure 2. Line Regulation
200
VOUT = 2.5V
180
1.5
VIN - VOUT (V)
Figure 1. Load Regulation
200
180
160
160
+125°C
+25°C
140
120
140
VDO (mV)
VDO (mV)
+25°C
+125°C
0.05
100
80
120
100
80
60
60
-40°C
40
40
20
20
0
0
0
100 200 300
400 500
600 700
800 900 1000
-50
-25
IOUT (mA)
0
25
50
75
100
125
150
Temperature (°C)
Figure 3. Dropout Voltage vs Output Current
Figure 4. Dropout Voltage vs Temperature
30
18
IOUT = 10mA
16
IOUT = 10mA
25
Percent of Units (%)
Percent of Units (%)
14
20
15
10
12
10
8
6
4
5
2
6
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/°C)
Figure 5. Output Voltage Histogram
Figure 6. Dropout Voltage Drift Histogram
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Typical Characteristics (continued)
TJ = 25°C, VIN = ( VOUT(nom) + 1 V ), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
3000
2500
IOUT = 1A
VIN = 5.0V
2500
2000
IGND (mA)
VIN = 5.0V
IGND (mA)
1500
VIN = 3.3V
2000
VIN = 3.3V
1500
1000
1000
VIN = 2.2V
VIN = 2.2V
500
500
0
0
0
200
400
600
800
-50
1000
-25
0
50
75
100
2.0
VENABLE = 0.5V
VIN = VOUT + 0.5V
1.8
ICL
Current Limit (mA)
1.6
0.1
1.4
1.2
1.0
0.8
0.6
ISC
0.4
0.2
0.01
-50
VOUT = 3.3V
0
-25
0
25
50
75
100
0
125
0.5
1.0
1.5
2.0
2.5
3.0
Temperature (°C)
VOUT (V)
Figure 9. Ground Pin Current In Shutdown vs Temperature
Figure 10. Current Limit vs VOUT (Foldback)
2.0
2.0
1.9
1.9
1.8
1.8
1.7
1.7
Current Limit (A)
Current Limit (A)
125
Figure 8. Ground Pin Current vs Temperature
Figure 7. Ground Pin Current vs Output Current
1
IGND (mA)
25
Temperature (°C)
IOUT (mA)
1.6
1.5
1.4
1.3
VOUT = 1.2V
1.6
1.5
1.4
1.3
1.2
1.2
1.1
1.1
1.0
3.5
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
-25
0
25
50
75
100
VIN (V)
Temperature (°C)
Figure 11. Current Limit vs VIN
Figure 12. Current Limit vs Temperature
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Typical Characteristics (continued)
TJ = 25°C, VIN = ( VOUT(nom) + 1 V ), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
90
40
IOUT = 100mA
COUT = Any
70
IOUT = 1mA
COUT = 1mF
35
30
IOUT = 1mA
COUT = 10mF
60
50
IO = 100mA
CO = 1mF
IOUT = 1mA
COUT = Any
40
30
20
PSRR (dB)
Ripple Rejection (dB)
80
20
15
Frequency = 10kHz
COUT = 10mF
VOUT = 2.5V
IOUT = 100mA
10
IOUT = 100mA
COUT = 10mF
10
25
5
0
0
10
100
1k
10k
100k
1M
0
10M
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VIN - VOUT (V)
Frequency (Hz)
Figure 13. PSRR (Ripple Rejection) vs Frequency
Figure 14. PSRR (Ripple Rejection) vs VIN – VOUT
60
1
55
COUT = 1mF
0.1
VN (RMS)
eN (mV/ÖHz)
50
COUT = 10mF
45
40
35
VOUT = 2.5V
COUT = 0mF
R1 = 39.2kW
10Hz < Frequency < 100kHz
30
25
IOUT = 150mA
20
10p
0.01
10
100
1k
10k
100k
100p
1n
10n
CFB (F)
Frequency (Hz)
Figure 15. Noise Spectral Density
Figure 16. TPS73701 RMS Noise Voltage vs CFB
60
140
50
120
VOUT = 5.0V
VOUT = 5.0V
100
30
VN (RMS)
VN (RMS)
40
VOUT = 3.3V
20
0
0.1
8
20
CNR = 0.01mF
10Hz < Frequency < 100kHz
0
1
10
VOUT = 3.3V
60
40
VOUT = 1.5V
10
80
VOUT = 1.5V
COUT = 0mF
10Hz < Frequency < 100kHz
1p
10p
100p
1n
COUT (mF)
CNR (F)
Figure 17. RMS Noise Voltage vs COUT
Figure 18. RMS Noise Voltage vs CNR
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Typical Characteristics (continued)
TJ = 25°C, VIN = ( VOUT(nom) + 1 V ), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
CNR = 10nF
CNR = 10nF
COUT = 10mF
VOUT
200mV/div
COUT = 10mF
100mV/div
VOUT
1A
5.3V
10mA
4.3V
IOUT
VIN
10ms/div
10ms/div
Figure 19. TPS73733 Load Transient Response
Figure 20. TPS73733 Line Transient Response
RL = 20W
COUT = 10mF
VOUT
1V/div
RL = 20W
COUT = 1mF
RL = 20W
COUT = 1mF
1V/div
RL = 20W
COUT = 10mF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100ms/div
100ms/div
Figure 21. TPS73701 Turn-On Response
Figure 22. TPS73701 Turn-Off Response
10
6
VIN
5
VOUT
IENABLE (nA)
4
Volts
3
2
1
1
0.1
0
-1
0.01
-50
-2
-25
0
25
50
75
100
50ms/div
Temperature (°C)
Figure 23. TPS73701, VOUT = 3.3 V
Power-Up And Power-Down
Figure 24. IENABLE vs Temperature
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Typical Characteristics (continued)
160
160
140
140
120
120
100
100
IFB (nA)
IFB (nA)
TJ = 25°C, VIN = ( VOUT(nom) + 1 V ), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
80
80
60
60
40
40
20
20
0
-50
0
-25
25
50
75
100
125
0
−50
−25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 25. TPS73701 IFB vs Temperature
Figure 26. TPS73701 IFB vs Temperature
CFB = 10nF
R1 = 39.2kW
COUT = 10mF
100mV/div
VOUT
COUT = 10mF
100mV/div
125
VOUT = 2.5V
CFB = 10nF
VOUT
4.5V
250mA
3.5V
10mA
10
IOUT
VIN
10ms/div
5ms/div
Figure 27. TPS73701 Load Transient, Adjustable Version
Figure 28. TPS73701 Line Transient, Adjustable Version
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7 Detailed Description
7.1 Overview
The TPS737xx-Q1 belongs to a family of new generation LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints.
These features combined with an enable input make the TPS737xx-Q1 ideal for portable applications. This
regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All
versions have thermal and over-current protection, including foldback current limit.
Table 1. Standard 1% Resistor Values for Common
Output Voltages
VOUT
R1
R2
1.2 V
Short
Open
1.5 V
23.2 kΩ
95.3 kΩ
1.8 V
28.kΩ
56.2 kΩ
2.5 V
39.2 kΩ
36.5 kΩ
2.8 V
44.2 kΩ
33.2 kΩ
3V
46.4 kΩ
33.2 kΩ
3.3 V
52.3 kΩ
30.1 kΩ
7.2 Functional Block Diagrams
IN
4-MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
Current
Limit
OUT
8 kW
GND
R1
R1 + R2 = 80 kW
R2
NR
Figure 29. Fixed Voltage Version
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Functional Block Diagrams (continued)
IN
4-MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
OUT
Current
Limit
GND
8 kW
80 kW
R1
FB
R2
See Table 1 for standard resistor values.
Figure 30. Adjustable Voltage Version
7.3 Feature Description
7.3.1 Output Noise
A precision bandgap reference is used to generate the internal reference voltage (VREF). This reference is the
dominant noise source within the TPS737xx-Q1 and it generates approximately 32 µVRMS (10 Hz to 100 kHz) at
the reference output (NR). The regulator control loop adds gain to the reference noise with the same gain as the
reference voltage, so that the noise voltage of the regulator is approximately given by Equation 1.
(R + R 2 )
V
VN = 32 µVRMS ´ 1
= 32 µVRMS ´ OUT
R2
VREF
(1)
Because the value of VREF is 1.2 V, this relationship reduces to:
æ µV
ö
VN (µVRMS ) = 27 ç RMS ÷ ´ VOUT (V )
è V ø
(2)
for the case of no CNR.
An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor (CNR) is connected from NR to ground. The total noise in
the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2 for CNR = 10 nF, giving the
approximate relationship for CNR = 10 nF in Equation 3.
æ µV
VN (µVRMS ) = 8.5 ç RMS
è V
ö
÷ ´ VOUT (V)
ø
(3)
This noise reduction effect is shown in Figure 18.
The TPS737xx-Q1 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate
of the NMOS pass element above VOUT. The charge pump generates approximately 250 µV of switching noise at
approximately 4 MHz, however, charge-pump noise contribution is negligible at the output of the regulator for
most values of IOUT and COUT.
12
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Feature Description (continued)
7.3.2 Internal Current Limit
The TPS737xx-Q1 internal current limit helps protect the regulator during fault conditions. Foldback current limit
helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when
VOUT drops below 0.5 V. See Figure 10.
7.3.3 Enable Pin and Shutdown
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5 V
(maximum) turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to
shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a
regulated VOUT (see Figure 21).
When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after
VIN is removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp
times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may overshoot
upon power-up.
7.3.4 Reverse Current
The NMOS pass element of the TPS737xx-Q1 provides inherent protection against current flow from the output
of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed
from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is
not done, the pass element may be left on because of stored charge on the gate.
After the EN pin is driven low, no bias voltage is required on any pin for reverse current blocking. Reverse
current is specified as the current flowing out of the IN pin because of voltage applied on the OUT pin. There is
additional current flowing into the OUT pin as a result of the 80-kΩ internal resistor divider to ground (see
Figure 29 and Figure 30).
For the TPS73701, reverse current may flow when VFB is more than 1 V above VIN.
7.3.5 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. Junction temperature must be limited to 125°C maximum for reliable operation. To estimate the margin
of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection
is triggered; use worst-case loads and signal conditions. Thermal protection must trigger at least 35°C above the
maximum expected ambient condition of your application for good reliability. This produces a worst-case junction
temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS737xx-Q1 is designed to protect against overload conditions. It was not
intended to replace proper heatsinking. Continuously running the TPS737xx-Q1 into thermal shutdown degrades
device reliability.
7.4 Device Functional Modes
Driving the EN pin over 1.7 V turns on the regulator. Driving the EN below 0.5 V causes the regulator to enter
shutdown mode. In shutdwon, the current consumption of the device is reduced to 20 nA (typical).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS737xx-Q1 family of LDO regulators use an NMOS pass transistor to achieve ultra-low-dropout
performance, reverse current blockage, and freedom from output capacitor constraints. These features,
combined with low noise and an enable input, make the TPS737xx-Q1 ideal for portable applications.
8.2 Typical Application
VIN
IN
VOUT
OUT
TPS737xx
EN
GND
ON
OFF
Figure 31. Typical Application Circuit For Fixed-Voltage Versions
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
EN
OFF
VOUT
OUT
TPS73701
GND
R1
CFB
FB
ON
R2
VOUT =
(R1 + R2)
R2
x 1.204
Optional capacitor
reduces output noise
and improves
transient response.
Figure 32. Typical Application Circuit For Adjustable-Voltage Version
8.2.1 Design Requirements
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 32. Sample resistor values
for common output voltages are shown in Table 1.
Make the parallel combination of R1 and R2 approximately equal to 19 kΩ for best accuracy. This 19 kΩ, in
addition to the internal 8-kΩ resistor, presents the same impedance to the error amplifier as the 27-kΩ bandgap
reference output. This impedance helps compensate for leakages into the error amplifier terminals.
The TPS73701 adjustable version does not have the NR pin available. However, connecting a feedback
capacitor (CFB) from the output to the feedback pin (FB) reduces output noise and improves load transient
performance. This capacitor must be limited to 0.1 µF.
14
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Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, if input impedance is very low, it is good analog design
practice to connect a 0.1-µF to 1-µF low equivalent series resistance (ESR) capacitor across the input supply
near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients
are anticipated or the device is located several inches from the power source.
The TPS737xx-Q1 requires a 1-µF output capacitor for stability. It is designed to be stable for all available types
and values of capacitors. In applications where multiple low ESR capacitors are in parallel, ringing may occur
when the product of COUT and total ESR drops below 50 nΩF. Total ESR includes all parasitic resistances,
including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor
ESR and trace resistance meets this requirement.
8.2.2.2 Dropout Voltage
The TPS737xx-Q1 uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less
than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS(ON) of the NMOS pass element.
The TPS737xx-Q1 requires a larger voltage drop from VIN to VOUT to avoid degraded transient response for large
step changes in load current. The boundary of this transient dropout region is approximately twice the DC
dropout. Values of VIN – VOUT above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions (full-scale
instantaneous load change with (VIN – VOUT) close to DC dropout levels), the TPS737xx-Q1 can take a couple of
hundred microseconds to return to the specified regulation accuracy.
8.2.2.3 Transient Response
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without a 1-µF output capacitor. As with any regulator, the addition of additional capacitance
from the OUT pin to ground reduces undershoot magnitude but increases its duration. In the adjustable version,
the addition of a capacitor (CFB) between the OUT pin and the FB pin also improves the transient response.
The TPS737xx-Q1 does not have active pulldown when the output is overvoltage. This architecture allows for
applications that connect higher voltage sources, such as alternate power supplies, to be connected to the
output. This architecture also results in an output overshoot of several percent if the load current quickly drops to
zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load
resistor. The overshoot decays at a rate determined by the output capacitor (COUT) and the internal and external
load resistance. The rate of decay is given by Equation 4 and Equation 5.
(Fixed voltage version)
VOUT
dV
=
dT C OUT ´ 80 kW P R LOAD
(4)
(Adjustable voltage version)
VOUT
dV
=
dT C OUT ´ 80 kW P (R 1 + R 2 ) P R LOAD
(5)
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Typical Application (continued)
8.2.3 Application Curves
Figure 33. TPS737xx-Q1 Start-Up
Figure 34. TPS737xx-Q1 Shutdown
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.2 V to 5.5 V. The input voltage
range provides adequate headroom for the device to have a regulated output. This input supply must be well
regulated. If the input supply is noisy, additional input capacitors with low ESR help improve the output noise
performance.
10 Layout
10.1 Layout Guidelines
10.1.1 Improve PSRR and Noise Performance
TI recommends that the printed circuit board (PCB) be designed with separate ground planes for VIN and VOUT,
with each ground plane connected only at the GND pin of the device, to improve AC performance such as
PSRR, output noise, and transient response. In addition, the ground connection for the bypass capacitor must
connect directly to the GND pin of the device.
10.1.2 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low-K and high-K boards are shown in Thermal
Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of
plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current multiplied by the voltage drop across the output pass element (VIN to VOUT). See Equation 6.
PD = (VIN - VOUT )´ IOUT
(6)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage.
16
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10.2 Layout Example
GND PLANE
COUT
VOUT
VIN
TPS737xx-Q1
R1
CFF
1
8
3
6
4
5
CIN
NR/FB
NC
R2
EN
GND PLANE
Figure 35. Layout Diagram
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Solder Pad Recommendations for Surface-Mount Devices (SBFA015)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Package Mounting
See Solder Pad Recommendations for Surface-Mount Devices (SBFA015) for TPS737xx-Q1 solder pad footprint
recommendations.
18
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS73719QDRBRQ1
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
719Q
TPS73733QDRBRQ1
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
733Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
OTHER QUALIFIED VERSIONS OF TPS737-Q1 :
• Catalog: TPS737
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS73719QDRBRQ1
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS73733QDRBRQ1
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS73719QDRBRQ1
SON
DRB
8
3000
367.0
367.0
35.0
TPS73733QDRBRQ1
SON
DRB
8
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.5 0.1
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
(0.65)
8X
0.37
0.25
0.1
0.05
C A B
C
0.5
0.3
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31) 1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.23)
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
8X (0.31)
4X
(0.725)
8
1
(2.674)
SYMM
(1.55)
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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