Texas Instruments | TPS63802 2-A, High-efficient, Low IQ Buck-boost Converter in DFN Package (Rev. B) | Datasheet | Texas Instruments TPS63802 2-A, High-efficient, Low IQ Buck-boost Converter in DFN Package (Rev. B) Datasheet

Texas Instruments TPS63802 2-A, High-efficient, Low IQ Buck-boost Converter in DFN Package (Rev. B) Datasheet
Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
TPS63802 2-A, High-efficient, Low IQ Buck-boost Converter in DFN Package
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
Input voltage range: 1.3 V to 5.5 V
– Device input voltage > 1.8 V for start-up
Output voltage range: 1.8 V to 5.2 V (adjustable)
2-A Output current for VI ≥ 2.3 V, VO = 3.3 V
High efficiency over the entire load range
– 11-µA Operating quiescent current
– Power save mode and mode selection for
forced PWM-mode
Peak current buck-boost mode architecture
– Defined transition points between buck, buckboost, and boost operation modes
– Forward and reverse current operation
– Start-up into pre-biased outputs
Safety and robust operation features
– Integrated soft start
– Overtemperature- and overvoltage-protection
– True shutdown function with load disconnect
– Forward and backward current limit
Small solution size of 21.5 mm2
– Tiny SON/DFN package (similar to QFN)
– Small 0.47 µH inductor
– Works with a 22 µF minimum output capacitor
Create a Custom Design Using the TPS63802
With the WEBENCH® Power Designer
•
•
•
•
System pre-regulator (tracking and telematics,
portable POS, home automation, IP network
camera)
Point-of-load regulation (wired sensor, port/cable
adapter and dongle, electronic smart lock, IoT)
Battery back-up supply (electricity meter, data
concentrator, power quality meter)
Thermoelectric device supply (TEC, optical
modules)
General purpose voltage stabilizer and converter
3 Description
The TPS63802 is a high efficiency, high output
current buck-boost converter. Depending on the input
voltage, it automatically operates in boost, buck, or in
a novel 4-cycle buck-boost mode when the input
voltage is approximately equal to the output voltage.
The transitions between modes happen at defined
thresholds and avoid unwanted toggling within the
modes to reduce output voltage ripple. The device
output voltages are individually set by a resistive
divider within a wide output voltage range. An 11-μA
quiescent current enables the highest efficiency for
little to no-load conditions.
Device Information(1)
PART NUMBER
PACKAGE
10-Pin VSON-HR
(0.5 mm pitch)
TPS63802
BODY SIZE (NOM)
3.0 mm × 2.0 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
Efficiency vs Output Current (VO = 3.3 V)
0.47 µH
100
90
VIN
1.3 V ± 5.5 V
80
L2
VIN
VOUT
EN
PG
VOUT
3.3 V
22 F
10 F
TPS63802
MODE
FB
70
Efficiency (%)
L1
60
50
40
30
VIN = 3.0 V
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
20
GND
AGND
10
0
100P
1m
10m
100m
Output Current (A)
1
2
D001
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics .............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
Changes from Revision A (January 2019) to Revision B
Page
•
Changed the device status from Advanced Information to Production Data ........................................................................ 1
•
Changed package group name ............................................................................................................................................. 1
•
Added related documentation .............................................................................................................................................. 28
2
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
5 Description (continued)
The TPS63802 comes in a 1.4 mm x 2.3 mm thermally enhanced HotRod™ dual flat no-lead (DFN) package.
With the tiny bill-off material, the solution size can be small.
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
3
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
6 Pin Configuration and Functions
DLA Package
10-Pin
Top View
EN
1
10
VIN
MODE
2
9
L1
AGND
3
FB
4
7
L2
PG
5
6
VOUT
8
GND
Not to scale
Pin Functions
PIN
4
NAME
NO.
DESCRIPTION
EN
1
Device Enable input. Set HIGH to enable and LOW to disable. It must not be left floating.
MODE
2
PFM/PWM mode selection. Set LOW for power safe mode, set HIGH for forced PWM mode. It must not be
left floating.
AGND
3
Analog ground
FB
4
Voltage feedback sensing pin
PG
5
Power good indicator, open-drain output
VOUT
6
Power stage output
L2
7
Connection for inductor
GND
8
Power ground
L1
9
Connection for inductor
VIN
10
Supply voltage input
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
7 Specifications
7.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted) (1)
VIN, L1, L2, EN, MODE, VOUT, FB, PG
Voltage (2)
MAX
6
UNIT
V
–3
9
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
L1, L2 (AC, less than 10 ns)
MIN
–0.3
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VI
Input voltage
VO
Output voltage
CI
Effective capacitance connected to VIN
L
Effective inductance
CO
TPS63802 Effective capacitance connected to
VOUT
TJ
(1)
(2)
1.3
NOM
(1)
1.8
1.8 V ≤ VO ≤ 2.3 V
VO > 2.3 V
Operating junction
temperature
Operating junction temperature
MAX
V
(2)
V
5.2
4
5
0.37
0.47
UNIT
5.5
μF
0.57
10
μH
μF
7
8.2
–40
µF
125
°C
Minimum startup voltage of VI > 1.8 V until power good
VO margin for accuracy and load steps is considerd in absolut maximum ratings
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
TPS63802
THERMAL METRIC
VSON
UNIT
10 PINS
RΘJA
Junction-to-ambient thermal resistance
81.0
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
36.4
°C/W
RΘJB
Junction-to-board thermal resistance
23.4
°C/W
ΨJT
Junction-to-top characterization parameter
0.9
°C/W
ΨJB
Junction-to-board characterization parameter
23.5
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
5
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
7.5 Electrical Characteristics
VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5.2 V , TJ= –40°C to +125°C, typical values are at VIN= 3.6 V, VOUT = 3.3 V and TJ=
25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN;LOAD
Minimum input voltage for full
load, once started
IOUT = 2 A, VOUT = 3.3 V, TJ = 25°C
2.3
V
IQ;VIN
Quiescent current into VIN
TPS63802; TJ = 25°C, EN = VIN = 3.6 V, VOUT = 3.3 V, not
switching
11
μA
ISD
Shutdown current into VIN
EN = low, -40°C ≤ TJ ≤ 85°C, VIN = 3.6 V, VOUT = 0 V
45
600
nA
Undervoltage lockout threshold
VIN falling, VOUT ≥ 1.8 V, once started
1.2
1.25
1.29
V
Undervoltage lockout threshold
VIN rising
1.6
1.7
1.79
TSD
Thermal shutdown
Temperature rising
TSD;HYST
Thermal shutdown hysteresis
UVLO
V
150
°C
20
°C
SOFT-START, POWER GOOD
Tramp
Soft-start, Current limit ramp time
TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V, IO = 3.5 A, time from
first switching to power good
224
µs
Tdelay
Delay from EN-edge until rising
VOUT
TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V, Delay from EN-edge
until rising
first switching
321
µs
LOGIC SIGNALS EN, MODE
VTHR;EN
Threshold Voltage rising for ENPin
1.07
1.1
1.13
V
VTHF;EN
Threshold Voltage falling for ENPin
0.97
1
1.03
V
VIH
High-level input voltage
VIL
Low-level input voltage
VPG;rising
Power Good threshold voltage
VPG;falling
1.2
V
0.4
V
VOUT rising, referenced to VOUT nominal
95
%
VOUT falling, referenced to VOUT nominal
90
%
VPG;Low
Power Good low-level output
voltage
ISINK = 1 mA
tPG;delay
Power Good delay time
VFB falling
Ilkg
Input leakage current
0.4
V
0.01
0.2
µA
±0.5
±600
14
µs
OUTPUT
ISD
Shutdown current into VOUT
VFB
Feedback Regulation Voltage
VFB
Feedback Voltage accuracy
Overvoltage Protection Threshold
EN = low, -40°C ≤ TJ ≤ 85°C, VIN = 3.6 V, VOUT = 3.3 V
500
PWM mode
–1
1
%
VOUT rising
5.5
5.7
5.9
V
VIN rising
5.5
5.7
5.9
V
IPWM/PFM
Peak Inductor Current to enter
PFM-Mode
VIN = 3.6 V; VOUT = 3.3 V
IFB
Feedback Input Bias Current
VFB = 500 mV
1.06
Peak Current Limit, Boost Mode
Peak Current Limit, Buck-Boost
Mode
IPK
4
TPS63802; VIN ≥ 2.5 V
Peak Current Limit, Buck Mode
IPK;Reverse
Buck
RDS;ON
Boost
RDS;ON
6
nA
mV
A
5
100
nA
5
5.75
A
5
A
3.8
A
–0.9
A
Peak Current Limit for Reverse
Operation
VI = 5 V, VO = 3.3 V
High-side FET on-resistance
VIN = 3 V, VOUT = 3.3 V; I(L2) =
0.19 A
VIN = 3 V, VOUT = 3.3
V; IO = 0.5 A
47
mΩ
Low-side FET on-resistance
VIN = 3 V, VOUT = 3.3 V; I(L2) =
0.19 A
VIN = 3 V, VOUT = 3.3
V; IO = 0.5 A
30
mΩ
High-side FET on-resistance
VIN = 3 V, VOUT = 3.3 V; I(L1) =
0.19 A
VIN = 3 V, VOUT = 3.3
V; IO = 0.5 A
43
mΩ
Low-side FET on-resistance
VIN = 3 V, VOUT = 3.3 V; I(L1) =
0.19 A
VIN = 3 V, VOUT = 3.3
V; IO = 0.5 A
18
mΩ
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
Electrical Characteristics (continued)
VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5.2 V , TJ= –40°C to +125°C, typical values are at VIN= 3.6 V, VOUT = 3.3 V and TJ=
25°C (unless otherwise noted)
PARAMETER
fSW
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Inductor Switching Frequency,
Boost Mode
VIN = 2.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ =
25°C
2.1
MHz
Inductor Switching Frequency,
Buck-Boost Mode
VIN = 3.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ =
25°C
1.4
MHz
Inductor Switching Frequency,
Buck Mode
VIN = 4.3, VOUT = 3.3V, no Load, MODE = HIGH, TJ =
25°C
1.6
MHz
Line regulation
VIN = 2.4 V to 5.5 V, VOUT = 3.3V, IOUT = 2 A
0.3
%
Load regulation
VIN= 3.6 V, VOUT = 3.3V, IOUT = 0 A to 2 A, forced-PWM
mode
0.1
%
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
7
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
7.6 Typical Characteristics
16
1.4
VI = 1.8 V
VI = 3.6 V
VI = 5.5 V
1.2
Shutdown Current (PA)
Quiescent Current (PA)
VI = 1.8 V
VI = 3.6 V
VI = 5.5 V
12
8
1
0.8
0.6
0.4
0.2
4
0
0
-40
-0.2
-40
-20
MODE = LOW
0
20
40
60
80
Temperature (qC)
VO = 3.3 V
100
120
140
0
20
40
60
80
Temperature (qC)
100
120
140
D004
D006
EN = LOW
IO = 0 mA, not
switching
Figure 1. Quiescent Current vs. Temperature
8
-20
Figure 2. Shutdown Current vs. Temperature
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
8 Detailed Description
8.1 Overview
The TPS63802 buck-boost converter uses four internal switches to maintain synchronous power conversion at all
possible operating conditions. This enables the device to keep high efficiency over a wide input voltage and
output load range. To regulate the output voltage at all possible input voltage conditions, the device automatically
transitions between buck, buck-boost, and boost operation as required by the operating conditions. Therefore, it
operates as a buck converter when the input voltage is higher than the output voltage, and as a boost converter
when the input voltage is lower than the output voltage. When the input voltage is close to the output voltage, it
operates in a 3-cycle buck-boost operation. In this mode, all four switches are active (see Buck-Boost Operation).
The RMS current through the switches and the inductor is kept at a minimum to minimize switching and
conduction losses. Controlling the switches this way allows the converter to always keep high efficiency over the
complete input voltage range. The device provides a seamless transition between all modes.
8.2 Functional Block Diagram
L
L1
L2
VOUT
VIN
CIN
COUT
Gate
Driver
Gate
Driver
Current
Sensor
Device
Control
Device
Control
VIN
VMAX Switch
VOUT
PG
Device
Control
EN
+
Ref
1.1V
Device Control
FB
+
±
VIN
MODE
VOUT
GND
+
Power Safe Mode
Protection
Current Limit
Buck/Boost Control
Off-time calculation
Soft-Start
±
±
Gate
Driver
Ref
500mV
Power
Good
AGND
L1, L2
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
9
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
8.3 Feature Description
8.3.1 Control Loop Description
The TPS63802 uses a peak current mode control architecture. It has an inner current loop where it measures the
peak current of the boost high-side MOSFET and compares it to a reference current. This current is the output of
the outer voltage loop. It measures the output voltage via the FB-pin and compares it with the internal voltage
reference. That means, the outer voltage loop measures the voltage error (VREF-VFB), and transforms it into the
system current demand (IREF) for the inner current loop.
Figure 3 shows the simplified schematic of the control loop. The error amplifier and the type-2 compensation
represent the voltage loop. The voltage output is converted into the reference current IREF and fed into the
current comparator.
The scheme shows the skip-comparator handling the power-save mode (PFM) to achieve high efficiency at light
loads. See Power Save Mode Operation for further details.
VIN
L1
IPK
±
IREF
+
FB
VEA
+
Ref
500mV
Gate
Driver
±
+
ISKIP
±
Figure 3. Control Loop Architecture Scheme
8.3.2 Precise Device Enable: Threshold- or Delayed Enable
The enable-pin is a digital input to enable or disable the device by applying a high or low level. The device enters
shutdown when EN is set low. In addition, this input features a precise threshold and can be used as a
comparator that enables and disables the part at a defined threshold. This allows you to drive the state by a
slowly changing voltage and enables the use of an external RC network to achieve a precise power-up delay.
The enable pin can also be used with an external voltage divider to set a user-defined minimum supply voltage.
For proper operation, the EN pin must be terminated and must not be left floating.
VTHRESHOLD
VDELAY
R4
R4
EN
R5
EN
C5
Figure 4. Circuit Example for How to Use the Precise Device Enable Feature
10
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
Feature Description (continued)
8.3.3 Mode Selection (PFM/PWM)
The mode-pin is a digital input to enable the automatic PWM/PFM mode that features the highest efficiency by
allowing pulse-frequency-modulation for lower output currents. This mode is enabled by applying a low level. The
device can be forced in PWM operation regardless of the output current to achieve minimum output ripple by
applying a high level. This pin must not be left floating.
8.3.4 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. It activates the
device once the input voltage (VI) has increased the UVLOrising value. Once active, the device allows operation
down to even smaller input voltages, which is determined by the UVLOfalling. This behavior requires VO to be
higher than the minimum value of 1.8 V.
UVLOrising
UVLOfalling
VIN
Device
active
Figure 5. Rising and Falling Undervoltage Lockout Behavior
8.3.5 Soft-start
To minimize inrush current and output voltage overshoot during start-up, the device features a controlled soft
start-up. After the device is enabled, the device starts all internal reference and control circuits within the enable
delay time, Tdelay. After that, the maximum switch current limit rises monotonically from 0 mA to the current limit.
The loop stops switching once VO is reached. This allows a quick output voltage raise for small capacitors at the
output. The bigger the output capacitor, the longer it takes to settle Vo. A potential load during start is lengthening
the ramp as well. The raise of the current limit allows the smallest inrush current for no-load conditions, as well
as the possibility to start into high loads at start-up.
The converter can start-up into pre-biased loads by a forced operation in PFM during the soft-start until the first
switching cycle request from the output voltage control loop.
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
11
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
Feature Description (continued)
VIN
EN
Current Limit
Inductor
Current
0.95 x VOUT
VOUT
Power Good
Tdelay
Tramp
TStart-up
Figure 6. Device Start-up Scheme
8.3.6 Adjustable Output Voltage
The output voltage of the device is adjusted by applying an external resistive divider between VO, the FB-pin, and
GND. This allows you to program the output voltage in the recommended range. The divider must provide a lowside resistor of less than 100 kΩ. The high-side resistor is chosen accordingly.
8.3.7 Overtemperature Protection - Thermal Shutdown
The device has a built-in temperature sensor which monitors the junction temperature. If the temperature
exceeds the threshold, the device stops operating. As soon as the IC temperature has decreased below the
programmed threshold, it starts operating again. There is a built-in hysteresis to avoid unstable operation at
junction temperatures at the overtemperature threshold.
8.3.8 Input Overvoltage - Reverse-Boost Protection (IVP)
The TPS63802 can operate in reverse mode where the device transfers energy from the output back to the input.
If the source is not able to sink the revers current, the negative current builds up a charge to the input
capacitance and VIN rises. To protect the device and other components from that scenario, the device features
an input voltage protection (IVP) for reverse boost operation. Once the input voltage is above the threshold, the
converter forces PFM mode and the negative current operation is interrupted.
The PG signal goes low to indicate that behavior.
8.3.9 Output Overvoltage Protection (OVP)
In case of a broken feedback-path connection, the device can loose VO information and is not able to regulate.
To avoid an uncontrolled boosting of VO, the TPS63802 features output overvoltage protection. It measures the
voltage on the VOUT pin and stops switching when VO is greater than the threshold to avoid harm to the
converter and other components.
12
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
Feature Description (continued)
8.3.10 Power-Good Indicator
The power good goes high-impedance once the output is above 95% of the nominal voltage, and is driven low
once the output voltage falls below typically 90% of the nominal voltage. This feature also indicates overvoltage
and device shutdown cases as shown in Table 1. The PG pin is an open-drain output and is specified to sink up
to 1 mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 5.5 V. The PG
signal can be used to sequence multiple rails by connecting it to the EN pin of other converters. Leave the PG
pin unconnected when not used.
Table 1. Power-Good Indicator Truth Table
LOGIC SIGNALS
EN
VO
VI
OVP
IVP
PG LOGIC STATUS
X
< 1.8 V
< UVLO_R
X
X
Undefined
LOW
X
> UVLO_F
X
X
LOW
HIGH
VO < 0.9 × target-VO
> 1.3V
X
X
LOW
HIGH
X
> UVLO_F
HIGH
X
LOW
HIGH
X
> UVLO_F
X
HIGH
LOW
HIGH
VO > 0.95 × target-VO
> UVLO_F
LOW
LOW
HIGH Z
8.4 Device Functional Modes
8.4.1 Peak-Current Mode Architecture
The TPS63802 is based on a peak-current mode architecture. The error amplifier provides a peak-current target
(voltage that is translated into an equivalent current, see Figure 3), based on the current demand from the
voltage loop. This target is compared to the actual inductor current during the ON-time. The ON-time is ended
once the inductor current is equal to the current target and OFF-time is initiated. The OFF-time is calculated by
the control and a function of VI and VO.
IPEAK
VEAmp
IPK-PK
TON
IIND
TOFF
0
time
Figure 7. Peak-Current Architecture Operation
8.4.1.1 Reverse Current Operation, Negative Current
When the TPS63802 is forced to PWM operation (MODE = HIGH), the device current can flow in reverse
direction. This happens by the negative current capability of the TPS63802 . The error amplifier provides a peakcurrent target (voltage that is translated into an equivalent current, see Figure 3), even if the target has a
negative value. The maximum average current is even more negative than the peak current.
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
13
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
Device Functional Modes (continued)
time
0
IPEAK
VEAmp
IIND
IAVG
IPK-PK
Figure 8. Peak-Current Operation, Reverse Current
8.4.1.2 Boost Operation
When VI is smaller than VO (and the voltages are not close enough to trigger buck-boost operation), the
TPS63802 operates in boost mode where the boost high-side and low-side switches are active. The buck highside switch is always turned on and the buck low-side switch is always turned off. This lets the TPS63802
operate as a classical boost converter.
IPEAK
VEAmp
IIND
TON
TOFF
Figure 9. Peak-Current Boost Operation
8.4.1.3 Buck-Boost Operation
When VI is close to VO, the TPS63802 operates in buck-boost mode where all switches are active and the device
repeats 3-cycles:
• TON: Boost-charge phase where boost low-side and buck high-side are closed and the inductor current is built
up
• TOFF: Buck discharge phase where boost high-side and buck low-side are closed and the inductor is
discharged
• TCOM: VI connected to VO where all high-side switches are closed and the input is connected to the output
14
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
Device Functional Modes (continued)
IPEAK
VEAmp
IIND
TON
TCOM
TOFF
TCOM
Figure 10. Peak-Current Buck-Boost Operation
8.4.1.4 Buck Operation
When VI is greater than VO (and the voltages are not close enough to trigger buck-boost operation), the
TPS63802 operates in buck mode where the buck high-side and low-side switches are active. The boost highside switch is always turned on and the boost low-side switch is always turned off. This lets the TPS63802
operate as a classical buck converter.
IPEAK
VEAmp
IIND
TON
TOFF
Figure 11. Peak-Current Buck Operation
8.4.2 Power Save Mode Operation
Besides continuos conduction mode (PWM), the TPS63802 features power safe mode (PFM) operation to
achieve high efficiency at light load currents. This is implemented by pausing the switching operation, depending
on the load current.
The skip comparator manages the switching or pause operation. It compares the current demand signal from the
voltage loop, IREF, with the skip threshold, ISKIP, as shown in Figure 3. If the current demand is lower than the
skip value, the comparator pauses switching operation. If the current demand goes higher (due to falling VO), the
comparator activates the current loop and allows switching according to the loop behavior. Whenever the current
loop has risen VO by bringing charge to the output, the voltage loop output, IREF (respectively VEA), decreases.
When IREF falls below ISKIP-hysteresis, it automatically pauses again.
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
15
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
Device Functional Modes (continued)
ICOIL
VO
ISKIP
VEA
/ IREF
Hysteresis
SKIP
Yes/No
Switching
Pause
t
Figure 12. Power Safe Mode Operation Curves
8.4.2.1 Current Limit Operation
To limit current and protect the device and application, the maximum peak inductor current is limited internally on
the IC. It is measured at the buck high-side switch which turns into an input current detection. To provide a
certain load current across all operation modes, the boost and buck-boost peak current limit is higher than in
buck mode. It limits the input current and allows no further increase of the delivered current. When using the
device in this mode, it behaves similar to a current source.
The current limit depends on the operation mode (buck, buck-boost, or boost mode).
16
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS63802 is a high efficiency, low quiescent current, non-inverting buck-boost converter, suitable for
applications that need a regulated output voltage from an input supply that can be higher or lower than the output
voltage.
9.2 Typical Application
L1
0.47 µH
L1
VIN
1.3V t 5.5V
VIN
L2
VOUT = 3.3V
VOUT
VIN
R3
100lQ
C1
10 …F
EN
PG
MODE
FB
C2
22 …F
R1
511lQ
R2
91lQ
GND
AGND
TPS63802
Figure 13. 3.3 VOUT Typical Application
9.2.1 Design Requirements
The design guideline provides a component selection to operate the device within the Table 2.
Table 2 shows the list of components for the application characteristic curves.
Table 2. Matrix of Output Capacitor and Inductor Combinations
NOMINAL
INDUCTOR VALUE
[µH] (1)
0.47
(1)
(2)
(3)
NOMINAL OUTPUT CAPACITOR VALUE [µF] (2)
10
22
-
+
(3)
47
66
100
+
+
+
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
Capacitance tolerance and DC bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
TPS63802 typical application. Other check marks indicate possible filter combinations.
9.2.2 Detailed Design Procedure
The first step is the selection of the output filter components. To simplify this process, the Absolute Maximum
Ratings outlines minimum and maximum values for inductance and capacitance. Take tolerance and derating
into account when selecting nominal inductance and capacitance.
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63802 device with the WEBENCH® Power Designer.
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
17
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Inductor Selection
The inductor selection is affected by several parameters such as the following:
• Inductor ripple current
• Output voltage ripple
• Transition point into power save mode
• Efficiency
See Table 3 for typical inductors.
For high efficiencies, the inductor must have a low DC resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a high impact on efficiency. When using small chip inductors,
the efficiency is reduced, mainly due to higher inductor core losses. This needs to be considered when selecting
the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value,
the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for
the inductor in steady-state operation is calculated using Equation 2. Only the equation which defines the switch
current in boost mode is shown because this provides the highest value of current and represents the critical
current value for selecting the right inductor.
Duty Cycle Boost
IPEAK
D=
V
-V
IN
OUT
V
OUT
(1)
Iout
Vin ´ D
=
+
η ´ (1 - D)
2 ´ f ´ L
where
•
•
•
•
D = Duty Cycle in Boost mode
f = Converter switching frequency
L = Inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.9 as an assumption)
(2)
NOTE
The calculation must be done for the minimum input voltage in boost mode.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It is recommended to choose an inductor with a saturation current 20% higher
than the value calculated using Equation 2. Table 3 lists the possible inductors.
Table 3. List of Recommended Inductors
(1)
INDUCTOR
VALUE [µH]
SATURATION CURRENT
[A]
DCR [mΩ]
PART NUMBER
MANUFACTURER
SIZE (LxWxH mm)
0.47
5.4
7.6
XFL4015-471ME
Coilcraft
4x4x2
(1)
See Third-party Products Disclaimer.
18
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
Table 3. List of Recommended Inductors
()
(continued)
INDUCTOR
VALUE [µH]
SATURATION CURRENT
[A]
DCR [mΩ]
PART NUMBER
MANUFACTURER
SIZE (LxWxH mm)
0.47
5.5
26
DFE201612E
Toko
2.0 x 1.6 x 1.2
9.2.2.3
Output Capacitor Selection
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and PGND pins of the IC. The recommended nominal output capacitor value is a single 22 µF for all
programmed output voltages ≤ 3.6 V. Above that voltage, 1x 22 µF capacitors are recommended.
It is important that the effective capacitance is given according to the recommended value in Recommended
Operating Conditions. In general, consider DC bias effects resulting in less effective capacitance. The choice of
the output capacitance is mainly a trade-off between size and transient behavior since higher capacitance
reduces transient response overshoot and undershoot and increases transient response time. Table 4 lists
possible output capacitors.
There is no upper limit for the output capacitance value.
Table 4. List of Recommended Capacitors (1)
CAPACITOR
[µF]
VOLTAGE RATING [V]
ESR [mΩ]
22
6.3
22
6.3
22
22
(1)
PART NUMBER
MANUFACTURER
SIZE
(METRIC)
10
GRM188R60J226MEA0
Murata
0603 (1608)
10
GRM187R61A226ME15
Murata
0603 (1608)
10
40
GRM188R61A226ME15
Murata
0603 (1608)
10
10
GRM187R60J226ME15
Murata
0603 (1608)
47
6.3
43
GRM188R60J476ME15
Murata
0603 (1608)
47
6.3
43
GRM219R60J476ME44
Murata
0805 (2012)
See Third-party Products Disclaimer.
9.2.2.4
Input Capacitor Selection
A 10 µF input capacitor is recommended to improve line transient behavior of the regulator and EMI behavior of
the total power supply circuit. An X5R or X7R ceramic capacitor placed as close as possible to the VIN and
PGND pins of the IC is recommended. This capacitance can be increased without limit. If the input supply is
located more than a few inches from the TPS63802 converter, additional bulk capacitance can be required in
addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 µF is a typical
choice.
Table 5. List of Recommended Capacitors (1)
CAPACITOR
[µF]
VOLTAGE RATING [V]
ESR [mΩ]
PART NUMBER
MANUFACTURER
SIZE
(METRIC)
10
6.3
10
GRM188R60J106ME84
Murata
0603 (1608)
10
10
40
GRM188R61A106ME69
Murata
0603 (1608)
22
6.3
10
GRM188R60J226MEA0
Murata
0603 (1608)
(1)
See Third-party Products Disclaimer.
9.2.2.5 Setting The Output Voltage
The output voltage is set by an external resistor divider. The resistor divider must be connected between VOUT,
FB, and GND. The feedback voltage is 500 mV nominal. The low-side resistor R2 (between FB and GND) must
not exceed 100 kΩ. The high-side resistor (between FB and VOUT) R1 is calculated by Equation 3.
æV
ö
R1 = R2 × ç OUT - 1÷
è VFB
ø
where
•
VFB = 500 mV
(3)
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
19
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
Table 6. Resistor Selection for Typ. Voltages
VO [V]
R1 [kΩ]
R2 [kΩ]
2.5
365
91
3.3
511
91
3.6
562
91
5
806
91
9.2.3 Application Curves
Table 7. Components for Application Characteristic Curves
REFERENCE
(1)
DESCRIPTION
PART NUMBER
MANUFACTURER
TPS63802 2 A Buck-Boost Converter (2
mm x 3 mm QFN)
TPS63802RMW
Texas Instruments
L1
0.47 µH, 4 mm x 4 mm x 1.5 mm, 5.4 A,
7.6 mΩ
XFL4015-471ME
Coilcraft
C1
10 µF, 0603, Ceramic Capacitor, ±20%,
6.3 V
GRM188R60J106ME84
Murata
C2
1x 22 µF, 0603, Ceramic Capacitor, ±20%,
6.3 V
GRM188R60J226MEA0
Murata
VO ≤ 3.6 V
C2
2x 22 µF, 0603, Ceramic Capacitor, ±20%,
6.3 V
GRM188R60J226MEA0
Murata
VO > 3.6 V
R1
511 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
VO = 3.3 V
R1
562 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
VO = 3.6 V
R1
806 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
VO = 5 V
R2
91 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
R3
100 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
(1)
See Third-party Products Disclaimer.
20
Submit Documentation Feedback
COMMENT
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
Table 8. Typical Characteristics Curves
PARAMETER
CONDITIONS
FIGURE
Output Current Capability
Typical Output Current Capability versus Input Voltage
VO = 3.3 V
Figure 14
Typical Inductor Switching Frequency versus Input
Voltage
IO = 0 A, MODE = High
Figure 15
Typical Inductor Burst Frequency versus Output Current
VO = 3.3 V
Figure 16
Efficiency versus Output Current (PFM/PWM)
VI = 2.5 V to 4.2 V, VO = 3.3 V, MODE =
Low
Figure 17
Efficiency versus Output Current (PWM only)
VI = 2.5 V to 4.2 V, VO = 3.3 V, MODE =
High
Figure 18
Efficiency versus Output Current (PFM/PWM)
VI = 1.8 V to 5 V, VO = 3.3 V, MODE = Low
Figure 19
Efficiency versus Output Current (PWM only)
VI = 1.8 V to 5 V, VO = 3.3 V, MODE = High
Figure 20
Efficiency versus. Input Voltage (PFM/PWM)
VO = 3.3 V, MODE = Low
Figure 21
Efficiency versus Input Voltage (PWM only)
IO = 1 A, MODE = High
Figure 22
Load Regulation, PWM Operation
VO = 3.3 V, MODE = High
Figure 23
Load Regulation, PFM/PWM Operation
VO = 3.3 V, MODE = Low
Figure 24
Line Regulation, PWM Operation
IO = 1 A, MODE = High
Figure 25
Line Regulation, PFM/PWM Operation
IO = 1 A, MODE = Low
Figure 26
Switching Waveforms, PFM Boost Operation
VI = 2.3 V, VO = 3.3 V, MODE = Low
Figure 27
Switching Waveforms, PFM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, MODE = Low
Figure 28
Switching Waveforms, PFM Buck Operation
VI = 4.3 V, VO = 3.3 V, MODE = Low
Figure 29
Switching Waveforms, PWM Boost Operation
VI = 2.3 V, VO = 3.3 V, MODE = High
Figure 30
Switching Waveforms, PWM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, MODE = High
Figure 31
Switching Waveforms, PWM Buck Operation
VI = 4.3 V, VO = 3.3 V, MODE = High
Figure 32
Load Transient, PFM/PWM Boost Operation
VI = 2.5 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = Low
Figure 33
Load Transient, PFM/PWM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = Low
Figure 34
Load Transient, PFM/PWM Buck Operation
VI = 4.2 V, VO = 3.3V, Load = 100 mA to 1A,
MODE = Low
Figure 35
Load Transient, PWM Boost Operation
VI = 2.5 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = High
Figure 36
Load Transient, PWM Buck-Boost Operation
VI = 3.3 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = High
Figure 37
Load Transient, PWM Buck Operation
VI = 4.2 V, VO = 3.3 V, Load = 100 mA to
1A, MODE = High
Figure 38
Line Transient, PWM Operation
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 0.5
A , MODE = Low
Figure 39
Line Transient, PWM Operation
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 1 A ,
MODE = Low
Figure 40
Line Transient, PWM Operation
VI = 3 V to 3.6 V, VO = 3.3 V, Load = 0.5 A ,
MODE = Low
Figure 41
Start-up Behavior from Rising Enable, PFM Operation
VI = 2.2 V, VO = 3.3 V, Load = 10 mA,
MODE = Low
Figure 42
Start-up Behavior from Rising Enable, PWM Operation
VI = 2.2 V, VO = 3.3 V, Load = 10 mA,
MODE = High
Figure 43
Switching Frequency
Efficiency
Regulation Accuracy
Switching Waveforms
Transient Performance
Start-up
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
21
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
4.5
3.0
Switching Frequency (MHz)
Maximum Output Current (A)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
VO = 3.3 V
VO = 3.6 V
VO = 5 V
0.5
0.0
1.3
1.8
2.3
2.8
3.3
3.8
Input Voltage (V)
4.3
4.8
2.0
1.5
1.0
0.5
2.5
5.3
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
2.7
2.9
D002
MODE = High
IO=0A
Figure 14. Typical Output Current Capability versus Input
Voltage
3.1
3.3
3.5
3.7
Input Voltage (V)
MODE = High
3.9
4.1
4.3
D007
VI rising
Figure 15. Typical Inductor Switching Frequency versus
Input Voltage
100
1M
90
100k
Efficiency (%)
PFM Burst Frequency (Hz)
2.5
80
10k
70
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
VI = 2.5 V
VI = 3.6 V
VI = 4.8 V
1k
1m
VO = 3.6 V
10m
100m
Output Current (A)
60
100P
D018
1m
VO = 3.3 V
MODE = Low
10m
100m
Output Current (A)
1
2
D019
MODE = High
Figure 17. Efficiency versus Output Current (PFM/PWM)
Figure 16. Typical Inductor Burst Frequency versus
Output Current
100
100
90
80
90
Efficiency (%)
Efficiency (%)
70
60
50
40
80
30
70
20
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
10
0
1m
VO = 3.3 V
10m
100m
Output Current (A)
1
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
2
D020
MODE = Low
VO = 3.3 V
Figure 18. Efficiency versus Output Current (PWM Only)
22
60
100P
1m
10m
100m
Output Current (A)
1
2
D021
MODE = High
Figure 19. Efficiency versus Output Current (PFM/PWM)
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
100
100
90
80
90
Efficiency (%)
Efficiency (%)
70
60
50
40
80
70
IO = 100 PA
IO = 10 mA
IO = 100 mA
IO = 1 A
IO = 1.5 A
30
20
60
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
10
0
1m
10m
VO = 3.3 V
100m
Output Current (A)
1
50
2.5
2
MODE = Low
VO = 3.3 V
Figure 20. Efficiency versus Input Voltage (PWM Only)
Output Voltage Regulation (%)
Efficiency (%)
3.7
4.1
D023
MODE = High
0.2
90
80
70
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
0.1
0.0
-0.1
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
-0.2
-0.3
2.3
2.8
IO = 1 A
3.3
3.8
4.3
Input Voltage (V)
4.8
0
5.3
0.5
D024
MODE = Low
1.0
0.2
Output Voltage Regulation (%)
0.3
0.5
0.0
-0.5
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
-1.0
-1.5
VO = 3.3 V
1.0
Output Current (A)
1.5
2.0
2.0
D026
MODE = High
0.1
0.0
-0.1
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-0.2
-0.3
2.5
2.7
D027
MODE = Low
1.5
Figure 23. Load Regulation (PWM Only)
1.5
0.5
1.0
Output Current (A)
VO = 3.3 V
Figure 22. Efficiency versus Input Voltage (PWM Only)
Output Voltage Regulation (%)
3.3
Input Voltage (V)
Figure 21. Efficiency versus Input Voltage (PFM/PWM)
100
60
1.8
2.9
D022
IO = 1 A
Figure 24. Load Regulation (PFM/PWM)
2.9
3.1
3.3
3.5
3.7
Input Voltage (V)
3.9
4.1
Product Folder Links: TPS63802
D028
MODE = Low
Figure 25. Line Regulation (PWM Only)
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
4.3
23
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
Output Voltage Regulation (%)
0.2
0.1
0.0
-0.1
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-0.2
2.5
2.7
IO = 1 A
2.9
3.1
3.3
3.5
3.7
Input Voltage (V)
3.9
4.1
4.3
D029
MODE = High
Figure 26. Line Regulation (PFM/PWM)
VI = 3.3 V,
VO = 3.3 V
MODE = Low
IO = 40 mA
Figure 28. Switching Waveforms, PFM Buck-Boost
Operation
VI = 2.3 V,
VO = 3.3 V
MODE = Low
IO = 2 A
Figure 30. Switching Waveforms, PWM Boost Operation
24
VI = 2.3 V,
VO = 3.3 V
MODE = Low
IO = 40 mA
Figure 27. Switching Waveforms, PFM Boost Operation
VI = 4.2 V,
VO = 3.3 V
MODE = Low
IO = 40 mA
Figure 29. Switching Waveforms, PFM Buck Operation
VI = 3.3 V,
VO = 3.3 V
MODE = Low
IO = 2 A
Figure 31. Switching Waveforms, PWM Buck-Boost
Operation
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
VI = 4.2 V,
VO = 3.3 V
MODE = Low
IO = 2 A
Figure 32. Switching Waveforms, PWM Buck Operation
VI = 3.3 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
MODE = Low
Figure 34. Load Transient, PFM/PWM Buck-Boost
Operation
VI = 2.5 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
MODE = High
Figure 36. Load Transient, PWM Boost Operation
VI = 2.5 V,
VO = 3.3 V
IO from 100 mA to
1A
tr = 1 µs, tf = 1 µs
MODE = Low
Figure 33. Load Transient, PFM/PWM Boost Operation
VI = 5 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
MODE = Low
Figure 35. Load Transient, PFM/PWM Buck Operation
VI = 3.3 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
MODE = High
Figure 37. Load Transient, PWM Buck-Boost Operation
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
25
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
VI = 5 V,
VO = 3.3 V
IO from 100 mA
to 1 A
tr = 1 µs, tf = 1
µs
www.ti.com
MODE = High
Figure 38. Load Transient, PWM Buck Operation
IO = 1 A
VI from 2.2 V to
4.2 V
tr = 1 µs, tf = 1
µs
MODE = High
Figure 40. Line Transient, PWM Operation
VI = 4.2 V,
VO = 3.3 V
MODE = Low
100 mΩ resistive
load
Figure 42. Start-up Behavior from Rising Enable, PFM
Operation
26
IO = 0.5 A
VI from 2.2
V to 4.2 V
tr =1 µs, tf =
1 µs
MODE =
High
Figure 39. Line Transient, PWM Operation
IO = 0.5 A
VI from 3 V to
3.6 V
tr = 1 µs, tf = 1
µs
MODE = High
Figure 41. Line Transient, PWM Operation
VI = 4.2 V,
VO = 3.3 V
MODE = High
100 mΩ resistive
load
Figure 43. Start-up Behavior from Rising Enable, PWM
Operation
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
10 Power Supply Recommendations
The TPS63802 device family has no special requirements for its input power supply. The input power supply
output current needs to be rated according to the supply voltage, output voltage, and output current of the
TPS63802.
11 Layout
11.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TPS63802 device.
1. Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Route wide
and direct traces to the input and output capacitor results in low trace resistance and low parasitic
inductance.
2. Separate AGND and PGND. Do not connect AGND and PGND directly at the IC. See Figure 44 as an
example.
3. Use a common-power GND, but connect AGND and PGND through a via at a different layer.
4. Use separate traces for the supply voltage of the power stage and the supply voltage of the analog stage.
5. The sense trace connected to FB is signal trace. Keep these traces away from L1 and L2 nodes.
11.2 Layout Example
L1
C1
C2
R2
R1
Figure 44. TPS63802 Layout
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
27
TPS63802
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63802 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.1.3 Development Support
QFN/SON Package FAQs
12.2 Documentation Support
For related documentation, see the following:
• Texas Instruments, Selecting a DC/DC Converter for Maximum Battery Life in Pulsed-Load Applications
Application Report
• Texas Instruments, Selecting the Right DC/DC Converter for Maximum Battery Life Application Report
• Texas Instruments, Supercapacitor Backup Power Supply with TPS63802 Application Report
• Texas Instruments, Extend Battery Lifetime in Wireless Network Cameras and Video Doorbells Application
Note
• Texas Instruments, Prevent Battery Overdischarge with Precise Threshold Enable Pin Application Note
• Texas Instruments, Using Non-Inverting Buck-Boost Converter for Voltage Stabilization Application Report
• Texas Instruments, Precise Delayed Start-up with Precise Threshold Enable-pin Application Note
• Texas Instruments, Buck-Boost Converters Solving Power Challenges in Optical Modules Application Note
• Texas Instruments, Improving Load Transient Response for Controlled Loads Application Report
• Texas Instruments, TPS63802EVM User's Guide
• Texas Instruments, HotRod QFN Package PCB Attachment Application Report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
28
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
TPS63802
www.ti.com
SLVSEU9B – NOVEMBER 2018 – REVISED OCTOBER 2019
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS63802
29
PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS63802DLAR
ACTIVE
VSON-HR
DLA
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
63802
TPS63802DLAT
ACTIVE
VSON-HR
DLA
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
63802
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS63802DLAR
VSONHR
DLA
10
3000
180.0
8.4
2.25
3.25
1.05
4.0
8.0
Q1
TPS63802DLAT
VSONHR
DLA
10
250
180.0
8.4
2.25
3.25
1.05
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS63802DLAR
VSON-HR
DLA
10
3000
182.0
182.0
20.0
TPS63802DLAT
VSON-HR
DLA
10
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
VSON-HR - 1 mm max height
DLA0010A
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
3.1
2.9
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
5X 0.5
0.3
5X 0.3
0.2
(0.1) TYP
SYMM
5
6
8X 0.5
SYMM
2
10
1
5X 0.3
0.2
4X 0.8
0.6
1.2
1
0.1
0.05
C A B
C
4223750/D 03/2019
NOTES:
1.
2.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VSON-HR - 1 mm max height
DLA0010A
PLASTIC SMALL OUTLINE - NO LEAD
PKG
5X (0.9)
4X (0.75)
5X (0.6)
(0.55)
5X (0.25)
10
1
8X
(0.5)
(0.25)
PKG
(2)
(R0.05) TYP
5
6
4X (0.25)
4X (0.9)
(1.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223750/D 03/2019
NOTES: (continued)
3.
4.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VSON-HR - 1 mm max height
DLA0010A
PLASTIC SMALL OUTLINE - NO LEAD
PKG
5X (0.9)
4X (0.75)
5X (0.6)
(0.175)
5X (0.25)
10
1
8X
(0.5)
2X
(0.25)
PKG
(2)
(R0.05) TYP
(0.5)
5
6
4X (0.25)
2X (0.55)
(0.75)
4X (0.9)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 8: 83%
SCALE: 30X
4223750/D 03/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising