Texas Instruments | LMR36520 SIMPLE SWITCHER 4.2-V to 65-V, 2-A Synchronous Step-down Converter | Datasheet | Texas Instruments LMR36520 SIMPLE SWITCHER 4.2-V to 65-V, 2-A Synchronous Step-down Converter Datasheet

Texas Instruments LMR36520 SIMPLE SWITCHER 4.2-V to 65-V, 2-A Synchronous Step-down Converter Datasheet
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LMR36520
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1 Features
3 Description
•
The LMR36520 regulator is an easy-to-use,
synchronous, step-down DC/DC SIMPLE SWITCHER
converter. With integrated high-side and low-side
power MOSFETs, output current up to 2 A is
delivered over a wide input voltage range of 4.2 V to
65 V. The transient tolerance that goes up to 70 V
reduces the solution size and cost to protect against
overvoltages and meets the surge immunity
requirements of IEC 61000-4-5.
1
•
•
•
•
Designed for reliable and rugged applications
– Input transient protection up to 70 V
– Protection features: thermal shutdown, input
undervoltage lockout, cycle-by-cycle current
limit, hiccup short-circuit protection
Well-suited for scalable industrial power supplies
– Pin compatible with:
– LMR36510 (65 V, 1 A)
– LMR33620/LMR33630 (36 V, 2 A, or 3 A)
– Internal compensation helps reduce solution
size, cost and design complexity
– 400-kHz frequency
Wide conversion range
– Input voltage range: 4.2 V to 65 V
– Output voltage range: 1 V to 95% of VIN
– Short minimum on time of 60 ns
Low-power dissipation across load spectrum
– 90% efficiency at 400 kHz (24 VIN, 5 VOUT,
1 A)
– Increased light-load efficiency in PFM mode
– Low operating quiescent current of 26 µA
Power-good output with filter and delayed release
The LMR36520 uses peak-current mode control to
provide optimal efficiency and output voltage
accuracy. Precision enable gives flexibility by
enabling a direct connection to the wide input voltage
or precise control over device start-up and shutdown.
The power-good flag, with built-in filtering and delay,
offers a true indication of system status, eliminating
the requirement for an external supervisor.
Integration and internal compensation eliminates
many external components and provides a pinout
designed for a simple PCB layout. The feature set of
the device is designed to simplify implementation for
a wide range of end equipment. The LMR36520 is
pin-to-pin compatible with the LMR36510 (65 V, 1 A)
and LMR33620 and LMR33630 (36 V, 2 A/3 A),
completing the family of scalable SIMPLE
SWITCHER power supplies. This minimizes the cost
and effort associated with board layout modifications.
The LMR36520 is in an 8-pin HSOIC package.
2 Applications
•
•
•
•
•
•
Device Information(1)
IP network cameras
Analog security cameras
HVAC valve and actuator control
AC drive and servo drive control modules
Analog input modules and mixed IO modules
General purpose wide VIN power supply
PART NUMBER
LMR36520
PACKAGE
HSOIC (8)
BODY SIZE (NOM)
5.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Figure 1. Simplified Schematic
BOOT
VIN
VIN
CBOOT
CIN
EN
SW
L1
VOUT
COUT
PGND
VCC
PG
RFBT
CVCC
FB
RFBB
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
LMR36520 SIMPLE SWITCHER® 4.2-V to 65-V, 2-A Synchronous Step-down Converter
LMR36520
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
5
5
5
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
System Characteristics .............................................
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 15
9.3 What to Do and What Not to Do ............................. 20
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Detailed Description .............................................. 9
ADVANCE INFORMATION
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
September 2019
*
Initial release
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5 Device Comparison Table
CURRENT
FPWM
fSW
AVAILABILITY
LMR36520ADDAR
2A
No
400 kHz
Now
LMR36520FADDAR
2A
Yes
400 kHz
No
ADVANCE INFORMATION
ORDERABLE PART
NUMBER
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6 Pin Configuration and Functions
DDA Package
8-Pin HSOIC
Top View
PGND
1
VIN
2
8
SW
7
BOOT
THERMAL PAD
EN
3
6
VCC
PG
4
5
FB
Not to scale
Pin Functions
ADVANCE INFORMATION
PIN
I/O
DESCRIPTION
1
G
Power ground terminal. Connect to system ground and AGND. Connect to bypass capacitor with short
wide traces.
VIN
2
P
Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin and
PGND.
EN
3
A
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; Do not float.
PG
4
A
Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can be left open when
not used.
FB
5
A
Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not float. Do not
ground.
VCC
6
P
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads.
Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to
PGND.
BOOT
7
P
Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from
this pin to the SW pin.
SW
8
P
Regulator switch node. Connect to a power inductor.
G
Analog ground for regulator and system. Ground reference for internal references and logic. All
electrical parameters are measured with respect to this pin. Connect to system ground on PCB. For
the HSOIC package, the pad on the bottom of the device serves as both the AGND connection and a
thermal connection to the heat sink ground plane. This pad must be soldered to a ground plane to
achieve good electrical and thermal performance.
NAME
NO.
PGND
AGND
THERMAL
PAD
A = Analog, P = Power, G = Ground
4
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7 Specifications
7.1 Absolute Maximum Ratings
Over junction temperature range of -40°C to 150°C (unless otherwise noted) (1)
MAX
VIN to PGND
–0.3
70
UNIT
V
Input voltage
EN to PGND
–0.3
70.3
V
Input voltage
FB to PGND
–0.3
5.5
V
Input voltage
PG to PGND
–0.3
20
V
Output voltage
SW to PGND
–0.3
70.3
V
Output voltage
SW to PGND less than 10-ns transients
–3.5
70
V
Output voltage
CBOOT to SW
–0.3
5.5
V
Output voltage
VCC to PGND
–0.3
5.5
V
Junction Temperature TJ
-40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM) (1)
±2500
Charged-device model (CDM) (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40 ℃ to 125 ℃ (unless otherwise noted) (1)
MIN
MAX
4.2
65
V
EN to PGND (2)
0
65
V
PG to PGND (2)
0
18
V
Output voltage
VOUT
1
28
V
Output current
IOUT
0
2
A
VIN to PGND
Input voltage
(1)
(2)
UNIT
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
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MIN
Input voltage
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7.4 Thermal Information
LMR36520
THERMAL METRIC (1)
DDA (HSOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
4.3
°C/W
ψJB
Junction-to-board characterization parameter
13.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.3
°C/W
(1)
42.9
°C/W
54
°C/W
13.6
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and
Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
ADVANCE INFORMATION
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
18
26
36
UNIT
SUPPLY VOLTAGE (VIN PIN)
IQ-nonSW
Operating quiescent current (nonswitching) (2)
VEN = 3.3 V (PFM variant only)
ISD
Shutdown quiescent current;
measured at VIN pin
VEN = 0 V
5.3
µA
µA
ENABLE (EN PIN)
VEN-VCC-H
Enable input high level for VCC output
VENABLE rising
VEN-VCC-L
Enable input low level for VCC output
VENABLE falling
0.3
1.14
V
VEN-VOUT-H
Enable input high level for VOUT
VENABLE rising
1.157
VEN-VOUT-HYS
Enable input hysteresis for VOUT
Hysteresis below VENABLE-H; falling
110
mV
ILKG-EN
Enable input leakage current
VEN = 3.3V
0.2
nA
V
1.231
1.3
V
INTERNAL LDO (VCC PIN)
VCC
VCC-UVLORising
VCC-UVLOFalling
Internal VCC voltage
6 V ≤ VIN ≤ 65 V
Internal VCC undervoltage lockout
Internal VCC undervoltage lockout
4.75
5
5.25
V
VCC rising
3.6
3.8
4.0
V
VCC falling
3.1
3.3
3.5
V
1
1.015
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
ILKG-FB
Feedback leakage current
0.985
FB = 1 V
0.2
V
nA
CURRENT LIMITS AND HICCUP
High-side current limit (3)
ISC
ILS-LIMIT
Low-side current limit
IL-ZC
Zero cross detector threshold
IPEAK-MIN
Minimum inductor peak current (3)
IL-NEG
(1)
(2)
(3)
6
Negative current limit
2.4
(3)
(3)
1.8
PFM variants only
FPWM variant only
3
3.6
A
2.3
2.8
A
0.04
A
0.5
A
–1.7
A
MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
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Electrical Characteristics (continued)
Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP
Power-Good upper threshold - rising
% of FB voltage
105%
107%
110%
VPG-LOW-DN
Power-Good lower threshold - falling
% of FB voltage
90%
93%
95%
VPG-HYS
Power-Good hysteresis (rising &
falling)
% of FB voltage
VPG-VALID
Minimum input voltage for proper
Power-Good function
RPG
Power-Good on-resistance
VEN = 2.5 V
RPG
Power-Good on-resistance
VEN = 0 V
RDS-ON-HS
High-side MOSFET ON-resistance
RDS-ON-LS
Low-side MOSFET ON-resistance
1.5%
2
V
80
165
Ω
35
90
Ω
IOUT = 0.5 A
245
465
mΩ
IOUT = 0.5 A
165
310
mΩ
7.6 Timing Requirements
Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and
Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
MIN
NOM
MAX
UNIT
tON-MIN
Minimum switch on-time
72
tOFF-MIN
Minimum switch off-time
80
102
ns
tON-MAX
Maximum switch on-time
7
12
µs
tSS
Internal soft-start time
4.5
6
ms
(1)
3
ns
MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
7.7 Switching Characteristics
TJ = -40°C to 125°C, VIN = 24 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
340
400
460
kHz
OSCILLATOR
FOSC
Internal oscillator frequency
400-kHz variant
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MOSFETS
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7.8 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25℃ only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –40℃ to 125℃. These specifications are not ensured by production
testing.
PARAMETER
TEST CONDITIONS
VIN
Operating input voltage range
VOUT
Adjustable output voltage regulation (1)
VOUT
ISUPPLY
MIN
TYP
MAX
4.2
65
PFM operation
–1.5%
2.5%
Adjustable output voltage regulation (1)
FPWM operation
–1.5%
1.5%
Input supply current when in regulation
VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
(2)
26
UNIT
V
µA
DMAX
Maximum switch duty cycle
VHC
FB pin voltage required to trip short-circuit
hiccup mode
tD
Switch voltage dead time
2
ns
TSD
Thermal shutdown temperature
Shutdown temperature
170
°C
TSD
Thermal shutdown temperature
Recovery temperature
158
°C
ADVANCE INFORMATION
(1)
(2)
8
98%
0.4
V
Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to full load
In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN =
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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8 Detailed Description
8.1 Overview
The LMR36520 is a synchronous peak-current mode buck regulator designed for a wide variety of industrial
applications. The regulator automatically switches modes between PFM and PWM depending on load. At heavy
loads, the device operates in PWM at a constant switching frequency. At light loads, the mode changes to PFM
with diode emulation, allowing DCM. This reduces the input supply current and keeps efficiency high. The device
features internal loop compensation, which reduces design time and requires fewer external components than
externally compensated regulators.
8.2 Functional Block Diagram
VCC
INT. REG.
BIAS
ENABLE
LOGIC
BOOT
ADVANCE INFORMATION
OSCILLATOR
EN
VIN
HS CURRENT
SENSE
1.0V
Reference
ERROR
AMPLIFIER
FB
+
-
PG
+
-
PWM
COMP.
CONTROL
LOGIC
PFM MODE
CONTROL
SW
DRIVER
LS CURRENT
SENSE
POWER GOOD
CONTROL
AGND
PGND
8.3 Feature Description
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR36520 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. Output voltage excursions
lasting less than tPG do not trip the power-good flag. Power-good operation can best be understood by
referencing Figure 2 and Figure 3. Note that during initial power-up, a delay of about 4 ms (typical) is inserted
from the time that EN is asserted to the time that the power-good flag goes high. This delay only occurs during
start-up and is not encountered during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. If this function
is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4
mA.
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Feature Description (continued)
Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
<TPG
PG
ADVANCE INFORMATION
TPG
TPG
TPG
Figure 2. Static Power-Good Operation
Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
<tPG
PG
tPG
tPG
tPG
Figure 3. Power-Good Timing Behavior
8.3.2 Enable and Start-up
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see the External UVLO section). Applying a
voltage of ≥ VEN-VCC_H causes the device to enter standby mode, powering the internal VCC, but not producing
an output voltage. Increasing the EN voltage to VEN-H fully enables the device, allowing it to enter start-up mode
and begin the soft-start period. When the EN input is brought below VEN-H by VEN-HYS, the regulator stops running
and enters standby mode. If the EN voltage decreases below VEN-VCC-L, the device shuts down. Figure 4 shows
this behavior. The EN input can be connected directly to VIN if this feature is not needed. This input must not be
allowed to float. The values for the various EN thresholds can be found in the Electrical Characteristics table.
10
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Feature Description (continued)
The LMR36520 utilizes a reference-based soft-start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up.
EN
VEN-H
VEN-H ± VEN-HYS
VEN-VCC-H
VEN-VCC-L
ADVANCE INFORMATION
VCC
5V
0
VOUT
VOUT
0
Figure 4. Precision Enable Behavior
8.3.3 Current Limit and Short Circuit
The LMR36520 incorporates valley current limit for normal overloads and for short-circuit protection. In addition,
the high-side power MOSFET is protected from excessive current by a peak-current limit circuit. Cycle-by-cycle
current limit is used for overloads while hiccup mode is used for short circuits. Finally, a zero current detector is
used on the low-side power MOSFET to implement diode emulation at light loads (see the Glossary).
During overloads, the low-side current limit, ILIMIT, determines the maximum load current that the LMR36520 can
supply. When the low-side switch turns on, the inductor current begins to ramp down. If the current does not fall
below ILIMIT before the next turnon cycle, then that cycle is skipped, and the low-side MOSFET is left on until the
current falls below ILIMIT. This is somewhat different than the more typical peak-current limit and results in
Equation 1 for the maximum load current.
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Feature Description (continued)
IOUT
max
ILIMIT
VIN VOUT VOUT
˜
2 ˜ fSW ˜ L
VIN
where
•
•
fSW = switching frequency
L = inductor value
(1)
If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
into hiccup mode. In this mode, the device stops switching for tHC, or about 94 ms, and then goes through a
normal re-start with soft-start. If the short-circuit condition remains, the device runs in current limit for about 20
ms (typical) and then shuts down again. This cycle repeats as long as the short-circuit condition persists. This
mode of operation reduces the temperature rise of the device during a hard short on the output. Of course, the
output current is greatly reduced during hiccup mode. Once the output short is removed and the hiccup delay is
passed, the output voltage recovers normally.
ADVANCE INFORMATION
The high-side current limit trips when the peak inductor current reaches ISC. This is a cycle-by-cycle current limit
and does not produce any frequency or load current fold back. It is meant to protect the high-side MOSFET from
excessive current. Under some conditions, such as high input voltages, this current limit can trip before the lowside protection. Under this condition, ISC determines the maximum output current. Note that ISC varies with duty
cycle.
8.3.4 Undervoltage Lockout and Thermal Shutdown
The LMR36520 incorporates an undervoltage lockout feature on the output of the internal LDO at the VCC pin.
When VCC reaches about 3.7 V, the device is ready to receive an EN signal and start-up. When VCC falls below
about 3 V, the device shuts down, regardless of EN status. Because the LDO is in dropout during these
transitions, the previously mentioned values roughly represent the input voltage levels during the transitions.
Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 170°C, the device shuts down; re-start occurs when the temperature falls to about
158°C. For safe operation, the device must not be allowed to go into a short circuit condition while in thermal
shutdown.
8.4 Device Functional Modes
8.4.1 Auto Mode
In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM.
In PWM, the regulator operates as a constant frequency, current mode, full-synchronous converter using PWM to
regulate the output voltage. While operating in this mode, the output voltage is regulated by switching at a
constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line
and load regulation and low output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The
duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The frequency of these
bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency (see the Glossary).
This mode provides high light-load efficiency by reducing the amount of input supply current required to regulate
the output voltage at small loads. This trades off very good light-load efficiency for larger output voltage ripple
and variable switching frequency. Also, a small increase in output voltage occurs at light loads. The actual
switching frequency and output voltage ripple depend on the input voltage, output voltage, and load.
8.4.2 Forced PWM Operation
The following select variant is a factory option made available for cases when constant frequency operation is
more important than light load efficiency.
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Device Functional Modes (continued)
Table 1. LMR36520 Device Variants with Fixed Frequency Operation at No Load
ORDERABLE PART NUMBER
OUTPUT CURRENT
FPWM
fSW
LMR36520FADDAR
2A
Yes
400 kHz
In FPWM operation, the diode emulation feature is turned off. This means that the device remains in CCM under
light loads. Under conditions where the device must reduce the on-time or off-time below the ensured minimum
to maintain regulation, the frequency reduces to maintain the effective duty cycle required for regulation. This
occurs for very high and very low input and output voltage ratios. In FPWM mode, a limited reverse current is
allowed through the inductor, allowing power to pass from the output of the regulator to the input of the regulator.
Note that in FPWM mode, larger currents pass through the inductor, if lightly loaded, than in auto mode. Once
loads are heavy enough to necessitate CCM operation, FPWM mode has no measurable effect on regulator
operation.
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage is
reduced to the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value.
Beyond this point, the switching can become erratic and the output voltage falls out of regulation. To avoid this
problem, the LMR36520 automatically reduces the switching frequency to increase the effective duty cycle and
maintain regulation. In this data sheet, the dropout voltage is defined as the difference between the input and
output voltage when the output has dropped by 1% of the nominal value. Under this condition, the switching
frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V short circuit detection
threshold is not activated when in dropout mode.
8.4.4 Minimum Switch On-Time
Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times
associated with the control circuits. This imposes a minimum switch duty cycle, therefore, a minimum conversion
ratio. The constraint is encountered at high input voltages and low output voltages. To help extend the minimum
controllable duty cycle, the LMR36520 automatically reduces the switching frequency when the minimum on-time
limit is reached. This way, the converter can regulate the lowest programmable output voltage at the maximum
input voltage. An estimate for the approximate input voltage, for a given output voltage, before frequency
foldback occurs is found in Equation 2. As the input voltage is increased, the switch on-time (duty cycle) reduces
to regulate the output voltage. When the on-time reaches the limit, the switching frequency drops, while the ontime remains fixed.
VOUT
VIN d
t ON ˜ fSW
(2)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMR36520 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 2 A. The following design procedure can be used to select components
for the LMR36520.
ADVANCE INFORMATION
NOTE
All of the capacitance values given in the following application information refer to effective
values; unless otherwise stated. The effective value is defined as the actual capacitance
under DC bias and temperature, not the rated or nameplate values. Use high-quality, lowESR, ceramic capacitors with an X7R or better dielectric throughout. All high value
ceramic capacitors have a large voltage coefficient in addition to normal tolerances and
temperature effects. Under DC bias, the capacitance drops considerably. Large case sizes
and higher voltage ratings are better in this regard. To help mitigate these effects, multiple
capacitors can be used in parallel to bring the minimum effective capacitance up to the
required value. This can also ease the RMS current requirements on a single capacitor. A
careful study of bias and temperature variation of any capacitor bank must be made in
order to ensure that the minimum value of effective capacitance is provided.
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9.2 Typical Application
Figure 5 shows a typical application circuit for the LMR36520. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick-start guide, Table 2 provides typical
component values for a range of the most common output voltages.
L
CIN
VIN
CHF
220 nF
2x 4.7 µF
VOUT
SW
VIN
CBOOT
COUT
BOOT
EN
VPU
0.1 µF
LMR36520
100 NŸ
CFF
PG
FB
VCC
CVCC
1 µF
RFBT
100 NŸ
PGND
PGND
RFBB
AGND
ADVANCE INFORMATION
VIN
Figure 5. Example Applications Circuit
Table 2. Typical External Component Values
NOMINAL COUT
(RATED
CAPACITANCE)
MINIMUM COUT
(RATED
CAPACITANCE)
RFBT (Ω)
RFBB (Ω)
CIN
CFF
10
3 × 22 µF
TBD
100 k
43.2 k
2 × 4.7 µF + 220 nF
20 pF
3.3
6.8
3 × 22 µF
TBD
100 k
43.2 k
2 × 4.7 µF + 220 nF
20 pF
5
10
2 × 22 µF
TBD
100 k
24.9 k
2 × 4.7 µF + 220 nF
20 pF
1000
5
6.8
2 × 22 µF
TBD
100 k
24.9 k
2 × 4.7 µF + 220 nF
20 pF
400
12
33
4 × 10 µF
TBD
100 k
9.09 k
2 × 4.7 µF + 220 nF
20 pF
1000
12
15
4 × 10 µF
TBD
100 k
9.09 k
2 × 4.7 µF + 220 nF
20 pF
ƒSW
(kHz)
VOUT (V)
400
3.3
1000
400
(1)
(2)
L (µH)
(1)
(2)
Optimized for superior load transient performance from 0 to 100% rated load.
Optimized for size constrained end applications.
9.2.1 Design 1: Low Power 24-V, 2-A Buck Converter
9.2.1.1 Design Requirements
Example requirements for a typical 5-V or 3.3-V application. The input voltages are here for illustration purposes
only. See the Specifications for the operating input voltage range.
Table 3. Detailed Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V to 24 V steady state, 4.2 V to 60-V transients
Output voltage
5 V/3.3 V
Maximum output current
0 A to 2 A
Switching frequency
400 kHz
Current consumption at 0-A load
Critical: Need to ensure low current consumption to reduce battery drain
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Table 3. Detailed Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
Switching frequency at 0-A load
Not critical: Need fixed frequency operation at high load only
Table 4. List of Components for Design 1
VOUT
FREQUENCY
RFBB
COUT
L
U1
5V
400 kHz
24.9 kΩ
4 × 22 µF
10 µH, 30 mΩ
LMR36520
3.3 V
400 kHz
43.2 kΩ
4 × 22 µF
10 µH, 30 mΩ
LMR36520
9.2.1.2 Detailed Design Procedure
The following design procedure applies to Figure 5 and Table 3.
9.2.1.2.1 Choosing the Switching Frequency
ADVANCE INFORMATION
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence a
more compact design. For this example, 400 kHz is used.
9.2.1.2.2 Setting the Output Voltage
The output voltage of LMR36520 is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in the Recommended Operating Conditions table. The divider network is
comprised of RFBT and RFBB, and closes the loop between the output voltage and the converter. The converter
regulates the output voltage by holding the voltage on the FB pin equal to the internal reference voltage, VREF.
The resistance of the divider is a compromise between excessive noise pick-up and excessive loading of the
output. Smaller values of resistance reduce noise sensitivity but also reduce the light-load efficiency. The
recommended value for RFBT is 100 kΩ with a maximum value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a
feed-forward capacitor must be used across this resistor to provide adequate loop phase margin (see the CFF
Selection section). Once RFBT is selected, use Equation 3 to select RFBB. VREF is nominally 1 V.
RFBT
RFBB
ª VOUT
º
1»
«
¬ VREF
¼
(3)
For this 5-V example, values are: RFBT = 100 kΩ and RFBB = 24.9 kΩ.
9.2.1.2.3 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum
output current. Experience shows that the best value for inductor ripple current is 30% of the maximum load
current. Note that when selecting the ripple current for applications with much smaller maximum load than the
maximum available from the device, use the maximum device current. Equation 4 can be used to determine the
value of inductance. The constant K is the percentage of inductor current ripple. This example uses K = 0.4 and
finds an inductance f L = 16 µH. The standard value of 10 µH is selected.
L
VIN VOUT
V
˜ OUT
fSW ˜ K ˜ IOUT max VIN
(4)
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, ISC.
This ensures that the inductor does not saturate even during a short circuit on the output. When the inductor core
material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly.
Although the valley current limit, ILIMIT, is designed to reduce the risk of current runaway, a saturated inductor can
cause the current to rise to high values very rapidly. This can lead to component damage. Do not allow the
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inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually
have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some
relaxation in the current rating of the inductor. However, they have more core losses at frequencies above about
1 MHz. In any case, the inductor saturation current must not be less than the device low-side current limit, ILIMIT.
In order to avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 5:
LMIN t 0.28 ˜
VOUT
fSW
(5)
9.2.1.2.4 Output Capacitor Selection
ESR d
D
2 K ˜ 'VOUT
ª
2 ˜ 'IOUT «1 K
¬«
K2
12
§
1 ·º
¸¸»
˜ ¨¨1
© (1 D) ¹¼»
VOUT
VIN
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = ripple factor from Inductor Selection
(6)
Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the output voltage
ripple.
Vr # 'IL ˜ ESR 2
1
8 ˜ fSW ˜ COUT
2
where
•
Vr = peak-to-peak output voltage ripple
(7)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range of 1
nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever
is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well
as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load
and loop stability must be performed.
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The value of the output capacitor, and the respective ESR, determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements, rather than the
output voltage ripple. Equation 6 can be used to estimate a lower bound on the total output capacitance, and an
upper bound on the ESR, that is required to meet a specified load transient.
º
ª
'IOUT
K2
COUT t
˜«1 D ˜ 1 K
˜ 2 D»
12
fSW ˜ 'VOUT ˜ K «¬
»¼
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9.2.1.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum ceramic capacitance of 4.7 µF is required on
the input of the LMR36520. This must be rated for at least the maximum input voltage that the application
requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple and maintain the input voltage during load transients. In addition, a small case size 220-nF ceramic
capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency bypass
for the control circuits internal to the device. For this example a 2 x 4.7-µF, 100-V, X7R (or better) ceramic
capacitor is chosen. The 220 nF must also be rated at 100-V with an X7R dielectric.
It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially
true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
ADVANCE INFORMATION
Most of the input switching current passes through the ceramic input capacitors. The approximate RMS value of
this current can be calculated from Equation 8 and must be checked against the manufacturer's maximum
ratings.
I
IRMS # OUT
2
(8)
9.2.1.2.6 CBOOT
The LMR36520 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor
stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of
100 nF and at least 16 V is required.
9.2.1.2.7 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this output
must not be loaded with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see the Power-Good Flag Output section). A value in the range of 10 kΩ to 100 kΩ is a
good choice in this case. The nominal output voltage on VCC is 5 V.
9.2.1.2.8 CFF Selection
In some cases a feed-forward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help mitigate this effect. Equation 9 can be used to estimate the value of CFF.
The value found with Equation 9 is a starting point; use lower values to determine if any advantage is gained by
the using a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters
with Feed-forward Capacitor Application Report is helpful when experimenting with a feed-forward capacitor.
VOUT ˜ COUT
CFF
VREF
120 ˜ RFBT ˜
VOUT
(9)
9.2.1.2.8.1 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in Figure 6. The input voltage at which the device turns on is designated
VON and the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100 kΩ and then
Equation 10 is used to calculate RENT and VOFF.
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VIN
RENT
EN
RENB
ADVANCE INFORMATION
Figure 6. Set-up for External UVLO Application
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RENT
§ VON
¨¨
© VEN H
VOFF
§
VEN HYS
VON ˜ ¨¨1
VEN
©
·
1¸¸ ˜ RENB
¹
·
¸¸
¹
where
•
•
VON = VIN turnon voltage
VOFF = VIN turnoff voltage
(10)
9.2.1.2.9 Maximum Ambient Temperature
ADVANCE INFORMATION
As with any power conversion device, the LMR36520 dissipates internal power while operating. The effect of this
power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance,
RθJA, of the device and PCB combination. The maximum internal die temperature for the LMR36520 must be
limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load
current. Equation 11 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The converter
efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions
cannot be found in one of the curves, then interpolation can be used to estimate the efficiency. Alternatively, the
EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly.
The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal
Metrics Application Report, the values given in Thermal Information are not valid for design purposes and must
not be used to estimate the thermal performance of the application. The values reported in that table were
measured under a specific set of conditions that are rarely obtained in an actual application.
IOUT
MAX
TJ TA
1
K
˜
˜
R TJA
1 K VOUT
where
•
η = efficiency
(11)
The effective RθJA is a critical parameter and depends on many factors such as the following:
• Power dissipation
• Air temperature/flow
• PCB area
• Cooper heat-sink area
• Number of thermal vias under the package
• Adjacent component placement
Use the following resources as guides to optimal thermal PCB design and estimate RθJA for a given application
environment:
• Thermal Design by Insight not Hindsight Application Report
• Semiconductor and IC Package Thermal Metrics Application Report
• Thermal Design Made Simple with LM43603 and LM43602 Application Report
• Using New Thermal Metrics Application Report
9.3 What to Do and What Not to Do
•
•
•
20
Do not allow the EN input to float.
Do not allow the output voltage to exceed the input voltage, nor go below ground.
Do not use the thermal data given in the Thermal Information table to design your application.
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10 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Specifications found in this data sheet. In
addition, the input supply must be capable of delivering the required input current to the loaded regulator. The
average input current can be estimated with Equation 12.
VOUT ˜ IOUT
IIN
VIN ˜ K
where
η is the efficiency
(12)
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the
regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with
the ceramics. The moderate ESR of these types of capacitors help damp the input resonant circuit and reduce
any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DC/DC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device and back into the input. This
uncontrolled current flow can damage the device.
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ADVANCE INFORMATION
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11 Layout
11.1 Layout Guidelines
ADVANCE INFORMATION
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad
PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck
converter, the most critical PCB feature is the loop formed by the input capacitors and power ground, as shown
in Figure 7. This loop carries large transient currents that can cause large transient voltages when reacting with
the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because
of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the
parasitic inductance. Figure 8 shows a recommended layout for the critical components of the LMR36520.
1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are
adjacent, simplifying the input capacitor placement.
2. Place the bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device
and routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short, wide traces to the
BOOT and SW pins. Route the SW pin to the N/C pin and used it to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as
a heat dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat-sinking. As stated in the Maximum Ambient Temperature section,
enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and
ambient temperature. The top and bottom PCB layers must be made with two ounce copper; and no less
than one ounce. If the PCB design uses multiple copper layers (recommended), these thermal vias can also
be connected to the inner layer heat-spreading ground planes.
8. Keep the switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide
as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies Application Report
• Simple Switcher PCB Layout Guidelines Application Report
• Constructing Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
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Layout Guidelines (continued)
VIN
CIN
SW
Figure 7. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control circuitry.
Connect the AGND and PGND pins to the ground planes using vias next to the bypass capacitors. PGND pins
are connected directly to the source of the low-side MOSFET switch and are also connected directly to the
grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can
bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one
side of the ground planes. The other side of the ground plane contains much less noise; use it for sensitive
routes.
Use as much copper as possible for the system ground plane, on the top and bottom layers for the best heat
dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1
oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current
conduction impedance, proper shielding, and lower thermal resistance.
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11.2 Layout Example
GND
HEATSINK
INDUCTOR
VOUT
COUT
COUT
ADVANCE INFORMATION
CBOOT
COUT
CHF
GND
CIN
EN
VIN
CVCC
PGOOD
RFBT
RFBB
GND
GND
HEATSINK
Top Trace
Bottom Trace
VIA
Ground Plane
VIA
Bottom
Figure 8. Example Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
• How a DC/DC Converter Package and Pinout Design Can Enhance Automotive EMI Performance Blog
• Introduction to Buck Converters Features: UVLO, Enable, Soft Start, Power Good Training Video
• Introduction to Buck Converters: Understanding Mode Transitions Training Video
• Introduction to Buck Converters: Minimum On-time and Minimum Off-time Operation Training Video
• Introduction to Buck Converters: Understanding Quiescent Current Specifications Training Video
• Trade-offs Between Thermal Performance and Small Solution Size with DC/DC Converters Training Video
• Reduce EMI and Shrink Solution Size with Hot Rod Packaging Training Video
12.2 Documentation Support
For related documentation see the following:
• Texas Instruments, Designing High-Performance, Low-EMI Automotive Power Supplies Application Report
• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
• Texas Instruments, Constructing Your Power Supply- Layout Considerations Seminar
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
SIMPLE SWITCHER is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: LMR36520
25
ADVANCE INFORMATION
12.2.1 Related Documentation
LMR36520
SNVSBF0 – SEPTEMBER 2019
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
ADVANCE INFORMATION
26
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: LMR36520
PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
PLMR36520ADDAR
Package Type Package Pins Package
Drawing
Qty
ACTIVE SO PowerPAD
DDA
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
GENERIC PACKAGE VIEW
DDA 8
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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